1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 47 #include "hw/ppc/xics.h" 48 #include "hw/qdev-properties.h" 49 #include "hw/ppc/pnv_xscom.h" 50 #include "hw/ppc/pnv_pnor.h" 51 52 #include "hw/isa/isa.h" 53 #include "hw/char/serial.h" 54 #include "hw/rtc/mc146818rtc.h" 55 56 #include <libfdt.h> 57 58 #define FDT_MAX_SIZE (1 * MiB) 59 60 #define FW_FILE_NAME "skiboot.lid" 61 #define FW_LOAD_ADDR 0x0 62 #define FW_MAX_SIZE (16 * MiB) 63 64 #define KERNEL_LOAD_ADDR 0x20000000 65 #define KERNEL_MAX_SIZE (128 * MiB) 66 #define INITRD_LOAD_ADDR 0x28000000 67 #define INITRD_MAX_SIZE (128 * MiB) 68 69 static const char *pnv_chip_core_typename(const PnvChip *o) 70 { 71 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 72 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 73 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 74 const char *core_type = object_class_get_name(object_class_by_name(s)); 75 g_free(s); 76 return core_type; 77 } 78 79 /* 80 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 81 * 4 * 4 sockets * 12 cores * 8 threads = 1536 82 * Let's make it 2^11 83 */ 84 #define MAX_CPUS 2048 85 86 /* 87 * Memory nodes are created by hostboot, one for each range of memory 88 * that has a different "affinity". In practice, it means one range 89 * per chip. 90 */ 91 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 92 { 93 char *mem_name; 94 uint64_t mem_reg_property[2]; 95 int off; 96 97 mem_reg_property[0] = cpu_to_be64(start); 98 mem_reg_property[1] = cpu_to_be64(size); 99 100 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 101 off = fdt_add_subnode(fdt, 0, mem_name); 102 g_free(mem_name); 103 104 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 105 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 106 sizeof(mem_reg_property)))); 107 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 108 } 109 110 static int get_cpus_node(void *fdt) 111 { 112 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 113 114 if (cpus_offset < 0) { 115 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 116 if (cpus_offset) { 117 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 119 } 120 } 121 _FDT(cpus_offset); 122 return cpus_offset; 123 } 124 125 /* 126 * The PowerNV cores (and threads) need to use real HW ids and not an 127 * incremental index like it has been done on other platforms. This HW 128 * id is stored in the CPU PIR, it is used to create cpu nodes in the 129 * device tree, used in XSCOM to address cores and in interrupt 130 * servers. 131 */ 132 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 133 { 134 PowerPCCPU *cpu = pc->threads[0]; 135 CPUState *cs = CPU(cpu); 136 DeviceClass *dc = DEVICE_GET_CLASS(cs); 137 int smt_threads = CPU_CORE(pc)->nr_threads; 138 CPUPPCState *env = &cpu->env; 139 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 140 uint32_t servers_prop[smt_threads]; 141 int i; 142 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 143 0xffffffff, 0xffffffff}; 144 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 145 uint32_t cpufreq = 1000000000; 146 uint32_t page_sizes_prop[64]; 147 size_t page_sizes_prop_size; 148 const uint8_t pa_features[] = { 24, 0, 149 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 150 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 151 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 152 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 153 int offset; 154 char *nodename; 155 int cpus_offset = get_cpus_node(fdt); 156 157 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 158 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 159 _FDT(offset); 160 g_free(nodename); 161 162 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 163 164 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 165 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 166 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 170 env->dcache_line_size))); 171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 172 env->dcache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 174 env->icache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 176 env->icache_line_size))); 177 178 if (pcc->l1_dcache_size) { 179 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 180 pcc->l1_dcache_size))); 181 } else { 182 warn_report("Unknown L1 dcache size for cpu"); 183 } 184 if (pcc->l1_icache_size) { 185 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 186 pcc->l1_icache_size))); 187 } else { 188 warn_report("Unknown L1 icache size for cpu"); 189 } 190 191 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 192 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 194 cpu->hash64_opts->slb_size))); 195 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 196 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 197 198 if (ppc_has_spr(cpu, SPR_PURR)) { 199 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 200 } 201 202 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 204 segs, sizeof(segs)))); 205 } 206 207 /* 208 * Advertise VMX/VSX (vector extensions) if available 209 * 0 / no property == no vector extensions 210 * 1 == VMX / Altivec available 211 * 2 == VSX available 212 */ 213 if (env->insns_flags & PPC_ALTIVEC) { 214 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 215 216 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 217 } 218 219 /* 220 * Advertise DFP (Decimal Floating Point) if available 221 * 0 / no property == no DFP 222 * 1 == DFP available 223 */ 224 if (env->insns_flags2 & PPC2_DFP) { 225 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 226 } 227 228 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 229 sizeof(page_sizes_prop)); 230 if (page_sizes_prop_size) { 231 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 232 page_sizes_prop, page_sizes_prop_size))); 233 } 234 235 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 236 pa_features, sizeof(pa_features)))); 237 238 /* Build interrupt servers properties */ 239 for (i = 0; i < smt_threads; i++) { 240 servers_prop[i] = cpu_to_be32(pc->pir + i); 241 } 242 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 243 servers_prop, sizeof(servers_prop)))); 244 } 245 246 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 247 uint32_t nr_threads) 248 { 249 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 250 char *name; 251 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 252 uint32_t irange[2], i, rsize; 253 uint64_t *reg; 254 int offset; 255 256 irange[0] = cpu_to_be32(pir); 257 irange[1] = cpu_to_be32(nr_threads); 258 259 rsize = sizeof(uint64_t) * 2 * nr_threads; 260 reg = g_malloc(rsize); 261 for (i = 0; i < nr_threads; i++) { 262 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 263 reg[i * 2 + 1] = cpu_to_be64(0x1000); 264 } 265 266 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 267 offset = fdt_add_subnode(fdt, 0, name); 268 _FDT(offset); 269 g_free(name); 270 271 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 272 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 273 _FDT((fdt_setprop_string(fdt, offset, "device_type", 274 "PowerPC-External-Interrupt-Presentation"))); 275 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 276 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 277 irange, sizeof(irange)))); 278 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 280 g_free(reg); 281 } 282 283 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 284 { 285 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 286 int i; 287 288 pnv_dt_xscom(chip, fdt, 0, 289 cpu_to_be64(PNV_XSCOM_BASE(chip)), 290 cpu_to_be64(PNV_XSCOM_SIZE), 291 compat, sizeof(compat)); 292 293 for (i = 0; i < chip->nr_cores; i++) { 294 PnvCore *pnv_core = chip->cores[i]; 295 296 pnv_dt_core(chip, pnv_core, fdt); 297 298 /* Interrupt Control Presenters (ICP). One per core. */ 299 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 300 } 301 302 if (chip->ram_size) { 303 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 304 } 305 } 306 307 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 308 { 309 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 310 int i; 311 312 pnv_dt_xscom(chip, fdt, 0, 313 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 314 cpu_to_be64(PNV9_XSCOM_SIZE), 315 compat, sizeof(compat)); 316 317 for (i = 0; i < chip->nr_cores; i++) { 318 PnvCore *pnv_core = chip->cores[i]; 319 320 pnv_dt_core(chip, pnv_core, fdt); 321 } 322 323 if (chip->ram_size) { 324 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 325 } 326 327 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 328 } 329 330 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 331 { 332 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 333 int i; 334 335 pnv_dt_xscom(chip, fdt, 0, 336 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 337 cpu_to_be64(PNV10_XSCOM_SIZE), 338 compat, sizeof(compat)); 339 340 for (i = 0; i < chip->nr_cores; i++) { 341 PnvCore *pnv_core = chip->cores[i]; 342 343 pnv_dt_core(chip, pnv_core, fdt); 344 } 345 346 if (chip->ram_size) { 347 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 348 } 349 350 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 351 } 352 353 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 354 { 355 uint32_t io_base = d->ioport_id; 356 uint32_t io_regs[] = { 357 cpu_to_be32(1), 358 cpu_to_be32(io_base), 359 cpu_to_be32(2) 360 }; 361 char *name; 362 int node; 363 364 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 365 node = fdt_add_subnode(fdt, lpc_off, name); 366 _FDT(node); 367 g_free(name); 368 369 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 370 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 371 } 372 373 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 374 { 375 const char compatible[] = "ns16550\0pnpPNP,501"; 376 uint32_t io_base = d->ioport_id; 377 uint32_t io_regs[] = { 378 cpu_to_be32(1), 379 cpu_to_be32(io_base), 380 cpu_to_be32(8) 381 }; 382 uint32_t irq; 383 char *name; 384 int node; 385 386 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 387 388 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 389 node = fdt_add_subnode(fdt, lpc_off, name); 390 _FDT(node); 391 g_free(name); 392 393 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 394 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 395 sizeof(compatible)))); 396 397 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 398 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 399 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 400 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 401 fdt_get_phandle(fdt, lpc_off)))); 402 403 /* This is needed by Linux */ 404 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 405 } 406 407 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 408 { 409 const char compatible[] = "bt\0ipmi-bt"; 410 uint32_t io_base; 411 uint32_t io_regs[] = { 412 cpu_to_be32(1), 413 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 414 cpu_to_be32(3) 415 }; 416 uint32_t irq; 417 char *name; 418 int node; 419 420 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 421 io_regs[1] = cpu_to_be32(io_base); 422 423 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 424 425 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 426 node = fdt_add_subnode(fdt, lpc_off, name); 427 _FDT(node); 428 g_free(name); 429 430 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 431 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 432 sizeof(compatible)))); 433 434 /* Mark it as reserved to avoid Linux trying to claim it */ 435 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 436 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 437 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 438 fdt_get_phandle(fdt, lpc_off)))); 439 } 440 441 typedef struct ForeachPopulateArgs { 442 void *fdt; 443 int offset; 444 } ForeachPopulateArgs; 445 446 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 447 { 448 ForeachPopulateArgs *args = opaque; 449 ISADevice *d = ISA_DEVICE(dev); 450 451 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 452 pnv_dt_rtc(d, args->fdt, args->offset); 453 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 454 pnv_dt_serial(d, args->fdt, args->offset); 455 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 456 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 457 } else { 458 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 459 d->ioport_id); 460 } 461 462 return 0; 463 } 464 465 /* 466 * The default LPC bus of a multichip system is on chip 0. It's 467 * recognized by the firmware (skiboot) using a "primary" property. 468 */ 469 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 470 { 471 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 472 ForeachPopulateArgs args = { 473 .fdt = fdt, 474 .offset = isa_offset, 475 }; 476 uint32_t phandle; 477 478 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 479 480 phandle = qemu_fdt_alloc_phandle(fdt); 481 assert(phandle > 0); 482 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 483 484 /* 485 * ISA devices are not necessarily parented to the ISA bus so we 486 * can not use object_child_foreach() 487 */ 488 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 489 &args); 490 } 491 492 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 493 { 494 int off; 495 496 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 497 off = fdt_add_subnode(fdt, off, "power-mgt"); 498 499 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 500 } 501 502 static void *pnv_dt_create(MachineState *machine) 503 { 504 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 505 PnvMachineState *pnv = PNV_MACHINE(machine); 506 void *fdt; 507 char *buf; 508 int off; 509 int i; 510 511 fdt = g_malloc0(FDT_MAX_SIZE); 512 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 513 514 /* /qemu node */ 515 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 516 517 /* Root node */ 518 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 519 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 520 _FDT((fdt_setprop_string(fdt, 0, "model", 521 "IBM PowerNV (emulated by qemu)"))); 522 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 523 524 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 525 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 526 if (qemu_uuid_set) { 527 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 528 } 529 g_free(buf); 530 531 off = fdt_add_subnode(fdt, 0, "chosen"); 532 if (machine->kernel_cmdline) { 533 _FDT((fdt_setprop_string(fdt, off, "bootargs", 534 machine->kernel_cmdline))); 535 } 536 537 if (pnv->initrd_size) { 538 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 539 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 540 541 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 542 &start_prop, sizeof(start_prop)))); 543 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 544 &end_prop, sizeof(end_prop)))); 545 } 546 547 /* Populate device tree for each chip */ 548 for (i = 0; i < pnv->num_chips; i++) { 549 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 550 } 551 552 /* Populate ISA devices on chip 0 */ 553 pnv_dt_isa(pnv, fdt); 554 555 if (pnv->bmc) { 556 pnv_dt_bmc_sensors(pnv->bmc, fdt); 557 } 558 559 /* Create an extra node for power management on machines that support it */ 560 if (pmc->dt_power_mgt) { 561 pmc->dt_power_mgt(pnv, fdt); 562 } 563 564 return fdt; 565 } 566 567 static void pnv_powerdown_notify(Notifier *n, void *opaque) 568 { 569 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 570 571 if (pnv->bmc) { 572 pnv_bmc_powerdown(pnv->bmc); 573 } 574 } 575 576 static void pnv_reset(MachineState *machine) 577 { 578 PnvMachineState *pnv = PNV_MACHINE(machine); 579 IPMIBmc *bmc; 580 void *fdt; 581 582 qemu_devices_reset(); 583 584 /* 585 * The machine should provide by default an internal BMC simulator. 586 * If not, try to use the BMC device that was provided on the command 587 * line. 588 */ 589 bmc = pnv_bmc_find(&error_fatal); 590 if (!pnv->bmc) { 591 if (!bmc) { 592 if (!qtest_enabled()) { 593 warn_report("machine has no BMC device. Use '-device " 594 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 595 "to define one"); 596 } 597 } else { 598 pnv_bmc_set_pnor(bmc, pnv->pnor); 599 pnv->bmc = bmc; 600 } 601 } 602 603 fdt = pnv_dt_create(machine); 604 605 /* Pack resulting tree */ 606 _FDT((fdt_pack(fdt))); 607 608 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 609 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 610 611 g_free(fdt); 612 } 613 614 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 615 { 616 Pnv8Chip *chip8 = PNV8_CHIP(chip); 617 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 618 } 619 620 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 621 { 622 Pnv8Chip *chip8 = PNV8_CHIP(chip); 623 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 624 } 625 626 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 627 { 628 Pnv9Chip *chip9 = PNV9_CHIP(chip); 629 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 630 } 631 632 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 633 { 634 Pnv10Chip *chip10 = PNV10_CHIP(chip); 635 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 636 } 637 638 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 639 { 640 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 641 } 642 643 static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaque) 644 { 645 Monitor *mon = opaque; 646 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); 647 648 if (phb3) { 649 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 650 ics_pic_print_info(&phb3->lsis, mon); 651 } 652 return 0; 653 } 654 655 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 656 { 657 Pnv8Chip *chip8 = PNV8_CHIP(chip); 658 659 ics_pic_print_info(&chip8->psi.ics, mon); 660 object_child_foreach(OBJECT(chip), 661 pnv_chip_power8_pic_print_info_child, mon); 662 } 663 664 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 665 { 666 Monitor *mon = opaque; 667 PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4); 668 669 if (phb4) { 670 pnv_phb4_pic_print_info(phb4, mon); 671 } 672 return 0; 673 } 674 675 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 676 { 677 Pnv9Chip *chip9 = PNV9_CHIP(chip); 678 679 pnv_xive_pic_print_info(&chip9->xive, mon); 680 pnv_psi_pic_print_info(&chip9->psi, mon); 681 682 object_child_foreach_recursive(OBJECT(chip), 683 pnv_chip_power9_pic_print_info_child, mon); 684 } 685 686 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 687 uint32_t core_id) 688 { 689 return PNV_XSCOM_EX_BASE(core_id); 690 } 691 692 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 693 uint32_t core_id) 694 { 695 return PNV9_XSCOM_EC_BASE(core_id); 696 } 697 698 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 699 uint32_t core_id) 700 { 701 return PNV10_XSCOM_EC_BASE(core_id); 702 } 703 704 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 705 { 706 PowerPCCPUClass *ppc_default = 707 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 708 PowerPCCPUClass *ppc = 709 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 710 711 return ppc_default->pvr_match(ppc_default, ppc->pvr); 712 } 713 714 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 715 { 716 ISADevice *dev = isa_new("isa-ipmi-bt"); 717 718 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 719 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 720 isa_realize_and_unref(dev, bus, &error_fatal); 721 } 722 723 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 724 { 725 Pnv10Chip *chip10 = PNV10_CHIP(chip); 726 727 pnv_xive2_pic_print_info(&chip10->xive, mon); 728 pnv_psi_pic_print_info(&chip10->psi, mon); 729 730 object_child_foreach_recursive(OBJECT(chip), 731 pnv_chip_power9_pic_print_info_child, mon); 732 } 733 734 /* Always give the first 1GB to chip 0 else we won't boot */ 735 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 736 { 737 MachineState *machine = MACHINE(pnv); 738 uint64_t ram_per_chip; 739 740 assert(machine->ram_size >= 1 * GiB); 741 742 ram_per_chip = machine->ram_size / pnv->num_chips; 743 if (ram_per_chip >= 1 * GiB) { 744 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 745 } 746 747 assert(pnv->num_chips > 1); 748 749 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 750 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 751 } 752 753 static void pnv_init(MachineState *machine) 754 { 755 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 756 PnvMachineState *pnv = PNV_MACHINE(machine); 757 MachineClass *mc = MACHINE_GET_CLASS(machine); 758 char *fw_filename; 759 long fw_size; 760 uint64_t chip_ram_start = 0; 761 int i; 762 char *chip_typename; 763 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 764 DeviceState *dev; 765 766 if (kvm_enabled()) { 767 error_report("The powernv machine does not work with KVM acceleration"); 768 exit(EXIT_FAILURE); 769 } 770 771 /* allocate RAM */ 772 if (machine->ram_size < mc->default_ram_size) { 773 char *sz = size_to_str(mc->default_ram_size); 774 error_report("Invalid RAM size, should be bigger than %s", sz); 775 g_free(sz); 776 exit(EXIT_FAILURE); 777 } 778 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 779 780 /* 781 * Create our simple PNOR device 782 */ 783 dev = qdev_new(TYPE_PNV_PNOR); 784 if (pnor) { 785 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 786 } 787 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 788 pnv->pnor = PNV_PNOR(dev); 789 790 /* load skiboot firmware */ 791 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 792 if (!fw_filename) { 793 error_report("Could not find OPAL firmware '%s'", bios_name); 794 exit(1); 795 } 796 797 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 798 if (fw_size < 0) { 799 error_report("Could not load OPAL firmware '%s'", fw_filename); 800 exit(1); 801 } 802 g_free(fw_filename); 803 804 /* load kernel */ 805 if (machine->kernel_filename) { 806 long kernel_size; 807 808 kernel_size = load_image_targphys(machine->kernel_filename, 809 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 810 if (kernel_size < 0) { 811 error_report("Could not load kernel '%s'", 812 machine->kernel_filename); 813 exit(1); 814 } 815 } 816 817 /* load initrd */ 818 if (machine->initrd_filename) { 819 pnv->initrd_base = INITRD_LOAD_ADDR; 820 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 821 pnv->initrd_base, INITRD_MAX_SIZE); 822 if (pnv->initrd_size < 0) { 823 error_report("Could not load initial ram disk '%s'", 824 machine->initrd_filename); 825 exit(1); 826 } 827 } 828 829 /* MSIs are supported on this platform */ 830 msi_nonbroken = true; 831 832 /* 833 * Check compatibility of the specified CPU with the machine 834 * default. 835 */ 836 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 837 error_report("invalid CPU model '%s' for %s machine", 838 machine->cpu_type, mc->name); 839 exit(1); 840 } 841 842 /* Create the processor chips */ 843 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 844 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 845 i, machine->cpu_type); 846 if (!object_class_by_name(chip_typename)) { 847 error_report("invalid chip model '%.*s' for %s machine", 848 i, machine->cpu_type, mc->name); 849 exit(1); 850 } 851 852 pnv->num_chips = 853 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 854 /* 855 * TODO: should we decide on how many chips we can create based 856 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 857 */ 858 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 859 error_report("invalid number of chips: '%d'", pnv->num_chips); 860 error_printf( 861 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 862 exit(1); 863 } 864 865 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 866 for (i = 0; i < pnv->num_chips; i++) { 867 char chip_name[32]; 868 Object *chip = OBJECT(qdev_new(chip_typename)); 869 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 870 871 pnv->chips[i] = PNV_CHIP(chip); 872 873 /* Distribute RAM among the chips */ 874 object_property_set_int(chip, "ram-start", chip_ram_start, 875 &error_fatal); 876 object_property_set_int(chip, "ram-size", chip_ram_size, 877 &error_fatal); 878 chip_ram_start += chip_ram_size; 879 880 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 881 object_property_add_child(OBJECT(pnv), chip_name, chip); 882 object_property_set_int(chip, "chip-id", i, &error_fatal); 883 object_property_set_int(chip, "nr-cores", machine->smp.cores, 884 &error_fatal); 885 object_property_set_int(chip, "nr-threads", machine->smp.threads, 886 &error_fatal); 887 /* 888 * The POWER8 machine use the XICS interrupt interface. 889 * Propagate the XICS fabric to the chip and its controllers. 890 */ 891 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 892 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 893 } 894 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 895 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 896 &error_abort); 897 } 898 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 899 } 900 g_free(chip_typename); 901 902 /* Instantiate ISA bus on chip 0 */ 903 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 904 905 /* Create serial port */ 906 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 907 908 /* Create an RTC ISA device too */ 909 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 910 911 /* 912 * Create the machine BMC simulator and the IPMI BT device for 913 * communication with the BMC 914 */ 915 if (defaults_enabled()) { 916 pnv->bmc = pnv_bmc_create(pnv->pnor); 917 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 918 } 919 920 /* 921 * The PNOR is mapped on the LPC FW address space by the BMC. 922 * Since we can not reach the remote BMC machine with LPC memops, 923 * map it always for now. 924 */ 925 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 926 &pnv->pnor->mmio); 927 928 /* 929 * OpenPOWER systems use a IPMI SEL Event message to notify the 930 * host to powerdown 931 */ 932 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 933 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 934 } 935 936 /* 937 * 0:21 Reserved - Read as zeros 938 * 22:24 Chip ID 939 * 25:28 Core number 940 * 29:31 Thread ID 941 */ 942 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 943 { 944 return (chip->chip_id << 7) | (core_id << 3); 945 } 946 947 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 948 Error **errp) 949 { 950 Pnv8Chip *chip8 = PNV8_CHIP(chip); 951 Error *local_err = NULL; 952 Object *obj; 953 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 954 955 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 956 if (local_err) { 957 error_propagate(errp, local_err); 958 return; 959 } 960 961 pnv_cpu->intc = obj; 962 } 963 964 965 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 966 { 967 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 968 969 icp_reset(ICP(pnv_cpu->intc)); 970 } 971 972 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 973 { 974 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 975 976 icp_destroy(ICP(pnv_cpu->intc)); 977 pnv_cpu->intc = NULL; 978 } 979 980 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 981 Monitor *mon) 982 { 983 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 984 } 985 986 /* 987 * 0:48 Reserved - Read as zeroes 988 * 49:52 Node ID 989 * 53:55 Chip ID 990 * 56 Reserved - Read as zero 991 * 57:61 Core number 992 * 62:63 Thread ID 993 * 994 * We only care about the lower bits. uint32_t is fine for the moment. 995 */ 996 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 997 { 998 return (chip->chip_id << 8) | (core_id << 2); 999 } 1000 1001 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1002 { 1003 return (chip->chip_id << 8) | (core_id << 2); 1004 } 1005 1006 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1007 Error **errp) 1008 { 1009 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1010 Error *local_err = NULL; 1011 Object *obj; 1012 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1013 1014 /* 1015 * The core creates its interrupt presenter but the XIVE interrupt 1016 * controller object is initialized afterwards. Hopefully, it's 1017 * only used at runtime. 1018 */ 1019 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1020 &local_err); 1021 if (local_err) { 1022 error_propagate(errp, local_err); 1023 return; 1024 } 1025 1026 pnv_cpu->intc = obj; 1027 } 1028 1029 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1030 { 1031 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1032 1033 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1034 } 1035 1036 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1037 { 1038 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1039 1040 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1041 pnv_cpu->intc = NULL; 1042 } 1043 1044 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1045 Monitor *mon) 1046 { 1047 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1048 } 1049 1050 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1051 Error **errp) 1052 { 1053 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1054 Error *local_err = NULL; 1055 Object *obj; 1056 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1057 1058 /* 1059 * The core creates its interrupt presenter but the XIVE2 interrupt 1060 * controller object is initialized afterwards. Hopefully, it's 1061 * only used at runtime. 1062 */ 1063 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1064 &local_err); 1065 if (local_err) { 1066 error_propagate(errp, local_err); 1067 return; 1068 } 1069 1070 pnv_cpu->intc = obj; 1071 } 1072 1073 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1074 { 1075 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1076 1077 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1078 } 1079 1080 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1081 { 1082 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1083 1084 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1085 pnv_cpu->intc = NULL; 1086 } 1087 1088 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1089 Monitor *mon) 1090 { 1091 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1092 } 1093 1094 /* 1095 * Allowed core identifiers on a POWER8 Processor Chip : 1096 * 1097 * <EX0 reserved> 1098 * EX1 - Venice only 1099 * EX2 - Venice only 1100 * EX3 - Venice only 1101 * EX4 1102 * EX5 1103 * EX6 1104 * <EX7,8 reserved> <reserved> 1105 * EX9 - Venice only 1106 * EX10 - Venice only 1107 * EX11 - Venice only 1108 * EX12 1109 * EX13 1110 * EX14 1111 * <EX15 reserved> 1112 */ 1113 #define POWER8E_CORE_MASK (0x7070ull) 1114 #define POWER8_CORE_MASK (0x7e7eull) 1115 1116 /* 1117 * POWER9 has 24 cores, ids starting at 0x0 1118 */ 1119 #define POWER9_CORE_MASK (0xffffffffffffffull) 1120 1121 1122 #define POWER10_CORE_MASK (0xffffffffffffffull) 1123 1124 static void pnv_chip_power8_instance_init(Object *obj) 1125 { 1126 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1127 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1128 int i; 1129 1130 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1131 (Object **)&chip8->xics, 1132 object_property_allow_set_link, 1133 OBJ_PROP_LINK_STRONG); 1134 1135 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1136 1137 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1138 1139 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1140 1141 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1142 1143 chip8->num_phbs = pcc->num_phbs; 1144 1145 for (i = 0; i < chip8->num_phbs; i++) { 1146 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1147 } 1148 1149 } 1150 1151 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1152 { 1153 PnvChip *chip = PNV_CHIP(chip8); 1154 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1155 int i, j; 1156 char *name; 1157 1158 name = g_strdup_printf("icp-%x", chip->chip_id); 1159 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1160 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1161 g_free(name); 1162 1163 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1164 1165 /* Map the ICP registers for each thread */ 1166 for (i = 0; i < chip->nr_cores; i++) { 1167 PnvCore *pnv_core = chip->cores[i]; 1168 int core_hwid = CPU_CORE(pnv_core)->core_id; 1169 1170 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1171 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1172 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1173 1174 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1175 &icp->mmio); 1176 } 1177 } 1178 } 1179 1180 /* Attach a root port device */ 1181 void pnv_phb_attach_root_port(PCIHostState *pci, const char *name) 1182 { 1183 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name); 1184 1185 pci_realize_and_unref(root, pci->bus, &error_fatal); 1186 } 1187 1188 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1189 { 1190 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1191 PnvChip *chip = PNV_CHIP(dev); 1192 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1193 Pnv8Psi *psi8 = &chip8->psi; 1194 Error *local_err = NULL; 1195 int i; 1196 1197 assert(chip8->xics); 1198 1199 /* XSCOM bridge is first */ 1200 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1201 if (local_err) { 1202 error_propagate(errp, local_err); 1203 return; 1204 } 1205 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1206 1207 pcc->parent_realize(dev, &local_err); 1208 if (local_err) { 1209 error_propagate(errp, local_err); 1210 return; 1211 } 1212 1213 /* Processor Service Interface (PSI) Host Bridge */ 1214 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1215 &error_fatal); 1216 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1217 OBJECT(chip8->xics), &error_abort); 1218 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1219 return; 1220 } 1221 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1222 &PNV_PSI(psi8)->xscom_regs); 1223 1224 /* Create LPC controller */ 1225 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi), 1226 &error_abort); 1227 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1228 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1229 1230 chip->fw_mr = &chip8->lpc.isa_fw; 1231 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1232 (uint64_t) PNV_XSCOM_BASE(chip), 1233 PNV_XSCOM_LPC_BASE); 1234 1235 /* 1236 * Interrupt Management Area. This is the memory region holding 1237 * all the Interrupt Control Presenter (ICP) registers 1238 */ 1239 pnv_chip_icp_realize(chip8, &local_err); 1240 if (local_err) { 1241 error_propagate(errp, local_err); 1242 return; 1243 } 1244 1245 /* Create the simplified OCC model */ 1246 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi), 1247 &error_abort); 1248 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1249 return; 1250 } 1251 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1252 1253 /* OCC SRAM model */ 1254 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1255 &chip8->occ.sram_regs); 1256 1257 /* HOMER */ 1258 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1259 &error_abort); 1260 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1261 return; 1262 } 1263 /* Homer Xscom region */ 1264 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1265 1266 /* Homer mmio region */ 1267 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1268 &chip8->homer.regs); 1269 1270 /* PHB3 controllers */ 1271 for (i = 0; i < chip8->num_phbs; i++) { 1272 PnvPHB3 *phb = &chip8->phbs[i]; 1273 1274 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1275 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1276 &error_fatal); 1277 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1278 &error_fatal); 1279 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1280 return; 1281 } 1282 } 1283 } 1284 1285 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1286 { 1287 addr &= (PNV_XSCOM_SIZE - 1); 1288 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1289 } 1290 1291 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1292 { 1293 DeviceClass *dc = DEVICE_CLASS(klass); 1294 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1295 1296 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1297 k->cores_mask = POWER8E_CORE_MASK; 1298 k->num_phbs = 3; 1299 k->core_pir = pnv_chip_core_pir_p8; 1300 k->intc_create = pnv_chip_power8_intc_create; 1301 k->intc_reset = pnv_chip_power8_intc_reset; 1302 k->intc_destroy = pnv_chip_power8_intc_destroy; 1303 k->intc_print_info = pnv_chip_power8_intc_print_info; 1304 k->isa_create = pnv_chip_power8_isa_create; 1305 k->dt_populate = pnv_chip_power8_dt_populate; 1306 k->pic_print_info = pnv_chip_power8_pic_print_info; 1307 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1308 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1309 dc->desc = "PowerNV Chip POWER8E"; 1310 1311 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1312 &k->parent_realize); 1313 } 1314 1315 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1316 { 1317 DeviceClass *dc = DEVICE_CLASS(klass); 1318 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1319 1320 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1321 k->cores_mask = POWER8_CORE_MASK; 1322 k->num_phbs = 3; 1323 k->core_pir = pnv_chip_core_pir_p8; 1324 k->intc_create = pnv_chip_power8_intc_create; 1325 k->intc_reset = pnv_chip_power8_intc_reset; 1326 k->intc_destroy = pnv_chip_power8_intc_destroy; 1327 k->intc_print_info = pnv_chip_power8_intc_print_info; 1328 k->isa_create = pnv_chip_power8_isa_create; 1329 k->dt_populate = pnv_chip_power8_dt_populate; 1330 k->pic_print_info = pnv_chip_power8_pic_print_info; 1331 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1332 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1333 dc->desc = "PowerNV Chip POWER8"; 1334 1335 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1336 &k->parent_realize); 1337 } 1338 1339 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1340 { 1341 DeviceClass *dc = DEVICE_CLASS(klass); 1342 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1343 1344 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1345 k->cores_mask = POWER8_CORE_MASK; 1346 k->num_phbs = 4; 1347 k->core_pir = pnv_chip_core_pir_p8; 1348 k->intc_create = pnv_chip_power8_intc_create; 1349 k->intc_reset = pnv_chip_power8_intc_reset; 1350 k->intc_destroy = pnv_chip_power8_intc_destroy; 1351 k->intc_print_info = pnv_chip_power8_intc_print_info; 1352 k->isa_create = pnv_chip_power8nvl_isa_create; 1353 k->dt_populate = pnv_chip_power8_dt_populate; 1354 k->pic_print_info = pnv_chip_power8_pic_print_info; 1355 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1356 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1357 dc->desc = "PowerNV Chip POWER8NVL"; 1358 1359 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1360 &k->parent_realize); 1361 } 1362 1363 static void pnv_chip_power9_instance_init(Object *obj) 1364 { 1365 PnvChip *chip = PNV_CHIP(obj); 1366 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1367 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1368 int i; 1369 1370 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1371 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1372 "xive-fabric"); 1373 1374 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1375 1376 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1377 1378 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1379 1380 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1381 1382 /* Number of PECs is the chip default */ 1383 chip->num_pecs = pcc->num_pecs; 1384 1385 for (i = 0; i < chip->num_pecs; i++) { 1386 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1387 TYPE_PNV_PHB4_PEC); 1388 } 1389 } 1390 1391 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1392 PnvCore *pnv_core) 1393 { 1394 char eq_name[32]; 1395 int core_id = CPU_CORE(pnv_core)->core_id; 1396 1397 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1398 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1399 sizeof(*eq), TYPE_PNV_QUAD, 1400 &error_fatal, NULL); 1401 1402 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1403 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1404 } 1405 1406 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1407 { 1408 PnvChip *chip = PNV_CHIP(chip9); 1409 int i; 1410 1411 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1412 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1413 1414 for (i = 0; i < chip9->nr_quads; i++) { 1415 PnvQuad *eq = &chip9->quads[i]; 1416 1417 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1418 1419 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1420 &eq->xscom_regs); 1421 } 1422 } 1423 1424 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1425 { 1426 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1427 int i; 1428 1429 for (i = 0; i < chip->num_pecs; i++) { 1430 PnvPhb4PecState *pec = &chip9->pecs[i]; 1431 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1432 uint32_t pec_nest_base; 1433 uint32_t pec_pci_base; 1434 1435 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1436 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1437 &error_fatal); 1438 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1439 &error_fatal); 1440 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1441 return; 1442 } 1443 1444 pec_nest_base = pecc->xscom_nest_base(pec); 1445 pec_pci_base = pecc->xscom_pci_base(pec); 1446 1447 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1448 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1449 } 1450 } 1451 1452 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1453 { 1454 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1455 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1456 PnvChip *chip = PNV_CHIP(dev); 1457 Pnv9Psi *psi9 = &chip9->psi; 1458 Error *local_err = NULL; 1459 1460 /* XSCOM bridge is first */ 1461 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1462 if (local_err) { 1463 error_propagate(errp, local_err); 1464 return; 1465 } 1466 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1467 1468 pcc->parent_realize(dev, &local_err); 1469 if (local_err) { 1470 error_propagate(errp, local_err); 1471 return; 1472 } 1473 1474 pnv_chip_quad_realize(chip9, &local_err); 1475 if (local_err) { 1476 error_propagate(errp, local_err); 1477 return; 1478 } 1479 1480 /* XIVE interrupt controller (POWER9) */ 1481 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1482 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1483 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1484 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1485 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1486 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1487 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1488 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1489 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1490 &error_abort); 1491 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1492 return; 1493 } 1494 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1495 &chip9->xive.xscom_regs); 1496 1497 /* Processor Service Interface (PSI) Host Bridge */ 1498 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1499 &error_fatal); 1500 /* This is the only device with 4k ESB pages */ 1501 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1502 &error_fatal); 1503 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1504 return; 1505 } 1506 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1507 &PNV_PSI(psi9)->xscom_regs); 1508 1509 /* LPC */ 1510 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi), 1511 &error_abort); 1512 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1513 return; 1514 } 1515 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1516 &chip9->lpc.xscom_regs); 1517 1518 chip->fw_mr = &chip9->lpc.isa_fw; 1519 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1520 (uint64_t) PNV9_LPCM_BASE(chip)); 1521 1522 /* Create the simplified OCC model */ 1523 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi), 1524 &error_abort); 1525 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1526 return; 1527 } 1528 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1529 1530 /* OCC SRAM model */ 1531 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1532 &chip9->occ.sram_regs); 1533 1534 /* HOMER */ 1535 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1536 &error_abort); 1537 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1538 return; 1539 } 1540 /* Homer Xscom region */ 1541 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1542 1543 /* Homer mmio region */ 1544 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1545 &chip9->homer.regs); 1546 1547 /* PEC PHBs */ 1548 pnv_chip_power9_pec_realize(chip, &local_err); 1549 if (local_err) { 1550 error_propagate(errp, local_err); 1551 return; 1552 } 1553 } 1554 1555 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1556 { 1557 addr &= (PNV9_XSCOM_SIZE - 1); 1558 return addr >> 3; 1559 } 1560 1561 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1562 { 1563 DeviceClass *dc = DEVICE_CLASS(klass); 1564 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1565 1566 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1567 k->cores_mask = POWER9_CORE_MASK; 1568 k->core_pir = pnv_chip_core_pir_p9; 1569 k->intc_create = pnv_chip_power9_intc_create; 1570 k->intc_reset = pnv_chip_power9_intc_reset; 1571 k->intc_destroy = pnv_chip_power9_intc_destroy; 1572 k->intc_print_info = pnv_chip_power9_intc_print_info; 1573 k->isa_create = pnv_chip_power9_isa_create; 1574 k->dt_populate = pnv_chip_power9_dt_populate; 1575 k->pic_print_info = pnv_chip_power9_pic_print_info; 1576 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1577 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1578 dc->desc = "PowerNV Chip POWER9"; 1579 k->num_pecs = PNV9_CHIP_MAX_PEC; 1580 1581 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1582 &k->parent_realize); 1583 } 1584 1585 static void pnv_chip_power10_instance_init(Object *obj) 1586 { 1587 PnvChip *chip = PNV_CHIP(obj); 1588 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1589 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1590 int i; 1591 1592 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1593 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1594 "xive-fabric"); 1595 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1596 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1597 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1598 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1599 1600 chip->num_pecs = pcc->num_pecs; 1601 1602 for (i = 0; i < chip->num_pecs; i++) { 1603 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1604 TYPE_PNV_PHB5_PEC); 1605 } 1606 } 1607 1608 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1609 { 1610 PnvChip *chip = PNV_CHIP(chip10); 1611 int i; 1612 1613 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1614 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1615 1616 for (i = 0; i < chip10->nr_quads; i++) { 1617 PnvQuad *eq = &chip10->quads[i]; 1618 1619 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1620 1621 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1622 &eq->xscom_regs); 1623 } 1624 } 1625 1626 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1627 { 1628 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1629 int i; 1630 1631 for (i = 0; i < chip->num_pecs; i++) { 1632 PnvPhb4PecState *pec = &chip10->pecs[i]; 1633 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1634 uint32_t pec_nest_base; 1635 uint32_t pec_pci_base; 1636 1637 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1638 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1639 &error_fatal); 1640 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1641 &error_fatal); 1642 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1643 return; 1644 } 1645 1646 pec_nest_base = pecc->xscom_nest_base(pec); 1647 pec_pci_base = pecc->xscom_pci_base(pec); 1648 1649 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1650 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1651 } 1652 } 1653 1654 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1655 { 1656 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1657 PnvChip *chip = PNV_CHIP(dev); 1658 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1659 Error *local_err = NULL; 1660 1661 /* XSCOM bridge is first */ 1662 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1663 if (local_err) { 1664 error_propagate(errp, local_err); 1665 return; 1666 } 1667 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1668 1669 pcc->parent_realize(dev, &local_err); 1670 if (local_err) { 1671 error_propagate(errp, local_err); 1672 return; 1673 } 1674 1675 pnv_chip_power10_quad_realize(chip10, &local_err); 1676 if (local_err) { 1677 error_propagate(errp, local_err); 1678 return; 1679 } 1680 1681 /* XIVE2 interrupt controller (POWER10) */ 1682 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1683 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1684 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1685 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1686 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1687 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1688 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1689 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1690 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1691 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1692 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1693 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1694 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1695 &error_abort); 1696 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1697 return; 1698 } 1699 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1700 &chip10->xive.xscom_regs); 1701 1702 /* Processor Service Interface (PSI) Host Bridge */ 1703 object_property_set_int(OBJECT(&chip10->psi), "bar", 1704 PNV10_PSIHB_BASE(chip), &error_fatal); 1705 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1706 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1707 &error_fatal); 1708 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1709 return; 1710 } 1711 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1712 &PNV_PSI(&chip10->psi)->xscom_regs); 1713 1714 /* LPC */ 1715 object_property_set_link(OBJECT(&chip10->lpc), "psi", 1716 OBJECT(&chip10->psi), &error_abort); 1717 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1718 return; 1719 } 1720 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1721 &chip10->lpc.xscom_regs); 1722 1723 chip->fw_mr = &chip10->lpc.isa_fw; 1724 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1725 (uint64_t) PNV10_LPCM_BASE(chip)); 1726 1727 /* Create the simplified OCC model */ 1728 object_property_set_link(OBJECT(&chip10->occ), "psi", OBJECT(&chip10->psi), 1729 &error_abort); 1730 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1731 return; 1732 } 1733 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1734 &chip10->occ.xscom_regs); 1735 1736 /* OCC SRAM model */ 1737 memory_region_add_subregion(get_system_memory(), 1738 PNV10_OCC_SENSOR_BASE(chip), 1739 &chip10->occ.sram_regs); 1740 1741 /* HOMER */ 1742 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1743 &error_abort); 1744 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1745 return; 1746 } 1747 /* Homer Xscom region */ 1748 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1749 &chip10->homer.pba_regs); 1750 1751 /* Homer mmio region */ 1752 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1753 &chip10->homer.regs); 1754 1755 /* PHBs */ 1756 pnv_chip_power10_phb_realize(chip, &local_err); 1757 if (local_err) { 1758 error_propagate(errp, local_err); 1759 return; 1760 } 1761 } 1762 1763 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1764 { 1765 addr &= (PNV10_XSCOM_SIZE - 1); 1766 return addr >> 3; 1767 } 1768 1769 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1770 { 1771 DeviceClass *dc = DEVICE_CLASS(klass); 1772 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1773 1774 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1775 k->cores_mask = POWER10_CORE_MASK; 1776 k->core_pir = pnv_chip_core_pir_p10; 1777 k->intc_create = pnv_chip_power10_intc_create; 1778 k->intc_reset = pnv_chip_power10_intc_reset; 1779 k->intc_destroy = pnv_chip_power10_intc_destroy; 1780 k->intc_print_info = pnv_chip_power10_intc_print_info; 1781 k->isa_create = pnv_chip_power10_isa_create; 1782 k->dt_populate = pnv_chip_power10_dt_populate; 1783 k->pic_print_info = pnv_chip_power10_pic_print_info; 1784 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1785 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1786 dc->desc = "PowerNV Chip POWER10"; 1787 k->num_pecs = PNV10_CHIP_MAX_PEC; 1788 1789 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1790 &k->parent_realize); 1791 } 1792 1793 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1794 { 1795 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1796 int cores_max; 1797 1798 /* 1799 * No custom mask for this chip, let's use the default one from * 1800 * the chip class 1801 */ 1802 if (!chip->cores_mask) { 1803 chip->cores_mask = pcc->cores_mask; 1804 } 1805 1806 /* filter alien core ids ! some are reserved */ 1807 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1808 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1809 chip->cores_mask); 1810 return; 1811 } 1812 chip->cores_mask &= pcc->cores_mask; 1813 1814 /* now that we have a sane layout, let check the number of cores */ 1815 cores_max = ctpop64(chip->cores_mask); 1816 if (chip->nr_cores > cores_max) { 1817 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1818 cores_max); 1819 return; 1820 } 1821 } 1822 1823 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1824 { 1825 Error *error = NULL; 1826 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1827 const char *typename = pnv_chip_core_typename(chip); 1828 int i, core_hwid; 1829 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1830 1831 if (!object_class_by_name(typename)) { 1832 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1833 return; 1834 } 1835 1836 /* Cores */ 1837 pnv_chip_core_sanitize(chip, &error); 1838 if (error) { 1839 error_propagate(errp, error); 1840 return; 1841 } 1842 1843 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1844 1845 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1846 && (i < chip->nr_cores); core_hwid++) { 1847 char core_name[32]; 1848 PnvCore *pnv_core; 1849 uint64_t xscom_core_base; 1850 1851 if (!(chip->cores_mask & (1ull << core_hwid))) { 1852 continue; 1853 } 1854 1855 pnv_core = PNV_CORE(object_new(typename)); 1856 1857 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1858 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1859 chip->cores[i] = pnv_core; 1860 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1861 chip->nr_threads, &error_fatal); 1862 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1863 core_hwid, &error_fatal); 1864 object_property_set_int(OBJECT(pnv_core), "pir", 1865 pcc->core_pir(chip, core_hwid), &error_fatal); 1866 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1867 &error_fatal); 1868 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1869 &error_abort); 1870 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1871 1872 /* Each core has an XSCOM MMIO region */ 1873 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1874 1875 pnv_xscom_add_subregion(chip, xscom_core_base, 1876 &pnv_core->xscom_regs); 1877 i++; 1878 } 1879 } 1880 1881 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1882 { 1883 PnvChip *chip = PNV_CHIP(dev); 1884 Error *error = NULL; 1885 1886 /* Cores */ 1887 pnv_chip_core_realize(chip, &error); 1888 if (error) { 1889 error_propagate(errp, error); 1890 return; 1891 } 1892 } 1893 1894 static Property pnv_chip_properties[] = { 1895 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1896 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1897 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1898 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1899 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1900 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1901 DEFINE_PROP_END_OF_LIST(), 1902 }; 1903 1904 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1905 { 1906 DeviceClass *dc = DEVICE_CLASS(klass); 1907 1908 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1909 dc->realize = pnv_chip_realize; 1910 device_class_set_props(dc, pnv_chip_properties); 1911 dc->desc = "PowerNV Chip"; 1912 } 1913 1914 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1915 { 1916 int i, j; 1917 1918 for (i = 0; i < chip->nr_cores; i++) { 1919 PnvCore *pc = chip->cores[i]; 1920 CPUCore *cc = CPU_CORE(pc); 1921 1922 for (j = 0; j < cc->nr_threads; j++) { 1923 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1924 return pc->threads[j]; 1925 } 1926 } 1927 } 1928 return NULL; 1929 } 1930 1931 typedef struct ForeachPhb3Args { 1932 int irq; 1933 ICSState *ics; 1934 } ForeachPhb3Args; 1935 1936 static int pnv_ics_get_child(Object *child, void *opaque) 1937 { 1938 ForeachPhb3Args *args = opaque; 1939 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); 1940 1941 if (phb3) { 1942 if (ics_valid_irq(&phb3->lsis, args->irq)) { 1943 args->ics = &phb3->lsis; 1944 } 1945 if (ics_valid_irq(ICS(&phb3->msis), args->irq)) { 1946 args->ics = ICS(&phb3->msis); 1947 } 1948 } 1949 return args->ics ? 1 : 0; 1950 } 1951 1952 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1953 { 1954 PnvMachineState *pnv = PNV_MACHINE(xi); 1955 ForeachPhb3Args args = { irq, NULL }; 1956 int i; 1957 1958 for (i = 0; i < pnv->num_chips; i++) { 1959 PnvChip *chip = pnv->chips[i]; 1960 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1961 1962 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1963 return &chip8->psi.ics; 1964 } 1965 1966 object_child_foreach(OBJECT(chip), pnv_ics_get_child, &args); 1967 if (args.ics) { 1968 return args.ics; 1969 } 1970 } 1971 return NULL; 1972 } 1973 1974 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 1975 { 1976 int i; 1977 1978 for (i = 0; i < pnv->num_chips; i++) { 1979 PnvChip *chip = pnv->chips[i]; 1980 if (chip->chip_id == chip_id) { 1981 return chip; 1982 } 1983 } 1984 return NULL; 1985 } 1986 1987 static int pnv_ics_resend_child(Object *child, void *opaque) 1988 { 1989 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); 1990 1991 if (phb3) { 1992 ics_resend(&phb3->lsis); 1993 ics_resend(ICS(&phb3->msis)); 1994 } 1995 return 0; 1996 } 1997 1998 static void pnv_ics_resend(XICSFabric *xi) 1999 { 2000 PnvMachineState *pnv = PNV_MACHINE(xi); 2001 int i; 2002 2003 for (i = 0; i < pnv->num_chips; i++) { 2004 PnvChip *chip = pnv->chips[i]; 2005 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2006 2007 ics_resend(&chip8->psi.ics); 2008 object_child_foreach(OBJECT(chip), pnv_ics_resend_child, NULL); 2009 } 2010 } 2011 2012 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2013 { 2014 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2015 2016 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2017 } 2018 2019 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2020 Monitor *mon) 2021 { 2022 PnvMachineState *pnv = PNV_MACHINE(obj); 2023 int i; 2024 CPUState *cs; 2025 2026 CPU_FOREACH(cs) { 2027 PowerPCCPU *cpu = POWERPC_CPU(cs); 2028 2029 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2030 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2031 mon); 2032 } 2033 2034 for (i = 0; i < pnv->num_chips; i++) { 2035 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2036 } 2037 } 2038 2039 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2040 uint8_t nvt_blk, uint32_t nvt_idx, 2041 bool cam_ignore, uint8_t priority, 2042 uint32_t logic_serv, 2043 XiveTCTXMatch *match) 2044 { 2045 PnvMachineState *pnv = PNV_MACHINE(xfb); 2046 int total_count = 0; 2047 int i; 2048 2049 for (i = 0; i < pnv->num_chips; i++) { 2050 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2051 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2052 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2053 int count; 2054 2055 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2056 priority, logic_serv, match); 2057 2058 if (count < 0) { 2059 return count; 2060 } 2061 2062 total_count += count; 2063 } 2064 2065 return total_count; 2066 } 2067 2068 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2069 uint8_t nvt_blk, uint32_t nvt_idx, 2070 bool cam_ignore, uint8_t priority, 2071 uint32_t logic_serv, 2072 XiveTCTXMatch *match) 2073 { 2074 PnvMachineState *pnv = PNV_MACHINE(xfb); 2075 int total_count = 0; 2076 int i; 2077 2078 for (i = 0; i < pnv->num_chips; i++) { 2079 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2080 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2081 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2082 int count; 2083 2084 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2085 priority, logic_serv, match); 2086 2087 if (count < 0) { 2088 return count; 2089 } 2090 2091 total_count += count; 2092 } 2093 2094 return total_count; 2095 } 2096 2097 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2098 { 2099 MachineClass *mc = MACHINE_CLASS(oc); 2100 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2101 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2102 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2103 2104 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2105 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2106 2107 xic->icp_get = pnv_icp_get; 2108 xic->ics_get = pnv_ics_get; 2109 xic->ics_resend = pnv_ics_resend; 2110 2111 pmc->compat = compat; 2112 pmc->compat_size = sizeof(compat); 2113 } 2114 2115 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2116 { 2117 MachineClass *mc = MACHINE_CLASS(oc); 2118 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2119 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2120 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2121 2122 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2123 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 2124 xfc->match_nvt = pnv_match_nvt; 2125 2126 mc->alias = "powernv"; 2127 2128 pmc->compat = compat; 2129 pmc->compat_size = sizeof(compat); 2130 pmc->dt_power_mgt = pnv_dt_power_mgt; 2131 } 2132 2133 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2134 { 2135 MachineClass *mc = MACHINE_CLASS(oc); 2136 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2137 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2138 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2139 2140 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2141 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2142 2143 pmc->compat = compat; 2144 pmc->compat_size = sizeof(compat); 2145 pmc->dt_power_mgt = pnv_dt_power_mgt; 2146 2147 xfc->match_nvt = pnv10_xive_match_nvt; 2148 } 2149 2150 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2151 { 2152 PnvMachineState *pnv = PNV_MACHINE(obj); 2153 2154 return !!pnv->fw_load_addr; 2155 } 2156 2157 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2158 { 2159 PnvMachineState *pnv = PNV_MACHINE(obj); 2160 2161 if (value) { 2162 pnv->fw_load_addr = 0x8000000; 2163 } 2164 } 2165 2166 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2167 { 2168 PowerPCCPU *cpu = POWERPC_CPU(cs); 2169 CPUPPCState *env = &cpu->env; 2170 2171 cpu_synchronize_state(cs); 2172 ppc_cpu_do_system_reset(cs); 2173 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2174 /* 2175 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2176 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2177 * (PPC_BIT(43)). 2178 */ 2179 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2180 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2181 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2182 } 2183 } else { 2184 /* 2185 * For non-powersave system resets, SRR1[42:45] are defined to be 2186 * implementation-dependent. The POWER9 User Manual specifies that 2187 * an external (SCOM driven, which may come from a BMC nmi command or 2188 * another CPU requesting a NMI IPI) system reset exception should be 2189 * 0b0010 (PPC_BIT(44)). 2190 */ 2191 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2192 } 2193 } 2194 2195 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2196 { 2197 CPUState *cs; 2198 2199 CPU_FOREACH(cs) { 2200 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2201 } 2202 } 2203 2204 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2205 { 2206 MachineClass *mc = MACHINE_CLASS(oc); 2207 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2208 NMIClass *nc = NMI_CLASS(oc); 2209 2210 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2211 mc->init = pnv_init; 2212 mc->reset = pnv_reset; 2213 mc->max_cpus = MAX_CPUS; 2214 /* Pnv provides a AHCI device for storage */ 2215 mc->block_default_type = IF_IDE; 2216 mc->no_parallel = 1; 2217 mc->default_boot_order = NULL; 2218 /* 2219 * RAM defaults to less than 2048 for 32-bit hosts, and large 2220 * enough to fit the maximum initrd size at it's load address 2221 */ 2222 mc->default_ram_size = 1 * GiB; 2223 mc->default_ram_id = "pnv.ram"; 2224 ispc->print_info = pnv_pic_print_info; 2225 nc->nmi_monitor_handler = pnv_nmi; 2226 2227 object_class_property_add_bool(oc, "hb-mode", 2228 pnv_machine_get_hb, pnv_machine_set_hb); 2229 object_class_property_set_description(oc, "hb-mode", 2230 "Use a hostboot like boot loader"); 2231 } 2232 2233 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2234 { \ 2235 .name = type, \ 2236 .class_init = class_initfn, \ 2237 .parent = TYPE_PNV8_CHIP, \ 2238 } 2239 2240 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2241 { \ 2242 .name = type, \ 2243 .class_init = class_initfn, \ 2244 .parent = TYPE_PNV9_CHIP, \ 2245 } 2246 2247 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2248 { \ 2249 .name = type, \ 2250 .class_init = class_initfn, \ 2251 .parent = TYPE_PNV10_CHIP, \ 2252 } 2253 2254 static const TypeInfo types[] = { 2255 { 2256 .name = MACHINE_TYPE_NAME("powernv10"), 2257 .parent = TYPE_PNV_MACHINE, 2258 .class_init = pnv_machine_power10_class_init, 2259 .interfaces = (InterfaceInfo[]) { 2260 { TYPE_XIVE_FABRIC }, 2261 { }, 2262 }, 2263 }, 2264 { 2265 .name = MACHINE_TYPE_NAME("powernv9"), 2266 .parent = TYPE_PNV_MACHINE, 2267 .class_init = pnv_machine_power9_class_init, 2268 .interfaces = (InterfaceInfo[]) { 2269 { TYPE_XIVE_FABRIC }, 2270 { }, 2271 }, 2272 }, 2273 { 2274 .name = MACHINE_TYPE_NAME("powernv8"), 2275 .parent = TYPE_PNV_MACHINE, 2276 .class_init = pnv_machine_power8_class_init, 2277 .interfaces = (InterfaceInfo[]) { 2278 { TYPE_XICS_FABRIC }, 2279 { }, 2280 }, 2281 }, 2282 { 2283 .name = TYPE_PNV_MACHINE, 2284 .parent = TYPE_MACHINE, 2285 .abstract = true, 2286 .instance_size = sizeof(PnvMachineState), 2287 .class_init = pnv_machine_class_init, 2288 .class_size = sizeof(PnvMachineClass), 2289 .interfaces = (InterfaceInfo[]) { 2290 { TYPE_INTERRUPT_STATS_PROVIDER }, 2291 { TYPE_NMI }, 2292 { }, 2293 }, 2294 }, 2295 { 2296 .name = TYPE_PNV_CHIP, 2297 .parent = TYPE_SYS_BUS_DEVICE, 2298 .class_init = pnv_chip_class_init, 2299 .instance_size = sizeof(PnvChip), 2300 .class_size = sizeof(PnvChipClass), 2301 .abstract = true, 2302 }, 2303 2304 /* 2305 * P10 chip and variants 2306 */ 2307 { 2308 .name = TYPE_PNV10_CHIP, 2309 .parent = TYPE_PNV_CHIP, 2310 .instance_init = pnv_chip_power10_instance_init, 2311 .instance_size = sizeof(Pnv10Chip), 2312 }, 2313 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2314 2315 /* 2316 * P9 chip and variants 2317 */ 2318 { 2319 .name = TYPE_PNV9_CHIP, 2320 .parent = TYPE_PNV_CHIP, 2321 .instance_init = pnv_chip_power9_instance_init, 2322 .instance_size = sizeof(Pnv9Chip), 2323 }, 2324 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2325 2326 /* 2327 * P8 chip and variants 2328 */ 2329 { 2330 .name = TYPE_PNV8_CHIP, 2331 .parent = TYPE_PNV_CHIP, 2332 .instance_init = pnv_chip_power8_instance_init, 2333 .instance_size = sizeof(Pnv8Chip), 2334 }, 2335 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2336 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2337 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2338 pnv_chip_power8nvl_class_init), 2339 }; 2340 2341 DEFINE_TYPES(types) 2342