1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qapi/error.h" 23 #include "sysemu/sysemu.h" 24 #include "sysemu/numa.h" 25 #include "sysemu/cpus.h" 26 #include "hw/hw.h" 27 #include "target/ppc/cpu.h" 28 #include "qemu/log.h" 29 #include "hw/ppc/fdt.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/ppc/pnv.h" 32 #include "hw/ppc/pnv_core.h" 33 #include "hw/loader.h" 34 #include "exec/address-spaces.h" 35 #include "qapi/visitor.h" 36 #include "monitor/monitor.h" 37 #include "hw/intc/intc.h" 38 #include "hw/ipmi/ipmi.h" 39 #include "target/ppc/mmu-hash64.h" 40 41 #include "hw/ppc/xics.h" 42 #include "hw/ppc/pnv_xscom.h" 43 44 #include "hw/isa/isa.h" 45 #include "hw/char/serial.h" 46 #include "hw/timer/mc146818rtc.h" 47 48 #include <libfdt.h> 49 50 #define FDT_MAX_SIZE (1 * MiB) 51 52 #define FW_FILE_NAME "skiboot.lid" 53 #define FW_LOAD_ADDR 0x0 54 #define FW_MAX_SIZE (4 * MiB) 55 56 #define KERNEL_LOAD_ADDR 0x20000000 57 #define KERNEL_MAX_SIZE (256 * MiB) 58 #define INITRD_LOAD_ADDR 0x60000000 59 #define INITRD_MAX_SIZE (256 * MiB) 60 61 static const char *pnv_chip_core_typename(const PnvChip *o) 62 { 63 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 64 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 65 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 66 const char *core_type = object_class_get_name(object_class_by_name(s)); 67 g_free(s); 68 return core_type; 69 } 70 71 /* 72 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 73 * 4 * 4 sockets * 12 cores * 8 threads = 1536 74 * Let's make it 2^11 75 */ 76 #define MAX_CPUS 2048 77 78 /* 79 * Memory nodes are created by hostboot, one for each range of memory 80 * that has a different "affinity". In practice, it means one range 81 * per chip. 82 */ 83 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 84 { 85 char *mem_name; 86 uint64_t mem_reg_property[2]; 87 int off; 88 89 mem_reg_property[0] = cpu_to_be64(start); 90 mem_reg_property[1] = cpu_to_be64(size); 91 92 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 93 off = fdt_add_subnode(fdt, 0, mem_name); 94 g_free(mem_name); 95 96 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 97 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 98 sizeof(mem_reg_property)))); 99 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 100 } 101 102 static int get_cpus_node(void *fdt) 103 { 104 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 105 106 if (cpus_offset < 0) { 107 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 108 if (cpus_offset) { 109 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 110 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 111 } 112 } 113 _FDT(cpus_offset); 114 return cpus_offset; 115 } 116 117 /* 118 * The PowerNV cores (and threads) need to use real HW ids and not an 119 * incremental index like it has been done on other platforms. This HW 120 * id is stored in the CPU PIR, it is used to create cpu nodes in the 121 * device tree, used in XSCOM to address cores and in interrupt 122 * servers. 123 */ 124 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 125 { 126 PowerPCCPU *cpu = pc->threads[0]; 127 CPUState *cs = CPU(cpu); 128 DeviceClass *dc = DEVICE_GET_CLASS(cs); 129 int smt_threads = CPU_CORE(pc)->nr_threads; 130 CPUPPCState *env = &cpu->env; 131 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 132 uint32_t servers_prop[smt_threads]; 133 int i; 134 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 135 0xffffffff, 0xffffffff}; 136 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 137 uint32_t cpufreq = 1000000000; 138 uint32_t page_sizes_prop[64]; 139 size_t page_sizes_prop_size; 140 const uint8_t pa_features[] = { 24, 0, 141 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 142 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 143 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 144 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 145 int offset; 146 char *nodename; 147 int cpus_offset = get_cpus_node(fdt); 148 149 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 150 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 151 _FDT(offset); 152 g_free(nodename); 153 154 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 155 156 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 157 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 158 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 159 160 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 161 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 162 env->dcache_line_size))); 163 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 164 env->dcache_line_size))); 165 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 166 env->icache_line_size))); 167 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 168 env->icache_line_size))); 169 170 if (pcc->l1_dcache_size) { 171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 172 pcc->l1_dcache_size))); 173 } else { 174 warn_report("Unknown L1 dcache size for cpu"); 175 } 176 if (pcc->l1_icache_size) { 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 178 pcc->l1_icache_size))); 179 } else { 180 warn_report("Unknown L1 icache size for cpu"); 181 } 182 183 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 184 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 185 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 186 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 187 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 188 189 if (env->spr_cb[SPR_PURR].oea_read) { 190 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 191 } 192 193 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 194 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 195 segs, sizeof(segs)))); 196 } 197 198 /* Advertise VMX/VSX (vector extensions) if available 199 * 0 / no property == no vector extensions 200 * 1 == VMX / Altivec available 201 * 2 == VSX available */ 202 if (env->insns_flags & PPC_ALTIVEC) { 203 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 204 205 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 206 } 207 208 /* Advertise DFP (Decimal Floating Point) if available 209 * 0 / no property == no DFP 210 * 1 == DFP available */ 211 if (env->insns_flags2 & PPC2_DFP) { 212 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 213 } 214 215 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 216 sizeof(page_sizes_prop)); 217 if (page_sizes_prop_size) { 218 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 219 page_sizes_prop, page_sizes_prop_size))); 220 } 221 222 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 223 pa_features, sizeof(pa_features)))); 224 225 /* Build interrupt servers properties */ 226 for (i = 0; i < smt_threads; i++) { 227 servers_prop[i] = cpu_to_be32(pc->pir + i); 228 } 229 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 230 servers_prop, sizeof(servers_prop)))); 231 } 232 233 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 234 uint32_t nr_threads) 235 { 236 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 237 char *name; 238 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 239 uint32_t irange[2], i, rsize; 240 uint64_t *reg; 241 int offset; 242 243 irange[0] = cpu_to_be32(pir); 244 irange[1] = cpu_to_be32(nr_threads); 245 246 rsize = sizeof(uint64_t) * 2 * nr_threads; 247 reg = g_malloc(rsize); 248 for (i = 0; i < nr_threads; i++) { 249 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 250 reg[i * 2 + 1] = cpu_to_be64(0x1000); 251 } 252 253 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 254 offset = fdt_add_subnode(fdt, 0, name); 255 _FDT(offset); 256 g_free(name); 257 258 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 259 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 260 _FDT((fdt_setprop_string(fdt, offset, "device_type", 261 "PowerPC-External-Interrupt-Presentation"))); 262 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 263 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 264 irange, sizeof(irange)))); 265 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 266 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 267 g_free(reg); 268 } 269 270 static void pnv_dt_chip(PnvChip *chip, void *fdt) 271 { 272 const char *typename = pnv_chip_core_typename(chip); 273 size_t typesize = object_type_get_instance_size(typename); 274 int i; 275 276 pnv_dt_xscom(chip, fdt, 0); 277 278 for (i = 0; i < chip->nr_cores; i++) { 279 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 280 281 pnv_dt_core(chip, pnv_core, fdt); 282 283 /* Interrupt Control Presenters (ICP). One per core. */ 284 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 285 } 286 287 if (chip->ram_size) { 288 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 289 } 290 } 291 292 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 293 { 294 uint32_t io_base = d->ioport_id; 295 uint32_t io_regs[] = { 296 cpu_to_be32(1), 297 cpu_to_be32(io_base), 298 cpu_to_be32(2) 299 }; 300 char *name; 301 int node; 302 303 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 304 node = fdt_add_subnode(fdt, lpc_off, name); 305 _FDT(node); 306 g_free(name); 307 308 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 309 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 310 } 311 312 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 313 { 314 const char compatible[] = "ns16550\0pnpPNP,501"; 315 uint32_t io_base = d->ioport_id; 316 uint32_t io_regs[] = { 317 cpu_to_be32(1), 318 cpu_to_be32(io_base), 319 cpu_to_be32(8) 320 }; 321 char *name; 322 int node; 323 324 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 325 node = fdt_add_subnode(fdt, lpc_off, name); 326 _FDT(node); 327 g_free(name); 328 329 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 330 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 331 sizeof(compatible)))); 332 333 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 334 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 335 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 336 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 337 fdt_get_phandle(fdt, lpc_off)))); 338 339 /* This is needed by Linux */ 340 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 341 } 342 343 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 344 { 345 const char compatible[] = "bt\0ipmi-bt"; 346 uint32_t io_base; 347 uint32_t io_regs[] = { 348 cpu_to_be32(1), 349 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 350 cpu_to_be32(3) 351 }; 352 uint32_t irq; 353 char *name; 354 int node; 355 356 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 357 io_regs[1] = cpu_to_be32(io_base); 358 359 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 360 361 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 362 node = fdt_add_subnode(fdt, lpc_off, name); 363 _FDT(node); 364 g_free(name); 365 366 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 367 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 368 sizeof(compatible)))); 369 370 /* Mark it as reserved to avoid Linux trying to claim it */ 371 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 372 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 373 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 374 fdt_get_phandle(fdt, lpc_off)))); 375 } 376 377 typedef struct ForeachPopulateArgs { 378 void *fdt; 379 int offset; 380 } ForeachPopulateArgs; 381 382 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 383 { 384 ForeachPopulateArgs *args = opaque; 385 ISADevice *d = ISA_DEVICE(dev); 386 387 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 388 pnv_dt_rtc(d, args->fdt, args->offset); 389 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 390 pnv_dt_serial(d, args->fdt, args->offset); 391 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 392 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 393 } else { 394 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 395 d->ioport_id); 396 } 397 398 return 0; 399 } 400 401 static int pnv_chip_isa_offset(PnvChip *chip, void *fdt) 402 { 403 char *name; 404 int offset; 405 406 name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 407 (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE); 408 offset = fdt_path_offset(fdt, name); 409 g_free(name); 410 return offset; 411 } 412 413 /* The default LPC bus of a multichip system is on chip 0. It's 414 * recognized by the firmware (skiboot) using a "primary" property. 415 */ 416 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 417 { 418 int isa_offset = pnv_chip_isa_offset(pnv->chips[0], fdt); 419 ForeachPopulateArgs args = { 420 .fdt = fdt, 421 .offset = isa_offset, 422 }; 423 424 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 425 426 /* ISA devices are not necessarily parented to the ISA bus so we 427 * can not use object_child_foreach() */ 428 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 429 &args); 430 } 431 432 static void *pnv_dt_create(MachineState *machine) 433 { 434 const char plat_compat[] = "qemu,powernv\0ibm,powernv"; 435 PnvMachineState *pnv = PNV_MACHINE(machine); 436 void *fdt; 437 char *buf; 438 int off; 439 int i; 440 441 fdt = g_malloc0(FDT_MAX_SIZE); 442 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 443 444 /* Root node */ 445 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 446 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 447 _FDT((fdt_setprop_string(fdt, 0, "model", 448 "IBM PowerNV (emulated by qemu)"))); 449 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat, 450 sizeof(plat_compat)))); 451 452 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 453 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 454 if (qemu_uuid_set) { 455 _FDT((fdt_property_string(fdt, "system-id", buf))); 456 } 457 g_free(buf); 458 459 off = fdt_add_subnode(fdt, 0, "chosen"); 460 if (machine->kernel_cmdline) { 461 _FDT((fdt_setprop_string(fdt, off, "bootargs", 462 machine->kernel_cmdline))); 463 } 464 465 if (pnv->initrd_size) { 466 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 467 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 468 469 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 470 &start_prop, sizeof(start_prop)))); 471 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 472 &end_prop, sizeof(end_prop)))); 473 } 474 475 /* Populate device tree for each chip */ 476 for (i = 0; i < pnv->num_chips; i++) { 477 pnv_dt_chip(pnv->chips[i], fdt); 478 } 479 480 /* Populate ISA devices on chip 0 */ 481 pnv_dt_isa(pnv, fdt); 482 483 if (pnv->bmc) { 484 pnv_dt_bmc_sensors(pnv->bmc, fdt); 485 } 486 487 return fdt; 488 } 489 490 static void pnv_powerdown_notify(Notifier *n, void *opaque) 491 { 492 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 493 494 if (pnv->bmc) { 495 pnv_bmc_powerdown(pnv->bmc); 496 } 497 } 498 499 static void pnv_reset(void) 500 { 501 MachineState *machine = MACHINE(qdev_get_machine()); 502 PnvMachineState *pnv = PNV_MACHINE(machine); 503 void *fdt; 504 Object *obj; 505 506 qemu_devices_reset(); 507 508 /* OpenPOWER systems have a BMC, which can be defined on the 509 * command line with: 510 * 511 * -device ipmi-bmc-sim,id=bmc0 512 * 513 * This is the internal simulator but it could also be an external 514 * BMC. 515 */ 516 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); 517 if (obj) { 518 pnv->bmc = IPMI_BMC(obj); 519 } 520 521 fdt = pnv_dt_create(machine); 522 523 /* Pack resulting tree */ 524 _FDT((fdt_pack(fdt))); 525 526 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 527 } 528 529 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 530 { 531 Pnv8Chip *chip8 = PNV8_CHIP(chip); 532 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 533 } 534 535 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 536 { 537 Pnv8Chip *chip8 = PNV8_CHIP(chip); 538 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 539 } 540 541 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 542 { 543 return NULL; 544 } 545 546 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 547 { 548 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 549 } 550 551 static void pnv_init(MachineState *machine) 552 { 553 PnvMachineState *pnv = PNV_MACHINE(machine); 554 MemoryRegion *ram; 555 char *fw_filename; 556 long fw_size; 557 int i; 558 char *chip_typename; 559 560 /* allocate RAM */ 561 if (machine->ram_size < (1 * GiB)) { 562 warn_report("skiboot may not work with < 1GB of RAM"); 563 } 564 565 ram = g_new(MemoryRegion, 1); 566 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 567 machine->ram_size); 568 memory_region_add_subregion(get_system_memory(), 0, ram); 569 570 /* load skiboot firmware */ 571 if (bios_name == NULL) { 572 bios_name = FW_FILE_NAME; 573 } 574 575 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 576 if (!fw_filename) { 577 error_report("Could not find OPAL firmware '%s'", bios_name); 578 exit(1); 579 } 580 581 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 582 if (fw_size < 0) { 583 error_report("Could not load OPAL firmware '%s'", fw_filename); 584 exit(1); 585 } 586 g_free(fw_filename); 587 588 /* load kernel */ 589 if (machine->kernel_filename) { 590 long kernel_size; 591 592 kernel_size = load_image_targphys(machine->kernel_filename, 593 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 594 if (kernel_size < 0) { 595 error_report("Could not load kernel '%s'", 596 machine->kernel_filename); 597 exit(1); 598 } 599 } 600 601 /* load initrd */ 602 if (machine->initrd_filename) { 603 pnv->initrd_base = INITRD_LOAD_ADDR; 604 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 605 pnv->initrd_base, INITRD_MAX_SIZE); 606 if (pnv->initrd_size < 0) { 607 error_report("Could not load initial ram disk '%s'", 608 machine->initrd_filename); 609 exit(1); 610 } 611 } 612 613 /* Create the processor chips */ 614 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 615 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 616 i, machine->cpu_type); 617 if (!object_class_by_name(chip_typename)) { 618 error_report("invalid CPU model '%.*s' for %s machine", 619 i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name); 620 exit(1); 621 } 622 623 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 624 for (i = 0; i < pnv->num_chips; i++) { 625 char chip_name[32]; 626 Object *chip = object_new(chip_typename); 627 628 pnv->chips[i] = PNV_CHIP(chip); 629 630 /* TODO: put all the memory in one node on chip 0 until we find a 631 * way to specify different ranges for each chip 632 */ 633 if (i == 0) { 634 object_property_set_int(chip, machine->ram_size, "ram-size", 635 &error_fatal); 636 } 637 638 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 639 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 640 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 641 &error_fatal); 642 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal); 643 object_property_set_bool(chip, true, "realized", &error_fatal); 644 } 645 g_free(chip_typename); 646 647 /* Instantiate ISA bus on chip 0 */ 648 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 649 650 /* Create serial port */ 651 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 652 653 /* Create an RTC ISA device too */ 654 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 655 656 /* OpenPOWER systems use a IPMI SEL Event message to notify the 657 * host to powerdown */ 658 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 659 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 660 } 661 662 /* 663 * 0:21 Reserved - Read as zeros 664 * 22:24 Chip ID 665 * 25:28 Core number 666 * 29:31 Thread ID 667 */ 668 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 669 { 670 return (chip->chip_id << 7) | (core_id << 3); 671 } 672 673 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 674 Error **errp) 675 { 676 Error *local_err = NULL; 677 Object *obj; 678 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 679 680 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 681 &local_err); 682 if (local_err) { 683 error_propagate(errp, local_err); 684 return; 685 } 686 687 pnv_cpu->icp = ICP(obj); 688 } 689 690 /* 691 * 0:48 Reserved - Read as zeroes 692 * 49:52 Node ID 693 * 53:55 Chip ID 694 * 56 Reserved - Read as zero 695 * 57:61 Core number 696 * 62:63 Thread ID 697 * 698 * We only care about the lower bits. uint32_t is fine for the moment. 699 */ 700 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 701 { 702 return (chip->chip_id << 8) | (core_id << 2); 703 } 704 705 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 706 Error **errp) 707 { 708 return; 709 } 710 711 /* Allowed core identifiers on a POWER8 Processor Chip : 712 * 713 * <EX0 reserved> 714 * EX1 - Venice only 715 * EX2 - Venice only 716 * EX3 - Venice only 717 * EX4 718 * EX5 719 * EX6 720 * <EX7,8 reserved> <reserved> 721 * EX9 - Venice only 722 * EX10 - Venice only 723 * EX11 - Venice only 724 * EX12 725 * EX13 726 * EX14 727 * <EX15 reserved> 728 */ 729 #define POWER8E_CORE_MASK (0x7070ull) 730 #define POWER8_CORE_MASK (0x7e7eull) 731 732 /* 733 * POWER9 has 24 cores, ids starting at 0x0 734 */ 735 #define POWER9_CORE_MASK (0xffffffffffffffull) 736 737 static void pnv_chip_power8_instance_init(Object *obj) 738 { 739 Pnv8Chip *chip8 = PNV8_CHIP(obj); 740 741 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 742 TYPE_PNV_PSI, &error_abort, NULL); 743 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 744 OBJECT(qdev_get_machine()), &error_abort); 745 746 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 747 TYPE_PNV_LPC, &error_abort, NULL); 748 object_property_add_const_link(OBJECT(&chip8->lpc), "psi", 749 OBJECT(&chip8->psi), &error_abort); 750 751 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 752 TYPE_PNV_OCC, &error_abort, NULL); 753 object_property_add_const_link(OBJECT(&chip8->occ), "psi", 754 OBJECT(&chip8->psi), &error_abort); 755 } 756 757 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 758 { 759 PnvChip *chip = PNV_CHIP(chip8); 760 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 761 const char *typename = pnv_chip_core_typename(chip); 762 size_t typesize = object_type_get_instance_size(typename); 763 int i, j; 764 char *name; 765 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 766 767 name = g_strdup_printf("icp-%x", chip->chip_id); 768 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 769 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 770 g_free(name); 771 772 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 773 774 /* Map the ICP registers for each thread */ 775 for (i = 0; i < chip->nr_cores; i++) { 776 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 777 int core_hwid = CPU_CORE(pnv_core)->core_id; 778 779 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 780 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 781 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 782 783 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 784 &icp->mmio); 785 } 786 } 787 } 788 789 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 790 { 791 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 792 PnvChip *chip = PNV_CHIP(dev); 793 Pnv8Chip *chip8 = PNV8_CHIP(dev); 794 Error *local_err = NULL; 795 796 pcc->parent_realize(dev, &local_err); 797 if (local_err) { 798 error_propagate(errp, local_err); 799 return; 800 } 801 802 /* Processor Service Interface (PSI) Host Bridge */ 803 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 804 "bar", &error_fatal); 805 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 806 if (local_err) { 807 error_propagate(errp, local_err); 808 return; 809 } 810 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip8->psi.xscom_regs); 811 812 /* Create LPC controller */ 813 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 814 &error_fatal); 815 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 816 817 /* Interrupt Management Area. This is the memory region holding 818 * all the Interrupt Control Presenter (ICP) registers */ 819 pnv_chip_icp_realize(chip8, &local_err); 820 if (local_err) { 821 error_propagate(errp, local_err); 822 return; 823 } 824 825 /* Create the simplified OCC model */ 826 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 827 if (local_err) { 828 error_propagate(errp, local_err); 829 return; 830 } 831 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 832 } 833 834 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 835 { 836 DeviceClass *dc = DEVICE_CLASS(klass); 837 PnvChipClass *k = PNV_CHIP_CLASS(klass); 838 839 k->chip_type = PNV_CHIP_POWER8E; 840 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 841 k->cores_mask = POWER8E_CORE_MASK; 842 k->core_pir = pnv_chip_core_pir_p8; 843 k->intc_create = pnv_chip_power8_intc_create; 844 k->isa_create = pnv_chip_power8_isa_create; 845 k->xscom_base = 0x003fc0000000000ull; 846 dc->desc = "PowerNV Chip POWER8E"; 847 848 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 849 &k->parent_realize); 850 } 851 852 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 853 { 854 DeviceClass *dc = DEVICE_CLASS(klass); 855 PnvChipClass *k = PNV_CHIP_CLASS(klass); 856 857 k->chip_type = PNV_CHIP_POWER8; 858 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 859 k->cores_mask = POWER8_CORE_MASK; 860 k->core_pir = pnv_chip_core_pir_p8; 861 k->intc_create = pnv_chip_power8_intc_create; 862 k->isa_create = pnv_chip_power8_isa_create; 863 k->xscom_base = 0x003fc0000000000ull; 864 dc->desc = "PowerNV Chip POWER8"; 865 866 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 867 &k->parent_realize); 868 } 869 870 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 871 { 872 DeviceClass *dc = DEVICE_CLASS(klass); 873 PnvChipClass *k = PNV_CHIP_CLASS(klass); 874 875 k->chip_type = PNV_CHIP_POWER8NVL; 876 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 877 k->cores_mask = POWER8_CORE_MASK; 878 k->core_pir = pnv_chip_core_pir_p8; 879 k->intc_create = pnv_chip_power8_intc_create; 880 k->isa_create = pnv_chip_power8nvl_isa_create; 881 k->xscom_base = 0x003fc0000000000ull; 882 dc->desc = "PowerNV Chip POWER8NVL"; 883 884 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 885 &k->parent_realize); 886 } 887 888 static void pnv_chip_power9_instance_init(Object *obj) 889 { 890 } 891 892 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 893 { 894 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 895 Error *local_err = NULL; 896 897 pcc->parent_realize(dev, &local_err); 898 if (local_err) { 899 error_propagate(errp, local_err); 900 return; 901 } 902 } 903 904 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 905 { 906 DeviceClass *dc = DEVICE_CLASS(klass); 907 PnvChipClass *k = PNV_CHIP_CLASS(klass); 908 909 k->chip_type = PNV_CHIP_POWER9; 910 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 911 k->cores_mask = POWER9_CORE_MASK; 912 k->core_pir = pnv_chip_core_pir_p9; 913 k->intc_create = pnv_chip_power9_intc_create; 914 k->isa_create = pnv_chip_power9_isa_create; 915 k->xscom_base = 0x00603fc00000000ull; 916 dc->desc = "PowerNV Chip POWER9"; 917 918 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 919 &k->parent_realize); 920 } 921 922 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 923 { 924 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 925 int cores_max; 926 927 /* 928 * No custom mask for this chip, let's use the default one from * 929 * the chip class 930 */ 931 if (!chip->cores_mask) { 932 chip->cores_mask = pcc->cores_mask; 933 } 934 935 /* filter alien core ids ! some are reserved */ 936 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 937 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 938 chip->cores_mask); 939 return; 940 } 941 chip->cores_mask &= pcc->cores_mask; 942 943 /* now that we have a sane layout, let check the number of cores */ 944 cores_max = ctpop64(chip->cores_mask); 945 if (chip->nr_cores > cores_max) { 946 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 947 cores_max); 948 return; 949 } 950 } 951 952 static void pnv_chip_instance_init(Object *obj) 953 { 954 PNV_CHIP(obj)->xscom_base = PNV_CHIP_GET_CLASS(obj)->xscom_base; 955 } 956 957 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 958 { 959 Error *error = NULL; 960 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 961 const char *typename = pnv_chip_core_typename(chip); 962 size_t typesize = object_type_get_instance_size(typename); 963 int i, core_hwid; 964 965 if (!object_class_by_name(typename)) { 966 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 967 return; 968 } 969 970 /* Cores */ 971 pnv_chip_core_sanitize(chip, &error); 972 if (error) { 973 error_propagate(errp, error); 974 return; 975 } 976 977 chip->cores = g_malloc0(typesize * chip->nr_cores); 978 979 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 980 && (i < chip->nr_cores); core_hwid++) { 981 char core_name[32]; 982 void *pnv_core = chip->cores + i * typesize; 983 uint64_t xscom_core_base; 984 985 if (!(chip->cores_mask & (1ull << core_hwid))) { 986 continue; 987 } 988 989 object_initialize(pnv_core, typesize, typename); 990 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 991 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 992 &error_fatal); 993 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads", 994 &error_fatal); 995 object_property_set_int(OBJECT(pnv_core), core_hwid, 996 CPU_CORE_PROP_CORE_ID, &error_fatal); 997 object_property_set_int(OBJECT(pnv_core), 998 pcc->core_pir(chip, core_hwid), 999 "pir", &error_fatal); 1000 object_property_add_const_link(OBJECT(pnv_core), "chip", 1001 OBJECT(chip), &error_fatal); 1002 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1003 &error_fatal); 1004 object_unref(OBJECT(pnv_core)); 1005 1006 /* Each core has an XSCOM MMIO region */ 1007 if (!pnv_chip_is_power9(chip)) { 1008 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); 1009 } else { 1010 xscom_core_base = PNV_XSCOM_P9_EC_BASE(core_hwid); 1011 } 1012 1013 pnv_xscom_add_subregion(chip, xscom_core_base, 1014 &PNV_CORE(pnv_core)->xscom_regs); 1015 i++; 1016 } 1017 } 1018 1019 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1020 { 1021 PnvChip *chip = PNV_CHIP(dev); 1022 Error *error = NULL; 1023 1024 /* XSCOM bridge */ 1025 pnv_xscom_realize(chip, &error); 1026 if (error) { 1027 error_propagate(errp, error); 1028 return; 1029 } 1030 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1031 1032 /* Cores */ 1033 pnv_chip_core_realize(chip, &error); 1034 if (error) { 1035 error_propagate(errp, error); 1036 return; 1037 } 1038 } 1039 1040 static Property pnv_chip_properties[] = { 1041 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1042 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1043 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1044 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1045 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1046 DEFINE_PROP_END_OF_LIST(), 1047 }; 1048 1049 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1050 { 1051 DeviceClass *dc = DEVICE_CLASS(klass); 1052 1053 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1054 dc->realize = pnv_chip_realize; 1055 dc->props = pnv_chip_properties; 1056 dc->desc = "PowerNV Chip"; 1057 } 1058 1059 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1060 { 1061 PnvMachineState *pnv = PNV_MACHINE(xi); 1062 int i; 1063 1064 for (i = 0; i < pnv->num_chips; i++) { 1065 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1066 1067 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1068 return &chip8->psi.ics; 1069 } 1070 } 1071 return NULL; 1072 } 1073 1074 static void pnv_ics_resend(XICSFabric *xi) 1075 { 1076 PnvMachineState *pnv = PNV_MACHINE(xi); 1077 int i; 1078 1079 for (i = 0; i < pnv->num_chips; i++) { 1080 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1081 ics_resend(&chip8->psi.ics); 1082 } 1083 } 1084 1085 static PowerPCCPU *ppc_get_vcpu_by_pir(int pir) 1086 { 1087 CPUState *cs; 1088 1089 CPU_FOREACH(cs) { 1090 PowerPCCPU *cpu = POWERPC_CPU(cs); 1091 CPUPPCState *env = &cpu->env; 1092 1093 if (env->spr_cb[SPR_PIR].default_value == pir) { 1094 return cpu; 1095 } 1096 } 1097 1098 return NULL; 1099 } 1100 1101 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1102 { 1103 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1104 1105 return cpu ? pnv_cpu_state(cpu)->icp : NULL; 1106 } 1107 1108 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1109 Monitor *mon) 1110 { 1111 PnvMachineState *pnv = PNV_MACHINE(obj); 1112 int i; 1113 CPUState *cs; 1114 1115 CPU_FOREACH(cs) { 1116 PowerPCCPU *cpu = POWERPC_CPU(cs); 1117 1118 icp_pic_print_info(pnv_cpu_state(cpu)->icp, mon); 1119 } 1120 1121 for (i = 0; i < pnv->num_chips; i++) { 1122 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1123 ics_pic_print_info(&chip8->psi.ics, mon); 1124 } 1125 } 1126 1127 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1128 void *opaque, Error **errp) 1129 { 1130 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1131 } 1132 1133 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1134 void *opaque, Error **errp) 1135 { 1136 PnvMachineState *pnv = PNV_MACHINE(obj); 1137 uint32_t num_chips; 1138 Error *local_err = NULL; 1139 1140 visit_type_uint32(v, name, &num_chips, &local_err); 1141 if (local_err) { 1142 error_propagate(errp, local_err); 1143 return; 1144 } 1145 1146 /* 1147 * TODO: should we decide on how many chips we can create based 1148 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1149 */ 1150 if (!is_power_of_2(num_chips) || num_chips > 4) { 1151 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1152 return; 1153 } 1154 1155 pnv->num_chips = num_chips; 1156 } 1157 1158 static void pnv_machine_instance_init(Object *obj) 1159 { 1160 PnvMachineState *pnv = PNV_MACHINE(obj); 1161 pnv->num_chips = 1; 1162 } 1163 1164 static void pnv_machine_class_props_init(ObjectClass *oc) 1165 { 1166 object_class_property_add(oc, "num-chips", "uint32", 1167 pnv_get_num_chips, pnv_set_num_chips, 1168 NULL, NULL, NULL); 1169 object_class_property_set_description(oc, "num-chips", 1170 "Specifies the number of processor chips", 1171 NULL); 1172 } 1173 1174 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1175 { 1176 MachineClass *mc = MACHINE_CLASS(oc); 1177 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1178 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1179 1180 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1181 mc->init = pnv_init; 1182 mc->reset = pnv_reset; 1183 mc->max_cpus = MAX_CPUS; 1184 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1185 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for 1186 * storage */ 1187 mc->no_parallel = 1; 1188 mc->default_boot_order = NULL; 1189 mc->default_ram_size = 1 * GiB; 1190 xic->icp_get = pnv_icp_get; 1191 xic->ics_get = pnv_ics_get; 1192 xic->ics_resend = pnv_ics_resend; 1193 ispc->print_info = pnv_pic_print_info; 1194 1195 pnv_machine_class_props_init(oc); 1196 } 1197 1198 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1199 { \ 1200 .name = type, \ 1201 .class_init = class_initfn, \ 1202 .parent = TYPE_PNV8_CHIP, \ 1203 } 1204 1205 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1206 { \ 1207 .name = type, \ 1208 .class_init = class_initfn, \ 1209 .parent = TYPE_PNV9_CHIP, \ 1210 } 1211 1212 static const TypeInfo types[] = { 1213 { 1214 .name = TYPE_PNV_MACHINE, 1215 .parent = TYPE_MACHINE, 1216 .instance_size = sizeof(PnvMachineState), 1217 .instance_init = pnv_machine_instance_init, 1218 .class_init = pnv_machine_class_init, 1219 .interfaces = (InterfaceInfo[]) { 1220 { TYPE_XICS_FABRIC }, 1221 { TYPE_INTERRUPT_STATS_PROVIDER }, 1222 { }, 1223 }, 1224 }, 1225 { 1226 .name = TYPE_PNV_CHIP, 1227 .parent = TYPE_SYS_BUS_DEVICE, 1228 .class_init = pnv_chip_class_init, 1229 .instance_init = pnv_chip_instance_init, 1230 .instance_size = sizeof(PnvChip), 1231 .class_size = sizeof(PnvChipClass), 1232 .abstract = true, 1233 }, 1234 1235 /* 1236 * P9 chip and variants 1237 */ 1238 { 1239 .name = TYPE_PNV9_CHIP, 1240 .parent = TYPE_PNV_CHIP, 1241 .instance_init = pnv_chip_power9_instance_init, 1242 .instance_size = sizeof(Pnv9Chip), 1243 }, 1244 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1245 1246 /* 1247 * P8 chip and variants 1248 */ 1249 { 1250 .name = TYPE_PNV8_CHIP, 1251 .parent = TYPE_PNV_CHIP, 1252 .instance_init = pnv_chip_power8_instance_init, 1253 .instance_size = sizeof(Pnv8Chip), 1254 }, 1255 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1256 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1257 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1258 pnv_chip_power8nvl_class_init), 1259 }; 1260 1261 DEFINE_TYPES(types) 1262