1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "sysemu/sysemu.h" 23 #include "sysemu/numa.h" 24 #include "hw/hw.h" 25 #include "target-ppc/cpu.h" 26 #include "qemu/log.h" 27 #include "hw/ppc/fdt.h" 28 #include "hw/ppc/ppc.h" 29 #include "hw/ppc/pnv.h" 30 #include "hw/ppc/pnv_core.h" 31 #include "hw/loader.h" 32 #include "exec/address-spaces.h" 33 #include "qemu/cutils.h" 34 #include "qapi/visitor.h" 35 36 #include "hw/ppc/pnv_xscom.h" 37 38 #include "hw/isa/isa.h" 39 #include "hw/char/serial.h" 40 #include "hw/timer/mc146818rtc.h" 41 42 #include <libfdt.h> 43 44 #define FDT_MAX_SIZE 0x00100000 45 46 #define FW_FILE_NAME "skiboot.lid" 47 #define FW_LOAD_ADDR 0x0 48 #define FW_MAX_SIZE 0x00400000 49 50 #define KERNEL_LOAD_ADDR 0x20000000 51 #define INITRD_LOAD_ADDR 0x40000000 52 53 /* 54 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 55 * 4 * 4 sockets * 12 cores * 8 threads = 1536 56 * Let's make it 2^11 57 */ 58 #define MAX_CPUS 2048 59 60 /* 61 * Memory nodes are created by hostboot, one for each range of memory 62 * that has a different "affinity". In practice, it means one range 63 * per chip. 64 */ 65 static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start, 66 hwaddr size) 67 { 68 char *mem_name; 69 uint64_t mem_reg_property[2]; 70 int off; 71 72 mem_reg_property[0] = cpu_to_be64(start); 73 mem_reg_property[1] = cpu_to_be64(size); 74 75 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 76 off = fdt_add_subnode(fdt, 0, mem_name); 77 g_free(mem_name); 78 79 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 80 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 81 sizeof(mem_reg_property)))); 82 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 83 } 84 85 static int get_cpus_node(void *fdt) 86 { 87 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 88 89 if (cpus_offset < 0) { 90 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 91 "cpus"); 92 if (cpus_offset) { 93 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 94 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 95 } 96 } 97 _FDT(cpus_offset); 98 return cpus_offset; 99 } 100 101 /* 102 * The PowerNV cores (and threads) need to use real HW ids and not an 103 * incremental index like it has been done on other platforms. This HW 104 * id is stored in the CPU PIR, it is used to create cpu nodes in the 105 * device tree, used in XSCOM to address cores and in interrupt 106 * servers. 107 */ 108 static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt) 109 { 110 CPUState *cs = CPU(DEVICE(pc->threads)); 111 DeviceClass *dc = DEVICE_GET_CLASS(cs); 112 PowerPCCPU *cpu = POWERPC_CPU(cs); 113 int smt_threads = ppc_get_compat_smt_threads(cpu); 114 CPUPPCState *env = &cpu->env; 115 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 116 uint32_t servers_prop[smt_threads]; 117 int i; 118 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 119 0xffffffff, 0xffffffff}; 120 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 121 uint32_t cpufreq = 1000000000; 122 uint32_t page_sizes_prop[64]; 123 size_t page_sizes_prop_size; 124 const uint8_t pa_features[] = { 24, 0, 125 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 126 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 127 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 128 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 129 int offset; 130 char *nodename; 131 int cpus_offset = get_cpus_node(fdt); 132 133 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 134 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 135 _FDT(offset); 136 g_free(nodename); 137 138 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 139 140 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 141 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 142 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 143 144 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 145 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 146 env->dcache_line_size))); 147 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 148 env->dcache_line_size))); 149 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 150 env->icache_line_size))); 151 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 152 env->icache_line_size))); 153 154 if (pcc->l1_dcache_size) { 155 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 156 pcc->l1_dcache_size))); 157 } else { 158 error_report("Warning: Unknown L1 dcache size for cpu"); 159 } 160 if (pcc->l1_icache_size) { 161 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 162 pcc->l1_icache_size))); 163 } else { 164 error_report("Warning: Unknown L1 icache size for cpu"); 165 } 166 167 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 168 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 170 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 171 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 172 173 if (env->spr_cb[SPR_PURR].oea_read) { 174 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 175 } 176 177 if (env->mmu_model & POWERPC_MMU_1TSEG) { 178 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 179 segs, sizeof(segs)))); 180 } 181 182 /* Advertise VMX/VSX (vector extensions) if available 183 * 0 / no property == no vector extensions 184 * 1 == VMX / Altivec available 185 * 2 == VSX available */ 186 if (env->insns_flags & PPC_ALTIVEC) { 187 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 188 189 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 190 } 191 192 /* Advertise DFP (Decimal Floating Point) if available 193 * 0 / no property == no DFP 194 * 1 == DFP available */ 195 if (env->insns_flags2 & PPC2_DFP) { 196 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 197 } 198 199 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 200 sizeof(page_sizes_prop)); 201 if (page_sizes_prop_size) { 202 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 203 page_sizes_prop, page_sizes_prop_size))); 204 } 205 206 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 207 pa_features, sizeof(pa_features)))); 208 209 if (cpu->cpu_version) { 210 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version))); 211 } 212 213 /* Build interrupt servers properties */ 214 for (i = 0; i < smt_threads; i++) { 215 servers_prop[i] = cpu_to_be32(pc->pir + i); 216 } 217 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 218 servers_prop, sizeof(servers_prop)))); 219 } 220 221 static void powernv_populate_chip(PnvChip *chip, void *fdt) 222 { 223 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 224 char *typename = pnv_core_typename(pcc->cpu_model); 225 size_t typesize = object_type_get_instance_size(typename); 226 int i; 227 228 pnv_xscom_populate(chip, fdt, 0); 229 230 for (i = 0; i < chip->nr_cores; i++) { 231 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 232 233 powernv_create_core_node(chip, pnv_core, fdt); 234 } 235 236 if (chip->ram_size) { 237 powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start, 238 chip->ram_size); 239 } 240 g_free(typename); 241 } 242 243 static void *powernv_create_fdt(MachineState *machine) 244 { 245 const char plat_compat[] = "qemu,powernv\0ibm,powernv"; 246 PnvMachineState *pnv = POWERNV_MACHINE(machine); 247 void *fdt; 248 char *buf; 249 int off; 250 int i; 251 252 fdt = g_malloc0(FDT_MAX_SIZE); 253 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 254 255 /* Root node */ 256 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 257 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 258 _FDT((fdt_setprop_string(fdt, 0, "model", 259 "IBM PowerNV (emulated by qemu)"))); 260 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat, 261 sizeof(plat_compat)))); 262 263 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 264 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 265 if (qemu_uuid_set) { 266 _FDT((fdt_property_string(fdt, "system-id", buf))); 267 } 268 g_free(buf); 269 270 off = fdt_add_subnode(fdt, 0, "chosen"); 271 if (machine->kernel_cmdline) { 272 _FDT((fdt_setprop_string(fdt, off, "bootargs", 273 machine->kernel_cmdline))); 274 } 275 276 if (pnv->initrd_size) { 277 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 278 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 279 280 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 281 &start_prop, sizeof(start_prop)))); 282 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 283 &end_prop, sizeof(end_prop)))); 284 } 285 286 /* Populate device tree for each chip */ 287 for (i = 0; i < pnv->num_chips; i++) { 288 powernv_populate_chip(pnv->chips[i], fdt); 289 } 290 return fdt; 291 } 292 293 static void ppc_powernv_reset(void) 294 { 295 MachineState *machine = MACHINE(qdev_get_machine()); 296 void *fdt; 297 298 qemu_devices_reset(); 299 300 fdt = powernv_create_fdt(machine); 301 302 /* Pack resulting tree */ 303 _FDT((fdt_pack(fdt))); 304 305 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 306 } 307 308 /* If we don't use the built-in LPC interrupt deserializer, we need 309 * to provide a set of qirqs for the ISA bus or things will go bad. 310 * 311 * Most machines using pre-Naples chips (without said deserializer) 312 * have a CPLD that will collect the SerIRQ and shoot them as a 313 * single level interrupt to the P8 chip. So let's setup a hook 314 * for doing just that. 315 * 316 * Note: The actual interrupt input isn't emulated yet, this will 317 * come with the PSI bridge model. 318 */ 319 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) 320 { 321 /* We don't yet emulate the PSI bridge which provides the external 322 * interrupt, so just drop interrupts on the floor 323 */ 324 } 325 326 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) 327 { 328 /* XXX TODO */ 329 } 330 331 static ISABus *pnv_isa_create(PnvChip *chip) 332 { 333 PnvLpcController *lpc = &chip->lpc; 334 ISABus *isa_bus; 335 qemu_irq *irqs; 336 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 337 338 /* let isa_bus_new() create its own bridge on SysBus otherwise 339 * devices speficied on the command line won't find the bus and 340 * will fail to create. 341 */ 342 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, 343 &error_fatal); 344 345 /* Not all variants have a working serial irq decoder. If not, 346 * handling of LPC interrupts becomes a platform issue (some 347 * platforms have a CPLD to do it). 348 */ 349 if (pcc->chip_type == PNV_CHIP_POWER8NVL) { 350 irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler, chip, ISA_NUM_IRQS); 351 } else { 352 irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, chip, 353 ISA_NUM_IRQS); 354 } 355 356 isa_bus_irqs(isa_bus, irqs); 357 return isa_bus; 358 } 359 360 static void ppc_powernv_init(MachineState *machine) 361 { 362 PnvMachineState *pnv = POWERNV_MACHINE(machine); 363 MemoryRegion *ram; 364 char *fw_filename; 365 long fw_size; 366 int i; 367 char *chip_typename; 368 369 /* allocate RAM */ 370 if (machine->ram_size < (1 * G_BYTE)) { 371 error_report("Warning: skiboot may not work with < 1GB of RAM"); 372 } 373 374 ram = g_new(MemoryRegion, 1); 375 memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram", 376 machine->ram_size); 377 memory_region_add_subregion(get_system_memory(), 0, ram); 378 379 /* load skiboot firmware */ 380 if (bios_name == NULL) { 381 bios_name = FW_FILE_NAME; 382 } 383 384 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 385 386 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 387 if (fw_size < 0) { 388 hw_error("qemu: could not load OPAL '%s'\n", fw_filename); 389 exit(1); 390 } 391 g_free(fw_filename); 392 393 /* load kernel */ 394 if (machine->kernel_filename) { 395 long kernel_size; 396 397 kernel_size = load_image_targphys(machine->kernel_filename, 398 KERNEL_LOAD_ADDR, 0x2000000); 399 if (kernel_size < 0) { 400 hw_error("qemu: could not load kernel'%s'\n", 401 machine->kernel_filename); 402 exit(1); 403 } 404 } 405 406 /* load initrd */ 407 if (machine->initrd_filename) { 408 pnv->initrd_base = INITRD_LOAD_ADDR; 409 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 410 pnv->initrd_base, 0x10000000); /* 128MB max */ 411 if (pnv->initrd_size < 0) { 412 error_report("qemu: could not load initial ram disk '%s'", 413 machine->initrd_filename); 414 exit(1); 415 } 416 } 417 418 /* We need some cpu model to instantiate the PnvChip class */ 419 if (machine->cpu_model == NULL) { 420 machine->cpu_model = "POWER8"; 421 } 422 423 /* Create the processor chips */ 424 chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model); 425 if (!object_class_by_name(chip_typename)) { 426 error_report("qemu: invalid CPU model '%s' for %s machine", 427 machine->cpu_model, MACHINE_GET_CLASS(machine)->name); 428 exit(1); 429 } 430 431 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 432 for (i = 0; i < pnv->num_chips; i++) { 433 char chip_name[32]; 434 Object *chip = object_new(chip_typename); 435 436 pnv->chips[i] = PNV_CHIP(chip); 437 438 /* TODO: put all the memory in one node on chip 0 until we find a 439 * way to specify different ranges for each chip 440 */ 441 if (i == 0) { 442 object_property_set_int(chip, machine->ram_size, "ram-size", 443 &error_fatal); 444 } 445 446 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 447 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 448 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 449 &error_fatal); 450 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal); 451 object_property_set_bool(chip, true, "realized", &error_fatal); 452 } 453 g_free(chip_typename); 454 455 /* Instantiate ISA bus on chip 0 */ 456 pnv->isa_bus = pnv_isa_create(pnv->chips[0]); 457 458 /* Create serial port */ 459 serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS); 460 461 /* Create an RTC ISA device too */ 462 rtc_init(pnv->isa_bus, 2000, NULL); 463 } 464 465 /* 466 * 0:21 Reserved - Read as zeros 467 * 22:24 Chip ID 468 * 25:28 Core number 469 * 29:31 Thread ID 470 */ 471 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 472 { 473 return (chip->chip_id << 7) | (core_id << 3); 474 } 475 476 /* 477 * 0:48 Reserved - Read as zeroes 478 * 49:52 Node ID 479 * 53:55 Chip ID 480 * 56 Reserved - Read as zero 481 * 57:61 Core number 482 * 62:63 Thread ID 483 * 484 * We only care about the lower bits. uint32_t is fine for the moment. 485 */ 486 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 487 { 488 return (chip->chip_id << 8) | (core_id << 2); 489 } 490 491 /* Allowed core identifiers on a POWER8 Processor Chip : 492 * 493 * <EX0 reserved> 494 * EX1 - Venice only 495 * EX2 - Venice only 496 * EX3 - Venice only 497 * EX4 498 * EX5 499 * EX6 500 * <EX7,8 reserved> <reserved> 501 * EX9 - Venice only 502 * EX10 - Venice only 503 * EX11 - Venice only 504 * EX12 505 * EX13 506 * EX14 507 * <EX15 reserved> 508 */ 509 #define POWER8E_CORE_MASK (0x7070ull) 510 #define POWER8_CORE_MASK (0x7e7eull) 511 512 /* 513 * POWER9 has 24 cores, ids starting at 0x20 514 */ 515 #define POWER9_CORE_MASK (0xffffff00000000ull) 516 517 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 518 { 519 DeviceClass *dc = DEVICE_CLASS(klass); 520 PnvChipClass *k = PNV_CHIP_CLASS(klass); 521 522 k->cpu_model = "POWER8E"; 523 k->chip_type = PNV_CHIP_POWER8E; 524 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 525 k->cores_mask = POWER8E_CORE_MASK; 526 k->core_pir = pnv_chip_core_pir_p8; 527 k->xscom_base = 0x003fc0000000000ull; 528 dc->desc = "PowerNV Chip POWER8E"; 529 } 530 531 static const TypeInfo pnv_chip_power8e_info = { 532 .name = TYPE_PNV_CHIP_POWER8E, 533 .parent = TYPE_PNV_CHIP, 534 .instance_size = sizeof(PnvChip), 535 .class_init = pnv_chip_power8e_class_init, 536 }; 537 538 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 539 { 540 DeviceClass *dc = DEVICE_CLASS(klass); 541 PnvChipClass *k = PNV_CHIP_CLASS(klass); 542 543 k->cpu_model = "POWER8"; 544 k->chip_type = PNV_CHIP_POWER8; 545 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 546 k->cores_mask = POWER8_CORE_MASK; 547 k->core_pir = pnv_chip_core_pir_p8; 548 k->xscom_base = 0x003fc0000000000ull; 549 dc->desc = "PowerNV Chip POWER8"; 550 } 551 552 static const TypeInfo pnv_chip_power8_info = { 553 .name = TYPE_PNV_CHIP_POWER8, 554 .parent = TYPE_PNV_CHIP, 555 .instance_size = sizeof(PnvChip), 556 .class_init = pnv_chip_power8_class_init, 557 }; 558 559 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 560 { 561 DeviceClass *dc = DEVICE_CLASS(klass); 562 PnvChipClass *k = PNV_CHIP_CLASS(klass); 563 564 k->cpu_model = "POWER8NVL"; 565 k->chip_type = PNV_CHIP_POWER8NVL; 566 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 567 k->cores_mask = POWER8_CORE_MASK; 568 k->core_pir = pnv_chip_core_pir_p8; 569 k->xscom_base = 0x003fc0000000000ull; 570 dc->desc = "PowerNV Chip POWER8NVL"; 571 } 572 573 static const TypeInfo pnv_chip_power8nvl_info = { 574 .name = TYPE_PNV_CHIP_POWER8NVL, 575 .parent = TYPE_PNV_CHIP, 576 .instance_size = sizeof(PnvChip), 577 .class_init = pnv_chip_power8nvl_class_init, 578 }; 579 580 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 581 { 582 DeviceClass *dc = DEVICE_CLASS(klass); 583 PnvChipClass *k = PNV_CHIP_CLASS(klass); 584 585 k->cpu_model = "POWER9"; 586 k->chip_type = PNV_CHIP_POWER9; 587 k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ 588 k->cores_mask = POWER9_CORE_MASK; 589 k->core_pir = pnv_chip_core_pir_p9; 590 k->xscom_base = 0x00603fc00000000ull; 591 dc->desc = "PowerNV Chip POWER9"; 592 } 593 594 static const TypeInfo pnv_chip_power9_info = { 595 .name = TYPE_PNV_CHIP_POWER9, 596 .parent = TYPE_PNV_CHIP, 597 .instance_size = sizeof(PnvChip), 598 .class_init = pnv_chip_power9_class_init, 599 }; 600 601 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 602 { 603 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 604 int cores_max; 605 606 /* 607 * No custom mask for this chip, let's use the default one from * 608 * the chip class 609 */ 610 if (!chip->cores_mask) { 611 chip->cores_mask = pcc->cores_mask; 612 } 613 614 /* filter alien core ids ! some are reserved */ 615 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 616 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 617 chip->cores_mask); 618 return; 619 } 620 chip->cores_mask &= pcc->cores_mask; 621 622 /* now that we have a sane layout, let check the number of cores */ 623 cores_max = hweight_long(chip->cores_mask); 624 if (chip->nr_cores > cores_max) { 625 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 626 cores_max); 627 return; 628 } 629 } 630 631 static void pnv_chip_init(Object *obj) 632 { 633 PnvChip *chip = PNV_CHIP(obj); 634 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 635 636 chip->xscom_base = pcc->xscom_base; 637 638 object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC); 639 object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); 640 } 641 642 static void pnv_chip_realize(DeviceState *dev, Error **errp) 643 { 644 PnvChip *chip = PNV_CHIP(dev); 645 Error *error = NULL; 646 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 647 char *typename = pnv_core_typename(pcc->cpu_model); 648 size_t typesize = object_type_get_instance_size(typename); 649 int i, core_hwid; 650 651 if (!object_class_by_name(typename)) { 652 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 653 return; 654 } 655 656 /* XSCOM bridge */ 657 pnv_xscom_realize(chip, &error); 658 if (error) { 659 error_propagate(errp, error); 660 return; 661 } 662 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 663 664 /* Cores */ 665 pnv_chip_core_sanitize(chip, &error); 666 if (error) { 667 error_propagate(errp, error); 668 return; 669 } 670 671 chip->cores = g_malloc0(typesize * chip->nr_cores); 672 673 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 674 && (i < chip->nr_cores); core_hwid++) { 675 char core_name[32]; 676 void *pnv_core = chip->cores + i * typesize; 677 678 if (!(chip->cores_mask & (1ull << core_hwid))) { 679 continue; 680 } 681 682 object_initialize(pnv_core, typesize, typename); 683 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 684 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 685 &error_fatal); 686 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads", 687 &error_fatal); 688 object_property_set_int(OBJECT(pnv_core), core_hwid, 689 CPU_CORE_PROP_CORE_ID, &error_fatal); 690 object_property_set_int(OBJECT(pnv_core), 691 pcc->core_pir(chip, core_hwid), 692 "pir", &error_fatal); 693 object_property_set_bool(OBJECT(pnv_core), true, "realized", 694 &error_fatal); 695 object_unref(OBJECT(pnv_core)); 696 697 /* Each core has an XSCOM MMIO region */ 698 pnv_xscom_add_subregion(chip, PNV_XSCOM_EX_CORE_BASE(core_hwid), 699 &PNV_CORE(pnv_core)->xscom_regs); 700 i++; 701 } 702 g_free(typename); 703 704 /* Create LPC controller */ 705 object_property_set_bool(OBJECT(&chip->lpc), true, "realized", 706 &error_fatal); 707 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs); 708 } 709 710 static Property pnv_chip_properties[] = { 711 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 712 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 713 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 714 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 715 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 716 DEFINE_PROP_END_OF_LIST(), 717 }; 718 719 static void pnv_chip_class_init(ObjectClass *klass, void *data) 720 { 721 DeviceClass *dc = DEVICE_CLASS(klass); 722 723 dc->realize = pnv_chip_realize; 724 dc->props = pnv_chip_properties; 725 dc->desc = "PowerNV Chip"; 726 } 727 728 static const TypeInfo pnv_chip_info = { 729 .name = TYPE_PNV_CHIP, 730 .parent = TYPE_SYS_BUS_DEVICE, 731 .class_init = pnv_chip_class_init, 732 .instance_init = pnv_chip_init, 733 .class_size = sizeof(PnvChipClass), 734 .abstract = true, 735 }; 736 737 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 738 void *opaque, Error **errp) 739 { 740 visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp); 741 } 742 743 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 744 void *opaque, Error **errp) 745 { 746 PnvMachineState *pnv = POWERNV_MACHINE(obj); 747 uint32_t num_chips; 748 Error *local_err = NULL; 749 750 visit_type_uint32(v, name, &num_chips, &local_err); 751 if (local_err) { 752 error_propagate(errp, local_err); 753 return; 754 } 755 756 /* 757 * TODO: should we decide on how many chips we can create based 758 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 759 */ 760 if (!is_power_of_2(num_chips) || num_chips > 4) { 761 error_setg(errp, "invalid number of chips: '%d'", num_chips); 762 return; 763 } 764 765 pnv->num_chips = num_chips; 766 } 767 768 static void powernv_machine_initfn(Object *obj) 769 { 770 PnvMachineState *pnv = POWERNV_MACHINE(obj); 771 pnv->num_chips = 1; 772 } 773 774 static void powernv_machine_class_props_init(ObjectClass *oc) 775 { 776 object_class_property_add(oc, "num-chips", "uint32_t", 777 pnv_get_num_chips, pnv_set_num_chips, 778 NULL, NULL, NULL); 779 object_class_property_set_description(oc, "num-chips", 780 "Specifies the number of processor chips", 781 NULL); 782 } 783 784 static void powernv_machine_class_init(ObjectClass *oc, void *data) 785 { 786 MachineClass *mc = MACHINE_CLASS(oc); 787 788 mc->desc = "IBM PowerNV (Non-Virtualized)"; 789 mc->init = ppc_powernv_init; 790 mc->reset = ppc_powernv_reset; 791 mc->max_cpus = MAX_CPUS; 792 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for 793 * storage */ 794 mc->no_parallel = 1; 795 mc->default_boot_order = NULL; 796 mc->default_ram_size = 1 * G_BYTE; 797 798 powernv_machine_class_props_init(oc); 799 } 800 801 static const TypeInfo powernv_machine_info = { 802 .name = TYPE_POWERNV_MACHINE, 803 .parent = TYPE_MACHINE, 804 .instance_size = sizeof(PnvMachineState), 805 .instance_init = powernv_machine_initfn, 806 .class_init = powernv_machine_class_init, 807 }; 808 809 static void powernv_machine_register_types(void) 810 { 811 type_register_static(&powernv_machine_info); 812 type_register_static(&pnv_chip_info); 813 type_register_static(&pnv_chip_power8e_info); 814 type_register_static(&pnv_chip_power8_info); 815 type_register_static(&pnv_chip_power8nvl_info); 816 type_register_static(&pnv_chip_power9_info); 817 } 818 819 type_init(powernv_machine_register_types) 820