1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 #include "hw/pci/msi.h" 44 45 #include "hw/ppc/xics.h" 46 #include "hw/qdev-properties.h" 47 #include "hw/ppc/pnv_xscom.h" 48 #include "hw/ppc/pnv_pnor.h" 49 50 #include "hw/isa/isa.h" 51 #include "hw/boards.h" 52 #include "hw/char/serial.h" 53 #include "hw/rtc/mc146818rtc.h" 54 55 #include <libfdt.h> 56 57 #define FDT_MAX_SIZE (1 * MiB) 58 59 #define FW_FILE_NAME "skiboot.lid" 60 #define FW_LOAD_ADDR 0x0 61 #define FW_MAX_SIZE (4 * MiB) 62 63 #define KERNEL_LOAD_ADDR 0x20000000 64 #define KERNEL_MAX_SIZE (256 * MiB) 65 #define INITRD_LOAD_ADDR 0x60000000 66 #define INITRD_MAX_SIZE (256 * MiB) 67 68 static const char *pnv_chip_core_typename(const PnvChip *o) 69 { 70 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 71 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 72 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 73 const char *core_type = object_class_get_name(object_class_by_name(s)); 74 g_free(s); 75 return core_type; 76 } 77 78 /* 79 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 80 * 4 * 4 sockets * 12 cores * 8 threads = 1536 81 * Let's make it 2^11 82 */ 83 #define MAX_CPUS 2048 84 85 /* 86 * Memory nodes are created by hostboot, one for each range of memory 87 * that has a different "affinity". In practice, it means one range 88 * per chip. 89 */ 90 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 91 { 92 char *mem_name; 93 uint64_t mem_reg_property[2]; 94 int off; 95 96 mem_reg_property[0] = cpu_to_be64(start); 97 mem_reg_property[1] = cpu_to_be64(size); 98 99 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 100 off = fdt_add_subnode(fdt, 0, mem_name); 101 g_free(mem_name); 102 103 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 104 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 105 sizeof(mem_reg_property)))); 106 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 107 } 108 109 static int get_cpus_node(void *fdt) 110 { 111 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 112 113 if (cpus_offset < 0) { 114 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 115 if (cpus_offset) { 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 117 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 118 } 119 } 120 _FDT(cpus_offset); 121 return cpus_offset; 122 } 123 124 /* 125 * The PowerNV cores (and threads) need to use real HW ids and not an 126 * incremental index like it has been done on other platforms. This HW 127 * id is stored in the CPU PIR, it is used to create cpu nodes in the 128 * device tree, used in XSCOM to address cores and in interrupt 129 * servers. 130 */ 131 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 132 { 133 PowerPCCPU *cpu = pc->threads[0]; 134 CPUState *cs = CPU(cpu); 135 DeviceClass *dc = DEVICE_GET_CLASS(cs); 136 int smt_threads = CPU_CORE(pc)->nr_threads; 137 CPUPPCState *env = &cpu->env; 138 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 139 uint32_t servers_prop[smt_threads]; 140 int i; 141 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 142 0xffffffff, 0xffffffff}; 143 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 144 uint32_t cpufreq = 1000000000; 145 uint32_t page_sizes_prop[64]; 146 size_t page_sizes_prop_size; 147 const uint8_t pa_features[] = { 24, 0, 148 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 149 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 150 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 151 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 152 int offset; 153 char *nodename; 154 int cpus_offset = get_cpus_node(fdt); 155 156 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 157 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 158 _FDT(offset); 159 g_free(nodename); 160 161 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 165 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 166 167 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 168 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 169 env->dcache_line_size))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 173 env->icache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 175 env->icache_line_size))); 176 177 if (pcc->l1_dcache_size) { 178 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 179 pcc->l1_dcache_size))); 180 } else { 181 warn_report("Unknown L1 dcache size for cpu"); 182 } 183 if (pcc->l1_icache_size) { 184 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 185 pcc->l1_icache_size))); 186 } else { 187 warn_report("Unknown L1 icache size for cpu"); 188 } 189 190 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 192 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 193 cpu->hash64_opts->slb_size))); 194 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 195 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 196 197 if (env->spr_cb[SPR_PURR].oea_read) { 198 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 199 } 200 201 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 202 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 203 segs, sizeof(segs)))); 204 } 205 206 /* 207 * Advertise VMX/VSX (vector extensions) if available 208 * 0 / no property == no vector extensions 209 * 1 == VMX / Altivec available 210 * 2 == VSX available 211 */ 212 if (env->insns_flags & PPC_ALTIVEC) { 213 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 214 215 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 216 } 217 218 /* 219 * Advertise DFP (Decimal Floating Point) if available 220 * 0 / no property == no DFP 221 * 1 == DFP available 222 */ 223 if (env->insns_flags2 & PPC2_DFP) { 224 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 225 } 226 227 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 228 sizeof(page_sizes_prop)); 229 if (page_sizes_prop_size) { 230 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 231 page_sizes_prop, page_sizes_prop_size))); 232 } 233 234 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 235 pa_features, sizeof(pa_features)))); 236 237 /* Build interrupt servers properties */ 238 for (i = 0; i < smt_threads; i++) { 239 servers_prop[i] = cpu_to_be32(pc->pir + i); 240 } 241 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 242 servers_prop, sizeof(servers_prop)))); 243 } 244 245 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 246 uint32_t nr_threads) 247 { 248 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 249 char *name; 250 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 251 uint32_t irange[2], i, rsize; 252 uint64_t *reg; 253 int offset; 254 255 irange[0] = cpu_to_be32(pir); 256 irange[1] = cpu_to_be32(nr_threads); 257 258 rsize = sizeof(uint64_t) * 2 * nr_threads; 259 reg = g_malloc(rsize); 260 for (i = 0; i < nr_threads; i++) { 261 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 262 reg[i * 2 + 1] = cpu_to_be64(0x1000); 263 } 264 265 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 266 offset = fdt_add_subnode(fdt, 0, name); 267 _FDT(offset); 268 g_free(name); 269 270 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 271 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 272 _FDT((fdt_setprop_string(fdt, offset, "device_type", 273 "PowerPC-External-Interrupt-Presentation"))); 274 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 275 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 276 irange, sizeof(irange)))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 278 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 279 g_free(reg); 280 } 281 282 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 283 { 284 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 285 int i; 286 287 pnv_dt_xscom(chip, fdt, 0, 288 cpu_to_be64(PNV_XSCOM_BASE(chip)), 289 cpu_to_be64(PNV_XSCOM_SIZE), 290 compat, sizeof(compat)); 291 292 for (i = 0; i < chip->nr_cores; i++) { 293 PnvCore *pnv_core = chip->cores[i]; 294 295 pnv_dt_core(chip, pnv_core, fdt); 296 297 /* Interrupt Control Presenters (ICP). One per core. */ 298 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 299 } 300 301 if (chip->ram_size) { 302 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 303 } 304 } 305 306 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 307 { 308 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 309 int i; 310 311 pnv_dt_xscom(chip, fdt, 0, 312 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 313 cpu_to_be64(PNV9_XSCOM_SIZE), 314 compat, sizeof(compat)); 315 316 for (i = 0; i < chip->nr_cores; i++) { 317 PnvCore *pnv_core = chip->cores[i]; 318 319 pnv_dt_core(chip, pnv_core, fdt); 320 } 321 322 if (chip->ram_size) { 323 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 324 } 325 326 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 327 } 328 329 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 330 { 331 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 332 int i; 333 334 pnv_dt_xscom(chip, fdt, 0, 335 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 336 cpu_to_be64(PNV10_XSCOM_SIZE), 337 compat, sizeof(compat)); 338 339 for (i = 0; i < chip->nr_cores; i++) { 340 PnvCore *pnv_core = chip->cores[i]; 341 342 pnv_dt_core(chip, pnv_core, fdt); 343 } 344 345 if (chip->ram_size) { 346 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 347 } 348 349 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 350 } 351 352 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 353 { 354 uint32_t io_base = d->ioport_id; 355 uint32_t io_regs[] = { 356 cpu_to_be32(1), 357 cpu_to_be32(io_base), 358 cpu_to_be32(2) 359 }; 360 char *name; 361 int node; 362 363 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 364 node = fdt_add_subnode(fdt, lpc_off, name); 365 _FDT(node); 366 g_free(name); 367 368 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 369 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 370 } 371 372 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 373 { 374 const char compatible[] = "ns16550\0pnpPNP,501"; 375 uint32_t io_base = d->ioport_id; 376 uint32_t io_regs[] = { 377 cpu_to_be32(1), 378 cpu_to_be32(io_base), 379 cpu_to_be32(8) 380 }; 381 char *name; 382 int node; 383 384 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 385 node = fdt_add_subnode(fdt, lpc_off, name); 386 _FDT(node); 387 g_free(name); 388 389 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 390 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 391 sizeof(compatible)))); 392 393 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 394 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 395 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 396 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 397 fdt_get_phandle(fdt, lpc_off)))); 398 399 /* This is needed by Linux */ 400 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 401 } 402 403 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 404 { 405 const char compatible[] = "bt\0ipmi-bt"; 406 uint32_t io_base; 407 uint32_t io_regs[] = { 408 cpu_to_be32(1), 409 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 410 cpu_to_be32(3) 411 }; 412 uint32_t irq; 413 char *name; 414 int node; 415 416 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 417 io_regs[1] = cpu_to_be32(io_base); 418 419 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 420 421 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 422 node = fdt_add_subnode(fdt, lpc_off, name); 423 _FDT(node); 424 g_free(name); 425 426 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 427 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 428 sizeof(compatible)))); 429 430 /* Mark it as reserved to avoid Linux trying to claim it */ 431 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 432 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 433 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 434 fdt_get_phandle(fdt, lpc_off)))); 435 } 436 437 typedef struct ForeachPopulateArgs { 438 void *fdt; 439 int offset; 440 } ForeachPopulateArgs; 441 442 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 443 { 444 ForeachPopulateArgs *args = opaque; 445 ISADevice *d = ISA_DEVICE(dev); 446 447 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 448 pnv_dt_rtc(d, args->fdt, args->offset); 449 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 450 pnv_dt_serial(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 452 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 453 } else { 454 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 455 d->ioport_id); 456 } 457 458 return 0; 459 } 460 461 /* 462 * The default LPC bus of a multichip system is on chip 0. It's 463 * recognized by the firmware (skiboot) using a "primary" property. 464 */ 465 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 466 { 467 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 468 ForeachPopulateArgs args = { 469 .fdt = fdt, 470 .offset = isa_offset, 471 }; 472 uint32_t phandle; 473 474 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 475 476 phandle = qemu_fdt_alloc_phandle(fdt); 477 assert(phandle > 0); 478 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 479 480 /* 481 * ISA devices are not necessarily parented to the ISA bus so we 482 * can not use object_child_foreach() 483 */ 484 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 485 &args); 486 } 487 488 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 489 { 490 int off; 491 492 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 493 off = fdt_add_subnode(fdt, off, "power-mgt"); 494 495 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 496 } 497 498 static void *pnv_dt_create(MachineState *machine) 499 { 500 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 501 PnvMachineState *pnv = PNV_MACHINE(machine); 502 void *fdt; 503 char *buf; 504 int off; 505 int i; 506 507 fdt = g_malloc0(FDT_MAX_SIZE); 508 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 509 510 /* /qemu node */ 511 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 512 513 /* Root node */ 514 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 515 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 516 _FDT((fdt_setprop_string(fdt, 0, "model", 517 "IBM PowerNV (emulated by qemu)"))); 518 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 519 520 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 521 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 522 if (qemu_uuid_set) { 523 _FDT((fdt_property_string(fdt, "system-id", buf))); 524 } 525 g_free(buf); 526 527 off = fdt_add_subnode(fdt, 0, "chosen"); 528 if (machine->kernel_cmdline) { 529 _FDT((fdt_setprop_string(fdt, off, "bootargs", 530 machine->kernel_cmdline))); 531 } 532 533 if (pnv->initrd_size) { 534 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 535 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 536 537 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 538 &start_prop, sizeof(start_prop)))); 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 540 &end_prop, sizeof(end_prop)))); 541 } 542 543 /* Populate device tree for each chip */ 544 for (i = 0; i < pnv->num_chips; i++) { 545 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 546 } 547 548 /* Populate ISA devices on chip 0 */ 549 pnv_dt_isa(pnv, fdt); 550 551 if (pnv->bmc) { 552 pnv_dt_bmc_sensors(pnv->bmc, fdt); 553 } 554 555 /* Create an extra node for power management on machines that support it */ 556 if (pmc->dt_power_mgt) { 557 pmc->dt_power_mgt(pnv, fdt); 558 } 559 560 return fdt; 561 } 562 563 static void pnv_powerdown_notify(Notifier *n, void *opaque) 564 { 565 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 566 567 if (pnv->bmc) { 568 pnv_bmc_powerdown(pnv->bmc); 569 } 570 } 571 572 static void pnv_reset(MachineState *machine) 573 { 574 void *fdt; 575 576 qemu_devices_reset(); 577 578 fdt = pnv_dt_create(machine); 579 580 /* Pack resulting tree */ 581 _FDT((fdt_pack(fdt))); 582 583 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 584 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 585 } 586 587 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 588 { 589 Pnv8Chip *chip8 = PNV8_CHIP(chip); 590 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 591 } 592 593 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 594 { 595 Pnv8Chip *chip8 = PNV8_CHIP(chip); 596 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 597 } 598 599 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 600 { 601 Pnv9Chip *chip9 = PNV9_CHIP(chip); 602 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 603 } 604 605 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 606 { 607 Pnv10Chip *chip10 = PNV10_CHIP(chip); 608 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 609 } 610 611 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 612 { 613 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 614 } 615 616 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 617 { 618 Pnv8Chip *chip8 = PNV8_CHIP(chip); 619 int i; 620 621 ics_pic_print_info(&chip8->psi.ics, mon); 622 for (i = 0; i < chip->num_phbs; i++) { 623 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 624 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 625 } 626 } 627 628 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 629 { 630 Pnv9Chip *chip9 = PNV9_CHIP(chip); 631 int i, j; 632 633 pnv_xive_pic_print_info(&chip9->xive, mon); 634 pnv_psi_pic_print_info(&chip9->psi, mon); 635 636 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 637 PnvPhb4PecState *pec = &chip9->pecs[i]; 638 for (j = 0; j < pec->num_stacks; j++) { 639 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 640 } 641 } 642 } 643 644 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 645 uint32_t core_id) 646 { 647 return PNV_XSCOM_EX_BASE(core_id); 648 } 649 650 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 651 uint32_t core_id) 652 { 653 return PNV9_XSCOM_EC_BASE(core_id); 654 } 655 656 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 657 uint32_t core_id) 658 { 659 return PNV10_XSCOM_EC_BASE(core_id); 660 } 661 662 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 663 { 664 PowerPCCPUClass *ppc_default = 665 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 666 PowerPCCPUClass *ppc = 667 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 668 669 return ppc_default->pvr_match(ppc_default, ppc->pvr); 670 } 671 672 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 673 { 674 Object *obj; 675 676 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 677 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 678 object_property_set_int(obj, irq, "irq", &error_fatal); 679 object_property_set_bool(obj, true, "realized", &error_fatal); 680 } 681 682 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 683 { 684 Pnv10Chip *chip10 = PNV10_CHIP(chip); 685 686 pnv_psi_pic_print_info(&chip10->psi, mon); 687 } 688 689 static void pnv_init(MachineState *machine) 690 { 691 PnvMachineState *pnv = PNV_MACHINE(machine); 692 MachineClass *mc = MACHINE_GET_CLASS(machine); 693 MemoryRegion *ram; 694 char *fw_filename; 695 long fw_size; 696 int i; 697 char *chip_typename; 698 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 699 DeviceState *dev; 700 701 /* allocate RAM */ 702 if (machine->ram_size < (1 * GiB)) { 703 warn_report("skiboot may not work with < 1GB of RAM"); 704 } 705 706 ram = g_new(MemoryRegion, 1); 707 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 708 machine->ram_size); 709 memory_region_add_subregion(get_system_memory(), 0, ram); 710 711 /* 712 * Create our simple PNOR device 713 */ 714 dev = qdev_create(NULL, TYPE_PNV_PNOR); 715 if (pnor) { 716 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 717 &error_abort); 718 } 719 qdev_init_nofail(dev); 720 pnv->pnor = PNV_PNOR(dev); 721 722 /* load skiboot firmware */ 723 if (bios_name == NULL) { 724 bios_name = FW_FILE_NAME; 725 } 726 727 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 728 if (!fw_filename) { 729 error_report("Could not find OPAL firmware '%s'", bios_name); 730 exit(1); 731 } 732 733 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 734 if (fw_size < 0) { 735 error_report("Could not load OPAL firmware '%s'", fw_filename); 736 exit(1); 737 } 738 g_free(fw_filename); 739 740 /* load kernel */ 741 if (machine->kernel_filename) { 742 long kernel_size; 743 744 kernel_size = load_image_targphys(machine->kernel_filename, 745 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 746 if (kernel_size < 0) { 747 error_report("Could not load kernel '%s'", 748 machine->kernel_filename); 749 exit(1); 750 } 751 } 752 753 /* load initrd */ 754 if (machine->initrd_filename) { 755 pnv->initrd_base = INITRD_LOAD_ADDR; 756 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 757 pnv->initrd_base, INITRD_MAX_SIZE); 758 if (pnv->initrd_size < 0) { 759 error_report("Could not load initial ram disk '%s'", 760 machine->initrd_filename); 761 exit(1); 762 } 763 } 764 765 /* MSIs are supported on this platform */ 766 msi_nonbroken = true; 767 768 /* 769 * Check compatibility of the specified CPU with the machine 770 * default. 771 */ 772 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 773 error_report("invalid CPU model '%s' for %s machine", 774 machine->cpu_type, mc->name); 775 exit(1); 776 } 777 778 /* Create the processor chips */ 779 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 780 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 781 i, machine->cpu_type); 782 if (!object_class_by_name(chip_typename)) { 783 error_report("invalid chip model '%.*s' for %s machine", 784 i, machine->cpu_type, mc->name); 785 exit(1); 786 } 787 788 pnv->num_chips = 789 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 790 /* 791 * TODO: should we decide on how many chips we can create based 792 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 793 */ 794 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 795 error_report("invalid number of chips: '%d'", pnv->num_chips); 796 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 797 exit(1); 798 } 799 800 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 801 for (i = 0; i < pnv->num_chips; i++) { 802 char chip_name[32]; 803 Object *chip = object_new(chip_typename); 804 805 pnv->chips[i] = PNV_CHIP(chip); 806 807 /* 808 * TODO: put all the memory in one node on chip 0 until we find a 809 * way to specify different ranges for each chip 810 */ 811 if (i == 0) { 812 object_property_set_int(chip, machine->ram_size, "ram-size", 813 &error_fatal); 814 } 815 816 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 817 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 818 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 819 &error_fatal); 820 object_property_set_int(chip, machine->smp.cores, 821 "nr-cores", &error_fatal); 822 object_property_set_int(chip, machine->smp.threads, 823 "nr-threads", &error_fatal); 824 /* 825 * The POWER8 machine use the XICS interrupt interface. 826 * Propagate the XICS fabric to the chip and its controllers. 827 */ 828 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 829 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); 830 } 831 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 832 object_property_set_link(chip, OBJECT(pnv), "xive-fabric", 833 &error_abort); 834 } 835 object_property_set_bool(chip, true, "realized", &error_fatal); 836 } 837 g_free(chip_typename); 838 839 /* Create the machine BMC simulator */ 840 pnv->bmc = pnv_bmc_create(pnv->pnor); 841 842 /* Instantiate ISA bus on chip 0 */ 843 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 844 845 /* Create serial port */ 846 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 847 848 /* Create an RTC ISA device too */ 849 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 850 851 /* Create the IPMI BT device for communication with the BMC */ 852 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 853 854 /* 855 * OpenPOWER systems use a IPMI SEL Event message to notify the 856 * host to powerdown 857 */ 858 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 859 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 860 } 861 862 /* 863 * 0:21 Reserved - Read as zeros 864 * 22:24 Chip ID 865 * 25:28 Core number 866 * 29:31 Thread ID 867 */ 868 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 869 { 870 return (chip->chip_id << 7) | (core_id << 3); 871 } 872 873 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 874 Error **errp) 875 { 876 Pnv8Chip *chip8 = PNV8_CHIP(chip); 877 Error *local_err = NULL; 878 Object *obj; 879 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 880 881 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 882 if (local_err) { 883 error_propagate(errp, local_err); 884 return; 885 } 886 887 pnv_cpu->intc = obj; 888 } 889 890 891 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 892 { 893 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 894 895 icp_reset(ICP(pnv_cpu->intc)); 896 } 897 898 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 899 { 900 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 901 902 icp_destroy(ICP(pnv_cpu->intc)); 903 pnv_cpu->intc = NULL; 904 } 905 906 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 907 Monitor *mon) 908 { 909 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 910 } 911 912 /* 913 * 0:48 Reserved - Read as zeroes 914 * 49:52 Node ID 915 * 53:55 Chip ID 916 * 56 Reserved - Read as zero 917 * 57:61 Core number 918 * 62:63 Thread ID 919 * 920 * We only care about the lower bits. uint32_t is fine for the moment. 921 */ 922 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 923 { 924 return (chip->chip_id << 8) | (core_id << 2); 925 } 926 927 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 928 { 929 return (chip->chip_id << 8) | (core_id << 2); 930 } 931 932 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 933 Error **errp) 934 { 935 Pnv9Chip *chip9 = PNV9_CHIP(chip); 936 Error *local_err = NULL; 937 Object *obj; 938 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 939 940 /* 941 * The core creates its interrupt presenter but the XIVE interrupt 942 * controller object is initialized afterwards. Hopefully, it's 943 * only used at runtime. 944 */ 945 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 946 &local_err); 947 if (local_err) { 948 error_propagate(errp, local_err); 949 return; 950 } 951 952 pnv_cpu->intc = obj; 953 } 954 955 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 956 { 957 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 958 959 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 960 } 961 962 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 963 { 964 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 965 966 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 967 pnv_cpu->intc = NULL; 968 } 969 970 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 971 Monitor *mon) 972 { 973 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 974 } 975 976 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 977 Error **errp) 978 { 979 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 980 981 /* Will be defined when the interrupt controller is */ 982 pnv_cpu->intc = NULL; 983 } 984 985 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 986 { 987 ; 988 } 989 990 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 991 { 992 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 993 994 pnv_cpu->intc = NULL; 995 } 996 997 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 998 Monitor *mon) 999 { 1000 } 1001 1002 /* 1003 * Allowed core identifiers on a POWER8 Processor Chip : 1004 * 1005 * <EX0 reserved> 1006 * EX1 - Venice only 1007 * EX2 - Venice only 1008 * EX3 - Venice only 1009 * EX4 1010 * EX5 1011 * EX6 1012 * <EX7,8 reserved> <reserved> 1013 * EX9 - Venice only 1014 * EX10 - Venice only 1015 * EX11 - Venice only 1016 * EX12 1017 * EX13 1018 * EX14 1019 * <EX15 reserved> 1020 */ 1021 #define POWER8E_CORE_MASK (0x7070ull) 1022 #define POWER8_CORE_MASK (0x7e7eull) 1023 1024 /* 1025 * POWER9 has 24 cores, ids starting at 0x0 1026 */ 1027 #define POWER9_CORE_MASK (0xffffffffffffffull) 1028 1029 1030 #define POWER10_CORE_MASK (0xffffffffffffffull) 1031 1032 static void pnv_chip_power8_instance_init(Object *obj) 1033 { 1034 PnvChip *chip = PNV_CHIP(obj); 1035 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1036 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1037 int i; 1038 1039 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1040 (Object **)&chip8->xics, 1041 object_property_allow_set_link, 1042 OBJ_PROP_LINK_STRONG, 1043 &error_abort); 1044 1045 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 1046 TYPE_PNV8_PSI, &error_abort, NULL); 1047 1048 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 1049 TYPE_PNV8_LPC, &error_abort, NULL); 1050 1051 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 1052 TYPE_PNV8_OCC, &error_abort, NULL); 1053 1054 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 1055 TYPE_PNV8_HOMER, &error_abort, NULL); 1056 1057 for (i = 0; i < pcc->num_phbs; i++) { 1058 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], 1059 sizeof(chip8->phbs[i]), TYPE_PNV_PHB3, 1060 &error_abort, NULL); 1061 } 1062 1063 /* 1064 * Number of PHBs is the chip default 1065 */ 1066 chip->num_phbs = pcc->num_phbs; 1067 } 1068 1069 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1070 { 1071 PnvChip *chip = PNV_CHIP(chip8); 1072 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1073 int i, j; 1074 char *name; 1075 1076 name = g_strdup_printf("icp-%x", chip->chip_id); 1077 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1078 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1079 g_free(name); 1080 1081 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1082 1083 /* Map the ICP registers for each thread */ 1084 for (i = 0; i < chip->nr_cores; i++) { 1085 PnvCore *pnv_core = chip->cores[i]; 1086 int core_hwid = CPU_CORE(pnv_core)->core_id; 1087 1088 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1089 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1090 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1091 1092 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1093 &icp->mmio); 1094 } 1095 } 1096 } 1097 1098 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1099 { 1100 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1101 PnvChip *chip = PNV_CHIP(dev); 1102 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1103 Pnv8Psi *psi8 = &chip8->psi; 1104 Error *local_err = NULL; 1105 int i; 1106 1107 assert(chip8->xics); 1108 1109 /* XSCOM bridge is first */ 1110 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1111 if (local_err) { 1112 error_propagate(errp, local_err); 1113 return; 1114 } 1115 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1116 1117 pcc->parent_realize(dev, &local_err); 1118 if (local_err) { 1119 error_propagate(errp, local_err); 1120 return; 1121 } 1122 1123 /* Processor Service Interface (PSI) Host Bridge */ 1124 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1125 "bar", &error_fatal); 1126 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), 1127 ICS_PROP_XICS, &error_abort); 1128 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 1129 if (local_err) { 1130 error_propagate(errp, local_err); 1131 return; 1132 } 1133 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1134 &PNV_PSI(psi8)->xscom_regs); 1135 1136 /* Create LPC controller */ 1137 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1138 &error_abort); 1139 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 1140 &error_fatal); 1141 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1142 1143 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1144 (uint64_t) PNV_XSCOM_BASE(chip), 1145 PNV_XSCOM_LPC_BASE); 1146 1147 /* 1148 * Interrupt Management Area. This is the memory region holding 1149 * all the Interrupt Control Presenter (ICP) registers 1150 */ 1151 pnv_chip_icp_realize(chip8, &local_err); 1152 if (local_err) { 1153 error_propagate(errp, local_err); 1154 return; 1155 } 1156 1157 /* Create the simplified OCC model */ 1158 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1159 &error_abort); 1160 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1161 if (local_err) { 1162 error_propagate(errp, local_err); 1163 return; 1164 } 1165 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1166 1167 /* OCC SRAM model */ 1168 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1169 &chip8->occ.sram_regs); 1170 1171 /* HOMER */ 1172 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1173 &error_abort); 1174 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1175 &local_err); 1176 if (local_err) { 1177 error_propagate(errp, local_err); 1178 return; 1179 } 1180 /* Homer Xscom region */ 1181 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1182 1183 /* Homer mmio region */ 1184 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1185 &chip8->homer.regs); 1186 1187 /* PHB3 controllers */ 1188 for (i = 0; i < chip->num_phbs; i++) { 1189 PnvPHB3 *phb = &chip8->phbs[i]; 1190 PnvPBCQState *pbcq = &phb->pbcq; 1191 1192 object_property_set_int(OBJECT(phb), i, "index", &error_fatal); 1193 object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id", 1194 &error_fatal); 1195 object_property_set_bool(OBJECT(phb), true, "realized", &local_err); 1196 if (local_err) { 1197 error_propagate(errp, local_err); 1198 return; 1199 } 1200 qdev_set_parent_bus(DEVICE(phb), sysbus_get_default()); 1201 1202 /* Populate the XSCOM address space. */ 1203 pnv_xscom_add_subregion(chip, 1204 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1205 &pbcq->xscom_nest_regs); 1206 pnv_xscom_add_subregion(chip, 1207 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1208 &pbcq->xscom_pci_regs); 1209 pnv_xscom_add_subregion(chip, 1210 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1211 &pbcq->xscom_spci_regs); 1212 } 1213 } 1214 1215 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1216 { 1217 addr &= (PNV_XSCOM_SIZE - 1); 1218 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1219 } 1220 1221 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1222 { 1223 DeviceClass *dc = DEVICE_CLASS(klass); 1224 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1225 1226 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1227 k->cores_mask = POWER8E_CORE_MASK; 1228 k->num_phbs = 3; 1229 k->core_pir = pnv_chip_core_pir_p8; 1230 k->intc_create = pnv_chip_power8_intc_create; 1231 k->intc_reset = pnv_chip_power8_intc_reset; 1232 k->intc_destroy = pnv_chip_power8_intc_destroy; 1233 k->intc_print_info = pnv_chip_power8_intc_print_info; 1234 k->isa_create = pnv_chip_power8_isa_create; 1235 k->dt_populate = pnv_chip_power8_dt_populate; 1236 k->pic_print_info = pnv_chip_power8_pic_print_info; 1237 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1238 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1239 dc->desc = "PowerNV Chip POWER8E"; 1240 1241 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1242 &k->parent_realize); 1243 } 1244 1245 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1246 { 1247 DeviceClass *dc = DEVICE_CLASS(klass); 1248 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1249 1250 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1251 k->cores_mask = POWER8_CORE_MASK; 1252 k->num_phbs = 3; 1253 k->core_pir = pnv_chip_core_pir_p8; 1254 k->intc_create = pnv_chip_power8_intc_create; 1255 k->intc_reset = pnv_chip_power8_intc_reset; 1256 k->intc_destroy = pnv_chip_power8_intc_destroy; 1257 k->intc_print_info = pnv_chip_power8_intc_print_info; 1258 k->isa_create = pnv_chip_power8_isa_create; 1259 k->dt_populate = pnv_chip_power8_dt_populate; 1260 k->pic_print_info = pnv_chip_power8_pic_print_info; 1261 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1262 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1263 dc->desc = "PowerNV Chip POWER8"; 1264 1265 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1266 &k->parent_realize); 1267 } 1268 1269 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1270 { 1271 DeviceClass *dc = DEVICE_CLASS(klass); 1272 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1273 1274 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1275 k->cores_mask = POWER8_CORE_MASK; 1276 k->num_phbs = 3; 1277 k->core_pir = pnv_chip_core_pir_p8; 1278 k->intc_create = pnv_chip_power8_intc_create; 1279 k->intc_reset = pnv_chip_power8_intc_reset; 1280 k->intc_destroy = pnv_chip_power8_intc_destroy; 1281 k->intc_print_info = pnv_chip_power8_intc_print_info; 1282 k->isa_create = pnv_chip_power8nvl_isa_create; 1283 k->dt_populate = pnv_chip_power8_dt_populate; 1284 k->pic_print_info = pnv_chip_power8_pic_print_info; 1285 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1286 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1287 dc->desc = "PowerNV Chip POWER8NVL"; 1288 1289 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1290 &k->parent_realize); 1291 } 1292 1293 static void pnv_chip_power9_instance_init(Object *obj) 1294 { 1295 PnvChip *chip = PNV_CHIP(obj); 1296 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1297 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1298 int i; 1299 1300 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1301 TYPE_PNV_XIVE, &error_abort, NULL); 1302 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1303 "xive-fabric", &error_abort); 1304 1305 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1306 TYPE_PNV9_PSI, &error_abort, NULL); 1307 1308 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1309 TYPE_PNV9_LPC, &error_abort, NULL); 1310 1311 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1312 TYPE_PNV9_OCC, &error_abort, NULL); 1313 1314 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1315 TYPE_PNV9_HOMER, &error_abort, NULL); 1316 1317 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1318 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1319 sizeof(chip9->pecs[i]), TYPE_PNV_PHB4_PEC, 1320 &error_abort, NULL); 1321 } 1322 1323 /* 1324 * Number of PHBs is the chip default 1325 */ 1326 chip->num_phbs = pcc->num_phbs; 1327 } 1328 1329 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1330 { 1331 PnvChip *chip = PNV_CHIP(chip9); 1332 int i; 1333 1334 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1335 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1336 1337 for (i = 0; i < chip9->nr_quads; i++) { 1338 char eq_name[32]; 1339 PnvQuad *eq = &chip9->quads[i]; 1340 PnvCore *pnv_core = chip->cores[i * 4]; 1341 int core_id = CPU_CORE(pnv_core)->core_id; 1342 1343 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1344 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1345 TYPE_PNV_QUAD, &error_fatal, NULL); 1346 1347 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1348 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1349 1350 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1351 &eq->xscom_regs); 1352 } 1353 } 1354 1355 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1356 { 1357 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1358 Error *local_err = NULL; 1359 int i, j; 1360 int phb_id = 0; 1361 1362 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1363 PnvPhb4PecState *pec = &chip9->pecs[i]; 1364 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1365 uint32_t pec_nest_base; 1366 uint32_t pec_pci_base; 1367 1368 object_property_set_int(OBJECT(pec), i, "index", &error_fatal); 1369 /* 1370 * PEC0 -> 1 stack 1371 * PEC1 -> 2 stacks 1372 * PEC2 -> 3 stacks 1373 */ 1374 object_property_set_int(OBJECT(pec), i + 1, "num-stacks", 1375 &error_fatal); 1376 object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id", 1377 &error_fatal); 1378 object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()), 1379 "system-memory", &error_abort); 1380 object_property_set_bool(OBJECT(pec), true, "realized", &local_err); 1381 if (local_err) { 1382 error_propagate(errp, local_err); 1383 return; 1384 } 1385 1386 pec_nest_base = pecc->xscom_nest_base(pec); 1387 pec_pci_base = pecc->xscom_pci_base(pec); 1388 1389 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1390 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1391 1392 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1393 j++, phb_id++) { 1394 PnvPhb4PecStack *stack = &pec->stacks[j]; 1395 Object *obj = OBJECT(&stack->phb); 1396 1397 object_property_set_int(obj, phb_id, "index", &error_fatal); 1398 object_property_set_int(obj, chip->chip_id, "chip-id", 1399 &error_fatal); 1400 object_property_set_int(obj, PNV_PHB4_VERSION, "version", 1401 &error_fatal); 1402 object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id", 1403 &error_fatal); 1404 object_property_set_link(obj, OBJECT(stack), "stack", &error_abort); 1405 object_property_set_bool(obj, true, "realized", &local_err); 1406 if (local_err) { 1407 error_propagate(errp, local_err); 1408 return; 1409 } 1410 qdev_set_parent_bus(DEVICE(obj), sysbus_get_default()); 1411 1412 /* Populate the XSCOM address space. */ 1413 pnv_xscom_add_subregion(chip, 1414 pec_nest_base + 0x40 * (stack->stack_no + 1), 1415 &stack->nest_regs_mr); 1416 pnv_xscom_add_subregion(chip, 1417 pec_pci_base + 0x40 * (stack->stack_no + 1), 1418 &stack->pci_regs_mr); 1419 pnv_xscom_add_subregion(chip, 1420 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1421 0x40 * stack->stack_no, 1422 &stack->phb_regs_mr); 1423 } 1424 } 1425 } 1426 1427 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1428 { 1429 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1430 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1431 PnvChip *chip = PNV_CHIP(dev); 1432 Pnv9Psi *psi9 = &chip9->psi; 1433 Error *local_err = NULL; 1434 1435 /* XSCOM bridge is first */ 1436 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1437 if (local_err) { 1438 error_propagate(errp, local_err); 1439 return; 1440 } 1441 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1442 1443 pcc->parent_realize(dev, &local_err); 1444 if (local_err) { 1445 error_propagate(errp, local_err); 1446 return; 1447 } 1448 1449 pnv_chip_quad_realize(chip9, &local_err); 1450 if (local_err) { 1451 error_propagate(errp, local_err); 1452 return; 1453 } 1454 1455 /* XIVE interrupt controller (POWER9) */ 1456 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1457 "ic-bar", &error_fatal); 1458 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1459 "vc-bar", &error_fatal); 1460 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1461 "pc-bar", &error_fatal); 1462 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1463 "tm-bar", &error_fatal); 1464 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1465 &error_abort); 1466 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1467 &local_err); 1468 if (local_err) { 1469 error_propagate(errp, local_err); 1470 return; 1471 } 1472 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1473 &chip9->xive.xscom_regs); 1474 1475 /* Processor Service Interface (PSI) Host Bridge */ 1476 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1477 "bar", &error_fatal); 1478 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1479 if (local_err) { 1480 error_propagate(errp, local_err); 1481 return; 1482 } 1483 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1484 &PNV_PSI(psi9)->xscom_regs); 1485 1486 /* LPC */ 1487 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1488 &error_abort); 1489 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1490 if (local_err) { 1491 error_propagate(errp, local_err); 1492 return; 1493 } 1494 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1495 &chip9->lpc.xscom_regs); 1496 1497 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1498 (uint64_t) PNV9_LPCM_BASE(chip)); 1499 1500 /* Create the simplified OCC model */ 1501 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1502 &error_abort); 1503 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1504 if (local_err) { 1505 error_propagate(errp, local_err); 1506 return; 1507 } 1508 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1509 1510 /* OCC SRAM model */ 1511 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1512 &chip9->occ.sram_regs); 1513 1514 /* HOMER */ 1515 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1516 &error_abort); 1517 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1518 &local_err); 1519 if (local_err) { 1520 error_propagate(errp, local_err); 1521 return; 1522 } 1523 /* Homer Xscom region */ 1524 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1525 1526 /* Homer mmio region */ 1527 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1528 &chip9->homer.regs); 1529 1530 /* PHBs */ 1531 pnv_chip_power9_phb_realize(chip, &local_err); 1532 if (local_err) { 1533 error_propagate(errp, local_err); 1534 return; 1535 } 1536 } 1537 1538 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1539 { 1540 addr &= (PNV9_XSCOM_SIZE - 1); 1541 return addr >> 3; 1542 } 1543 1544 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1545 { 1546 DeviceClass *dc = DEVICE_CLASS(klass); 1547 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1548 1549 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1550 k->cores_mask = POWER9_CORE_MASK; 1551 k->core_pir = pnv_chip_core_pir_p9; 1552 k->intc_create = pnv_chip_power9_intc_create; 1553 k->intc_reset = pnv_chip_power9_intc_reset; 1554 k->intc_destroy = pnv_chip_power9_intc_destroy; 1555 k->intc_print_info = pnv_chip_power9_intc_print_info; 1556 k->isa_create = pnv_chip_power9_isa_create; 1557 k->dt_populate = pnv_chip_power9_dt_populate; 1558 k->pic_print_info = pnv_chip_power9_pic_print_info; 1559 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1560 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1561 dc->desc = "PowerNV Chip POWER9"; 1562 k->num_phbs = 6; 1563 1564 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1565 &k->parent_realize); 1566 } 1567 1568 static void pnv_chip_power10_instance_init(Object *obj) 1569 { 1570 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1571 1572 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), 1573 TYPE_PNV10_PSI, &error_abort, NULL); 1574 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), 1575 TYPE_PNV10_LPC, &error_abort, NULL); 1576 } 1577 1578 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1579 { 1580 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1581 PnvChip *chip = PNV_CHIP(dev); 1582 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1583 Error *local_err = NULL; 1584 1585 /* XSCOM bridge is first */ 1586 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1587 if (local_err) { 1588 error_propagate(errp, local_err); 1589 return; 1590 } 1591 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1592 1593 pcc->parent_realize(dev, &local_err); 1594 if (local_err) { 1595 error_propagate(errp, local_err); 1596 return; 1597 } 1598 1599 /* Processor Service Interface (PSI) Host Bridge */ 1600 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1601 "bar", &error_fatal); 1602 object_property_set_bool(OBJECT(&chip10->psi), true, "realized", 1603 &local_err); 1604 if (local_err) { 1605 error_propagate(errp, local_err); 1606 return; 1607 } 1608 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1609 &PNV_PSI(&chip10->psi)->xscom_regs); 1610 1611 /* LPC */ 1612 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1613 &error_abort); 1614 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", 1615 &local_err); 1616 if (local_err) { 1617 error_propagate(errp, local_err); 1618 return; 1619 } 1620 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1621 &chip10->lpc.xscom_regs); 1622 1623 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1624 (uint64_t) PNV10_LPCM_BASE(chip)); 1625 } 1626 1627 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1628 { 1629 addr &= (PNV10_XSCOM_SIZE - 1); 1630 return addr >> 3; 1631 } 1632 1633 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1634 { 1635 DeviceClass *dc = DEVICE_CLASS(klass); 1636 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1637 1638 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1639 k->cores_mask = POWER10_CORE_MASK; 1640 k->core_pir = pnv_chip_core_pir_p10; 1641 k->intc_create = pnv_chip_power10_intc_create; 1642 k->intc_reset = pnv_chip_power10_intc_reset; 1643 k->intc_destroy = pnv_chip_power10_intc_destroy; 1644 k->intc_print_info = pnv_chip_power10_intc_print_info; 1645 k->isa_create = pnv_chip_power10_isa_create; 1646 k->dt_populate = pnv_chip_power10_dt_populate; 1647 k->pic_print_info = pnv_chip_power10_pic_print_info; 1648 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1649 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1650 dc->desc = "PowerNV Chip POWER10"; 1651 1652 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1653 &k->parent_realize); 1654 } 1655 1656 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1657 { 1658 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1659 int cores_max; 1660 1661 /* 1662 * No custom mask for this chip, let's use the default one from * 1663 * the chip class 1664 */ 1665 if (!chip->cores_mask) { 1666 chip->cores_mask = pcc->cores_mask; 1667 } 1668 1669 /* filter alien core ids ! some are reserved */ 1670 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1671 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1672 chip->cores_mask); 1673 return; 1674 } 1675 chip->cores_mask &= pcc->cores_mask; 1676 1677 /* now that we have a sane layout, let check the number of cores */ 1678 cores_max = ctpop64(chip->cores_mask); 1679 if (chip->nr_cores > cores_max) { 1680 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1681 cores_max); 1682 return; 1683 } 1684 } 1685 1686 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1687 { 1688 Error *error = NULL; 1689 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1690 const char *typename = pnv_chip_core_typename(chip); 1691 int i, core_hwid; 1692 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1693 1694 if (!object_class_by_name(typename)) { 1695 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1696 return; 1697 } 1698 1699 /* Cores */ 1700 pnv_chip_core_sanitize(chip, &error); 1701 if (error) { 1702 error_propagate(errp, error); 1703 return; 1704 } 1705 1706 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1707 1708 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1709 && (i < chip->nr_cores); core_hwid++) { 1710 char core_name[32]; 1711 PnvCore *pnv_core; 1712 uint64_t xscom_core_base; 1713 1714 if (!(chip->cores_mask & (1ull << core_hwid))) { 1715 continue; 1716 } 1717 1718 pnv_core = PNV_CORE(object_new(typename)); 1719 1720 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1721 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1722 &error_abort); 1723 chip->cores[i] = pnv_core; 1724 object_property_set_int(OBJECT(pnv_core), chip->nr_threads, 1725 "nr-threads", &error_fatal); 1726 object_property_set_int(OBJECT(pnv_core), core_hwid, 1727 CPU_CORE_PROP_CORE_ID, &error_fatal); 1728 object_property_set_int(OBJECT(pnv_core), 1729 pcc->core_pir(chip, core_hwid), 1730 "pir", &error_fatal); 1731 object_property_set_int(OBJECT(pnv_core), pnv->fw_load_addr, 1732 "hrmor", &error_fatal); 1733 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1734 &error_abort); 1735 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1736 &error_fatal); 1737 1738 /* Each core has an XSCOM MMIO region */ 1739 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1740 1741 pnv_xscom_add_subregion(chip, xscom_core_base, 1742 &pnv_core->xscom_regs); 1743 i++; 1744 } 1745 } 1746 1747 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1748 { 1749 PnvChip *chip = PNV_CHIP(dev); 1750 Error *error = NULL; 1751 1752 /* Cores */ 1753 pnv_chip_core_realize(chip, &error); 1754 if (error) { 1755 error_propagate(errp, error); 1756 return; 1757 } 1758 } 1759 1760 static Property pnv_chip_properties[] = { 1761 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1762 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1763 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1764 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1765 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1766 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1767 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1768 DEFINE_PROP_END_OF_LIST(), 1769 }; 1770 1771 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1772 { 1773 DeviceClass *dc = DEVICE_CLASS(klass); 1774 1775 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1776 dc->realize = pnv_chip_realize; 1777 device_class_set_props(dc, pnv_chip_properties); 1778 dc->desc = "PowerNV Chip"; 1779 } 1780 1781 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1782 { 1783 int i, j; 1784 1785 for (i = 0; i < chip->nr_cores; i++) { 1786 PnvCore *pc = chip->cores[i]; 1787 CPUCore *cc = CPU_CORE(pc); 1788 1789 for (j = 0; j < cc->nr_threads; j++) { 1790 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1791 return pc->threads[j]; 1792 } 1793 } 1794 } 1795 return NULL; 1796 } 1797 1798 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1799 { 1800 PnvMachineState *pnv = PNV_MACHINE(xi); 1801 int i, j; 1802 1803 for (i = 0; i < pnv->num_chips; i++) { 1804 PnvChip *chip = pnv->chips[i]; 1805 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1806 1807 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1808 return &chip8->psi.ics; 1809 } 1810 for (j = 0; j < chip->num_phbs; j++) { 1811 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1812 return &chip8->phbs[j].lsis; 1813 } 1814 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1815 return ICS(&chip8->phbs[j].msis); 1816 } 1817 } 1818 } 1819 return NULL; 1820 } 1821 1822 static void pnv_ics_resend(XICSFabric *xi) 1823 { 1824 PnvMachineState *pnv = PNV_MACHINE(xi); 1825 int i, j; 1826 1827 for (i = 0; i < pnv->num_chips; i++) { 1828 PnvChip *chip = pnv->chips[i]; 1829 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1830 1831 ics_resend(&chip8->psi.ics); 1832 for (j = 0; j < chip->num_phbs; j++) { 1833 ics_resend(&chip8->phbs[j].lsis); 1834 ics_resend(ICS(&chip8->phbs[j].msis)); 1835 } 1836 } 1837 } 1838 1839 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1840 { 1841 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1842 1843 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1844 } 1845 1846 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1847 Monitor *mon) 1848 { 1849 PnvMachineState *pnv = PNV_MACHINE(obj); 1850 int i; 1851 CPUState *cs; 1852 1853 CPU_FOREACH(cs) { 1854 PowerPCCPU *cpu = POWERPC_CPU(cs); 1855 1856 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1857 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1858 mon); 1859 } 1860 1861 for (i = 0; i < pnv->num_chips; i++) { 1862 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1863 } 1864 } 1865 1866 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1867 uint8_t nvt_blk, uint32_t nvt_idx, 1868 bool cam_ignore, uint8_t priority, 1869 uint32_t logic_serv, 1870 XiveTCTXMatch *match) 1871 { 1872 PnvMachineState *pnv = PNV_MACHINE(xfb); 1873 int total_count = 0; 1874 int i; 1875 1876 for (i = 0; i < pnv->num_chips; i++) { 1877 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1878 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1879 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1880 int count; 1881 1882 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1883 priority, logic_serv, match); 1884 1885 if (count < 0) { 1886 return count; 1887 } 1888 1889 total_count += count; 1890 } 1891 1892 return total_count; 1893 } 1894 1895 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1896 { 1897 MachineClass *mc = MACHINE_CLASS(oc); 1898 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1899 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1900 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1901 1902 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1903 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1904 1905 xic->icp_get = pnv_icp_get; 1906 xic->ics_get = pnv_ics_get; 1907 xic->ics_resend = pnv_ics_resend; 1908 1909 pmc->compat = compat; 1910 pmc->compat_size = sizeof(compat); 1911 } 1912 1913 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1914 { 1915 MachineClass *mc = MACHINE_CLASS(oc); 1916 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1917 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1918 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1919 1920 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1921 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1922 xfc->match_nvt = pnv_match_nvt; 1923 1924 mc->alias = "powernv"; 1925 1926 pmc->compat = compat; 1927 pmc->compat_size = sizeof(compat); 1928 pmc->dt_power_mgt = pnv_dt_power_mgt; 1929 } 1930 1931 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1932 { 1933 MachineClass *mc = MACHINE_CLASS(oc); 1934 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1935 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1936 1937 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1938 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1939 1940 pmc->compat = compat; 1941 pmc->compat_size = sizeof(compat); 1942 pmc->dt_power_mgt = pnv_dt_power_mgt; 1943 } 1944 1945 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1946 { 1947 PnvMachineState *pnv = PNV_MACHINE(obj); 1948 1949 return !!pnv->fw_load_addr; 1950 } 1951 1952 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1953 { 1954 PnvMachineState *pnv = PNV_MACHINE(obj); 1955 1956 if (value) { 1957 pnv->fw_load_addr = 0x8000000; 1958 } 1959 } 1960 1961 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1962 { 1963 MachineClass *mc = MACHINE_CLASS(oc); 1964 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1965 1966 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1967 mc->init = pnv_init; 1968 mc->reset = pnv_reset; 1969 mc->max_cpus = MAX_CPUS; 1970 /* Pnv provides a AHCI device for storage */ 1971 mc->block_default_type = IF_IDE; 1972 mc->no_parallel = 1; 1973 mc->default_boot_order = NULL; 1974 /* 1975 * RAM defaults to less than 2048 for 32-bit hosts, and large 1976 * enough to fit the maximum initrd size at it's load address 1977 */ 1978 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1979 ispc->print_info = pnv_pic_print_info; 1980 1981 object_class_property_add_bool(oc, "hb-mode", 1982 pnv_machine_get_hb, pnv_machine_set_hb, 1983 &error_abort); 1984 object_class_property_set_description(oc, "hb-mode", 1985 "Use a hostboot like boot loader", 1986 NULL); 1987 } 1988 1989 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1990 { \ 1991 .name = type, \ 1992 .class_init = class_initfn, \ 1993 .parent = TYPE_PNV8_CHIP, \ 1994 } 1995 1996 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1997 { \ 1998 .name = type, \ 1999 .class_init = class_initfn, \ 2000 .parent = TYPE_PNV9_CHIP, \ 2001 } 2002 2003 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2004 { \ 2005 .name = type, \ 2006 .class_init = class_initfn, \ 2007 .parent = TYPE_PNV10_CHIP, \ 2008 } 2009 2010 static const TypeInfo types[] = { 2011 { 2012 .name = MACHINE_TYPE_NAME("powernv10"), 2013 .parent = TYPE_PNV_MACHINE, 2014 .class_init = pnv_machine_power10_class_init, 2015 }, 2016 { 2017 .name = MACHINE_TYPE_NAME("powernv9"), 2018 .parent = TYPE_PNV_MACHINE, 2019 .class_init = pnv_machine_power9_class_init, 2020 .interfaces = (InterfaceInfo[]) { 2021 { TYPE_XIVE_FABRIC }, 2022 { }, 2023 }, 2024 }, 2025 { 2026 .name = MACHINE_TYPE_NAME("powernv8"), 2027 .parent = TYPE_PNV_MACHINE, 2028 .class_init = pnv_machine_power8_class_init, 2029 .interfaces = (InterfaceInfo[]) { 2030 { TYPE_XICS_FABRIC }, 2031 { }, 2032 }, 2033 }, 2034 { 2035 .name = TYPE_PNV_MACHINE, 2036 .parent = TYPE_MACHINE, 2037 .abstract = true, 2038 .instance_size = sizeof(PnvMachineState), 2039 .class_init = pnv_machine_class_init, 2040 .class_size = sizeof(PnvMachineClass), 2041 .interfaces = (InterfaceInfo[]) { 2042 { TYPE_INTERRUPT_STATS_PROVIDER }, 2043 { }, 2044 }, 2045 }, 2046 { 2047 .name = TYPE_PNV_CHIP, 2048 .parent = TYPE_SYS_BUS_DEVICE, 2049 .class_init = pnv_chip_class_init, 2050 .instance_size = sizeof(PnvChip), 2051 .class_size = sizeof(PnvChipClass), 2052 .abstract = true, 2053 }, 2054 2055 /* 2056 * P10 chip and variants 2057 */ 2058 { 2059 .name = TYPE_PNV10_CHIP, 2060 .parent = TYPE_PNV_CHIP, 2061 .instance_init = pnv_chip_power10_instance_init, 2062 .instance_size = sizeof(Pnv10Chip), 2063 }, 2064 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2065 2066 /* 2067 * P9 chip and variants 2068 */ 2069 { 2070 .name = TYPE_PNV9_CHIP, 2071 .parent = TYPE_PNV_CHIP, 2072 .instance_init = pnv_chip_power9_instance_init, 2073 .instance_size = sizeof(Pnv9Chip), 2074 }, 2075 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2076 2077 /* 2078 * P8 chip and variants 2079 */ 2080 { 2081 .name = TYPE_PNV8_CHIP, 2082 .parent = TYPE_PNV_CHIP, 2083 .instance_init = pnv_chip_power8_instance_init, 2084 .instance_size = sizeof(Pnv8Chip), 2085 }, 2086 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2087 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2088 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2089 pnv_chip_power8nvl_class_init), 2090 }; 2091 2092 DEFINE_TYPES(types) 2093