1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 47 #include "hw/ppc/xics.h" 48 #include "hw/qdev-properties.h" 49 #include "hw/ppc/pnv_xscom.h" 50 #include "hw/ppc/pnv_pnor.h" 51 52 #include "hw/isa/isa.h" 53 #include "hw/char/serial.h" 54 #include "hw/rtc/mc146818rtc.h" 55 56 #include <libfdt.h> 57 58 #define FDT_MAX_SIZE (1 * MiB) 59 60 #define FW_FILE_NAME "skiboot.lid" 61 #define FW_LOAD_ADDR 0x0 62 #define FW_MAX_SIZE (16 * MiB) 63 64 #define KERNEL_LOAD_ADDR 0x20000000 65 #define KERNEL_MAX_SIZE (128 * MiB) 66 #define INITRD_LOAD_ADDR 0x28000000 67 #define INITRD_MAX_SIZE (128 * MiB) 68 69 static const char *pnv_chip_core_typename(const PnvChip *o) 70 { 71 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 72 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 73 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 74 const char *core_type = object_class_get_name(object_class_by_name(s)); 75 g_free(s); 76 return core_type; 77 } 78 79 /* 80 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 81 * 4 * 4 sockets * 12 cores * 8 threads = 1536 82 * Let's make it 2^11 83 */ 84 #define MAX_CPUS 2048 85 86 /* 87 * Memory nodes are created by hostboot, one for each range of memory 88 * that has a different "affinity". In practice, it means one range 89 * per chip. 90 */ 91 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 92 { 93 char *mem_name; 94 uint64_t mem_reg_property[2]; 95 int off; 96 97 mem_reg_property[0] = cpu_to_be64(start); 98 mem_reg_property[1] = cpu_to_be64(size); 99 100 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 101 off = fdt_add_subnode(fdt, 0, mem_name); 102 g_free(mem_name); 103 104 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 105 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 106 sizeof(mem_reg_property)))); 107 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 108 } 109 110 static int get_cpus_node(void *fdt) 111 { 112 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 113 114 if (cpus_offset < 0) { 115 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 116 if (cpus_offset) { 117 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 119 } 120 } 121 _FDT(cpus_offset); 122 return cpus_offset; 123 } 124 125 /* 126 * The PowerNV cores (and threads) need to use real HW ids and not an 127 * incremental index like it has been done on other platforms. This HW 128 * id is stored in the CPU PIR, it is used to create cpu nodes in the 129 * device tree, used in XSCOM to address cores and in interrupt 130 * servers. 131 */ 132 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 133 { 134 PowerPCCPU *cpu = pc->threads[0]; 135 CPUState *cs = CPU(cpu); 136 DeviceClass *dc = DEVICE_GET_CLASS(cs); 137 int smt_threads = CPU_CORE(pc)->nr_threads; 138 CPUPPCState *env = &cpu->env; 139 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 140 uint32_t servers_prop[smt_threads]; 141 int i; 142 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 143 0xffffffff, 0xffffffff}; 144 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 145 uint32_t cpufreq = 1000000000; 146 uint32_t page_sizes_prop[64]; 147 size_t page_sizes_prop_size; 148 const uint8_t pa_features[] = { 24, 0, 149 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 150 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 151 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 152 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 153 int offset; 154 char *nodename; 155 int cpus_offset = get_cpus_node(fdt); 156 157 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 158 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 159 _FDT(offset); 160 g_free(nodename); 161 162 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 163 164 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 165 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 166 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 170 env->dcache_line_size))); 171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 172 env->dcache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 174 env->icache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 176 env->icache_line_size))); 177 178 if (pcc->l1_dcache_size) { 179 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 180 pcc->l1_dcache_size))); 181 } else { 182 warn_report("Unknown L1 dcache size for cpu"); 183 } 184 if (pcc->l1_icache_size) { 185 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 186 pcc->l1_icache_size))); 187 } else { 188 warn_report("Unknown L1 icache size for cpu"); 189 } 190 191 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 192 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 194 cpu->hash64_opts->slb_size))); 195 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 196 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 197 198 if (ppc_has_spr(cpu, SPR_PURR)) { 199 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 200 } 201 202 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 204 segs, sizeof(segs)))); 205 } 206 207 /* 208 * Advertise VMX/VSX (vector extensions) if available 209 * 0 / no property == no vector extensions 210 * 1 == VMX / Altivec available 211 * 2 == VSX available 212 */ 213 if (env->insns_flags & PPC_ALTIVEC) { 214 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 215 216 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 217 } 218 219 /* 220 * Advertise DFP (Decimal Floating Point) if available 221 * 0 / no property == no DFP 222 * 1 == DFP available 223 */ 224 if (env->insns_flags2 & PPC2_DFP) { 225 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 226 } 227 228 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 229 sizeof(page_sizes_prop)); 230 if (page_sizes_prop_size) { 231 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 232 page_sizes_prop, page_sizes_prop_size))); 233 } 234 235 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 236 pa_features, sizeof(pa_features)))); 237 238 /* Build interrupt servers properties */ 239 for (i = 0; i < smt_threads; i++) { 240 servers_prop[i] = cpu_to_be32(pc->pir + i); 241 } 242 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 243 servers_prop, sizeof(servers_prop)))); 244 } 245 246 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 247 uint32_t nr_threads) 248 { 249 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 250 char *name; 251 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 252 uint32_t irange[2], i, rsize; 253 uint64_t *reg; 254 int offset; 255 256 irange[0] = cpu_to_be32(pir); 257 irange[1] = cpu_to_be32(nr_threads); 258 259 rsize = sizeof(uint64_t) * 2 * nr_threads; 260 reg = g_malloc(rsize); 261 for (i = 0; i < nr_threads; i++) { 262 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 263 reg[i * 2 + 1] = cpu_to_be64(0x1000); 264 } 265 266 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 267 offset = fdt_add_subnode(fdt, 0, name); 268 _FDT(offset); 269 g_free(name); 270 271 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 272 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 273 _FDT((fdt_setprop_string(fdt, offset, "device_type", 274 "PowerPC-External-Interrupt-Presentation"))); 275 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 276 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 277 irange, sizeof(irange)))); 278 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 280 g_free(reg); 281 } 282 283 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 284 { 285 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 286 int i; 287 288 pnv_dt_xscom(chip, fdt, 0, 289 cpu_to_be64(PNV_XSCOM_BASE(chip)), 290 cpu_to_be64(PNV_XSCOM_SIZE), 291 compat, sizeof(compat)); 292 293 for (i = 0; i < chip->nr_cores; i++) { 294 PnvCore *pnv_core = chip->cores[i]; 295 296 pnv_dt_core(chip, pnv_core, fdt); 297 298 /* Interrupt Control Presenters (ICP). One per core. */ 299 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 300 } 301 302 if (chip->ram_size) { 303 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 304 } 305 } 306 307 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 308 { 309 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 310 int i; 311 312 pnv_dt_xscom(chip, fdt, 0, 313 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 314 cpu_to_be64(PNV9_XSCOM_SIZE), 315 compat, sizeof(compat)); 316 317 for (i = 0; i < chip->nr_cores; i++) { 318 PnvCore *pnv_core = chip->cores[i]; 319 320 pnv_dt_core(chip, pnv_core, fdt); 321 } 322 323 if (chip->ram_size) { 324 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 325 } 326 327 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 328 } 329 330 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 331 { 332 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 333 int i; 334 335 pnv_dt_xscom(chip, fdt, 0, 336 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 337 cpu_to_be64(PNV10_XSCOM_SIZE), 338 compat, sizeof(compat)); 339 340 for (i = 0; i < chip->nr_cores; i++) { 341 PnvCore *pnv_core = chip->cores[i]; 342 343 pnv_dt_core(chip, pnv_core, fdt); 344 } 345 346 if (chip->ram_size) { 347 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 348 } 349 350 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 351 } 352 353 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 354 { 355 uint32_t io_base = d->ioport_id; 356 uint32_t io_regs[] = { 357 cpu_to_be32(1), 358 cpu_to_be32(io_base), 359 cpu_to_be32(2) 360 }; 361 char *name; 362 int node; 363 364 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 365 node = fdt_add_subnode(fdt, lpc_off, name); 366 _FDT(node); 367 g_free(name); 368 369 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 370 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 371 } 372 373 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 374 { 375 const char compatible[] = "ns16550\0pnpPNP,501"; 376 uint32_t io_base = d->ioport_id; 377 uint32_t io_regs[] = { 378 cpu_to_be32(1), 379 cpu_to_be32(io_base), 380 cpu_to_be32(8) 381 }; 382 uint32_t irq; 383 char *name; 384 int node; 385 386 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 387 388 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 389 node = fdt_add_subnode(fdt, lpc_off, name); 390 _FDT(node); 391 g_free(name); 392 393 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 394 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 395 sizeof(compatible)))); 396 397 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 398 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 399 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 400 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 401 fdt_get_phandle(fdt, lpc_off)))); 402 403 /* This is needed by Linux */ 404 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 405 } 406 407 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 408 { 409 const char compatible[] = "bt\0ipmi-bt"; 410 uint32_t io_base; 411 uint32_t io_regs[] = { 412 cpu_to_be32(1), 413 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 414 cpu_to_be32(3) 415 }; 416 uint32_t irq; 417 char *name; 418 int node; 419 420 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 421 io_regs[1] = cpu_to_be32(io_base); 422 423 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 424 425 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 426 node = fdt_add_subnode(fdt, lpc_off, name); 427 _FDT(node); 428 g_free(name); 429 430 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 431 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 432 sizeof(compatible)))); 433 434 /* Mark it as reserved to avoid Linux trying to claim it */ 435 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 436 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 437 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 438 fdt_get_phandle(fdt, lpc_off)))); 439 } 440 441 typedef struct ForeachPopulateArgs { 442 void *fdt; 443 int offset; 444 } ForeachPopulateArgs; 445 446 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 447 { 448 ForeachPopulateArgs *args = opaque; 449 ISADevice *d = ISA_DEVICE(dev); 450 451 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 452 pnv_dt_rtc(d, args->fdt, args->offset); 453 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 454 pnv_dt_serial(d, args->fdt, args->offset); 455 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 456 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 457 } else { 458 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 459 d->ioport_id); 460 } 461 462 return 0; 463 } 464 465 /* 466 * The default LPC bus of a multichip system is on chip 0. It's 467 * recognized by the firmware (skiboot) using a "primary" property. 468 */ 469 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 470 { 471 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 472 ForeachPopulateArgs args = { 473 .fdt = fdt, 474 .offset = isa_offset, 475 }; 476 uint32_t phandle; 477 478 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 479 480 phandle = qemu_fdt_alloc_phandle(fdt); 481 assert(phandle > 0); 482 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 483 484 /* 485 * ISA devices are not necessarily parented to the ISA bus so we 486 * can not use object_child_foreach() 487 */ 488 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 489 &args); 490 } 491 492 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 493 { 494 int off; 495 496 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 497 off = fdt_add_subnode(fdt, off, "power-mgt"); 498 499 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 500 } 501 502 static void *pnv_dt_create(MachineState *machine) 503 { 504 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 505 PnvMachineState *pnv = PNV_MACHINE(machine); 506 void *fdt; 507 char *buf; 508 int off; 509 int i; 510 511 fdt = g_malloc0(FDT_MAX_SIZE); 512 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 513 514 /* /qemu node */ 515 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 516 517 /* Root node */ 518 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 519 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 520 _FDT((fdt_setprop_string(fdt, 0, "model", 521 "IBM PowerNV (emulated by qemu)"))); 522 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 523 524 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 525 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 526 if (qemu_uuid_set) { 527 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 528 } 529 g_free(buf); 530 531 off = fdt_add_subnode(fdt, 0, "chosen"); 532 if (machine->kernel_cmdline) { 533 _FDT((fdt_setprop_string(fdt, off, "bootargs", 534 machine->kernel_cmdline))); 535 } 536 537 if (pnv->initrd_size) { 538 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 539 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 540 541 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 542 &start_prop, sizeof(start_prop)))); 543 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 544 &end_prop, sizeof(end_prop)))); 545 } 546 547 /* Populate device tree for each chip */ 548 for (i = 0; i < pnv->num_chips; i++) { 549 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 550 } 551 552 /* Populate ISA devices on chip 0 */ 553 pnv_dt_isa(pnv, fdt); 554 555 if (pnv->bmc) { 556 pnv_dt_bmc_sensors(pnv->bmc, fdt); 557 } 558 559 /* Create an extra node for power management on machines that support it */ 560 if (pmc->dt_power_mgt) { 561 pmc->dt_power_mgt(pnv, fdt); 562 } 563 564 return fdt; 565 } 566 567 static void pnv_powerdown_notify(Notifier *n, void *opaque) 568 { 569 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 570 571 if (pnv->bmc) { 572 pnv_bmc_powerdown(pnv->bmc); 573 } 574 } 575 576 static void pnv_reset(MachineState *machine) 577 { 578 PnvMachineState *pnv = PNV_MACHINE(machine); 579 IPMIBmc *bmc; 580 void *fdt; 581 582 qemu_devices_reset(); 583 584 /* 585 * The machine should provide by default an internal BMC simulator. 586 * If not, try to use the BMC device that was provided on the command 587 * line. 588 */ 589 bmc = pnv_bmc_find(&error_fatal); 590 if (!pnv->bmc) { 591 if (!bmc) { 592 if (!qtest_enabled()) { 593 warn_report("machine has no BMC device. Use '-device " 594 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 595 "to define one"); 596 } 597 } else { 598 pnv_bmc_set_pnor(bmc, pnv->pnor); 599 pnv->bmc = bmc; 600 } 601 } 602 603 fdt = pnv_dt_create(machine); 604 605 /* Pack resulting tree */ 606 _FDT((fdt_pack(fdt))); 607 608 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 609 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 610 611 g_free(fdt); 612 } 613 614 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 615 { 616 Pnv8Chip *chip8 = PNV8_CHIP(chip); 617 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 618 619 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 620 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 621 } 622 623 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 624 { 625 Pnv8Chip *chip8 = PNV8_CHIP(chip); 626 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 627 628 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 629 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 630 } 631 632 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 633 { 634 Pnv9Chip *chip9 = PNV9_CHIP(chip); 635 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 636 637 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 638 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 639 } 640 641 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 642 { 643 Pnv10Chip *chip10 = PNV10_CHIP(chip); 644 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 645 646 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 647 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 648 } 649 650 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 651 { 652 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 653 } 654 655 static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaque) 656 { 657 Monitor *mon = opaque; 658 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); 659 660 if (phb3) { 661 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 662 ics_pic_print_info(&phb3->lsis, mon); 663 } 664 return 0; 665 } 666 667 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 668 { 669 Pnv8Chip *chip8 = PNV8_CHIP(chip); 670 671 ics_pic_print_info(&chip8->psi.ics, mon); 672 object_child_foreach(OBJECT(chip), 673 pnv_chip_power8_pic_print_info_child, mon); 674 } 675 676 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 677 { 678 Monitor *mon = opaque; 679 PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4); 680 681 if (phb4) { 682 pnv_phb4_pic_print_info(phb4, mon); 683 } 684 return 0; 685 } 686 687 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 688 { 689 Pnv9Chip *chip9 = PNV9_CHIP(chip); 690 691 pnv_xive_pic_print_info(&chip9->xive, mon); 692 pnv_psi_pic_print_info(&chip9->psi, mon); 693 694 object_child_foreach_recursive(OBJECT(chip), 695 pnv_chip_power9_pic_print_info_child, mon); 696 } 697 698 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 699 uint32_t core_id) 700 { 701 return PNV_XSCOM_EX_BASE(core_id); 702 } 703 704 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 705 uint32_t core_id) 706 { 707 return PNV9_XSCOM_EC_BASE(core_id); 708 } 709 710 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 711 uint32_t core_id) 712 { 713 return PNV10_XSCOM_EC_BASE(core_id); 714 } 715 716 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 717 { 718 PowerPCCPUClass *ppc_default = 719 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 720 PowerPCCPUClass *ppc = 721 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 722 723 return ppc_default->pvr_match(ppc_default, ppc->pvr); 724 } 725 726 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 727 { 728 ISADevice *dev = isa_new("isa-ipmi-bt"); 729 730 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 731 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 732 isa_realize_and_unref(dev, bus, &error_fatal); 733 } 734 735 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 736 { 737 Pnv10Chip *chip10 = PNV10_CHIP(chip); 738 739 pnv_xive2_pic_print_info(&chip10->xive, mon); 740 pnv_psi_pic_print_info(&chip10->psi, mon); 741 742 object_child_foreach_recursive(OBJECT(chip), 743 pnv_chip_power9_pic_print_info_child, mon); 744 } 745 746 /* Always give the first 1GB to chip 0 else we won't boot */ 747 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 748 { 749 MachineState *machine = MACHINE(pnv); 750 uint64_t ram_per_chip; 751 752 assert(machine->ram_size >= 1 * GiB); 753 754 ram_per_chip = machine->ram_size / pnv->num_chips; 755 if (ram_per_chip >= 1 * GiB) { 756 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 757 } 758 759 assert(pnv->num_chips > 1); 760 761 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 762 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 763 } 764 765 static void pnv_init(MachineState *machine) 766 { 767 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 768 PnvMachineState *pnv = PNV_MACHINE(machine); 769 MachineClass *mc = MACHINE_GET_CLASS(machine); 770 char *fw_filename; 771 long fw_size; 772 uint64_t chip_ram_start = 0; 773 int i; 774 char *chip_typename; 775 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 776 DeviceState *dev; 777 778 if (kvm_enabled()) { 779 error_report("The powernv machine does not work with KVM acceleration"); 780 exit(EXIT_FAILURE); 781 } 782 783 /* allocate RAM */ 784 if (machine->ram_size < mc->default_ram_size) { 785 char *sz = size_to_str(mc->default_ram_size); 786 error_report("Invalid RAM size, should be bigger than %s", sz); 787 g_free(sz); 788 exit(EXIT_FAILURE); 789 } 790 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 791 792 /* 793 * Create our simple PNOR device 794 */ 795 dev = qdev_new(TYPE_PNV_PNOR); 796 if (pnor) { 797 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 798 } 799 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 800 pnv->pnor = PNV_PNOR(dev); 801 802 /* load skiboot firmware */ 803 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 804 if (!fw_filename) { 805 error_report("Could not find OPAL firmware '%s'", bios_name); 806 exit(1); 807 } 808 809 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 810 if (fw_size < 0) { 811 error_report("Could not load OPAL firmware '%s'", fw_filename); 812 exit(1); 813 } 814 g_free(fw_filename); 815 816 /* load kernel */ 817 if (machine->kernel_filename) { 818 long kernel_size; 819 820 kernel_size = load_image_targphys(machine->kernel_filename, 821 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 822 if (kernel_size < 0) { 823 error_report("Could not load kernel '%s'", 824 machine->kernel_filename); 825 exit(1); 826 } 827 } 828 829 /* load initrd */ 830 if (machine->initrd_filename) { 831 pnv->initrd_base = INITRD_LOAD_ADDR; 832 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 833 pnv->initrd_base, INITRD_MAX_SIZE); 834 if (pnv->initrd_size < 0) { 835 error_report("Could not load initial ram disk '%s'", 836 machine->initrd_filename); 837 exit(1); 838 } 839 } 840 841 /* MSIs are supported on this platform */ 842 msi_nonbroken = true; 843 844 /* 845 * Check compatibility of the specified CPU with the machine 846 * default. 847 */ 848 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 849 error_report("invalid CPU model '%s' for %s machine", 850 machine->cpu_type, mc->name); 851 exit(1); 852 } 853 854 /* Create the processor chips */ 855 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 856 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 857 i, machine->cpu_type); 858 if (!object_class_by_name(chip_typename)) { 859 error_report("invalid chip model '%.*s' for %s machine", 860 i, machine->cpu_type, mc->name); 861 exit(1); 862 } 863 864 pnv->num_chips = 865 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 866 /* 867 * TODO: should we decide on how many chips we can create based 868 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 869 */ 870 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 871 error_report("invalid number of chips: '%d'", pnv->num_chips); 872 error_printf( 873 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 874 exit(1); 875 } 876 877 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 878 for (i = 0; i < pnv->num_chips; i++) { 879 char chip_name[32]; 880 Object *chip = OBJECT(qdev_new(chip_typename)); 881 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 882 883 pnv->chips[i] = PNV_CHIP(chip); 884 885 /* Distribute RAM among the chips */ 886 object_property_set_int(chip, "ram-start", chip_ram_start, 887 &error_fatal); 888 object_property_set_int(chip, "ram-size", chip_ram_size, 889 &error_fatal); 890 chip_ram_start += chip_ram_size; 891 892 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 893 object_property_add_child(OBJECT(pnv), chip_name, chip); 894 object_property_set_int(chip, "chip-id", i, &error_fatal); 895 object_property_set_int(chip, "nr-cores", machine->smp.cores, 896 &error_fatal); 897 object_property_set_int(chip, "nr-threads", machine->smp.threads, 898 &error_fatal); 899 /* 900 * The POWER8 machine use the XICS interrupt interface. 901 * Propagate the XICS fabric to the chip and its controllers. 902 */ 903 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 904 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 905 } 906 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 907 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 908 &error_abort); 909 } 910 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 911 } 912 g_free(chip_typename); 913 914 /* Instantiate ISA bus on chip 0 */ 915 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 916 917 /* Create serial port */ 918 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 919 920 /* Create an RTC ISA device too */ 921 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 922 923 /* 924 * Create the machine BMC simulator and the IPMI BT device for 925 * communication with the BMC 926 */ 927 if (defaults_enabled()) { 928 pnv->bmc = pnv_bmc_create(pnv->pnor); 929 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 930 } 931 932 /* 933 * The PNOR is mapped on the LPC FW address space by the BMC. 934 * Since we can not reach the remote BMC machine with LPC memops, 935 * map it always for now. 936 */ 937 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 938 &pnv->pnor->mmio); 939 940 /* 941 * OpenPOWER systems use a IPMI SEL Event message to notify the 942 * host to powerdown 943 */ 944 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 945 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 946 } 947 948 /* 949 * 0:21 Reserved - Read as zeros 950 * 22:24 Chip ID 951 * 25:28 Core number 952 * 29:31 Thread ID 953 */ 954 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 955 { 956 return (chip->chip_id << 7) | (core_id << 3); 957 } 958 959 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 960 Error **errp) 961 { 962 Pnv8Chip *chip8 = PNV8_CHIP(chip); 963 Error *local_err = NULL; 964 Object *obj; 965 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 966 967 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 968 if (local_err) { 969 error_propagate(errp, local_err); 970 return; 971 } 972 973 pnv_cpu->intc = obj; 974 } 975 976 977 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 978 { 979 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 980 981 icp_reset(ICP(pnv_cpu->intc)); 982 } 983 984 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 985 { 986 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 987 988 icp_destroy(ICP(pnv_cpu->intc)); 989 pnv_cpu->intc = NULL; 990 } 991 992 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 993 Monitor *mon) 994 { 995 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 996 } 997 998 /* 999 * 0:48 Reserved - Read as zeroes 1000 * 49:52 Node ID 1001 * 53:55 Chip ID 1002 * 56 Reserved - Read as zero 1003 * 57:61 Core number 1004 * 62:63 Thread ID 1005 * 1006 * We only care about the lower bits. uint32_t is fine for the moment. 1007 */ 1008 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 1009 { 1010 return (chip->chip_id << 8) | (core_id << 2); 1011 } 1012 1013 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1014 { 1015 return (chip->chip_id << 8) | (core_id << 2); 1016 } 1017 1018 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1019 Error **errp) 1020 { 1021 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1022 Error *local_err = NULL; 1023 Object *obj; 1024 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1025 1026 /* 1027 * The core creates its interrupt presenter but the XIVE interrupt 1028 * controller object is initialized afterwards. Hopefully, it's 1029 * only used at runtime. 1030 */ 1031 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1032 &local_err); 1033 if (local_err) { 1034 error_propagate(errp, local_err); 1035 return; 1036 } 1037 1038 pnv_cpu->intc = obj; 1039 } 1040 1041 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1042 { 1043 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1044 1045 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1046 } 1047 1048 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1049 { 1050 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1051 1052 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1053 pnv_cpu->intc = NULL; 1054 } 1055 1056 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1057 Monitor *mon) 1058 { 1059 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1060 } 1061 1062 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1063 Error **errp) 1064 { 1065 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1066 Error *local_err = NULL; 1067 Object *obj; 1068 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1069 1070 /* 1071 * The core creates its interrupt presenter but the XIVE2 interrupt 1072 * controller object is initialized afterwards. Hopefully, it's 1073 * only used at runtime. 1074 */ 1075 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1076 &local_err); 1077 if (local_err) { 1078 error_propagate(errp, local_err); 1079 return; 1080 } 1081 1082 pnv_cpu->intc = obj; 1083 } 1084 1085 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1086 { 1087 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1088 1089 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1090 } 1091 1092 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1093 { 1094 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1095 1096 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1097 pnv_cpu->intc = NULL; 1098 } 1099 1100 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1101 Monitor *mon) 1102 { 1103 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1104 } 1105 1106 /* 1107 * Allowed core identifiers on a POWER8 Processor Chip : 1108 * 1109 * <EX0 reserved> 1110 * EX1 - Venice only 1111 * EX2 - Venice only 1112 * EX3 - Venice only 1113 * EX4 1114 * EX5 1115 * EX6 1116 * <EX7,8 reserved> <reserved> 1117 * EX9 - Venice only 1118 * EX10 - Venice only 1119 * EX11 - Venice only 1120 * EX12 1121 * EX13 1122 * EX14 1123 * <EX15 reserved> 1124 */ 1125 #define POWER8E_CORE_MASK (0x7070ull) 1126 #define POWER8_CORE_MASK (0x7e7eull) 1127 1128 /* 1129 * POWER9 has 24 cores, ids starting at 0x0 1130 */ 1131 #define POWER9_CORE_MASK (0xffffffffffffffull) 1132 1133 1134 #define POWER10_CORE_MASK (0xffffffffffffffull) 1135 1136 static void pnv_chip_power8_instance_init(Object *obj) 1137 { 1138 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1139 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1140 int i; 1141 1142 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1143 (Object **)&chip8->xics, 1144 object_property_allow_set_link, 1145 OBJ_PROP_LINK_STRONG); 1146 1147 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1148 1149 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1150 1151 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1152 1153 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1154 1155 chip8->num_phbs = pcc->num_phbs; 1156 1157 for (i = 0; i < chip8->num_phbs; i++) { 1158 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1159 } 1160 1161 } 1162 1163 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1164 { 1165 PnvChip *chip = PNV_CHIP(chip8); 1166 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1167 int i, j; 1168 char *name; 1169 1170 name = g_strdup_printf("icp-%x", chip->chip_id); 1171 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1172 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1173 g_free(name); 1174 1175 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1176 1177 /* Map the ICP registers for each thread */ 1178 for (i = 0; i < chip->nr_cores; i++) { 1179 PnvCore *pnv_core = chip->cores[i]; 1180 int core_hwid = CPU_CORE(pnv_core)->core_id; 1181 1182 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1183 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1184 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1185 1186 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1187 &icp->mmio); 1188 } 1189 } 1190 } 1191 1192 /* Attach a root port device */ 1193 void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, int index) 1194 { 1195 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name); 1196 g_autofree char *default_id = g_strdup_printf("%s[%d]", name, index); 1197 const char *dev_id = DEVICE(root)->id; 1198 1199 object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id, 1200 OBJECT(root)); 1201 1202 pci_realize_and_unref(root, pci->bus, &error_fatal); 1203 } 1204 1205 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1206 { 1207 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1208 PnvChip *chip = PNV_CHIP(dev); 1209 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1210 Pnv8Psi *psi8 = &chip8->psi; 1211 Error *local_err = NULL; 1212 int i; 1213 1214 assert(chip8->xics); 1215 1216 /* XSCOM bridge is first */ 1217 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1218 if (local_err) { 1219 error_propagate(errp, local_err); 1220 return; 1221 } 1222 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1223 1224 pcc->parent_realize(dev, &local_err); 1225 if (local_err) { 1226 error_propagate(errp, local_err); 1227 return; 1228 } 1229 1230 /* Processor Service Interface (PSI) Host Bridge */ 1231 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1232 &error_fatal); 1233 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1234 OBJECT(chip8->xics), &error_abort); 1235 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1236 return; 1237 } 1238 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1239 &PNV_PSI(psi8)->xscom_regs); 1240 1241 /* Create LPC controller */ 1242 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1243 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1244 1245 chip->fw_mr = &chip8->lpc.isa_fw; 1246 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1247 (uint64_t) PNV_XSCOM_BASE(chip), 1248 PNV_XSCOM_LPC_BASE); 1249 1250 /* 1251 * Interrupt Management Area. This is the memory region holding 1252 * all the Interrupt Control Presenter (ICP) registers 1253 */ 1254 pnv_chip_icp_realize(chip8, &local_err); 1255 if (local_err) { 1256 error_propagate(errp, local_err); 1257 return; 1258 } 1259 1260 /* Create the simplified OCC model */ 1261 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1262 return; 1263 } 1264 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1265 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1266 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); 1267 1268 /* OCC SRAM model */ 1269 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1270 &chip8->occ.sram_regs); 1271 1272 /* HOMER */ 1273 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1274 &error_abort); 1275 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1276 return; 1277 } 1278 /* Homer Xscom region */ 1279 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1280 1281 /* Homer mmio region */ 1282 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1283 &chip8->homer.regs); 1284 1285 /* PHB3 controllers */ 1286 for (i = 0; i < chip8->num_phbs; i++) { 1287 PnvPHB3 *phb = &chip8->phbs[i]; 1288 1289 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1290 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1291 &error_fatal); 1292 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1293 &error_fatal); 1294 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1295 return; 1296 } 1297 } 1298 } 1299 1300 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1301 { 1302 addr &= (PNV_XSCOM_SIZE - 1); 1303 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1304 } 1305 1306 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1307 { 1308 DeviceClass *dc = DEVICE_CLASS(klass); 1309 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1310 1311 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1312 k->cores_mask = POWER8E_CORE_MASK; 1313 k->num_phbs = 3; 1314 k->core_pir = pnv_chip_core_pir_p8; 1315 k->intc_create = pnv_chip_power8_intc_create; 1316 k->intc_reset = pnv_chip_power8_intc_reset; 1317 k->intc_destroy = pnv_chip_power8_intc_destroy; 1318 k->intc_print_info = pnv_chip_power8_intc_print_info; 1319 k->isa_create = pnv_chip_power8_isa_create; 1320 k->dt_populate = pnv_chip_power8_dt_populate; 1321 k->pic_print_info = pnv_chip_power8_pic_print_info; 1322 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1323 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1324 dc->desc = "PowerNV Chip POWER8E"; 1325 1326 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1327 &k->parent_realize); 1328 } 1329 1330 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1331 { 1332 DeviceClass *dc = DEVICE_CLASS(klass); 1333 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1334 1335 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1336 k->cores_mask = POWER8_CORE_MASK; 1337 k->num_phbs = 3; 1338 k->core_pir = pnv_chip_core_pir_p8; 1339 k->intc_create = pnv_chip_power8_intc_create; 1340 k->intc_reset = pnv_chip_power8_intc_reset; 1341 k->intc_destroy = pnv_chip_power8_intc_destroy; 1342 k->intc_print_info = pnv_chip_power8_intc_print_info; 1343 k->isa_create = pnv_chip_power8_isa_create; 1344 k->dt_populate = pnv_chip_power8_dt_populate; 1345 k->pic_print_info = pnv_chip_power8_pic_print_info; 1346 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1347 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1348 dc->desc = "PowerNV Chip POWER8"; 1349 1350 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1351 &k->parent_realize); 1352 } 1353 1354 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1355 { 1356 DeviceClass *dc = DEVICE_CLASS(klass); 1357 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1358 1359 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1360 k->cores_mask = POWER8_CORE_MASK; 1361 k->num_phbs = 4; 1362 k->core_pir = pnv_chip_core_pir_p8; 1363 k->intc_create = pnv_chip_power8_intc_create; 1364 k->intc_reset = pnv_chip_power8_intc_reset; 1365 k->intc_destroy = pnv_chip_power8_intc_destroy; 1366 k->intc_print_info = pnv_chip_power8_intc_print_info; 1367 k->isa_create = pnv_chip_power8nvl_isa_create; 1368 k->dt_populate = pnv_chip_power8_dt_populate; 1369 k->pic_print_info = pnv_chip_power8_pic_print_info; 1370 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1371 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1372 dc->desc = "PowerNV Chip POWER8NVL"; 1373 1374 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1375 &k->parent_realize); 1376 } 1377 1378 static void pnv_chip_power9_instance_init(Object *obj) 1379 { 1380 PnvChip *chip = PNV_CHIP(obj); 1381 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1382 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1383 int i; 1384 1385 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1386 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1387 "xive-fabric"); 1388 1389 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1390 1391 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1392 1393 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1394 1395 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1396 1397 /* Number of PECs is the chip default */ 1398 chip->num_pecs = pcc->num_pecs; 1399 1400 for (i = 0; i < chip->num_pecs; i++) { 1401 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1402 TYPE_PNV_PHB4_PEC); 1403 } 1404 } 1405 1406 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1407 PnvCore *pnv_core) 1408 { 1409 char eq_name[32]; 1410 int core_id = CPU_CORE(pnv_core)->core_id; 1411 1412 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1413 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1414 sizeof(*eq), TYPE_PNV_QUAD, 1415 &error_fatal, NULL); 1416 1417 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1418 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1419 } 1420 1421 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1422 { 1423 PnvChip *chip = PNV_CHIP(chip9); 1424 int i; 1425 1426 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1427 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1428 1429 for (i = 0; i < chip9->nr_quads; i++) { 1430 PnvQuad *eq = &chip9->quads[i]; 1431 1432 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1433 1434 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1435 &eq->xscom_regs); 1436 } 1437 } 1438 1439 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1440 { 1441 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1442 int i; 1443 1444 for (i = 0; i < chip->num_pecs; i++) { 1445 PnvPhb4PecState *pec = &chip9->pecs[i]; 1446 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1447 uint32_t pec_nest_base; 1448 uint32_t pec_pci_base; 1449 1450 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1451 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1452 &error_fatal); 1453 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1454 &error_fatal); 1455 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1456 return; 1457 } 1458 1459 pec_nest_base = pecc->xscom_nest_base(pec); 1460 pec_pci_base = pecc->xscom_pci_base(pec); 1461 1462 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1463 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1464 } 1465 } 1466 1467 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1468 { 1469 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1470 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1471 PnvChip *chip = PNV_CHIP(dev); 1472 Pnv9Psi *psi9 = &chip9->psi; 1473 Error *local_err = NULL; 1474 1475 /* XSCOM bridge is first */ 1476 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1477 if (local_err) { 1478 error_propagate(errp, local_err); 1479 return; 1480 } 1481 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1482 1483 pcc->parent_realize(dev, &local_err); 1484 if (local_err) { 1485 error_propagate(errp, local_err); 1486 return; 1487 } 1488 1489 pnv_chip_quad_realize(chip9, &local_err); 1490 if (local_err) { 1491 error_propagate(errp, local_err); 1492 return; 1493 } 1494 1495 /* XIVE interrupt controller (POWER9) */ 1496 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1497 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1498 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1499 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1500 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1501 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1502 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1503 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1504 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1505 &error_abort); 1506 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1507 return; 1508 } 1509 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1510 &chip9->xive.xscom_regs); 1511 1512 /* Processor Service Interface (PSI) Host Bridge */ 1513 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1514 &error_fatal); 1515 /* This is the only device with 4k ESB pages */ 1516 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1517 &error_fatal); 1518 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1519 return; 1520 } 1521 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1522 &PNV_PSI(psi9)->xscom_regs); 1523 1524 /* LPC */ 1525 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1526 return; 1527 } 1528 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1529 &chip9->lpc.xscom_regs); 1530 1531 chip->fw_mr = &chip9->lpc.isa_fw; 1532 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1533 (uint64_t) PNV9_LPCM_BASE(chip)); 1534 1535 /* Create the simplified OCC model */ 1536 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1537 return; 1538 } 1539 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1540 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1541 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); 1542 1543 /* OCC SRAM model */ 1544 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1545 &chip9->occ.sram_regs); 1546 1547 /* HOMER */ 1548 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1549 &error_abort); 1550 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1551 return; 1552 } 1553 /* Homer Xscom region */ 1554 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1555 1556 /* Homer mmio region */ 1557 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1558 &chip9->homer.regs); 1559 1560 /* PEC PHBs */ 1561 pnv_chip_power9_pec_realize(chip, &local_err); 1562 if (local_err) { 1563 error_propagate(errp, local_err); 1564 return; 1565 } 1566 } 1567 1568 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1569 { 1570 addr &= (PNV9_XSCOM_SIZE - 1); 1571 return addr >> 3; 1572 } 1573 1574 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1575 { 1576 DeviceClass *dc = DEVICE_CLASS(klass); 1577 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1578 1579 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1580 k->cores_mask = POWER9_CORE_MASK; 1581 k->core_pir = pnv_chip_core_pir_p9; 1582 k->intc_create = pnv_chip_power9_intc_create; 1583 k->intc_reset = pnv_chip_power9_intc_reset; 1584 k->intc_destroy = pnv_chip_power9_intc_destroy; 1585 k->intc_print_info = pnv_chip_power9_intc_print_info; 1586 k->isa_create = pnv_chip_power9_isa_create; 1587 k->dt_populate = pnv_chip_power9_dt_populate; 1588 k->pic_print_info = pnv_chip_power9_pic_print_info; 1589 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1590 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1591 dc->desc = "PowerNV Chip POWER9"; 1592 k->num_pecs = PNV9_CHIP_MAX_PEC; 1593 1594 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1595 &k->parent_realize); 1596 } 1597 1598 static void pnv_chip_power10_instance_init(Object *obj) 1599 { 1600 PnvChip *chip = PNV_CHIP(obj); 1601 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1602 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1603 int i; 1604 1605 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1606 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1607 "xive-fabric"); 1608 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1609 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1610 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1611 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1612 1613 chip->num_pecs = pcc->num_pecs; 1614 1615 for (i = 0; i < chip->num_pecs; i++) { 1616 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1617 TYPE_PNV_PHB5_PEC); 1618 } 1619 } 1620 1621 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1622 { 1623 PnvChip *chip = PNV_CHIP(chip10); 1624 int i; 1625 1626 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1627 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1628 1629 for (i = 0; i < chip10->nr_quads; i++) { 1630 PnvQuad *eq = &chip10->quads[i]; 1631 1632 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1633 1634 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1635 &eq->xscom_regs); 1636 } 1637 } 1638 1639 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1640 { 1641 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1642 int i; 1643 1644 for (i = 0; i < chip->num_pecs; i++) { 1645 PnvPhb4PecState *pec = &chip10->pecs[i]; 1646 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1647 uint32_t pec_nest_base; 1648 uint32_t pec_pci_base; 1649 1650 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1651 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1652 &error_fatal); 1653 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1654 &error_fatal); 1655 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1656 return; 1657 } 1658 1659 pec_nest_base = pecc->xscom_nest_base(pec); 1660 pec_pci_base = pecc->xscom_pci_base(pec); 1661 1662 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1663 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1664 } 1665 } 1666 1667 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1668 { 1669 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1670 PnvChip *chip = PNV_CHIP(dev); 1671 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1672 Error *local_err = NULL; 1673 1674 /* XSCOM bridge is first */ 1675 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1676 if (local_err) { 1677 error_propagate(errp, local_err); 1678 return; 1679 } 1680 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1681 1682 pcc->parent_realize(dev, &local_err); 1683 if (local_err) { 1684 error_propagate(errp, local_err); 1685 return; 1686 } 1687 1688 pnv_chip_power10_quad_realize(chip10, &local_err); 1689 if (local_err) { 1690 error_propagate(errp, local_err); 1691 return; 1692 } 1693 1694 /* XIVE2 interrupt controller (POWER10) */ 1695 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1696 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1697 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1698 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1699 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1700 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1701 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1702 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1703 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1704 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1705 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1706 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1707 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1708 &error_abort); 1709 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1710 return; 1711 } 1712 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1713 &chip10->xive.xscom_regs); 1714 1715 /* Processor Service Interface (PSI) Host Bridge */ 1716 object_property_set_int(OBJECT(&chip10->psi), "bar", 1717 PNV10_PSIHB_BASE(chip), &error_fatal); 1718 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1719 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1720 &error_fatal); 1721 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1722 return; 1723 } 1724 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1725 &PNV_PSI(&chip10->psi)->xscom_regs); 1726 1727 /* LPC */ 1728 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1729 return; 1730 } 1731 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1732 &chip10->lpc.xscom_regs); 1733 1734 chip->fw_mr = &chip10->lpc.isa_fw; 1735 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1736 (uint64_t) PNV10_LPCM_BASE(chip)); 1737 1738 /* Create the simplified OCC model */ 1739 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1740 return; 1741 } 1742 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1743 &chip10->occ.xscom_regs); 1744 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1745 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1746 1747 /* OCC SRAM model */ 1748 memory_region_add_subregion(get_system_memory(), 1749 PNV10_OCC_SENSOR_BASE(chip), 1750 &chip10->occ.sram_regs); 1751 1752 /* HOMER */ 1753 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1754 &error_abort); 1755 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1756 return; 1757 } 1758 /* Homer Xscom region */ 1759 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1760 &chip10->homer.pba_regs); 1761 1762 /* Homer mmio region */ 1763 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1764 &chip10->homer.regs); 1765 1766 /* PHBs */ 1767 pnv_chip_power10_phb_realize(chip, &local_err); 1768 if (local_err) { 1769 error_propagate(errp, local_err); 1770 return; 1771 } 1772 } 1773 1774 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1775 { 1776 addr &= (PNV10_XSCOM_SIZE - 1); 1777 return addr >> 3; 1778 } 1779 1780 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1781 { 1782 DeviceClass *dc = DEVICE_CLASS(klass); 1783 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1784 1785 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1786 k->cores_mask = POWER10_CORE_MASK; 1787 k->core_pir = pnv_chip_core_pir_p10; 1788 k->intc_create = pnv_chip_power10_intc_create; 1789 k->intc_reset = pnv_chip_power10_intc_reset; 1790 k->intc_destroy = pnv_chip_power10_intc_destroy; 1791 k->intc_print_info = pnv_chip_power10_intc_print_info; 1792 k->isa_create = pnv_chip_power10_isa_create; 1793 k->dt_populate = pnv_chip_power10_dt_populate; 1794 k->pic_print_info = pnv_chip_power10_pic_print_info; 1795 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1796 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1797 dc->desc = "PowerNV Chip POWER10"; 1798 k->num_pecs = PNV10_CHIP_MAX_PEC; 1799 1800 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1801 &k->parent_realize); 1802 } 1803 1804 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1805 { 1806 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1807 int cores_max; 1808 1809 /* 1810 * No custom mask for this chip, let's use the default one from * 1811 * the chip class 1812 */ 1813 if (!chip->cores_mask) { 1814 chip->cores_mask = pcc->cores_mask; 1815 } 1816 1817 /* filter alien core ids ! some are reserved */ 1818 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1819 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1820 chip->cores_mask); 1821 return; 1822 } 1823 chip->cores_mask &= pcc->cores_mask; 1824 1825 /* now that we have a sane layout, let check the number of cores */ 1826 cores_max = ctpop64(chip->cores_mask); 1827 if (chip->nr_cores > cores_max) { 1828 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1829 cores_max); 1830 return; 1831 } 1832 } 1833 1834 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1835 { 1836 Error *error = NULL; 1837 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1838 const char *typename = pnv_chip_core_typename(chip); 1839 int i, core_hwid; 1840 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1841 1842 if (!object_class_by_name(typename)) { 1843 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1844 return; 1845 } 1846 1847 /* Cores */ 1848 pnv_chip_core_sanitize(chip, &error); 1849 if (error) { 1850 error_propagate(errp, error); 1851 return; 1852 } 1853 1854 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1855 1856 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1857 && (i < chip->nr_cores); core_hwid++) { 1858 char core_name[32]; 1859 PnvCore *pnv_core; 1860 uint64_t xscom_core_base; 1861 1862 if (!(chip->cores_mask & (1ull << core_hwid))) { 1863 continue; 1864 } 1865 1866 pnv_core = PNV_CORE(object_new(typename)); 1867 1868 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1869 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1870 chip->cores[i] = pnv_core; 1871 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1872 chip->nr_threads, &error_fatal); 1873 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1874 core_hwid, &error_fatal); 1875 object_property_set_int(OBJECT(pnv_core), "pir", 1876 pcc->core_pir(chip, core_hwid), &error_fatal); 1877 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1878 &error_fatal); 1879 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1880 &error_abort); 1881 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1882 1883 /* Each core has an XSCOM MMIO region */ 1884 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1885 1886 pnv_xscom_add_subregion(chip, xscom_core_base, 1887 &pnv_core->xscom_regs); 1888 i++; 1889 } 1890 } 1891 1892 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1893 { 1894 PnvChip *chip = PNV_CHIP(dev); 1895 Error *error = NULL; 1896 1897 /* Cores */ 1898 pnv_chip_core_realize(chip, &error); 1899 if (error) { 1900 error_propagate(errp, error); 1901 return; 1902 } 1903 } 1904 1905 static Property pnv_chip_properties[] = { 1906 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1907 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1908 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1909 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1910 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1911 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1912 DEFINE_PROP_END_OF_LIST(), 1913 }; 1914 1915 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1916 { 1917 DeviceClass *dc = DEVICE_CLASS(klass); 1918 1919 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1920 dc->realize = pnv_chip_realize; 1921 device_class_set_props(dc, pnv_chip_properties); 1922 dc->desc = "PowerNV Chip"; 1923 } 1924 1925 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1926 { 1927 int i, j; 1928 1929 for (i = 0; i < chip->nr_cores; i++) { 1930 PnvCore *pc = chip->cores[i]; 1931 CPUCore *cc = CPU_CORE(pc); 1932 1933 for (j = 0; j < cc->nr_threads; j++) { 1934 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1935 return pc->threads[j]; 1936 } 1937 } 1938 } 1939 return NULL; 1940 } 1941 1942 typedef struct ForeachPhb3Args { 1943 int irq; 1944 ICSState *ics; 1945 } ForeachPhb3Args; 1946 1947 static int pnv_ics_get_child(Object *child, void *opaque) 1948 { 1949 ForeachPhb3Args *args = opaque; 1950 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); 1951 1952 if (phb3) { 1953 if (ics_valid_irq(&phb3->lsis, args->irq)) { 1954 args->ics = &phb3->lsis; 1955 } 1956 if (ics_valid_irq(ICS(&phb3->msis), args->irq)) { 1957 args->ics = ICS(&phb3->msis); 1958 } 1959 } 1960 return args->ics ? 1 : 0; 1961 } 1962 1963 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1964 { 1965 PnvMachineState *pnv = PNV_MACHINE(xi); 1966 ForeachPhb3Args args = { irq, NULL }; 1967 int i; 1968 1969 for (i = 0; i < pnv->num_chips; i++) { 1970 PnvChip *chip = pnv->chips[i]; 1971 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1972 1973 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1974 return &chip8->psi.ics; 1975 } 1976 1977 object_child_foreach(OBJECT(chip), pnv_ics_get_child, &args); 1978 if (args.ics) { 1979 return args.ics; 1980 } 1981 } 1982 return NULL; 1983 } 1984 1985 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 1986 { 1987 int i; 1988 1989 for (i = 0; i < pnv->num_chips; i++) { 1990 PnvChip *chip = pnv->chips[i]; 1991 if (chip->chip_id == chip_id) { 1992 return chip; 1993 } 1994 } 1995 return NULL; 1996 } 1997 1998 static int pnv_ics_resend_child(Object *child, void *opaque) 1999 { 2000 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); 2001 2002 if (phb3) { 2003 ics_resend(&phb3->lsis); 2004 ics_resend(ICS(&phb3->msis)); 2005 } 2006 return 0; 2007 } 2008 2009 static void pnv_ics_resend(XICSFabric *xi) 2010 { 2011 PnvMachineState *pnv = PNV_MACHINE(xi); 2012 int i; 2013 2014 for (i = 0; i < pnv->num_chips; i++) { 2015 PnvChip *chip = pnv->chips[i]; 2016 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2017 2018 ics_resend(&chip8->psi.ics); 2019 object_child_foreach(OBJECT(chip), pnv_ics_resend_child, NULL); 2020 } 2021 } 2022 2023 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2024 { 2025 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2026 2027 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2028 } 2029 2030 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2031 Monitor *mon) 2032 { 2033 PnvMachineState *pnv = PNV_MACHINE(obj); 2034 int i; 2035 CPUState *cs; 2036 2037 CPU_FOREACH(cs) { 2038 PowerPCCPU *cpu = POWERPC_CPU(cs); 2039 2040 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2041 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2042 mon); 2043 } 2044 2045 for (i = 0; i < pnv->num_chips; i++) { 2046 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2047 } 2048 } 2049 2050 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2051 uint8_t nvt_blk, uint32_t nvt_idx, 2052 bool cam_ignore, uint8_t priority, 2053 uint32_t logic_serv, 2054 XiveTCTXMatch *match) 2055 { 2056 PnvMachineState *pnv = PNV_MACHINE(xfb); 2057 int total_count = 0; 2058 int i; 2059 2060 for (i = 0; i < pnv->num_chips; i++) { 2061 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2062 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2063 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2064 int count; 2065 2066 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2067 priority, logic_serv, match); 2068 2069 if (count < 0) { 2070 return count; 2071 } 2072 2073 total_count += count; 2074 } 2075 2076 return total_count; 2077 } 2078 2079 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2080 uint8_t nvt_blk, uint32_t nvt_idx, 2081 bool cam_ignore, uint8_t priority, 2082 uint32_t logic_serv, 2083 XiveTCTXMatch *match) 2084 { 2085 PnvMachineState *pnv = PNV_MACHINE(xfb); 2086 int total_count = 0; 2087 int i; 2088 2089 for (i = 0; i < pnv->num_chips; i++) { 2090 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2091 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2092 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2093 int count; 2094 2095 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2096 priority, logic_serv, match); 2097 2098 if (count < 0) { 2099 return count; 2100 } 2101 2102 total_count += count; 2103 } 2104 2105 return total_count; 2106 } 2107 2108 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2109 { 2110 MachineClass *mc = MACHINE_CLASS(oc); 2111 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2112 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2113 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2114 2115 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2116 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2117 2118 xic->icp_get = pnv_icp_get; 2119 xic->ics_get = pnv_ics_get; 2120 xic->ics_resend = pnv_ics_resend; 2121 2122 pmc->compat = compat; 2123 pmc->compat_size = sizeof(compat); 2124 } 2125 2126 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2127 { 2128 MachineClass *mc = MACHINE_CLASS(oc); 2129 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2130 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2131 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2132 2133 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2134 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 2135 xfc->match_nvt = pnv_match_nvt; 2136 2137 mc->alias = "powernv"; 2138 2139 pmc->compat = compat; 2140 pmc->compat_size = sizeof(compat); 2141 pmc->dt_power_mgt = pnv_dt_power_mgt; 2142 } 2143 2144 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2145 { 2146 MachineClass *mc = MACHINE_CLASS(oc); 2147 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2148 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2149 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2150 2151 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2152 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2153 2154 pmc->compat = compat; 2155 pmc->compat_size = sizeof(compat); 2156 pmc->dt_power_mgt = pnv_dt_power_mgt; 2157 2158 xfc->match_nvt = pnv10_xive_match_nvt; 2159 } 2160 2161 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2162 { 2163 PnvMachineState *pnv = PNV_MACHINE(obj); 2164 2165 return !!pnv->fw_load_addr; 2166 } 2167 2168 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2169 { 2170 PnvMachineState *pnv = PNV_MACHINE(obj); 2171 2172 if (value) { 2173 pnv->fw_load_addr = 0x8000000; 2174 } 2175 } 2176 2177 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2178 { 2179 PowerPCCPU *cpu = POWERPC_CPU(cs); 2180 CPUPPCState *env = &cpu->env; 2181 2182 cpu_synchronize_state(cs); 2183 ppc_cpu_do_system_reset(cs); 2184 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2185 /* 2186 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2187 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2188 * (PPC_BIT(43)). 2189 */ 2190 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2191 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2192 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2193 } 2194 } else { 2195 /* 2196 * For non-powersave system resets, SRR1[42:45] are defined to be 2197 * implementation-dependent. The POWER9 User Manual specifies that 2198 * an external (SCOM driven, which may come from a BMC nmi command or 2199 * another CPU requesting a NMI IPI) system reset exception should be 2200 * 0b0010 (PPC_BIT(44)). 2201 */ 2202 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2203 } 2204 } 2205 2206 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2207 { 2208 CPUState *cs; 2209 2210 CPU_FOREACH(cs) { 2211 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2212 } 2213 } 2214 2215 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2216 { 2217 MachineClass *mc = MACHINE_CLASS(oc); 2218 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2219 NMIClass *nc = NMI_CLASS(oc); 2220 2221 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2222 mc->init = pnv_init; 2223 mc->reset = pnv_reset; 2224 mc->max_cpus = MAX_CPUS; 2225 /* Pnv provides a AHCI device for storage */ 2226 mc->block_default_type = IF_IDE; 2227 mc->no_parallel = 1; 2228 mc->default_boot_order = NULL; 2229 /* 2230 * RAM defaults to less than 2048 for 32-bit hosts, and large 2231 * enough to fit the maximum initrd size at it's load address 2232 */ 2233 mc->default_ram_size = 1 * GiB; 2234 mc->default_ram_id = "pnv.ram"; 2235 ispc->print_info = pnv_pic_print_info; 2236 nc->nmi_monitor_handler = pnv_nmi; 2237 2238 object_class_property_add_bool(oc, "hb-mode", 2239 pnv_machine_get_hb, pnv_machine_set_hb); 2240 object_class_property_set_description(oc, "hb-mode", 2241 "Use a hostboot like boot loader"); 2242 } 2243 2244 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2245 { \ 2246 .name = type, \ 2247 .class_init = class_initfn, \ 2248 .parent = TYPE_PNV8_CHIP, \ 2249 } 2250 2251 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2252 { \ 2253 .name = type, \ 2254 .class_init = class_initfn, \ 2255 .parent = TYPE_PNV9_CHIP, \ 2256 } 2257 2258 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2259 { \ 2260 .name = type, \ 2261 .class_init = class_initfn, \ 2262 .parent = TYPE_PNV10_CHIP, \ 2263 } 2264 2265 static const TypeInfo types[] = { 2266 { 2267 .name = MACHINE_TYPE_NAME("powernv10"), 2268 .parent = TYPE_PNV_MACHINE, 2269 .class_init = pnv_machine_power10_class_init, 2270 .interfaces = (InterfaceInfo[]) { 2271 { TYPE_XIVE_FABRIC }, 2272 { }, 2273 }, 2274 }, 2275 { 2276 .name = MACHINE_TYPE_NAME("powernv9"), 2277 .parent = TYPE_PNV_MACHINE, 2278 .class_init = pnv_machine_power9_class_init, 2279 .interfaces = (InterfaceInfo[]) { 2280 { TYPE_XIVE_FABRIC }, 2281 { }, 2282 }, 2283 }, 2284 { 2285 .name = MACHINE_TYPE_NAME("powernv8"), 2286 .parent = TYPE_PNV_MACHINE, 2287 .class_init = pnv_machine_power8_class_init, 2288 .interfaces = (InterfaceInfo[]) { 2289 { TYPE_XICS_FABRIC }, 2290 { }, 2291 }, 2292 }, 2293 { 2294 .name = TYPE_PNV_MACHINE, 2295 .parent = TYPE_MACHINE, 2296 .abstract = true, 2297 .instance_size = sizeof(PnvMachineState), 2298 .class_init = pnv_machine_class_init, 2299 .class_size = sizeof(PnvMachineClass), 2300 .interfaces = (InterfaceInfo[]) { 2301 { TYPE_INTERRUPT_STATS_PROVIDER }, 2302 { TYPE_NMI }, 2303 { }, 2304 }, 2305 }, 2306 { 2307 .name = TYPE_PNV_CHIP, 2308 .parent = TYPE_SYS_BUS_DEVICE, 2309 .class_init = pnv_chip_class_init, 2310 .instance_size = sizeof(PnvChip), 2311 .class_size = sizeof(PnvChipClass), 2312 .abstract = true, 2313 }, 2314 2315 /* 2316 * P10 chip and variants 2317 */ 2318 { 2319 .name = TYPE_PNV10_CHIP, 2320 .parent = TYPE_PNV_CHIP, 2321 .instance_init = pnv_chip_power10_instance_init, 2322 .instance_size = sizeof(Pnv10Chip), 2323 }, 2324 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2325 2326 /* 2327 * P9 chip and variants 2328 */ 2329 { 2330 .name = TYPE_PNV9_CHIP, 2331 .parent = TYPE_PNV_CHIP, 2332 .instance_init = pnv_chip_power9_instance_init, 2333 .instance_size = sizeof(Pnv9Chip), 2334 }, 2335 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2336 2337 /* 2338 * P8 chip and variants 2339 */ 2340 { 2341 .name = TYPE_PNV8_CHIP, 2342 .parent = TYPE_PNV_CHIP, 2343 .instance_init = pnv_chip_power8_instance_init, 2344 .instance_size = sizeof(Pnv8Chip), 2345 }, 2346 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2347 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2348 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2349 pnv_chip_power8nvl_class_init), 2350 }; 2351 2352 DEFINE_TYPES(types) 2353