1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "sysemu/sysemu.h" 23 #include "sysemu/numa.h" 24 #include "sysemu/cpus.h" 25 #include "hw/hw.h" 26 #include "target/ppc/cpu.h" 27 #include "qemu/log.h" 28 #include "hw/ppc/fdt.h" 29 #include "hw/ppc/ppc.h" 30 #include "hw/ppc/pnv.h" 31 #include "hw/ppc/pnv_core.h" 32 #include "hw/loader.h" 33 #include "exec/address-spaces.h" 34 #include "qemu/cutils.h" 35 #include "qapi/visitor.h" 36 #include "monitor/monitor.h" 37 #include "hw/intc/intc.h" 38 #include "hw/ipmi/ipmi.h" 39 40 #include "hw/ppc/xics.h" 41 #include "hw/ppc/pnv_xscom.h" 42 43 #include "hw/isa/isa.h" 44 #include "hw/char/serial.h" 45 #include "hw/timer/mc146818rtc.h" 46 47 #include <libfdt.h> 48 49 #define FDT_MAX_SIZE 0x00100000 50 51 #define FW_FILE_NAME "skiboot.lid" 52 #define FW_LOAD_ADDR 0x0 53 #define FW_MAX_SIZE 0x00400000 54 55 #define KERNEL_LOAD_ADDR 0x20000000 56 #define INITRD_LOAD_ADDR 0x40000000 57 58 /* 59 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 60 * 4 * 4 sockets * 12 cores * 8 threads = 1536 61 * Let's make it 2^11 62 */ 63 #define MAX_CPUS 2048 64 65 /* 66 * Memory nodes are created by hostboot, one for each range of memory 67 * that has a different "affinity". In practice, it means one range 68 * per chip. 69 */ 70 static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start, 71 hwaddr size) 72 { 73 char *mem_name; 74 uint64_t mem_reg_property[2]; 75 int off; 76 77 mem_reg_property[0] = cpu_to_be64(start); 78 mem_reg_property[1] = cpu_to_be64(size); 79 80 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 81 off = fdt_add_subnode(fdt, 0, mem_name); 82 g_free(mem_name); 83 84 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 85 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 86 sizeof(mem_reg_property)))); 87 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 88 } 89 90 static int get_cpus_node(void *fdt) 91 { 92 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 93 94 if (cpus_offset < 0) { 95 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 96 "cpus"); 97 if (cpus_offset) { 98 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 99 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 100 } 101 } 102 _FDT(cpus_offset); 103 return cpus_offset; 104 } 105 106 /* 107 * The PowerNV cores (and threads) need to use real HW ids and not an 108 * incremental index like it has been done on other platforms. This HW 109 * id is stored in the CPU PIR, it is used to create cpu nodes in the 110 * device tree, used in XSCOM to address cores and in interrupt 111 * servers. 112 */ 113 static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt) 114 { 115 CPUState *cs = CPU(DEVICE(pc->threads)); 116 DeviceClass *dc = DEVICE_GET_CLASS(cs); 117 PowerPCCPU *cpu = POWERPC_CPU(cs); 118 int smt_threads = CPU_CORE(pc)->nr_threads; 119 CPUPPCState *env = &cpu->env; 120 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 121 uint32_t servers_prop[smt_threads]; 122 int i; 123 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 124 0xffffffff, 0xffffffff}; 125 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 126 uint32_t cpufreq = 1000000000; 127 uint32_t page_sizes_prop[64]; 128 size_t page_sizes_prop_size; 129 const uint8_t pa_features[] = { 24, 0, 130 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 131 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 132 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 133 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 134 int offset; 135 char *nodename; 136 int cpus_offset = get_cpus_node(fdt); 137 138 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 139 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 140 _FDT(offset); 141 g_free(nodename); 142 143 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 144 145 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 146 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 147 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 148 149 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 150 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 151 env->dcache_line_size))); 152 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 153 env->dcache_line_size))); 154 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 155 env->icache_line_size))); 156 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 157 env->icache_line_size))); 158 159 if (pcc->l1_dcache_size) { 160 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 161 pcc->l1_dcache_size))); 162 } else { 163 error_report("Warning: Unknown L1 dcache size for cpu"); 164 } 165 if (pcc->l1_icache_size) { 166 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 167 pcc->l1_icache_size))); 168 } else { 169 error_report("Warning: Unknown L1 icache size for cpu"); 170 } 171 172 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 173 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 174 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 175 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 176 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 177 178 if (env->spr_cb[SPR_PURR].oea_read) { 179 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 180 } 181 182 if (env->mmu_model & POWERPC_MMU_1TSEG) { 183 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 184 segs, sizeof(segs)))); 185 } 186 187 /* Advertise VMX/VSX (vector extensions) if available 188 * 0 / no property == no vector extensions 189 * 1 == VMX / Altivec available 190 * 2 == VSX available */ 191 if (env->insns_flags & PPC_ALTIVEC) { 192 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 193 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 195 } 196 197 /* Advertise DFP (Decimal Floating Point) if available 198 * 0 / no property == no DFP 199 * 1 == DFP available */ 200 if (env->insns_flags2 & PPC2_DFP) { 201 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 202 } 203 204 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 205 sizeof(page_sizes_prop)); 206 if (page_sizes_prop_size) { 207 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 208 page_sizes_prop, page_sizes_prop_size))); 209 } 210 211 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 212 pa_features, sizeof(pa_features)))); 213 214 /* Build interrupt servers properties */ 215 for (i = 0; i < smt_threads; i++) { 216 servers_prop[i] = cpu_to_be32(pc->pir + i); 217 } 218 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 219 servers_prop, sizeof(servers_prop)))); 220 } 221 222 static void powernv_populate_icp(PnvChip *chip, void *fdt, uint32_t pir, 223 uint32_t nr_threads) 224 { 225 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 226 char *name; 227 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 228 uint32_t irange[2], i, rsize; 229 uint64_t *reg; 230 int offset; 231 232 irange[0] = cpu_to_be32(pir); 233 irange[1] = cpu_to_be32(nr_threads); 234 235 rsize = sizeof(uint64_t) * 2 * nr_threads; 236 reg = g_malloc(rsize); 237 for (i = 0; i < nr_threads; i++) { 238 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 239 reg[i * 2 + 1] = cpu_to_be64(0x1000); 240 } 241 242 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 243 offset = fdt_add_subnode(fdt, 0, name); 244 _FDT(offset); 245 g_free(name); 246 247 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 248 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 249 _FDT((fdt_setprop_string(fdt, offset, "device_type", 250 "PowerPC-External-Interrupt-Presentation"))); 251 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 252 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 253 irange, sizeof(irange)))); 254 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 255 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 256 g_free(reg); 257 } 258 259 static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt) 260 { 261 char *name; 262 int offset; 263 264 name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 265 (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE); 266 offset = fdt_path_offset(fdt, name); 267 g_free(name); 268 return offset; 269 } 270 271 static void powernv_populate_chip(PnvChip *chip, void *fdt) 272 { 273 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 274 char *typename = pnv_core_typename(pcc->cpu_model); 275 size_t typesize = object_type_get_instance_size(typename); 276 int i; 277 278 pnv_xscom_populate(chip, fdt, 0); 279 280 /* The default LPC bus of a multichip system is on chip 0. It's 281 * recognized by the firmware (skiboot) using a "primary" 282 * property. 283 */ 284 if (chip->chip_id == 0x0) { 285 int lpc_offset = pnv_chip_lpc_offset(chip, fdt); 286 287 _FDT((fdt_setprop(fdt, lpc_offset, "primary", NULL, 0))); 288 } 289 290 for (i = 0; i < chip->nr_cores; i++) { 291 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 292 293 powernv_create_core_node(chip, pnv_core, fdt); 294 295 /* Interrupt Control Presenters (ICP). One per core. */ 296 powernv_populate_icp(chip, fdt, pnv_core->pir, 297 CPU_CORE(pnv_core)->nr_threads); 298 } 299 300 if (chip->ram_size) { 301 powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start, 302 chip->ram_size); 303 } 304 g_free(typename); 305 } 306 307 static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off) 308 { 309 uint32_t io_base = d->ioport_id; 310 uint32_t io_regs[] = { 311 cpu_to_be32(1), 312 cpu_to_be32(io_base), 313 cpu_to_be32(2) 314 }; 315 char *name; 316 int node; 317 318 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 319 node = fdt_add_subnode(fdt, lpc_off, name); 320 _FDT(node); 321 g_free(name); 322 323 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 324 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 325 } 326 327 static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off) 328 { 329 const char compatible[] = "ns16550\0pnpPNP,501"; 330 uint32_t io_base = d->ioport_id; 331 uint32_t io_regs[] = { 332 cpu_to_be32(1), 333 cpu_to_be32(io_base), 334 cpu_to_be32(8) 335 }; 336 char *name; 337 int node; 338 339 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 340 node = fdt_add_subnode(fdt, lpc_off, name); 341 _FDT(node); 342 g_free(name); 343 344 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 345 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 346 sizeof(compatible)))); 347 348 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 349 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 350 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 351 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 352 fdt_get_phandle(fdt, lpc_off)))); 353 354 /* This is needed by Linux */ 355 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 356 } 357 358 static void powernv_populate_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 359 { 360 const char compatible[] = "bt\0ipmi-bt"; 361 uint32_t io_base; 362 uint32_t io_regs[] = { 363 cpu_to_be32(1), 364 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 365 cpu_to_be32(3) 366 }; 367 uint32_t irq; 368 char *name; 369 int node; 370 371 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 372 io_regs[1] = cpu_to_be32(io_base); 373 374 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 375 376 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 377 node = fdt_add_subnode(fdt, lpc_off, name); 378 _FDT(node); 379 g_free(name); 380 381 fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)); 382 fdt_setprop(fdt, node, "compatible", compatible, sizeof(compatible)); 383 384 /* Mark it as reserved to avoid Linux trying to claim it */ 385 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 386 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 387 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 388 fdt_get_phandle(fdt, lpc_off)))); 389 } 390 391 typedef struct ForeachPopulateArgs { 392 void *fdt; 393 int offset; 394 } ForeachPopulateArgs; 395 396 static int powernv_populate_isa_device(DeviceState *dev, void *opaque) 397 { 398 ForeachPopulateArgs *args = opaque; 399 ISADevice *d = ISA_DEVICE(dev); 400 401 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 402 powernv_populate_rtc(d, args->fdt, args->offset); 403 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 404 powernv_populate_serial(d, args->fdt, args->offset); 405 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 406 powernv_populate_ipmi_bt(d, args->fdt, args->offset); 407 } else { 408 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 409 d->ioport_id); 410 } 411 412 return 0; 413 } 414 415 static void powernv_populate_isa(ISABus *bus, void *fdt, int lpc_offset) 416 { 417 ForeachPopulateArgs args = { 418 .fdt = fdt, 419 .offset = lpc_offset, 420 }; 421 422 /* ISA devices are not necessarily parented to the ISA bus so we 423 * can not use object_child_foreach() */ 424 qbus_walk_children(BUS(bus), powernv_populate_isa_device, 425 NULL, NULL, NULL, &args); 426 } 427 428 static void *powernv_create_fdt(MachineState *machine) 429 { 430 const char plat_compat[] = "qemu,powernv\0ibm,powernv"; 431 PnvMachineState *pnv = POWERNV_MACHINE(machine); 432 void *fdt; 433 char *buf; 434 int off; 435 int i; 436 int lpc_offset; 437 438 fdt = g_malloc0(FDT_MAX_SIZE); 439 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 440 441 /* Root node */ 442 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 443 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 444 _FDT((fdt_setprop_string(fdt, 0, "model", 445 "IBM PowerNV (emulated by qemu)"))); 446 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat, 447 sizeof(plat_compat)))); 448 449 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 450 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 451 if (qemu_uuid_set) { 452 _FDT((fdt_property_string(fdt, "system-id", buf))); 453 } 454 g_free(buf); 455 456 off = fdt_add_subnode(fdt, 0, "chosen"); 457 if (machine->kernel_cmdline) { 458 _FDT((fdt_setprop_string(fdt, off, "bootargs", 459 machine->kernel_cmdline))); 460 } 461 462 if (pnv->initrd_size) { 463 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 464 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 465 466 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 467 &start_prop, sizeof(start_prop)))); 468 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 469 &end_prop, sizeof(end_prop)))); 470 } 471 472 /* Populate device tree for each chip */ 473 for (i = 0; i < pnv->num_chips; i++) { 474 powernv_populate_chip(pnv->chips[i], fdt); 475 } 476 477 /* Populate ISA devices on chip 0 */ 478 lpc_offset = pnv_chip_lpc_offset(pnv->chips[0], fdt); 479 powernv_populate_isa(pnv->isa_bus, fdt, lpc_offset); 480 481 if (pnv->bmc) { 482 pnv_bmc_populate_sensors(pnv->bmc, fdt); 483 } 484 485 return fdt; 486 } 487 488 static void pnv_powerdown_notify(Notifier *n, void *opaque) 489 { 490 PnvMachineState *pnv = POWERNV_MACHINE(qdev_get_machine()); 491 492 if (pnv->bmc) { 493 pnv_bmc_powerdown(pnv->bmc); 494 } 495 } 496 497 static void ppc_powernv_reset(void) 498 { 499 MachineState *machine = MACHINE(qdev_get_machine()); 500 PnvMachineState *pnv = POWERNV_MACHINE(machine); 501 void *fdt; 502 Object *obj; 503 504 qemu_devices_reset(); 505 506 /* OpenPOWER systems have a BMC, which can be defined on the 507 * command line with: 508 * 509 * -device ipmi-bmc-sim,id=bmc0 510 * 511 * This is the internal simulator but it could also be an external 512 * BMC. 513 */ 514 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); 515 if (obj) { 516 pnv->bmc = IPMI_BMC(obj); 517 } 518 519 fdt = powernv_create_fdt(machine); 520 521 /* Pack resulting tree */ 522 _FDT((fdt_pack(fdt))); 523 524 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 525 } 526 527 static ISABus *pnv_isa_create(PnvChip *chip) 528 { 529 PnvLpcController *lpc = &chip->lpc; 530 ISABus *isa_bus; 531 qemu_irq *irqs; 532 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 533 534 /* let isa_bus_new() create its own bridge on SysBus otherwise 535 * devices speficied on the command line won't find the bus and 536 * will fail to create. 537 */ 538 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, 539 &error_fatal); 540 541 irqs = pnv_lpc_isa_irq_create(lpc, pcc->chip_type, ISA_NUM_IRQS); 542 543 isa_bus_irqs(isa_bus, irqs); 544 return isa_bus; 545 } 546 547 static void ppc_powernv_init(MachineState *machine) 548 { 549 PnvMachineState *pnv = POWERNV_MACHINE(machine); 550 MemoryRegion *ram; 551 char *fw_filename; 552 long fw_size; 553 int i; 554 char *chip_typename; 555 556 /* allocate RAM */ 557 if (machine->ram_size < (1 * G_BYTE)) { 558 error_report("Warning: skiboot may not work with < 1GB of RAM"); 559 } 560 561 ram = g_new(MemoryRegion, 1); 562 memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram", 563 machine->ram_size); 564 memory_region_add_subregion(get_system_memory(), 0, ram); 565 566 /* load skiboot firmware */ 567 if (bios_name == NULL) { 568 bios_name = FW_FILE_NAME; 569 } 570 571 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 572 573 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 574 if (fw_size < 0) { 575 error_report("Could not load OPAL '%s'", fw_filename); 576 exit(1); 577 } 578 g_free(fw_filename); 579 580 /* load kernel */ 581 if (machine->kernel_filename) { 582 long kernel_size; 583 584 kernel_size = load_image_targphys(machine->kernel_filename, 585 KERNEL_LOAD_ADDR, 0x2000000); 586 if (kernel_size < 0) { 587 error_report("Could not load kernel '%s'", 588 machine->kernel_filename); 589 exit(1); 590 } 591 } 592 593 /* load initrd */ 594 if (machine->initrd_filename) { 595 pnv->initrd_base = INITRD_LOAD_ADDR; 596 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 597 pnv->initrd_base, 0x10000000); /* 128MB max */ 598 if (pnv->initrd_size < 0) { 599 error_report("Could not load initial ram disk '%s'", 600 machine->initrd_filename); 601 exit(1); 602 } 603 } 604 605 /* We need some cpu model to instantiate the PnvChip class */ 606 if (machine->cpu_model == NULL) { 607 machine->cpu_model = "POWER8"; 608 } 609 610 /* Create the processor chips */ 611 chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model); 612 if (!object_class_by_name(chip_typename)) { 613 error_report("invalid CPU model '%s' for %s machine", 614 machine->cpu_model, MACHINE_GET_CLASS(machine)->name); 615 exit(1); 616 } 617 618 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 619 for (i = 0; i < pnv->num_chips; i++) { 620 char chip_name[32]; 621 Object *chip = object_new(chip_typename); 622 623 pnv->chips[i] = PNV_CHIP(chip); 624 625 /* TODO: put all the memory in one node on chip 0 until we find a 626 * way to specify different ranges for each chip 627 */ 628 if (i == 0) { 629 object_property_set_int(chip, machine->ram_size, "ram-size", 630 &error_fatal); 631 } 632 633 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 634 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 635 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 636 &error_fatal); 637 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal); 638 object_property_set_bool(chip, true, "realized", &error_fatal); 639 } 640 g_free(chip_typename); 641 642 /* Instantiate ISA bus on chip 0 */ 643 pnv->isa_bus = pnv_isa_create(pnv->chips[0]); 644 645 /* Create serial port */ 646 serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS); 647 648 /* Create an RTC ISA device too */ 649 rtc_init(pnv->isa_bus, 2000, NULL); 650 651 /* OpenPOWER systems use a IPMI SEL Event message to notify the 652 * host to powerdown */ 653 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 654 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 655 } 656 657 /* 658 * 0:21 Reserved - Read as zeros 659 * 22:24 Chip ID 660 * 25:28 Core number 661 * 29:31 Thread ID 662 */ 663 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 664 { 665 return (chip->chip_id << 7) | (core_id << 3); 666 } 667 668 /* 669 * 0:48 Reserved - Read as zeroes 670 * 49:52 Node ID 671 * 53:55 Chip ID 672 * 56 Reserved - Read as zero 673 * 57:61 Core number 674 * 62:63 Thread ID 675 * 676 * We only care about the lower bits. uint32_t is fine for the moment. 677 */ 678 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 679 { 680 return (chip->chip_id << 8) | (core_id << 2); 681 } 682 683 /* Allowed core identifiers on a POWER8 Processor Chip : 684 * 685 * <EX0 reserved> 686 * EX1 - Venice only 687 * EX2 - Venice only 688 * EX3 - Venice only 689 * EX4 690 * EX5 691 * EX6 692 * <EX7,8 reserved> <reserved> 693 * EX9 - Venice only 694 * EX10 - Venice only 695 * EX11 - Venice only 696 * EX12 697 * EX13 698 * EX14 699 * <EX15 reserved> 700 */ 701 #define POWER8E_CORE_MASK (0x7070ull) 702 #define POWER8_CORE_MASK (0x7e7eull) 703 704 /* 705 * POWER9 has 24 cores, ids starting at 0x20 706 */ 707 #define POWER9_CORE_MASK (0xffffff00000000ull) 708 709 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 710 { 711 DeviceClass *dc = DEVICE_CLASS(klass); 712 PnvChipClass *k = PNV_CHIP_CLASS(klass); 713 714 k->cpu_model = "POWER8E"; 715 k->chip_type = PNV_CHIP_POWER8E; 716 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 717 k->cores_mask = POWER8E_CORE_MASK; 718 k->core_pir = pnv_chip_core_pir_p8; 719 k->xscom_base = 0x003fc0000000000ull; 720 k->xscom_core_base = 0x10000000ull; 721 dc->desc = "PowerNV Chip POWER8E"; 722 } 723 724 static const TypeInfo pnv_chip_power8e_info = { 725 .name = TYPE_PNV_CHIP_POWER8E, 726 .parent = TYPE_PNV_CHIP, 727 .instance_size = sizeof(PnvChip), 728 .class_init = pnv_chip_power8e_class_init, 729 }; 730 731 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 732 { 733 DeviceClass *dc = DEVICE_CLASS(klass); 734 PnvChipClass *k = PNV_CHIP_CLASS(klass); 735 736 k->cpu_model = "POWER8"; 737 k->chip_type = PNV_CHIP_POWER8; 738 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 739 k->cores_mask = POWER8_CORE_MASK; 740 k->core_pir = pnv_chip_core_pir_p8; 741 k->xscom_base = 0x003fc0000000000ull; 742 k->xscom_core_base = 0x10000000ull; 743 dc->desc = "PowerNV Chip POWER8"; 744 } 745 746 static const TypeInfo pnv_chip_power8_info = { 747 .name = TYPE_PNV_CHIP_POWER8, 748 .parent = TYPE_PNV_CHIP, 749 .instance_size = sizeof(PnvChip), 750 .class_init = pnv_chip_power8_class_init, 751 }; 752 753 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 754 { 755 DeviceClass *dc = DEVICE_CLASS(klass); 756 PnvChipClass *k = PNV_CHIP_CLASS(klass); 757 758 k->cpu_model = "POWER8NVL"; 759 k->chip_type = PNV_CHIP_POWER8NVL; 760 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 761 k->cores_mask = POWER8_CORE_MASK; 762 k->core_pir = pnv_chip_core_pir_p8; 763 k->xscom_base = 0x003fc0000000000ull; 764 k->xscom_core_base = 0x10000000ull; 765 dc->desc = "PowerNV Chip POWER8NVL"; 766 } 767 768 static const TypeInfo pnv_chip_power8nvl_info = { 769 .name = TYPE_PNV_CHIP_POWER8NVL, 770 .parent = TYPE_PNV_CHIP, 771 .instance_size = sizeof(PnvChip), 772 .class_init = pnv_chip_power8nvl_class_init, 773 }; 774 775 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 776 { 777 DeviceClass *dc = DEVICE_CLASS(klass); 778 PnvChipClass *k = PNV_CHIP_CLASS(klass); 779 780 k->cpu_model = "POWER9"; 781 k->chip_type = PNV_CHIP_POWER9; 782 k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ 783 k->cores_mask = POWER9_CORE_MASK; 784 k->core_pir = pnv_chip_core_pir_p9; 785 k->xscom_base = 0x00603fc00000000ull; 786 k->xscom_core_base = 0x0ull; 787 dc->desc = "PowerNV Chip POWER9"; 788 } 789 790 static const TypeInfo pnv_chip_power9_info = { 791 .name = TYPE_PNV_CHIP_POWER9, 792 .parent = TYPE_PNV_CHIP, 793 .instance_size = sizeof(PnvChip), 794 .class_init = pnv_chip_power9_class_init, 795 }; 796 797 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 798 { 799 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 800 int cores_max; 801 802 /* 803 * No custom mask for this chip, let's use the default one from * 804 * the chip class 805 */ 806 if (!chip->cores_mask) { 807 chip->cores_mask = pcc->cores_mask; 808 } 809 810 /* filter alien core ids ! some are reserved */ 811 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 812 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 813 chip->cores_mask); 814 return; 815 } 816 chip->cores_mask &= pcc->cores_mask; 817 818 /* now that we have a sane layout, let check the number of cores */ 819 cores_max = ctpop64(chip->cores_mask); 820 if (chip->nr_cores > cores_max) { 821 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 822 cores_max); 823 return; 824 } 825 } 826 827 static void pnv_chip_init(Object *obj) 828 { 829 PnvChip *chip = PNV_CHIP(obj); 830 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 831 832 chip->xscom_base = pcc->xscom_base; 833 834 object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC); 835 object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); 836 837 object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI); 838 object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL); 839 object_property_add_const_link(OBJECT(&chip->psi), "xics", 840 OBJECT(qdev_get_machine()), &error_abort); 841 842 object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC); 843 object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); 844 object_property_add_const_link(OBJECT(&chip->occ), "psi", 845 OBJECT(&chip->psi), &error_abort); 846 847 /* The LPC controller needs PSI to generate interrupts */ 848 object_property_add_const_link(OBJECT(&chip->lpc), "psi", 849 OBJECT(&chip->psi), &error_abort); 850 } 851 852 static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) 853 { 854 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 855 char *typename = pnv_core_typename(pcc->cpu_model); 856 size_t typesize = object_type_get_instance_size(typename); 857 int i, j; 858 char *name; 859 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 860 861 name = g_strdup_printf("icp-%x", chip->chip_id); 862 memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 863 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio); 864 g_free(name); 865 866 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 867 868 /* Map the ICP registers for each thread */ 869 for (i = 0; i < chip->nr_cores; i++) { 870 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 871 int core_hwid = CPU_CORE(pnv_core)->core_id; 872 873 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 874 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 875 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 876 877 memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->mmio); 878 } 879 } 880 881 g_free(typename); 882 } 883 884 static void pnv_chip_realize(DeviceState *dev, Error **errp) 885 { 886 PnvChip *chip = PNV_CHIP(dev); 887 Error *error = NULL; 888 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 889 char *typename = pnv_core_typename(pcc->cpu_model); 890 size_t typesize = object_type_get_instance_size(typename); 891 int i, core_hwid; 892 893 if (!object_class_by_name(typename)) { 894 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 895 return; 896 } 897 898 /* XSCOM bridge */ 899 pnv_xscom_realize(chip, &error); 900 if (error) { 901 error_propagate(errp, error); 902 return; 903 } 904 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 905 906 /* Cores */ 907 pnv_chip_core_sanitize(chip, &error); 908 if (error) { 909 error_propagate(errp, error); 910 return; 911 } 912 913 chip->cores = g_malloc0(typesize * chip->nr_cores); 914 915 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 916 && (i < chip->nr_cores); core_hwid++) { 917 char core_name[32]; 918 void *pnv_core = chip->cores + i * typesize; 919 920 if (!(chip->cores_mask & (1ull << core_hwid))) { 921 continue; 922 } 923 924 object_initialize(pnv_core, typesize, typename); 925 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 926 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 927 &error_fatal); 928 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads", 929 &error_fatal); 930 object_property_set_int(OBJECT(pnv_core), core_hwid, 931 CPU_CORE_PROP_CORE_ID, &error_fatal); 932 object_property_set_int(OBJECT(pnv_core), 933 pcc->core_pir(chip, core_hwid), 934 "pir", &error_fatal); 935 object_property_add_const_link(OBJECT(pnv_core), "xics", 936 qdev_get_machine(), &error_fatal); 937 object_property_set_bool(OBJECT(pnv_core), true, "realized", 938 &error_fatal); 939 object_unref(OBJECT(pnv_core)); 940 941 /* Each core has an XSCOM MMIO region */ 942 pnv_xscom_add_subregion(chip, 943 PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base, 944 core_hwid), 945 &PNV_CORE(pnv_core)->xscom_regs); 946 i++; 947 } 948 g_free(typename); 949 950 /* Create LPC controller */ 951 object_property_set_bool(OBJECT(&chip->lpc), true, "realized", 952 &error_fatal); 953 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs); 954 955 /* Interrupt Management Area. This is the memory region holding 956 * all the Interrupt Control Presenter (ICP) registers */ 957 pnv_chip_icp_realize(chip, &error); 958 if (error) { 959 error_propagate(errp, error); 960 return; 961 } 962 963 /* Processor Service Interface (PSI) Host Bridge */ 964 object_property_set_int(OBJECT(&chip->psi), PNV_PSIHB_BASE(chip), 965 "bar", &error_fatal); 966 object_property_set_bool(OBJECT(&chip->psi), true, "realized", &error); 967 if (error) { 968 error_propagate(errp, error); 969 return; 970 } 971 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip->psi.xscom_regs); 972 973 /* Create the simplified OCC model */ 974 object_property_set_bool(OBJECT(&chip->occ), true, "realized", &error); 975 if (error) { 976 error_propagate(errp, error); 977 return; 978 } 979 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_regs); 980 } 981 982 static Property pnv_chip_properties[] = { 983 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 984 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 985 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 986 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 987 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 988 DEFINE_PROP_END_OF_LIST(), 989 }; 990 991 static void pnv_chip_class_init(ObjectClass *klass, void *data) 992 { 993 DeviceClass *dc = DEVICE_CLASS(klass); 994 995 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 996 dc->realize = pnv_chip_realize; 997 dc->props = pnv_chip_properties; 998 dc->desc = "PowerNV Chip"; 999 } 1000 1001 static const TypeInfo pnv_chip_info = { 1002 .name = TYPE_PNV_CHIP, 1003 .parent = TYPE_SYS_BUS_DEVICE, 1004 .class_init = pnv_chip_class_init, 1005 .instance_init = pnv_chip_init, 1006 .class_size = sizeof(PnvChipClass), 1007 .abstract = true, 1008 }; 1009 1010 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1011 { 1012 PnvMachineState *pnv = POWERNV_MACHINE(xi); 1013 int i; 1014 1015 for (i = 0; i < pnv->num_chips; i++) { 1016 if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) { 1017 return &pnv->chips[i]->psi.ics; 1018 } 1019 } 1020 return NULL; 1021 } 1022 1023 static void pnv_ics_resend(XICSFabric *xi) 1024 { 1025 PnvMachineState *pnv = POWERNV_MACHINE(xi); 1026 int i; 1027 1028 for (i = 0; i < pnv->num_chips; i++) { 1029 ics_resend(&pnv->chips[i]->psi.ics); 1030 } 1031 } 1032 1033 static PowerPCCPU *ppc_get_vcpu_by_pir(int pir) 1034 { 1035 CPUState *cs; 1036 1037 CPU_FOREACH(cs) { 1038 PowerPCCPU *cpu = POWERPC_CPU(cs); 1039 CPUPPCState *env = &cpu->env; 1040 1041 if (env->spr_cb[SPR_PIR].default_value == pir) { 1042 return cpu; 1043 } 1044 } 1045 1046 return NULL; 1047 } 1048 1049 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1050 { 1051 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1052 1053 return cpu ? ICP(cpu->intc) : NULL; 1054 } 1055 1056 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1057 Monitor *mon) 1058 { 1059 PnvMachineState *pnv = POWERNV_MACHINE(obj); 1060 int i; 1061 CPUState *cs; 1062 1063 CPU_FOREACH(cs) { 1064 PowerPCCPU *cpu = POWERPC_CPU(cs); 1065 1066 icp_pic_print_info(ICP(cpu->intc), mon); 1067 } 1068 1069 for (i = 0; i < pnv->num_chips; i++) { 1070 ics_pic_print_info(&pnv->chips[i]->psi.ics, mon); 1071 } 1072 } 1073 1074 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1075 void *opaque, Error **errp) 1076 { 1077 visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp); 1078 } 1079 1080 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1081 void *opaque, Error **errp) 1082 { 1083 PnvMachineState *pnv = POWERNV_MACHINE(obj); 1084 uint32_t num_chips; 1085 Error *local_err = NULL; 1086 1087 visit_type_uint32(v, name, &num_chips, &local_err); 1088 if (local_err) { 1089 error_propagate(errp, local_err); 1090 return; 1091 } 1092 1093 /* 1094 * TODO: should we decide on how many chips we can create based 1095 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1096 */ 1097 if (!is_power_of_2(num_chips) || num_chips > 4) { 1098 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1099 return; 1100 } 1101 1102 pnv->num_chips = num_chips; 1103 } 1104 1105 static void powernv_machine_initfn(Object *obj) 1106 { 1107 PnvMachineState *pnv = POWERNV_MACHINE(obj); 1108 pnv->num_chips = 1; 1109 } 1110 1111 static void powernv_machine_class_props_init(ObjectClass *oc) 1112 { 1113 object_class_property_add(oc, "num-chips", "uint32_t", 1114 pnv_get_num_chips, pnv_set_num_chips, 1115 NULL, NULL, NULL); 1116 object_class_property_set_description(oc, "num-chips", 1117 "Specifies the number of processor chips", 1118 NULL); 1119 } 1120 1121 static void powernv_machine_class_init(ObjectClass *oc, void *data) 1122 { 1123 MachineClass *mc = MACHINE_CLASS(oc); 1124 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1125 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1126 1127 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1128 mc->init = ppc_powernv_init; 1129 mc->reset = ppc_powernv_reset; 1130 mc->max_cpus = MAX_CPUS; 1131 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for 1132 * storage */ 1133 mc->no_parallel = 1; 1134 mc->default_boot_order = NULL; 1135 mc->default_ram_size = 1 * G_BYTE; 1136 xic->icp_get = pnv_icp_get; 1137 xic->ics_get = pnv_ics_get; 1138 xic->ics_resend = pnv_ics_resend; 1139 ispc->print_info = pnv_pic_print_info; 1140 1141 powernv_machine_class_props_init(oc); 1142 } 1143 1144 static const TypeInfo powernv_machine_info = { 1145 .name = TYPE_POWERNV_MACHINE, 1146 .parent = TYPE_MACHINE, 1147 .instance_size = sizeof(PnvMachineState), 1148 .instance_init = powernv_machine_initfn, 1149 .class_init = powernv_machine_class_init, 1150 .interfaces = (InterfaceInfo[]) { 1151 { TYPE_XICS_FABRIC }, 1152 { TYPE_INTERRUPT_STATS_PROVIDER }, 1153 { }, 1154 }, 1155 }; 1156 1157 static void powernv_machine_register_types(void) 1158 { 1159 type_register_static(&powernv_machine_info); 1160 type_register_static(&pnv_chip_info); 1161 type_register_static(&pnv_chip_power8e_info); 1162 type_register_static(&pnv_chip_power8_info); 1163 type_register_static(&pnv_chip_power8nvl_info); 1164 type_register_static(&pnv_chip_power9_info); 1165 } 1166 1167 type_init(powernv_machine_register_types) 1168