1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "system/qtest.h" 26 #include "system/system.h" 27 #include "system/numa.h" 28 #include "system/reset.h" 29 #include "system/runstate.h" 30 #include "system/cpus.h" 31 #include "system/device_tree.h" 32 #include "system/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "hw/intc/intc.h" 42 #include "hw/ipmi/ipmi.h" 43 #include "target/ppc/mmu-hash64.h" 44 #include "hw/pci/msi.h" 45 #include "hw/pci-host/pnv_phb.h" 46 #include "hw/pci-host/pnv_phb3.h" 47 #include "hw/pci-host/pnv_phb4.h" 48 49 #include "hw/ppc/xics.h" 50 #include "hw/qdev-properties.h" 51 #include "hw/ppc/pnv_chip.h" 52 #include "hw/ppc/pnv_xscom.h" 53 #include "hw/ppc/pnv_pnor.h" 54 55 #include "hw/isa/isa.h" 56 #include "hw/char/serial-isa.h" 57 #include "hw/rtc/mc146818rtc.h" 58 59 #include <libfdt.h> 60 61 #define FDT_MAX_SIZE (1 * MiB) 62 63 #define FW_FILE_NAME "skiboot.lid" 64 #define FW_LOAD_ADDR 0x0 65 #define FW_MAX_SIZE (16 * MiB) 66 67 #define KERNEL_LOAD_ADDR 0x20000000 68 #define KERNEL_MAX_SIZE (128 * MiB) 69 #define INITRD_LOAD_ADDR 0x28000000 70 #define INITRD_MAX_SIZE (128 * MiB) 71 72 static const char *pnv_chip_core_typename(const PnvChip *o) 73 { 74 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 75 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 76 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 77 const char *core_type = object_class_get_name(object_class_by_name(s)); 78 g_free(s); 79 return core_type; 80 } 81 82 /* 83 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 84 * 4 * 4 sockets * 12 cores * 8 threads = 1536 85 * Let's make it 2^11 86 */ 87 #define MAX_CPUS 2048 88 89 /* 90 * Memory nodes are created by hostboot, one for each range of memory 91 * that has a different "affinity". In practice, it means one range 92 * per chip. 93 */ 94 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 95 { 96 char *mem_name; 97 uint64_t mem_reg_property[2]; 98 int off; 99 100 mem_reg_property[0] = cpu_to_be64(start); 101 mem_reg_property[1] = cpu_to_be64(size); 102 103 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 104 off = fdt_add_subnode(fdt, 0, mem_name); 105 g_free(mem_name); 106 107 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 108 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 109 sizeof(mem_reg_property)))); 110 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 111 } 112 113 static int get_cpus_node(void *fdt) 114 { 115 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 116 117 if (cpus_offset < 0) { 118 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 119 if (cpus_offset) { 120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 122 } 123 } 124 _FDT(cpus_offset); 125 return cpus_offset; 126 } 127 128 /* 129 * The PowerNV cores (and threads) need to use real HW ids and not an 130 * incremental index like it has been done on other platforms. This HW 131 * id is stored in the CPU PIR, it is used to create cpu nodes in the 132 * device tree, used in XSCOM to address cores and in interrupt 133 * servers. 134 */ 135 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 136 { 137 PowerPCCPU *cpu = pc->threads[0]; 138 CPUState *cs = CPU(cpu); 139 DeviceClass *dc = DEVICE_GET_CLASS(cs); 140 int smt_threads = CPU_CORE(pc)->nr_threads; 141 CPUPPCState *env = &cpu->env; 142 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 143 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 144 uint32_t *servers_prop; 145 int i; 146 uint32_t pir, tir; 147 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 148 0xffffffff, 0xffffffff}; 149 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 150 uint32_t cpufreq = 1000000000; 151 uint32_t page_sizes_prop[64]; 152 size_t page_sizes_prop_size; 153 int offset; 154 char *nodename; 155 int cpus_offset = get_cpus_node(fdt); 156 157 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir); 158 159 /* Only one DT node per (big) core */ 160 g_assert(tir == 0); 161 162 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 163 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 164 _FDT(offset); 165 g_free(nodename); 166 167 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 170 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 171 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 172 173 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 174 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 175 env->dcache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 177 env->dcache_line_size))); 178 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 179 env->icache_line_size))); 180 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 181 env->icache_line_size))); 182 183 if (pcc->l1_dcache_size) { 184 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 185 pcc->l1_dcache_size))); 186 } else { 187 warn_report("Unknown L1 dcache size for cpu"); 188 } 189 if (pcc->l1_icache_size) { 190 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 191 pcc->l1_icache_size))); 192 } else { 193 warn_report("Unknown L1 icache size for cpu"); 194 } 195 196 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 198 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 199 cpu->hash64_opts->slb_size))); 200 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 201 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 202 203 if (ppc_has_spr(cpu, SPR_PURR)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 205 } 206 207 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 208 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 209 segs, sizeof(segs)))); 210 } 211 212 /* 213 * Advertise VMX/VSX (vector extensions) if available 214 * 0 / no property == no vector extensions 215 * 1 == VMX / Altivec available 216 * 2 == VSX available 217 */ 218 if (env->insns_flags & PPC_ALTIVEC) { 219 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 220 221 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 222 } 223 224 /* 225 * Advertise DFP (Decimal Floating Point) if available 226 * 0 / no property == no DFP 227 * 1 == DFP available 228 */ 229 if (env->insns_flags2 & PPC2_DFP) { 230 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 231 } 232 233 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 234 sizeof(page_sizes_prop)); 235 if (page_sizes_prop_size) { 236 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 237 page_sizes_prop, page_sizes_prop_size))); 238 } 239 240 /* Build interrupt servers properties */ 241 if (pc->big_core) { 242 servers_prop = g_new(uint32_t, smt_threads * 2); 243 for (i = 0; i < smt_threads; i++) { 244 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 245 servers_prop[i * 2] = cpu_to_be32(pir); 246 247 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL); 248 servers_prop[i * 2 + 1] = cpu_to_be32(pir); 249 } 250 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 251 servers_prop, sizeof(*servers_prop) * smt_threads 252 * 2))); 253 } else { 254 servers_prop = g_new(uint32_t, smt_threads); 255 for (i = 0; i < smt_threads; i++) { 256 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 257 servers_prop[i] = cpu_to_be32(pir); 258 } 259 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 260 servers_prop, sizeof(*servers_prop) * smt_threads))); 261 } 262 g_free(servers_prop); 263 264 return offset; 265 } 266 267 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 268 uint32_t nr_threads) 269 { 270 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 271 uint32_t pir; 272 uint64_t addr; 273 char *name; 274 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 275 uint32_t irange[2], i, rsize; 276 uint64_t *reg; 277 int offset; 278 279 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); 280 addr = PNV_ICP_BASE(chip) | (pir << 12); 281 282 irange[0] = cpu_to_be32(pir); 283 irange[1] = cpu_to_be32(nr_threads); 284 285 rsize = sizeof(uint64_t) * 2 * nr_threads; 286 reg = g_malloc(rsize); 287 for (i = 0; i < nr_threads; i++) { 288 /* We know P8 PIR is linear with thread id */ 289 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 290 reg[i * 2 + 1] = cpu_to_be64(0x1000); 291 } 292 293 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 294 offset = fdt_add_subnode(fdt, 0, name); 295 _FDT(offset); 296 g_free(name); 297 298 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 299 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 300 _FDT((fdt_setprop_string(fdt, offset, "device_type", 301 "PowerPC-External-Interrupt-Presentation"))); 302 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 303 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 304 irange, sizeof(irange)))); 305 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 306 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 307 g_free(reg); 308 } 309 310 /* 311 * Adds a PnvPHB to the chip on P8. 312 * Implemented here, like for defaults PHBs 313 */ 314 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 315 { 316 Pnv8Chip *chip8 = PNV8_CHIP(chip); 317 318 phb->chip = chip; 319 320 chip8->phbs[chip8->num_phbs] = phb; 321 chip8->num_phbs++; 322 return chip; 323 } 324 325 /* 326 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 327 * HTM is always enabled because TCG does implement HTM, it's just a 328 * degenerate implementation. 329 */ 330 static const uint8_t pa_features_207[] = { 24, 0, 331 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 332 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 333 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 334 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 335 336 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 337 { 338 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 339 int i; 340 341 pnv_dt_xscom(chip, fdt, 0, 342 cpu_to_be64(PNV_XSCOM_BASE(chip)), 343 cpu_to_be64(PNV_XSCOM_SIZE), 344 compat, sizeof(compat)); 345 346 for (i = 0; i < chip->nr_cores; i++) { 347 PnvCore *pnv_core = chip->cores[i]; 348 int offset; 349 350 offset = pnv_dt_core(chip, pnv_core, fdt); 351 352 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 353 pa_features_207, sizeof(pa_features_207)))); 354 355 /* Interrupt Control Presenters (ICP). One per core. */ 356 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 357 } 358 359 if (chip->ram_size) { 360 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 361 } 362 } 363 364 /* 365 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 366 */ 367 static const uint8_t pa_features_300[] = { 66, 0, 368 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 369 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 370 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 371 /* 6: DS207 */ 372 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 373 /* 16: Vector */ 374 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 375 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 376 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 377 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 378 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 379 /* 32: LE atomic, 34: EBB + ext EBB */ 380 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 381 /* 40: Radix MMU */ 382 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 383 /* 42: PM, 44: PC RA, 46: SC vec'd */ 384 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 385 /* 48: SIMD, 50: QP BFP, 52: String */ 386 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 387 /* 54: DecFP, 56: DecI, 58: SHA */ 388 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 389 /* 60: NM atomic, 62: RNG */ 390 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 391 }; 392 393 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 394 { 395 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 396 int i; 397 398 pnv_dt_xscom(chip, fdt, 0, 399 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 400 cpu_to_be64(PNV9_XSCOM_SIZE), 401 compat, sizeof(compat)); 402 403 for (i = 0; i < chip->nr_cores; i++) { 404 PnvCore *pnv_core = chip->cores[i]; 405 int offset; 406 407 offset = pnv_dt_core(chip, pnv_core, fdt); 408 409 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 410 pa_features_300, sizeof(pa_features_300)))); 411 412 if (pnv_core->big_core) { 413 i++; /* Big-core groups two QEMU cores */ 414 } 415 } 416 417 if (chip->ram_size) { 418 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 419 } 420 421 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 422 } 423 424 /* 425 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 426 * always disables copy/paste. 427 */ 428 static const uint8_t pa_features_31[] = { 74, 0, 429 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 430 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 431 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 432 /* 6: DS207 */ 433 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 434 /* 16: Vector */ 435 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 436 /* 18: Vec. Scalar, 20: Vec. XOR */ 437 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 438 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 439 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 440 /* 32: LE atomic, 34: EBB + ext EBB */ 441 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 442 /* 40: Radix MMU */ 443 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 444 /* 42: PM, 44: PC RA, 46: SC vec'd */ 445 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 446 /* 48: SIMD, 50: QP BFP, 52: String */ 447 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 448 /* 54: DecFP, 56: DecI, 58: SHA */ 449 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 450 /* 60: NM atomic, 62: RNG */ 451 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 452 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 453 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 454 /* 72: [P]HASHST/[P]HASHCHK */ 455 0x80, 0x00, /* 72 - 73 */ 456 }; 457 458 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 459 { 460 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 461 int i; 462 463 pnv_dt_xscom(chip, fdt, 0, 464 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 465 cpu_to_be64(PNV10_XSCOM_SIZE), 466 compat, sizeof(compat)); 467 468 for (i = 0; i < chip->nr_cores; i++) { 469 PnvCore *pnv_core = chip->cores[i]; 470 int offset; 471 472 offset = pnv_dt_core(chip, pnv_core, fdt); 473 474 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 475 pa_features_31, sizeof(pa_features_31)))); 476 477 if (pnv_core->big_core) { 478 i++; /* Big-core groups two QEMU cores */ 479 } 480 } 481 482 if (chip->ram_size) { 483 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 484 } 485 486 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 487 } 488 489 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 490 { 491 uint32_t io_base = d->ioport_id; 492 uint32_t io_regs[] = { 493 cpu_to_be32(1), 494 cpu_to_be32(io_base), 495 cpu_to_be32(2) 496 }; 497 char *name; 498 int node; 499 500 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 501 node = fdt_add_subnode(fdt, lpc_off, name); 502 _FDT(node); 503 g_free(name); 504 505 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 506 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 507 } 508 509 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 510 { 511 const char compatible[] = "ns16550\0pnpPNP,501"; 512 uint32_t io_base = d->ioport_id; 513 uint32_t io_regs[] = { 514 cpu_to_be32(1), 515 cpu_to_be32(io_base), 516 cpu_to_be32(8) 517 }; 518 uint32_t irq; 519 char *name; 520 int node; 521 522 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 523 524 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 525 node = fdt_add_subnode(fdt, lpc_off, name); 526 _FDT(node); 527 g_free(name); 528 529 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 530 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 531 sizeof(compatible)))); 532 533 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 534 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 535 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 536 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 537 fdt_get_phandle(fdt, lpc_off)))); 538 539 /* This is needed by Linux */ 540 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 541 } 542 543 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 544 { 545 const char compatible[] = "bt\0ipmi-bt"; 546 uint32_t io_base; 547 uint32_t io_regs[] = { 548 cpu_to_be32(1), 549 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 550 cpu_to_be32(3) 551 }; 552 uint32_t irq; 553 char *name; 554 int node; 555 556 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 557 io_regs[1] = cpu_to_be32(io_base); 558 559 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 560 561 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 562 node = fdt_add_subnode(fdt, lpc_off, name); 563 _FDT(node); 564 g_free(name); 565 566 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 567 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 568 sizeof(compatible)))); 569 570 /* Mark it as reserved to avoid Linux trying to claim it */ 571 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 572 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 573 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 574 fdt_get_phandle(fdt, lpc_off)))); 575 } 576 577 typedef struct ForeachPopulateArgs { 578 void *fdt; 579 int offset; 580 } ForeachPopulateArgs; 581 582 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 583 { 584 ForeachPopulateArgs *args = opaque; 585 ISADevice *d = ISA_DEVICE(dev); 586 587 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 588 pnv_dt_rtc(d, args->fdt, args->offset); 589 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 590 pnv_dt_serial(d, args->fdt, args->offset); 591 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 592 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 593 } else { 594 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 595 d->ioport_id); 596 } 597 598 return 0; 599 } 600 601 /* 602 * The default LPC bus of a multichip system is on chip 0. It's 603 * recognized by the firmware (skiboot) using a "primary" property. 604 */ 605 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 606 { 607 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 608 ForeachPopulateArgs args = { 609 .fdt = fdt, 610 .offset = isa_offset, 611 }; 612 uint32_t phandle; 613 614 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 615 616 phandle = qemu_fdt_alloc_phandle(fdt); 617 assert(phandle > 0); 618 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 619 620 /* 621 * ISA devices are not necessarily parented to the ISA bus so we 622 * can not use object_child_foreach() 623 */ 624 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 625 &args); 626 } 627 628 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 629 { 630 int off; 631 632 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 633 off = fdt_add_subnode(fdt, off, "power-mgt"); 634 635 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 636 } 637 638 static void *pnv_dt_create(MachineState *machine) 639 { 640 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 641 PnvMachineState *pnv = PNV_MACHINE(machine); 642 void *fdt; 643 char *buf; 644 int off; 645 int i; 646 647 fdt = g_malloc0(FDT_MAX_SIZE); 648 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 649 650 /* /qemu node */ 651 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 652 653 /* Root node */ 654 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 655 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 656 _FDT((fdt_setprop_string(fdt, 0, "model", 657 "IBM PowerNV (emulated by qemu)"))); 658 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 659 660 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 661 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 662 if (qemu_uuid_set) { 663 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 664 } 665 g_free(buf); 666 667 off = fdt_add_subnode(fdt, 0, "chosen"); 668 if (machine->kernel_cmdline) { 669 _FDT((fdt_setprop_string(fdt, off, "bootargs", 670 machine->kernel_cmdline))); 671 } 672 673 if (pnv->initrd_size) { 674 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 675 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 676 677 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 678 &start_prop, sizeof(start_prop)))); 679 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 680 &end_prop, sizeof(end_prop)))); 681 } 682 683 /* Populate device tree for each chip */ 684 for (i = 0; i < pnv->num_chips; i++) { 685 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 686 } 687 688 /* Populate ISA devices on chip 0 */ 689 pnv_dt_isa(pnv, fdt); 690 691 if (pnv->bmc) { 692 pnv_dt_bmc_sensors(pnv->bmc, fdt); 693 } 694 695 /* Create an extra node for power management on machines that support it */ 696 if (pmc->dt_power_mgt) { 697 pmc->dt_power_mgt(pnv, fdt); 698 } 699 700 return fdt; 701 } 702 703 static void pnv_powerdown_notify(Notifier *n, void *opaque) 704 { 705 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 706 707 if (pnv->bmc) { 708 pnv_bmc_powerdown(pnv->bmc); 709 } 710 } 711 712 static void pnv_reset(MachineState *machine, ResetType type) 713 { 714 PnvMachineState *pnv = PNV_MACHINE(machine); 715 IPMIBmc *bmc; 716 void *fdt; 717 718 qemu_devices_reset(type); 719 720 /* 721 * The machine should provide by default an internal BMC simulator. 722 * If not, try to use the BMC device that was provided on the command 723 * line. 724 */ 725 bmc = pnv_bmc_find(&error_fatal); 726 if (!pnv->bmc) { 727 if (!bmc) { 728 if (!qtest_enabled()) { 729 warn_report("machine has no BMC device. Use '-device " 730 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 731 "to define one"); 732 } 733 } else { 734 pnv_bmc_set_pnor(bmc, pnv->pnor); 735 pnv->bmc = bmc; 736 } 737 } 738 739 if (machine->fdt) { 740 fdt = machine->fdt; 741 } else { 742 fdt = pnv_dt_create(machine); 743 /* Pack resulting tree */ 744 _FDT((fdt_pack(fdt))); 745 } 746 747 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 748 749 /* Update machine->fdt with latest fdt */ 750 if (machine->fdt != fdt) { 751 /* 752 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 753 * the existing machine->fdt to avoid leaking it during 754 * a reset. 755 */ 756 g_free(machine->fdt); 757 machine->fdt = fdt; 758 } 759 } 760 761 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 762 { 763 Pnv8Chip *chip8 = PNV8_CHIP(chip); 764 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 765 766 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 767 768 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 769 } 770 771 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 772 { 773 Pnv8Chip *chip8 = PNV8_CHIP(chip); 774 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 775 776 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 777 778 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 779 } 780 781 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 782 { 783 Pnv9Chip *chip9 = PNV9_CHIP(chip); 784 qemu_irq irq; 785 786 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 787 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq); 788 789 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0); 790 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); 791 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1); 792 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); 793 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2); 794 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); 795 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3); 796 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); 797 798 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 799 } 800 801 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 802 { 803 Pnv10Chip *chip10 = PNV10_CHIP(chip); 804 qemu_irq irq; 805 806 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 807 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq); 808 809 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0); 810 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); 811 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1); 812 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); 813 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2); 814 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); 815 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3); 816 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); 817 818 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 819 } 820 821 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 822 { 823 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 824 } 825 826 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf) 827 { 828 Pnv8Chip *chip8 = PNV8_CHIP(chip); 829 int i; 830 831 ics_pic_print_info(&chip8->psi.ics, buf); 832 833 for (i = 0; i < chip8->num_phbs; i++) { 834 PnvPHB *phb = chip8->phbs[i]; 835 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 836 837 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 838 ics_pic_print_info(&phb3->lsis, buf); 839 } 840 } 841 842 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 843 { 844 GString *buf = opaque; 845 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 846 847 if (!phb) { 848 return 0; 849 } 850 851 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 852 853 return 0; 854 } 855 856 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf) 857 { 858 Pnv9Chip *chip9 = PNV9_CHIP(chip); 859 860 pnv_xive_pic_print_info(&chip9->xive, buf); 861 pnv_psi_pic_print_info(&chip9->psi, buf); 862 object_child_foreach_recursive(OBJECT(chip), 863 pnv_chip_power9_pic_print_info_child, buf); 864 } 865 866 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 867 uint32_t core_id) 868 { 869 return PNV_XSCOM_EX_BASE(core_id); 870 } 871 872 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 873 uint32_t core_id) 874 { 875 return PNV9_XSCOM_EC_BASE(core_id); 876 } 877 878 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 879 uint32_t core_id) 880 { 881 return PNV10_XSCOM_EC_BASE(core_id); 882 } 883 884 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 885 { 886 PowerPCCPUClass *ppc_default = 887 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 888 PowerPCCPUClass *ppc = 889 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 890 891 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 892 } 893 894 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 895 { 896 ISADevice *dev = isa_new("isa-ipmi-bt"); 897 898 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 899 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 900 isa_realize_and_unref(dev, bus, &error_fatal); 901 } 902 903 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf) 904 { 905 Pnv10Chip *chip10 = PNV10_CHIP(chip); 906 907 pnv_xive2_pic_print_info(&chip10->xive, buf); 908 pnv_psi_pic_print_info(&chip10->psi, buf); 909 object_child_foreach_recursive(OBJECT(chip), 910 pnv_chip_power9_pic_print_info_child, buf); 911 } 912 913 /* Always give the first 1GB to chip 0 else we won't boot */ 914 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 915 { 916 MachineState *machine = MACHINE(pnv); 917 uint64_t ram_per_chip; 918 919 assert(machine->ram_size >= 1 * GiB); 920 921 ram_per_chip = machine->ram_size / pnv->num_chips; 922 if (ram_per_chip >= 1 * GiB) { 923 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 924 } 925 926 assert(pnv->num_chips > 1); 927 928 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 929 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 930 } 931 932 static void pnv_init(MachineState *machine) 933 { 934 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 935 PnvMachineState *pnv = PNV_MACHINE(machine); 936 MachineClass *mc = MACHINE_GET_CLASS(machine); 937 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 938 int max_smt_threads = pmc->max_smt_threads; 939 char *fw_filename; 940 long fw_size; 941 uint64_t chip_ram_start = 0; 942 int i; 943 char *chip_typename; 944 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 945 DeviceState *dev; 946 947 if (kvm_enabled()) { 948 error_report("machine %s does not support the KVM accelerator", 949 mc->name); 950 exit(EXIT_FAILURE); 951 } 952 953 /* allocate RAM */ 954 if (machine->ram_size < mc->default_ram_size) { 955 char *sz = size_to_str(mc->default_ram_size); 956 error_report("Invalid RAM size, should be bigger than %s", sz); 957 g_free(sz); 958 exit(EXIT_FAILURE); 959 } 960 961 /* checks for invalid option combinations */ 962 if (machine->dtb && (strlen(machine->kernel_cmdline) != 0)) { 963 error_report("-append and -dtb cannot be used together, as passed" 964 " command line is ignored in case of custom dtb"); 965 exit(EXIT_FAILURE); 966 } 967 968 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 969 970 /* 971 * Create our simple PNOR device 972 */ 973 dev = qdev_new(TYPE_PNV_PNOR); 974 if (pnor) { 975 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 976 } 977 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 978 pnv->pnor = PNV_PNOR(dev); 979 980 /* load skiboot firmware */ 981 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 982 if (!fw_filename) { 983 error_report("Could not find OPAL firmware '%s'", bios_name); 984 exit(1); 985 } 986 987 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 988 if (fw_size < 0) { 989 error_report("Could not load OPAL firmware '%s'", fw_filename); 990 exit(1); 991 } 992 g_free(fw_filename); 993 994 /* load kernel */ 995 if (machine->kernel_filename) { 996 long kernel_size; 997 998 kernel_size = load_image_targphys(machine->kernel_filename, 999 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 1000 if (kernel_size < 0) { 1001 error_report("Could not load kernel '%s'", 1002 machine->kernel_filename); 1003 exit(1); 1004 } 1005 } 1006 1007 /* load initrd */ 1008 if (machine->initrd_filename) { 1009 pnv->initrd_base = INITRD_LOAD_ADDR; 1010 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 1011 pnv->initrd_base, INITRD_MAX_SIZE); 1012 if (pnv->initrd_size < 0) { 1013 error_report("Could not load initial ram disk '%s'", 1014 machine->initrd_filename); 1015 exit(1); 1016 } 1017 } 1018 1019 /* load dtb if passed */ 1020 if (machine->dtb) { 1021 int fdt_size; 1022 1023 warn_report("with manually passed dtb, some options like '-append'" 1024 " will get ignored and the dtb passed will be used as-is"); 1025 1026 /* read the file 'machine->dtb', and load it into 'fdt' buffer */ 1027 machine->fdt = load_device_tree(machine->dtb, &fdt_size); 1028 if (!machine->fdt) { 1029 error_report("Could not load dtb '%s'", machine->dtb); 1030 exit(1); 1031 } 1032 } 1033 1034 /* MSIs are supported on this platform */ 1035 msi_nonbroken = true; 1036 1037 /* 1038 * Check compatibility of the specified CPU with the machine 1039 * default. 1040 */ 1041 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 1042 error_report("invalid CPU model '%s' for %s machine", 1043 machine->cpu_type, mc->name); 1044 exit(1); 1045 } 1046 1047 /* Create the processor chips */ 1048 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 1049 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 1050 i, machine->cpu_type); 1051 if (!object_class_by_name(chip_typename)) { 1052 error_report("invalid chip model '%.*s' for %s machine", 1053 i, machine->cpu_type, mc->name); 1054 exit(1); 1055 } 1056 1057 /* Set lpar-per-core mode if lpar-per-thread is not supported */ 1058 if (!pmc->has_lpar_per_thread) { 1059 pnv->lpar_per_core = true; 1060 } 1061 1062 pnv->num_chips = 1063 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 1064 1065 if (pnv->big_core) { 1066 if (machine->smp.threads % 2 == 1) { 1067 error_report("Cannot support %d threads with big-core option " 1068 "because it must be an even number", 1069 machine->smp.threads); 1070 exit(1); 1071 } 1072 max_smt_threads *= 2; 1073 } 1074 1075 if (machine->smp.threads > max_smt_threads) { 1076 error_report("Cannot support more than %d threads/core " 1077 "on %s machine", max_smt_threads, mc->desc); 1078 if (pmc->max_smt_threads == 4) { 1079 error_report("(use big-core=on for 8 threads per core)"); 1080 } 1081 exit(1); 1082 } 1083 1084 if (pnv->big_core) { 1085 /* 1086 * powernv models PnvCore as a SMT4 core. Big-core requires 2xPnvCore 1087 * per core, so adjust topology here. pnv_dt_core() processor 1088 * device-tree and TCG SMT code make the 2 cores appear as one big core 1089 * from software point of view. pnv pervasive models and xscoms tend to 1090 * see the big core as 2 small core halves. 1091 */ 1092 machine->smp.cores *= 2; 1093 machine->smp.threads /= 2; 1094 } 1095 1096 if (!is_power_of_2(machine->smp.threads)) { 1097 error_report("Cannot support %d threads/core on a powernv " 1098 "machine because it must be a power of 2", 1099 machine->smp.threads); 1100 exit(1); 1101 } 1102 1103 /* 1104 * TODO: should we decide on how many chips we can create based 1105 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1106 */ 1107 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1108 error_report("invalid number of chips: '%d'", pnv->num_chips); 1109 error_printf( 1110 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1111 exit(1); 1112 } 1113 1114 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1115 for (i = 0; i < pnv->num_chips; i++) { 1116 char chip_name[32]; 1117 Object *chip = OBJECT(qdev_new(chip_typename)); 1118 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1119 1120 pnv->chips[i] = PNV_CHIP(chip); 1121 1122 /* Distribute RAM among the chips */ 1123 object_property_set_int(chip, "ram-start", chip_ram_start, 1124 &error_fatal); 1125 object_property_set_int(chip, "ram-size", chip_ram_size, 1126 &error_fatal); 1127 chip_ram_start += chip_ram_size; 1128 1129 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1130 object_property_add_child(OBJECT(pnv), chip_name, chip); 1131 object_property_set_int(chip, "chip-id", i, &error_fatal); 1132 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1133 &error_fatal); 1134 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1135 &error_fatal); 1136 object_property_set_bool(chip, "big-core", pnv->big_core, 1137 &error_fatal); 1138 object_property_set_bool(chip, "lpar-per-core", pnv->lpar_per_core, 1139 &error_fatal); 1140 /* 1141 * The POWER8 machine use the XICS interrupt interface. 1142 * Propagate the XICS fabric to the chip and its controllers. 1143 */ 1144 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1145 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1146 } 1147 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1148 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1149 &error_abort); 1150 } 1151 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1152 } 1153 g_free(chip_typename); 1154 1155 /* Instantiate ISA bus on chip 0 */ 1156 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1157 1158 /* Create serial port */ 1159 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1160 1161 /* Create an RTC ISA device too */ 1162 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1163 1164 /* 1165 * Create the machine BMC simulator and the IPMI BT device for 1166 * communication with the BMC 1167 */ 1168 if (defaults_enabled()) { 1169 pnv->bmc = pnv_bmc_create(pnv->pnor); 1170 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1171 } 1172 1173 /* 1174 * The PNOR is mapped on the LPC FW address space by the BMC. 1175 * Since we can not reach the remote BMC machine with LPC memops, 1176 * map it always for now. 1177 */ 1178 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1179 &pnv->pnor->mmio); 1180 1181 /* 1182 * OpenPOWER systems use a IPMI SEL Event message to notify the 1183 * host to powerdown 1184 */ 1185 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1186 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1187 1188 /* 1189 * Create/Connect any machine-specific I2C devices 1190 */ 1191 if (pmc->i2c_init) { 1192 pmc->i2c_init(pnv); 1193 } 1194 } 1195 1196 /* 1197 * 0:21 Reserved - Read as zeros 1198 * 22:24 Chip ID 1199 * 25:28 Core number 1200 * 29:31 Thread ID 1201 */ 1202 static void pnv_get_pir_tir_p8(PnvChip *chip, 1203 uint32_t core_id, uint32_t thread_id, 1204 uint32_t *pir, uint32_t *tir) 1205 { 1206 if (pir) { 1207 *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id; 1208 } 1209 if (tir) { 1210 *tir = thread_id; 1211 } 1212 } 1213 1214 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1215 Error **errp) 1216 { 1217 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1218 Error *local_err = NULL; 1219 Object *obj; 1220 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1221 1222 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1223 if (local_err) { 1224 error_propagate(errp, local_err); 1225 return; 1226 } 1227 1228 pnv_cpu->intc = obj; 1229 } 1230 1231 1232 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1233 { 1234 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1235 1236 icp_reset(ICP(pnv_cpu->intc)); 1237 } 1238 1239 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1240 { 1241 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1242 1243 icp_destroy(ICP(pnv_cpu->intc)); 1244 pnv_cpu->intc = NULL; 1245 } 1246 1247 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1248 GString *buf) 1249 { 1250 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1251 } 1252 1253 /* 1254 * 0:48 Reserved - Read as zeroes 1255 * 49:52 Node ID 1256 * 53:55 Chip ID 1257 * 56 Reserved - Read as zero 1258 * 57:61 Core number 1259 * 62:63 Thread ID 1260 * 1261 * We only care about the lower bits. uint32_t is fine for the moment. 1262 */ 1263 static void pnv_get_pir_tir_p9(PnvChip *chip, 1264 uint32_t core_id, uint32_t thread_id, 1265 uint32_t *pir, uint32_t *tir) 1266 { 1267 if (chip->big_core) { 1268 /* Big-core interleaves thread ID between small-cores */ 1269 thread_id <<= 1; 1270 thread_id |= core_id & 1; 1271 core_id >>= 1; 1272 1273 if (pir) { 1274 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1275 } 1276 } else { 1277 if (pir) { 1278 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1279 } 1280 } 1281 if (tir) { 1282 *tir = thread_id; 1283 } 1284 } 1285 1286 /* 1287 * 0:48 Reserved - Read as zeroes 1288 * 49:52 Node ID 1289 * 53:55 Chip ID 1290 * 56 Reserved - Read as zero 1291 * 57:59 Quad ID 1292 * 60 Core Chiplet Pair ID 1293 * 61:63 Thread/Core Chiplet ID t0-t2 1294 * 1295 * We only care about the lower bits. uint32_t is fine for the moment. 1296 */ 1297 static void pnv_get_pir_tir_p10(PnvChip *chip, 1298 uint32_t core_id, uint32_t thread_id, 1299 uint32_t *pir, uint32_t *tir) 1300 { 1301 if (chip->big_core) { 1302 /* Big-core interleaves thread ID between small-cores */ 1303 thread_id <<= 1; 1304 thread_id |= core_id & 1; 1305 core_id >>= 1; 1306 1307 if (pir) { 1308 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1309 } 1310 } else { 1311 if (pir) { 1312 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1313 } 1314 } 1315 if (tir) { 1316 *tir = thread_id; 1317 } 1318 } 1319 1320 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1321 Error **errp) 1322 { 1323 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1324 Error *local_err = NULL; 1325 Object *obj; 1326 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1327 1328 /* 1329 * The core creates its interrupt presenter but the XIVE interrupt 1330 * controller object is initialized afterwards. Hopefully, it's 1331 * only used at runtime. 1332 */ 1333 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1334 &local_err); 1335 if (local_err) { 1336 error_propagate(errp, local_err); 1337 return; 1338 } 1339 1340 pnv_cpu->intc = obj; 1341 } 1342 1343 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1344 { 1345 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1346 1347 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1348 } 1349 1350 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1351 { 1352 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1353 1354 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1355 pnv_cpu->intc = NULL; 1356 } 1357 1358 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1359 GString *buf) 1360 { 1361 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1362 } 1363 1364 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1365 Error **errp) 1366 { 1367 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1368 Error *local_err = NULL; 1369 Object *obj; 1370 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1371 1372 /* 1373 * The core creates its interrupt presenter but the XIVE2 interrupt 1374 * controller object is initialized afterwards. Hopefully, it's 1375 * only used at runtime. 1376 */ 1377 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1378 &local_err); 1379 if (local_err) { 1380 error_propagate(errp, local_err); 1381 return; 1382 } 1383 1384 pnv_cpu->intc = obj; 1385 } 1386 1387 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1388 { 1389 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1390 1391 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1392 } 1393 1394 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1395 { 1396 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1397 1398 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1399 pnv_cpu->intc = NULL; 1400 } 1401 1402 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1403 GString *buf) 1404 { 1405 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1406 } 1407 1408 /* 1409 * Allowed core identifiers on a POWER8 Processor Chip : 1410 * 1411 * <EX0 reserved> 1412 * EX1 - Venice only 1413 * EX2 - Venice only 1414 * EX3 - Venice only 1415 * EX4 1416 * EX5 1417 * EX6 1418 * <EX7,8 reserved> <reserved> 1419 * EX9 - Venice only 1420 * EX10 - Venice only 1421 * EX11 - Venice only 1422 * EX12 1423 * EX13 1424 * EX14 1425 * <EX15 reserved> 1426 */ 1427 #define POWER8E_CORE_MASK (0x7070ull) 1428 #define POWER8_CORE_MASK (0x7e7eull) 1429 1430 /* 1431 * POWER9 has 24 cores, ids starting at 0x0 1432 */ 1433 #define POWER9_CORE_MASK (0xffffffffffffffull) 1434 1435 1436 #define POWER10_CORE_MASK (0xffffffffffffffull) 1437 1438 static void pnv_chip_power8_instance_init(Object *obj) 1439 { 1440 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1441 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1442 int i; 1443 1444 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1445 (Object **)&chip8->xics, 1446 object_property_allow_set_link, 1447 OBJ_PROP_LINK_STRONG); 1448 1449 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1450 1451 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1452 1453 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1454 1455 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1456 1457 if (defaults_enabled()) { 1458 chip8->num_phbs = pcc->num_phbs; 1459 1460 for (i = 0; i < chip8->num_phbs; i++) { 1461 Object *phb = object_new(TYPE_PNV_PHB); 1462 1463 /* 1464 * We need the chip to parent the PHB to allow the DT 1465 * to build correctly (via pnv_xscom_dt()). 1466 * 1467 * TODO: the PHB should be parented by a PEC device that, at 1468 * this moment, is not modelled powernv8/phb3. 1469 */ 1470 object_property_add_child(obj, "phb[*]", phb); 1471 chip8->phbs[i] = PNV_PHB(phb); 1472 } 1473 } 1474 1475 } 1476 1477 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1478 { 1479 PnvChip *chip = PNV_CHIP(chip8); 1480 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1481 int i, j; 1482 char *name; 1483 1484 name = g_strdup_printf("icp-%x", chip->chip_id); 1485 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1486 g_free(name); 1487 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1488 &chip8->icp_mmio); 1489 1490 /* Map the ICP registers for each thread */ 1491 for (i = 0; i < chip->nr_cores; i++) { 1492 PnvCore *pnv_core = chip->cores[i]; 1493 int core_hwid = CPU_CORE(pnv_core)->core_id; 1494 1495 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1496 uint32_t pir; 1497 PnvICPState *icp; 1498 1499 pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL); 1500 icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1501 1502 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1503 &icp->mmio); 1504 } 1505 } 1506 } 1507 1508 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1509 { 1510 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1511 PnvChip *chip = PNV_CHIP(dev); 1512 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1513 Pnv8Psi *psi8 = &chip8->psi; 1514 Error *local_err = NULL; 1515 int i; 1516 1517 assert(chip8->xics); 1518 1519 /* XSCOM bridge is first */ 1520 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1521 1522 pcc->parent_realize(dev, &local_err); 1523 if (local_err) { 1524 error_propagate(errp, local_err); 1525 return; 1526 } 1527 1528 /* Processor Service Interface (PSI) Host Bridge */ 1529 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1530 &error_fatal); 1531 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1532 OBJECT(chip8->xics), &error_abort); 1533 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1534 return; 1535 } 1536 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1537 &PNV_PSI(psi8)->xscom_regs); 1538 1539 /* Create LPC controller */ 1540 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1541 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1542 1543 chip->fw_mr = &chip8->lpc.isa_fw; 1544 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1545 (uint64_t) PNV_XSCOM_BASE(chip), 1546 PNV_XSCOM_LPC_BASE); 1547 1548 /* 1549 * Interrupt Management Area. This is the memory region holding 1550 * all the Interrupt Control Presenter (ICP) registers 1551 */ 1552 pnv_chip_icp_realize(chip8, &local_err); 1553 if (local_err) { 1554 error_propagate(errp, local_err); 1555 return; 1556 } 1557 1558 /* HOMER (must be created before OCC) */ 1559 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1560 &error_abort); 1561 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1562 return; 1563 } 1564 /* Homer Xscom region */ 1565 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1566 /* Homer RAM region */ 1567 memory_region_add_subregion(get_system_memory(), chip8->homer.base, 1568 &chip8->homer.mem); 1569 1570 /* Create the simplified OCC model */ 1571 object_property_set_link(OBJECT(&chip8->occ), "homer", 1572 OBJECT(&chip8->homer), &error_abort); 1573 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1574 return; 1575 } 1576 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1577 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1578 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1579 1580 /* OCC SRAM model */ 1581 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1582 &chip8->occ.sram_regs); 1583 1584 /* PHB controllers */ 1585 for (i = 0; i < chip8->num_phbs; i++) { 1586 PnvPHB *phb = chip8->phbs[i]; 1587 1588 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1589 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1590 &error_fatal); 1591 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1592 &error_fatal); 1593 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1594 return; 1595 } 1596 } 1597 } 1598 1599 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1600 { 1601 addr &= (PNV_XSCOM_SIZE - 1); 1602 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1603 } 1604 1605 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1606 { 1607 DeviceClass *dc = DEVICE_CLASS(klass); 1608 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1609 1610 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1611 k->cores_mask = POWER8E_CORE_MASK; 1612 k->num_phbs = 3; 1613 k->get_pir_tir = pnv_get_pir_tir_p8; 1614 k->intc_create = pnv_chip_power8_intc_create; 1615 k->intc_reset = pnv_chip_power8_intc_reset; 1616 k->intc_destroy = pnv_chip_power8_intc_destroy; 1617 k->intc_print_info = pnv_chip_power8_intc_print_info; 1618 k->isa_create = pnv_chip_power8_isa_create; 1619 k->dt_populate = pnv_chip_power8_dt_populate; 1620 k->pic_print_info = pnv_chip_power8_pic_print_info; 1621 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1622 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1623 dc->desc = "PowerNV Chip POWER8E"; 1624 1625 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1626 &k->parent_realize); 1627 } 1628 1629 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1630 { 1631 DeviceClass *dc = DEVICE_CLASS(klass); 1632 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1633 1634 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1635 k->cores_mask = POWER8_CORE_MASK; 1636 k->num_phbs = 3; 1637 k->get_pir_tir = pnv_get_pir_tir_p8; 1638 k->intc_create = pnv_chip_power8_intc_create; 1639 k->intc_reset = pnv_chip_power8_intc_reset; 1640 k->intc_destroy = pnv_chip_power8_intc_destroy; 1641 k->intc_print_info = pnv_chip_power8_intc_print_info; 1642 k->isa_create = pnv_chip_power8_isa_create; 1643 k->dt_populate = pnv_chip_power8_dt_populate; 1644 k->pic_print_info = pnv_chip_power8_pic_print_info; 1645 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1646 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1647 dc->desc = "PowerNV Chip POWER8"; 1648 1649 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1650 &k->parent_realize); 1651 } 1652 1653 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1654 { 1655 DeviceClass *dc = DEVICE_CLASS(klass); 1656 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1657 1658 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1659 k->cores_mask = POWER8_CORE_MASK; 1660 k->num_phbs = 4; 1661 k->get_pir_tir = pnv_get_pir_tir_p8; 1662 k->intc_create = pnv_chip_power8_intc_create; 1663 k->intc_reset = pnv_chip_power8_intc_reset; 1664 k->intc_destroy = pnv_chip_power8_intc_destroy; 1665 k->intc_print_info = pnv_chip_power8_intc_print_info; 1666 k->isa_create = pnv_chip_power8nvl_isa_create; 1667 k->dt_populate = pnv_chip_power8_dt_populate; 1668 k->pic_print_info = pnv_chip_power8_pic_print_info; 1669 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1670 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1671 dc->desc = "PowerNV Chip POWER8NVL"; 1672 1673 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1674 &k->parent_realize); 1675 } 1676 1677 static void pnv_chip_power9_instance_init(Object *obj) 1678 { 1679 PnvChip *chip = PNV_CHIP(obj); 1680 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1681 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1682 int i; 1683 1684 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU); 1685 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1686 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1687 "xive-fabric"); 1688 1689 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1690 1691 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1692 1693 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1694 1695 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1696 1697 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1698 1699 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1700 1701 /* Number of PECs is the chip default */ 1702 chip->num_pecs = pcc->num_pecs; 1703 1704 for (i = 0; i < chip->num_pecs; i++) { 1705 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1706 TYPE_PNV_PHB4_PEC); 1707 } 1708 1709 for (i = 0; i < pcc->i2c_num_engines; i++) { 1710 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1711 } 1712 } 1713 1714 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1715 PnvCore *pnv_core, 1716 const char *type) 1717 { 1718 char eq_name[32]; 1719 int core_id = CPU_CORE(pnv_core)->core_id; 1720 1721 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1722 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1723 sizeof(*eq), type, 1724 &error_fatal, NULL); 1725 1726 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1727 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1728 } 1729 1730 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1731 { 1732 PnvChip *chip = PNV_CHIP(chip9); 1733 int i; 1734 1735 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1736 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1737 1738 for (i = 0; i < chip9->nr_quads; i++) { 1739 PnvQuad *eq = &chip9->quads[i]; 1740 1741 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1742 PNV_QUAD_TYPE_NAME("power9")); 1743 1744 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1745 &eq->xscom_regs); 1746 } 1747 } 1748 1749 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1750 { 1751 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1752 int i; 1753 1754 for (i = 0; i < chip->num_pecs; i++) { 1755 PnvPhb4PecState *pec = &chip9->pecs[i]; 1756 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1757 uint32_t pec_cplt_base; 1758 uint32_t pec_nest_base; 1759 uint32_t pec_pci_base; 1760 1761 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1762 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1763 &error_fatal); 1764 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1765 &error_fatal); 1766 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1767 return; 1768 } 1769 1770 pec_cplt_base = pecc->xscom_cplt_base(pec); 1771 pec_nest_base = pecc->xscom_nest_base(pec); 1772 pec_pci_base = pecc->xscom_pci_base(pec); 1773 1774 pnv_xscom_add_subregion(chip, pec_cplt_base, 1775 &pec->nest_pervasive.xscom_ctrl_regs_mr); 1776 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1777 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1778 } 1779 } 1780 1781 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1782 { 1783 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1784 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1785 PnvChip *chip = PNV_CHIP(dev); 1786 Pnv9Psi *psi9 = &chip9->psi; 1787 Error *local_err = NULL; 1788 int i; 1789 1790 /* XSCOM bridge is first */ 1791 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1792 1793 pcc->parent_realize(dev, &local_err); 1794 if (local_err) { 1795 error_propagate(errp, local_err); 1796 return; 1797 } 1798 1799 /* ADU */ 1800 object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc), 1801 &error_abort); 1802 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { 1803 return; 1804 } 1805 pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE, 1806 &chip9->adu.xscom_regs); 1807 1808 pnv_chip_quad_realize(chip9, &local_err); 1809 if (local_err) { 1810 error_propagate(errp, local_err); 1811 return; 1812 } 1813 1814 /* XIVE interrupt controller (POWER9) */ 1815 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1816 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1817 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1818 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1819 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1820 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1821 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1822 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1823 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1824 &error_abort); 1825 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1826 return; 1827 } 1828 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1829 &chip9->xive.xscom_regs); 1830 1831 /* Processor Service Interface (PSI) Host Bridge */ 1832 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1833 &error_fatal); 1834 /* This is the only device with 4k ESB pages */ 1835 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1836 &error_fatal); 1837 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1838 return; 1839 } 1840 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1841 &PNV_PSI(psi9)->xscom_regs); 1842 1843 /* LPC */ 1844 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1845 return; 1846 } 1847 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1848 &chip9->lpc.xscom_regs); 1849 1850 chip->fw_mr = &chip9->lpc.isa_fw; 1851 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1852 (uint64_t) PNV9_LPCM_BASE(chip)); 1853 1854 /* ChipTOD */ 1855 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1856 chip->chip_id == 0, &error_abort); 1857 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1858 chip->chip_id == 1, &error_abort); 1859 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1860 &error_abort); 1861 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1862 return; 1863 } 1864 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1865 &chip9->chiptod.xscom_regs); 1866 1867 /* SBE */ 1868 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1869 return; 1870 } 1871 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1872 &chip9->sbe.xscom_ctrl_regs); 1873 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1874 &chip9->sbe.xscom_mbox_regs); 1875 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1876 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1877 1878 /* HOMER (must be created before OCC) */ 1879 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1880 &error_abort); 1881 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1882 return; 1883 } 1884 /* Homer Xscom region */ 1885 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1886 /* Homer RAM region */ 1887 memory_region_add_subregion(get_system_memory(), chip9->homer.base, 1888 &chip9->homer.mem); 1889 1890 /* Create the simplified OCC model */ 1891 object_property_set_link(OBJECT(&chip9->occ), "homer", 1892 OBJECT(&chip9->homer), &error_abort); 1893 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1894 return; 1895 } 1896 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1897 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1898 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1899 1900 /* OCC SRAM model */ 1901 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1902 &chip9->occ.sram_regs); 1903 1904 /* PEC PHBs */ 1905 pnv_chip_power9_pec_realize(chip, &local_err); 1906 if (local_err) { 1907 error_propagate(errp, local_err); 1908 return; 1909 } 1910 1911 /* 1912 * I2C 1913 */ 1914 for (i = 0; i < pcc->i2c_num_engines; i++) { 1915 Object *obj = OBJECT(&chip9->i2c[i]); 1916 1917 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1918 object_property_set_int(obj, "num-busses", 1919 pcc->i2c_ports_per_engine[i], 1920 &error_fatal); 1921 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1922 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1923 return; 1924 } 1925 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1926 (chip9->i2c[i].engine - 1) * 1927 PNV9_XSCOM_I2CM_SIZE, 1928 &chip9->i2c[i].xscom_regs); 1929 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1930 qdev_get_gpio_in(DEVICE(psi9), 1931 PSIHB9_IRQ_SBE_I2C)); 1932 } 1933 } 1934 1935 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1936 { 1937 addr &= (PNV9_XSCOM_SIZE - 1); 1938 return addr >> 3; 1939 } 1940 1941 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1942 { 1943 DeviceClass *dc = DEVICE_CLASS(klass); 1944 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1945 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1946 1947 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1948 k->cores_mask = POWER9_CORE_MASK; 1949 k->get_pir_tir = pnv_get_pir_tir_p9; 1950 k->intc_create = pnv_chip_power9_intc_create; 1951 k->intc_reset = pnv_chip_power9_intc_reset; 1952 k->intc_destroy = pnv_chip_power9_intc_destroy; 1953 k->intc_print_info = pnv_chip_power9_intc_print_info; 1954 k->isa_create = pnv_chip_power9_isa_create; 1955 k->dt_populate = pnv_chip_power9_dt_populate; 1956 k->pic_print_info = pnv_chip_power9_pic_print_info; 1957 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1958 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1959 dc->desc = "PowerNV Chip POWER9"; 1960 k->num_pecs = PNV9_CHIP_MAX_PEC; 1961 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1962 k->i2c_ports_per_engine = i2c_ports_per_engine; 1963 1964 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1965 &k->parent_realize); 1966 } 1967 1968 static void pnv_chip_power10_instance_init(Object *obj) 1969 { 1970 PnvChip *chip = PNV_CHIP(obj); 1971 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1972 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1973 int i; 1974 1975 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); 1976 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1977 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1978 "xive-fabric"); 1979 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1980 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1981 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1982 TYPE_PNV10_CHIPTOD); 1983 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1984 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1985 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1986 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1987 TYPE_PNV_N1_CHIPLET); 1988 1989 chip->num_pecs = pcc->num_pecs; 1990 1991 for (i = 0; i < chip->num_pecs; i++) { 1992 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1993 TYPE_PNV_PHB5_PEC); 1994 } 1995 1996 for (i = 0; i < pcc->i2c_num_engines; i++) { 1997 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1998 } 1999 2000 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 2001 object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i], 2002 TYPE_PNV_SPI); 2003 } 2004 } 2005 2006 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 2007 { 2008 PnvChip *chip = PNV_CHIP(chip10); 2009 int i; 2010 2011 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 2012 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 2013 2014 for (i = 0; i < chip10->nr_quads; i++) { 2015 PnvQuad *eq = &chip10->quads[i]; 2016 2017 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 2018 PNV_QUAD_TYPE_NAME("power10")); 2019 2020 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 2021 &eq->xscom_regs); 2022 2023 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 2024 &eq->xscom_qme_regs); 2025 } 2026 } 2027 2028 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 2029 { 2030 Pnv10Chip *chip10 = PNV10_CHIP(chip); 2031 int i; 2032 2033 for (i = 0; i < chip->num_pecs; i++) { 2034 PnvPhb4PecState *pec = &chip10->pecs[i]; 2035 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 2036 uint32_t pec_cplt_base; 2037 uint32_t pec_nest_base; 2038 uint32_t pec_pci_base; 2039 2040 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 2041 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 2042 &error_fatal); 2043 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 2044 &error_fatal); 2045 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 2046 return; 2047 } 2048 2049 pec_cplt_base = pecc->xscom_cplt_base(pec); 2050 pec_nest_base = pecc->xscom_nest_base(pec); 2051 pec_pci_base = pecc->xscom_pci_base(pec); 2052 2053 pnv_xscom_add_subregion(chip, pec_cplt_base, 2054 &pec->nest_pervasive.xscom_ctrl_regs_mr); 2055 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 2056 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 2057 } 2058 } 2059 2060 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 2061 { 2062 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 2063 PnvChip *chip = PNV_CHIP(dev); 2064 Pnv10Chip *chip10 = PNV10_CHIP(dev); 2065 Error *local_err = NULL; 2066 int i; 2067 2068 /* XSCOM bridge is first */ 2069 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 2070 2071 pcc->parent_realize(dev, &local_err); 2072 if (local_err) { 2073 error_propagate(errp, local_err); 2074 return; 2075 } 2076 2077 /* ADU */ 2078 object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc), 2079 &error_abort); 2080 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { 2081 return; 2082 } 2083 pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE, 2084 &chip10->adu.xscom_regs); 2085 2086 pnv_chip_power10_quad_realize(chip10, &local_err); 2087 if (local_err) { 2088 error_propagate(errp, local_err); 2089 return; 2090 } 2091 2092 /* XIVE2 interrupt controller (POWER10) */ 2093 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 2094 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 2095 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 2096 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 2097 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 2098 PNV10_XIVE2_END_BASE(chip), &error_fatal); 2099 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 2100 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 2101 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 2102 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 2103 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 2104 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 2105 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 2106 &error_abort); 2107 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 2108 return; 2109 } 2110 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 2111 &chip10->xive.xscom_regs); 2112 2113 /* Processor Service Interface (PSI) Host Bridge */ 2114 object_property_set_int(OBJECT(&chip10->psi), "bar", 2115 PNV10_PSIHB_BASE(chip), &error_fatal); 2116 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 2117 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 2118 &error_fatal); 2119 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 2120 return; 2121 } 2122 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 2123 &PNV_PSI(&chip10->psi)->xscom_regs); 2124 2125 /* LPC */ 2126 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 2127 return; 2128 } 2129 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 2130 &chip10->lpc.xscom_regs); 2131 2132 chip->fw_mr = &chip10->lpc.isa_fw; 2133 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 2134 (uint64_t) PNV10_LPCM_BASE(chip)); 2135 2136 /* ChipTOD */ 2137 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 2138 chip->chip_id == 0, &error_abort); 2139 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 2140 chip->chip_id == 1, &error_abort); 2141 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 2142 &error_abort); 2143 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 2144 return; 2145 } 2146 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 2147 &chip10->chiptod.xscom_regs); 2148 2149 /* HOMER (must be created before OCC) */ 2150 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2151 &error_abort); 2152 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2153 return; 2154 } 2155 /* Homer Xscom region */ 2156 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2157 &chip10->homer.pba_regs); 2158 /* Homer RAM region */ 2159 memory_region_add_subregion(get_system_memory(), chip10->homer.base, 2160 &chip10->homer.mem); 2161 2162 /* Create the simplified OCC model */ 2163 object_property_set_link(OBJECT(&chip10->occ), "homer", 2164 OBJECT(&chip10->homer), &error_abort); 2165 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 2166 return; 2167 } 2168 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 2169 &chip10->occ.xscom_regs); 2170 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 2171 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 2172 2173 /* OCC SRAM model */ 2174 memory_region_add_subregion(get_system_memory(), 2175 PNV10_OCC_SENSOR_BASE(chip), 2176 &chip10->occ.sram_regs); 2177 2178 /* SBE */ 2179 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 2180 return; 2181 } 2182 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2183 &chip10->sbe.xscom_ctrl_regs); 2184 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2185 &chip10->sbe.xscom_mbox_regs); 2186 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2187 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2188 2189 /* N1 chiplet */ 2190 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2191 return; 2192 } 2193 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2194 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2195 2196 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2197 &chip10->n1_chiplet.xscom_pb_eq_mr); 2198 2199 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2200 &chip10->n1_chiplet.xscom_pb_es_mr); 2201 2202 /* PHBs */ 2203 pnv_chip_power10_phb_realize(chip, &local_err); 2204 if (local_err) { 2205 error_propagate(errp, local_err); 2206 return; 2207 } 2208 2209 2210 /* 2211 * I2C 2212 */ 2213 for (i = 0; i < pcc->i2c_num_engines; i++) { 2214 Object *obj = OBJECT(&chip10->i2c[i]); 2215 2216 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2217 object_property_set_int(obj, "num-busses", 2218 pcc->i2c_ports_per_engine[i], 2219 &error_fatal); 2220 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2221 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2222 return; 2223 } 2224 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2225 (chip10->i2c[i].engine - 1) * 2226 PNV10_XSCOM_I2CM_SIZE, 2227 &chip10->i2c[i].xscom_regs); 2228 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2229 qdev_get_gpio_in(DEVICE(&chip10->psi), 2230 PSIHB9_IRQ_SBE_I2C)); 2231 } 2232 /* PIB SPI Controller */ 2233 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 2234 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num", 2235 i, &error_fatal); 2236 /* pib_spic[2] connected to 25csm04 which implements 1 byte transfer */ 2237 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "transfer_len", 2238 (i == 2) ? 1 : 4, &error_fatal); 2239 if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT 2240 (&chip10->pib_spic[i])), errp)) { 2241 return; 2242 } 2243 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE + 2244 i * PNV10_XSCOM_PIB_SPIC_SIZE, 2245 &chip10->pib_spic[i].xscom_spic_regs); 2246 } 2247 } 2248 2249 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2250 { 2251 int i; 2252 for (i = 0; i < pnv->num_chips; i++) { 2253 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2254 2255 /* 2256 * Add a PCA9552 I2C device for PCIe hotplug control 2257 * to engine 2, bus 1, address 0x63 2258 */ 2259 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2260 "pca9552", 0x63); 2261 2262 /* 2263 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2264 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2265 * after hypervisor code sets a SLOTx_EN pin high. 2266 */ 2267 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2268 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2269 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2270 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2271 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2272 2273 /* 2274 * Add a PCA9554 I2C device for cable card presence detection 2275 * to engine 2, bus 1, address 0x25 2276 */ 2277 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2278 } 2279 } 2280 2281 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2282 { 2283 addr &= (PNV10_XSCOM_SIZE - 1); 2284 return addr >> 3; 2285 } 2286 2287 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2288 { 2289 DeviceClass *dc = DEVICE_CLASS(klass); 2290 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2291 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2292 2293 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */ 2294 k->cores_mask = POWER10_CORE_MASK; 2295 k->get_pir_tir = pnv_get_pir_tir_p10; 2296 k->intc_create = pnv_chip_power10_intc_create; 2297 k->intc_reset = pnv_chip_power10_intc_reset; 2298 k->intc_destroy = pnv_chip_power10_intc_destroy; 2299 k->intc_print_info = pnv_chip_power10_intc_print_info; 2300 k->isa_create = pnv_chip_power10_isa_create; 2301 k->dt_populate = pnv_chip_power10_dt_populate; 2302 k->pic_print_info = pnv_chip_power10_pic_print_info; 2303 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2304 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2305 dc->desc = "PowerNV Chip POWER10"; 2306 k->num_pecs = PNV10_CHIP_MAX_PEC; 2307 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2308 k->i2c_ports_per_engine = i2c_ports_per_engine; 2309 2310 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2311 &k->parent_realize); 2312 } 2313 2314 static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip, 2315 Error **errp) 2316 { 2317 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2318 int cores_max; 2319 2320 /* 2321 * No custom mask for this chip, let's use the default one from * 2322 * the chip class 2323 */ 2324 if (!chip->cores_mask) { 2325 chip->cores_mask = pcc->cores_mask; 2326 } 2327 2328 /* filter alien core ids ! some are reserved */ 2329 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2330 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2331 chip->cores_mask); 2332 return; 2333 } 2334 chip->cores_mask &= pcc->cores_mask; 2335 2336 /* Ensure small-cores a paired up in big-core mode */ 2337 if (pnv->big_core) { 2338 uint64_t even_cores = chip->cores_mask & 0x5555555555555555ULL; 2339 uint64_t odd_cores = chip->cores_mask & 0xaaaaaaaaaaaaaaaaULL; 2340 2341 if (even_cores ^ (odd_cores >> 1)) { 2342 error_setg(errp, "warning: unpaired cores in big-core mode !"); 2343 return; 2344 } 2345 } 2346 2347 /* now that we have a sane layout, let check the number of cores */ 2348 cores_max = ctpop64(chip->cores_mask); 2349 if (chip->nr_cores > cores_max) { 2350 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2351 cores_max); 2352 return; 2353 } 2354 } 2355 2356 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2357 { 2358 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2359 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(pnv); 2360 Error *error = NULL; 2361 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2362 const char *typename = pnv_chip_core_typename(chip); 2363 int i, core_hwid; 2364 2365 if (!object_class_by_name(typename)) { 2366 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2367 return; 2368 } 2369 2370 /* Cores */ 2371 pnv_chip_core_sanitize(pnv, chip, &error); 2372 if (error) { 2373 error_propagate(errp, error); 2374 return; 2375 } 2376 2377 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2378 2379 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2380 && (i < chip->nr_cores); core_hwid++) { 2381 char core_name[32]; 2382 PnvCore *pnv_core; 2383 uint64_t xscom_core_base; 2384 2385 if (!(chip->cores_mask & (1ull << core_hwid))) { 2386 continue; 2387 } 2388 2389 pnv_core = PNV_CORE(object_new(typename)); 2390 2391 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2392 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2393 chip->cores[i] = pnv_core; 2394 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2395 chip->nr_threads, &error_fatal); 2396 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2397 core_hwid, &error_fatal); 2398 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2399 &error_fatal); 2400 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2401 &error_fatal); 2402 object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core, 2403 &error_fatal); 2404 object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core", 2405 pmc->quirk_tb_big_core, &error_fatal); 2406 object_property_set_bool(OBJECT(pnv_core), "lpar-per-core", 2407 chip->lpar_per_core, &error_fatal); 2408 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2409 &error_abort); 2410 2411 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2412 2413 /* Each core has an XSCOM MMIO region */ 2414 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2415 2416 pnv_xscom_add_subregion(chip, xscom_core_base, 2417 &pnv_core->xscom_regs); 2418 i++; 2419 } 2420 } 2421 2422 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2423 { 2424 PnvChip *chip = PNV_CHIP(dev); 2425 Error *error = NULL; 2426 2427 /* Cores */ 2428 pnv_chip_core_realize(chip, &error); 2429 if (error) { 2430 error_propagate(errp, error); 2431 return; 2432 } 2433 } 2434 2435 static const Property pnv_chip_properties[] = { 2436 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2437 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2438 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2439 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2440 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2441 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2442 DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false), 2443 DEFINE_PROP_BOOL("lpar-per-core", PnvChip, lpar_per_core, false), 2444 }; 2445 2446 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2447 { 2448 DeviceClass *dc = DEVICE_CLASS(klass); 2449 2450 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2451 dc->realize = pnv_chip_realize; 2452 device_class_set_props(dc, pnv_chip_properties); 2453 dc->desc = "PowerNV Chip"; 2454 } 2455 2456 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2457 { 2458 int i; 2459 2460 for (i = 0; i < chip->nr_cores; i++) { 2461 PnvCore *pc = chip->cores[i]; 2462 CPUCore *cc = CPU_CORE(pc); 2463 2464 if (cc->core_id == core_id) { 2465 return pc; 2466 } 2467 } 2468 return NULL; 2469 } 2470 2471 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2472 { 2473 int i, j; 2474 2475 for (i = 0; i < chip->nr_cores; i++) { 2476 PnvCore *pc = chip->cores[i]; 2477 CPUCore *cc = CPU_CORE(pc); 2478 2479 for (j = 0; j < cc->nr_threads; j++) { 2480 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2481 return pc->threads[j]; 2482 } 2483 } 2484 } 2485 return NULL; 2486 } 2487 2488 static void pnv_chip_foreach_cpu(PnvChip *chip, 2489 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque), 2490 void *opaque) 2491 { 2492 int i, j; 2493 2494 for (i = 0; i < chip->nr_cores; i++) { 2495 PnvCore *pc = chip->cores[i]; 2496 2497 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) { 2498 fn(chip, pc->threads[j], opaque); 2499 } 2500 } 2501 } 2502 2503 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2504 { 2505 PnvMachineState *pnv = PNV_MACHINE(xi); 2506 int i, j; 2507 2508 for (i = 0; i < pnv->num_chips; i++) { 2509 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2510 2511 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2512 return &chip8->psi.ics; 2513 } 2514 2515 for (j = 0; j < chip8->num_phbs; j++) { 2516 PnvPHB *phb = chip8->phbs[j]; 2517 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2518 2519 if (ics_valid_irq(&phb3->lsis, irq)) { 2520 return &phb3->lsis; 2521 } 2522 2523 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2524 return ICS(&phb3->msis); 2525 } 2526 } 2527 } 2528 return NULL; 2529 } 2530 2531 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2532 { 2533 int i; 2534 2535 for (i = 0; i < pnv->num_chips; i++) { 2536 PnvChip *chip = pnv->chips[i]; 2537 if (chip->chip_id == chip_id) { 2538 return chip; 2539 } 2540 } 2541 return NULL; 2542 } 2543 2544 static void pnv_ics_resend(XICSFabric *xi) 2545 { 2546 PnvMachineState *pnv = PNV_MACHINE(xi); 2547 int i, j; 2548 2549 for (i = 0; i < pnv->num_chips; i++) { 2550 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2551 2552 ics_resend(&chip8->psi.ics); 2553 2554 for (j = 0; j < chip8->num_phbs; j++) { 2555 PnvPHB *phb = chip8->phbs[j]; 2556 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2557 2558 ics_resend(&phb3->lsis); 2559 ics_resend(ICS(&phb3->msis)); 2560 } 2561 } 2562 } 2563 2564 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2565 { 2566 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2567 2568 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2569 } 2570 2571 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 2572 void *opaque) 2573 { 2574 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); 2575 } 2576 2577 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf) 2578 { 2579 PnvMachineState *pnv = PNV_MACHINE(obj); 2580 int i; 2581 2582 for (i = 0; i < pnv->num_chips; i++) { 2583 PnvChip *chip = pnv->chips[i]; 2584 2585 /* First CPU presenters */ 2586 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf); 2587 2588 /* Then other devices, PHB, PSI, XIVE */ 2589 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); 2590 } 2591 } 2592 2593 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2594 uint8_t nvt_blk, uint32_t nvt_idx, 2595 bool cam_ignore, uint8_t priority, 2596 uint32_t logic_serv, 2597 XiveTCTXMatch *match) 2598 { 2599 PnvMachineState *pnv = PNV_MACHINE(xfb); 2600 int total_count = 0; 2601 int i; 2602 2603 for (i = 0; i < pnv->num_chips; i++) { 2604 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2605 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2606 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2607 int count; 2608 2609 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2610 priority, logic_serv, match); 2611 2612 if (count < 0) { 2613 return count; 2614 } 2615 2616 total_count += count; 2617 } 2618 2619 return total_count; 2620 } 2621 2622 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2623 uint8_t nvt_blk, uint32_t nvt_idx, 2624 bool cam_ignore, uint8_t priority, 2625 uint32_t logic_serv, 2626 XiveTCTXMatch *match) 2627 { 2628 PnvMachineState *pnv = PNV_MACHINE(xfb); 2629 int total_count = 0; 2630 int i; 2631 2632 for (i = 0; i < pnv->num_chips; i++) { 2633 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2634 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2635 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2636 int count; 2637 2638 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2639 priority, logic_serv, match); 2640 2641 if (count < 0) { 2642 return count; 2643 } 2644 2645 total_count += count; 2646 } 2647 2648 return total_count; 2649 } 2650 2651 static bool pnv_machine_get_big_core(Object *obj, Error **errp) 2652 { 2653 PnvMachineState *pnv = PNV_MACHINE(obj); 2654 return pnv->big_core; 2655 } 2656 2657 static void pnv_machine_set_big_core(Object *obj, bool value, Error **errp) 2658 { 2659 PnvMachineState *pnv = PNV_MACHINE(obj); 2660 pnv->big_core = value; 2661 } 2662 2663 static bool pnv_machine_get_lpar_per_core(Object *obj, Error **errp) 2664 { 2665 PnvMachineState *pnv = PNV_MACHINE(obj); 2666 return pnv->lpar_per_core; 2667 } 2668 2669 static void pnv_machine_set_lpar_per_core(Object *obj, bool value, Error **errp) 2670 { 2671 PnvMachineState *pnv = PNV_MACHINE(obj); 2672 pnv->lpar_per_core = value; 2673 } 2674 2675 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2676 { 2677 PnvMachineState *pnv = PNV_MACHINE(obj); 2678 2679 return !!pnv->fw_load_addr; 2680 } 2681 2682 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2683 { 2684 PnvMachineState *pnv = PNV_MACHINE(obj); 2685 2686 if (value) { 2687 pnv->fw_load_addr = 0x8000000; 2688 } 2689 } 2690 2691 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2692 { 2693 MachineClass *mc = MACHINE_CLASS(oc); 2694 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2695 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2696 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2697 2698 static GlobalProperty phb_compat[] = { 2699 { TYPE_PNV_PHB, "version", "3" }, 2700 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2701 }; 2702 2703 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2704 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2705 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2706 2707 xic->icp_get = pnv_icp_get; 2708 xic->ics_get = pnv_ics_get; 2709 xic->ics_resend = pnv_ics_resend; 2710 2711 pmc->compat = compat; 2712 pmc->compat_size = sizeof(compat); 2713 pmc->max_smt_threads = 8; 2714 /* POWER8 is always lpar-per-core mode */ 2715 pmc->has_lpar_per_thread = false; 2716 2717 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2718 } 2719 2720 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2721 { 2722 MachineClass *mc = MACHINE_CLASS(oc); 2723 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2724 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2725 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2726 2727 static GlobalProperty phb_compat[] = { 2728 { TYPE_PNV_PHB, "version", "4" }, 2729 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2730 }; 2731 2732 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2733 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2734 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2735 2736 xfc->match_nvt = pnv_match_nvt; 2737 2738 pmc->compat = compat; 2739 pmc->compat_size = sizeof(compat); 2740 pmc->max_smt_threads = 4; 2741 pmc->has_lpar_per_thread = true; 2742 pmc->dt_power_mgt = pnv_dt_power_mgt; 2743 2744 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2745 2746 object_class_property_add_bool(oc, "big-core", 2747 pnv_machine_get_big_core, 2748 pnv_machine_set_big_core); 2749 object_class_property_set_description(oc, "big-core", 2750 "Use big-core (aka fused-core) mode"); 2751 2752 object_class_property_add_bool(oc, "lpar-per-core", 2753 pnv_machine_get_lpar_per_core, 2754 pnv_machine_set_lpar_per_core); 2755 object_class_property_set_description(oc, "lpar-per-core", 2756 "Use 1 LPAR per core mode"); 2757 } 2758 2759 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2760 { 2761 MachineClass *mc = MACHINE_CLASS(oc); 2762 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2763 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2764 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2765 2766 static GlobalProperty phb_compat[] = { 2767 { TYPE_PNV_PHB, "version", "5" }, 2768 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2769 }; 2770 2771 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2772 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2773 2774 mc->alias = "powernv"; 2775 2776 pmc->compat = compat; 2777 pmc->compat_size = sizeof(compat); 2778 pmc->max_smt_threads = 4; 2779 pmc->has_lpar_per_thread = true; 2780 pmc->quirk_tb_big_core = true; 2781 pmc->dt_power_mgt = pnv_dt_power_mgt; 2782 2783 xfc->match_nvt = pnv10_xive_match_nvt; 2784 2785 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2786 } 2787 2788 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2789 { 2790 MachineClass *mc = MACHINE_CLASS(oc); 2791 2792 pnv_machine_p10_common_class_init(oc, data); 2793 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2794 2795 /* 2796 * This is the parent of POWER10 Rainier class, so properies go here 2797 * rather than common init (which would add them to both parent and 2798 * child which is invalid). 2799 */ 2800 object_class_property_add_bool(oc, "big-core", 2801 pnv_machine_get_big_core, 2802 pnv_machine_set_big_core); 2803 object_class_property_set_description(oc, "big-core", 2804 "Use big-core (aka fused-core) mode"); 2805 2806 object_class_property_add_bool(oc, "lpar-per-core", 2807 pnv_machine_get_lpar_per_core, 2808 pnv_machine_set_lpar_per_core); 2809 object_class_property_set_description(oc, "lpar-per-core", 2810 "Use 1 LPAR per core mode"); 2811 } 2812 2813 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2814 { 2815 MachineClass *mc = MACHINE_CLASS(oc); 2816 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2817 2818 pnv_machine_p10_common_class_init(oc, data); 2819 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2820 pmc->i2c_init = pnv_rainier_i2c_init; 2821 } 2822 2823 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2824 { 2825 CPUPPCState *env = cpu_env(cs); 2826 2827 cpu_synchronize_state(cs); 2828 ppc_cpu_do_system_reset(cs); 2829 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2830 /* 2831 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2832 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2833 * (PPC_BIT(43)). 2834 */ 2835 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2836 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2837 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2838 } 2839 } else { 2840 /* 2841 * For non-powersave system resets, SRR1[42:45] are defined to be 2842 * implementation-dependent. The POWER9 User Manual specifies that 2843 * an external (SCOM driven, which may come from a BMC nmi command or 2844 * another CPU requesting a NMI IPI) system reset exception should be 2845 * 0b0010 (PPC_BIT(44)). 2846 */ 2847 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2848 } 2849 if (arg.host_int == 1) { 2850 cpu_resume(cs); 2851 } 2852 } 2853 2854 /* 2855 * Send a SRESET (NMI) interrupt to the CPU, and resume execution if it was 2856 * paused. 2857 */ 2858 void pnv_cpu_do_nmi_resume(CPUState *cs) 2859 { 2860 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(1)); 2861 } 2862 2863 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque) 2864 { 2865 async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(0)); 2866 } 2867 2868 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2869 { 2870 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2871 int i; 2872 2873 for (i = 0; i < pnv->num_chips; i++) { 2874 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL); 2875 } 2876 } 2877 2878 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2879 { 2880 MachineClass *mc = MACHINE_CLASS(oc); 2881 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2882 NMIClass *nc = NMI_CLASS(oc); 2883 2884 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2885 mc->init = pnv_init; 2886 mc->reset = pnv_reset; 2887 mc->max_cpus = MAX_CPUS; 2888 /* Pnv provides a AHCI device for storage */ 2889 mc->block_default_type = IF_IDE; 2890 mc->no_parallel = 1; 2891 mc->default_boot_order = NULL; 2892 /* 2893 * RAM defaults to less than 2048 for 32-bit hosts, and large 2894 * enough to fit the maximum initrd size at it's load address 2895 */ 2896 mc->default_ram_size = 1 * GiB; 2897 mc->default_ram_id = "pnv.ram"; 2898 ispc->print_info = pnv_pic_print_info; 2899 nc->nmi_monitor_handler = pnv_nmi; 2900 2901 object_class_property_add_bool(oc, "hb-mode", 2902 pnv_machine_get_hb, pnv_machine_set_hb); 2903 object_class_property_set_description(oc, "hb-mode", 2904 "Use a hostboot like boot loader"); 2905 } 2906 2907 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2908 { \ 2909 .name = type, \ 2910 .class_init = class_initfn, \ 2911 .parent = TYPE_PNV8_CHIP, \ 2912 } 2913 2914 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2915 { \ 2916 .name = type, \ 2917 .class_init = class_initfn, \ 2918 .parent = TYPE_PNV9_CHIP, \ 2919 } 2920 2921 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2922 { \ 2923 .name = type, \ 2924 .class_init = class_initfn, \ 2925 .parent = TYPE_PNV10_CHIP, \ 2926 } 2927 2928 static const TypeInfo types[] = { 2929 { 2930 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2931 .parent = MACHINE_TYPE_NAME("powernv10"), 2932 .class_init = pnv_machine_p10_rainier_class_init, 2933 }, 2934 { 2935 .name = MACHINE_TYPE_NAME("powernv10"), 2936 .parent = TYPE_PNV_MACHINE, 2937 .class_init = pnv_machine_power10_class_init, 2938 .interfaces = (InterfaceInfo[]) { 2939 { TYPE_XIVE_FABRIC }, 2940 { }, 2941 }, 2942 }, 2943 { 2944 .name = MACHINE_TYPE_NAME("powernv9"), 2945 .parent = TYPE_PNV_MACHINE, 2946 .class_init = pnv_machine_power9_class_init, 2947 .interfaces = (InterfaceInfo[]) { 2948 { TYPE_XIVE_FABRIC }, 2949 { }, 2950 }, 2951 }, 2952 { 2953 .name = MACHINE_TYPE_NAME("powernv8"), 2954 .parent = TYPE_PNV_MACHINE, 2955 .class_init = pnv_machine_power8_class_init, 2956 .interfaces = (InterfaceInfo[]) { 2957 { TYPE_XICS_FABRIC }, 2958 { }, 2959 }, 2960 }, 2961 { 2962 .name = TYPE_PNV_MACHINE, 2963 .parent = TYPE_MACHINE, 2964 .abstract = true, 2965 .instance_size = sizeof(PnvMachineState), 2966 .class_init = pnv_machine_class_init, 2967 .class_size = sizeof(PnvMachineClass), 2968 .interfaces = (InterfaceInfo[]) { 2969 { TYPE_INTERRUPT_STATS_PROVIDER }, 2970 { TYPE_NMI }, 2971 { }, 2972 }, 2973 }, 2974 { 2975 .name = TYPE_PNV_CHIP, 2976 .parent = TYPE_SYS_BUS_DEVICE, 2977 .class_init = pnv_chip_class_init, 2978 .instance_size = sizeof(PnvChip), 2979 .class_size = sizeof(PnvChipClass), 2980 .abstract = true, 2981 }, 2982 2983 /* 2984 * P10 chip and variants 2985 */ 2986 { 2987 .name = TYPE_PNV10_CHIP, 2988 .parent = TYPE_PNV_CHIP, 2989 .instance_init = pnv_chip_power10_instance_init, 2990 .instance_size = sizeof(Pnv10Chip), 2991 }, 2992 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2993 2994 /* 2995 * P9 chip and variants 2996 */ 2997 { 2998 .name = TYPE_PNV9_CHIP, 2999 .parent = TYPE_PNV_CHIP, 3000 .instance_init = pnv_chip_power9_instance_init, 3001 .instance_size = sizeof(Pnv9Chip), 3002 }, 3003 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 3004 3005 /* 3006 * P8 chip and variants 3007 */ 3008 { 3009 .name = TYPE_PNV8_CHIP, 3010 .parent = TYPE_PNV_CHIP, 3011 .instance_init = pnv_chip_power8_instance_init, 3012 .instance_size = sizeof(Pnv8Chip), 3013 }, 3014 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 3015 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 3016 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 3017 pnv_chip_power8nvl_class_init), 3018 }; 3019 3020 DEFINE_TYPES(types) 3021