1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 #include "hw/pci/msi.h" 44 45 #include "hw/ppc/xics.h" 46 #include "hw/qdev-properties.h" 47 #include "hw/ppc/pnv_xscom.h" 48 #include "hw/ppc/pnv_pnor.h" 49 50 #include "hw/isa/isa.h" 51 #include "hw/boards.h" 52 #include "hw/char/serial.h" 53 #include "hw/rtc/mc146818rtc.h" 54 55 #include <libfdt.h> 56 57 #define FDT_MAX_SIZE (1 * MiB) 58 59 #define FW_FILE_NAME "skiboot.lid" 60 #define FW_LOAD_ADDR 0x0 61 #define FW_MAX_SIZE (4 * MiB) 62 63 #define KERNEL_LOAD_ADDR 0x20000000 64 #define KERNEL_MAX_SIZE (256 * MiB) 65 #define INITRD_LOAD_ADDR 0x60000000 66 #define INITRD_MAX_SIZE (256 * MiB) 67 68 static const char *pnv_chip_core_typename(const PnvChip *o) 69 { 70 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 71 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 72 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 73 const char *core_type = object_class_get_name(object_class_by_name(s)); 74 g_free(s); 75 return core_type; 76 } 77 78 /* 79 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 80 * 4 * 4 sockets * 12 cores * 8 threads = 1536 81 * Let's make it 2^11 82 */ 83 #define MAX_CPUS 2048 84 85 /* 86 * Memory nodes are created by hostboot, one for each range of memory 87 * that has a different "affinity". In practice, it means one range 88 * per chip. 89 */ 90 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 91 { 92 char *mem_name; 93 uint64_t mem_reg_property[2]; 94 int off; 95 96 mem_reg_property[0] = cpu_to_be64(start); 97 mem_reg_property[1] = cpu_to_be64(size); 98 99 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 100 off = fdt_add_subnode(fdt, 0, mem_name); 101 g_free(mem_name); 102 103 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 104 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 105 sizeof(mem_reg_property)))); 106 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 107 } 108 109 static int get_cpus_node(void *fdt) 110 { 111 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 112 113 if (cpus_offset < 0) { 114 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 115 if (cpus_offset) { 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 117 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 118 } 119 } 120 _FDT(cpus_offset); 121 return cpus_offset; 122 } 123 124 /* 125 * The PowerNV cores (and threads) need to use real HW ids and not an 126 * incremental index like it has been done on other platforms. This HW 127 * id is stored in the CPU PIR, it is used to create cpu nodes in the 128 * device tree, used in XSCOM to address cores and in interrupt 129 * servers. 130 */ 131 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 132 { 133 PowerPCCPU *cpu = pc->threads[0]; 134 CPUState *cs = CPU(cpu); 135 DeviceClass *dc = DEVICE_GET_CLASS(cs); 136 int smt_threads = CPU_CORE(pc)->nr_threads; 137 CPUPPCState *env = &cpu->env; 138 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 139 uint32_t servers_prop[smt_threads]; 140 int i; 141 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 142 0xffffffff, 0xffffffff}; 143 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 144 uint32_t cpufreq = 1000000000; 145 uint32_t page_sizes_prop[64]; 146 size_t page_sizes_prop_size; 147 const uint8_t pa_features[] = { 24, 0, 148 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 149 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 150 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 151 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 152 int offset; 153 char *nodename; 154 int cpus_offset = get_cpus_node(fdt); 155 156 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 157 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 158 _FDT(offset); 159 g_free(nodename); 160 161 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 165 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 166 167 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 168 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 169 env->dcache_line_size))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 173 env->icache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 175 env->icache_line_size))); 176 177 if (pcc->l1_dcache_size) { 178 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 179 pcc->l1_dcache_size))); 180 } else { 181 warn_report("Unknown L1 dcache size for cpu"); 182 } 183 if (pcc->l1_icache_size) { 184 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 185 pcc->l1_icache_size))); 186 } else { 187 warn_report("Unknown L1 icache size for cpu"); 188 } 189 190 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 192 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 193 cpu->hash64_opts->slb_size))); 194 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 195 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 196 197 if (env->spr_cb[SPR_PURR].oea_read) { 198 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 199 } 200 201 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 202 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 203 segs, sizeof(segs)))); 204 } 205 206 /* 207 * Advertise VMX/VSX (vector extensions) if available 208 * 0 / no property == no vector extensions 209 * 1 == VMX / Altivec available 210 * 2 == VSX available 211 */ 212 if (env->insns_flags & PPC_ALTIVEC) { 213 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 214 215 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 216 } 217 218 /* 219 * Advertise DFP (Decimal Floating Point) if available 220 * 0 / no property == no DFP 221 * 1 == DFP available 222 */ 223 if (env->insns_flags2 & PPC2_DFP) { 224 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 225 } 226 227 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 228 sizeof(page_sizes_prop)); 229 if (page_sizes_prop_size) { 230 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 231 page_sizes_prop, page_sizes_prop_size))); 232 } 233 234 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 235 pa_features, sizeof(pa_features)))); 236 237 /* Build interrupt servers properties */ 238 for (i = 0; i < smt_threads; i++) { 239 servers_prop[i] = cpu_to_be32(pc->pir + i); 240 } 241 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 242 servers_prop, sizeof(servers_prop)))); 243 } 244 245 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 246 uint32_t nr_threads) 247 { 248 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 249 char *name; 250 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 251 uint32_t irange[2], i, rsize; 252 uint64_t *reg; 253 int offset; 254 255 irange[0] = cpu_to_be32(pir); 256 irange[1] = cpu_to_be32(nr_threads); 257 258 rsize = sizeof(uint64_t) * 2 * nr_threads; 259 reg = g_malloc(rsize); 260 for (i = 0; i < nr_threads; i++) { 261 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 262 reg[i * 2 + 1] = cpu_to_be64(0x1000); 263 } 264 265 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 266 offset = fdt_add_subnode(fdt, 0, name); 267 _FDT(offset); 268 g_free(name); 269 270 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 271 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 272 _FDT((fdt_setprop_string(fdt, offset, "device_type", 273 "PowerPC-External-Interrupt-Presentation"))); 274 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 275 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 276 irange, sizeof(irange)))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 278 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 279 g_free(reg); 280 } 281 282 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 283 { 284 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 285 int i; 286 287 pnv_dt_xscom(chip, fdt, 0, 288 cpu_to_be64(PNV_XSCOM_BASE(chip)), 289 cpu_to_be64(PNV_XSCOM_SIZE), 290 compat, sizeof(compat)); 291 292 for (i = 0; i < chip->nr_cores; i++) { 293 PnvCore *pnv_core = chip->cores[i]; 294 295 pnv_dt_core(chip, pnv_core, fdt); 296 297 /* Interrupt Control Presenters (ICP). One per core. */ 298 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 299 } 300 301 if (chip->ram_size) { 302 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 303 } 304 } 305 306 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 307 { 308 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 309 int i; 310 311 pnv_dt_xscom(chip, fdt, 0, 312 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 313 cpu_to_be64(PNV9_XSCOM_SIZE), 314 compat, sizeof(compat)); 315 316 for (i = 0; i < chip->nr_cores; i++) { 317 PnvCore *pnv_core = chip->cores[i]; 318 319 pnv_dt_core(chip, pnv_core, fdt); 320 } 321 322 if (chip->ram_size) { 323 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 324 } 325 326 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 327 } 328 329 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 330 { 331 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 332 int i; 333 334 pnv_dt_xscom(chip, fdt, 0, 335 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 336 cpu_to_be64(PNV10_XSCOM_SIZE), 337 compat, sizeof(compat)); 338 339 for (i = 0; i < chip->nr_cores; i++) { 340 PnvCore *pnv_core = chip->cores[i]; 341 342 pnv_dt_core(chip, pnv_core, fdt); 343 } 344 345 if (chip->ram_size) { 346 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 347 } 348 349 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 350 } 351 352 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 353 { 354 uint32_t io_base = d->ioport_id; 355 uint32_t io_regs[] = { 356 cpu_to_be32(1), 357 cpu_to_be32(io_base), 358 cpu_to_be32(2) 359 }; 360 char *name; 361 int node; 362 363 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 364 node = fdt_add_subnode(fdt, lpc_off, name); 365 _FDT(node); 366 g_free(name); 367 368 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 369 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 370 } 371 372 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 373 { 374 const char compatible[] = "ns16550\0pnpPNP,501"; 375 uint32_t io_base = d->ioport_id; 376 uint32_t io_regs[] = { 377 cpu_to_be32(1), 378 cpu_to_be32(io_base), 379 cpu_to_be32(8) 380 }; 381 char *name; 382 int node; 383 384 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 385 node = fdt_add_subnode(fdt, lpc_off, name); 386 _FDT(node); 387 g_free(name); 388 389 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 390 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 391 sizeof(compatible)))); 392 393 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 394 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 395 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 396 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 397 fdt_get_phandle(fdt, lpc_off)))); 398 399 /* This is needed by Linux */ 400 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 401 } 402 403 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 404 { 405 const char compatible[] = "bt\0ipmi-bt"; 406 uint32_t io_base; 407 uint32_t io_regs[] = { 408 cpu_to_be32(1), 409 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 410 cpu_to_be32(3) 411 }; 412 uint32_t irq; 413 char *name; 414 int node; 415 416 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 417 io_regs[1] = cpu_to_be32(io_base); 418 419 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 420 421 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 422 node = fdt_add_subnode(fdt, lpc_off, name); 423 _FDT(node); 424 g_free(name); 425 426 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 427 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 428 sizeof(compatible)))); 429 430 /* Mark it as reserved to avoid Linux trying to claim it */ 431 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 432 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 433 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 434 fdt_get_phandle(fdt, lpc_off)))); 435 } 436 437 typedef struct ForeachPopulateArgs { 438 void *fdt; 439 int offset; 440 } ForeachPopulateArgs; 441 442 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 443 { 444 ForeachPopulateArgs *args = opaque; 445 ISADevice *d = ISA_DEVICE(dev); 446 447 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 448 pnv_dt_rtc(d, args->fdt, args->offset); 449 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 450 pnv_dt_serial(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 452 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 453 } else { 454 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 455 d->ioport_id); 456 } 457 458 return 0; 459 } 460 461 /* 462 * The default LPC bus of a multichip system is on chip 0. It's 463 * recognized by the firmware (skiboot) using a "primary" property. 464 */ 465 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 466 { 467 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 468 ForeachPopulateArgs args = { 469 .fdt = fdt, 470 .offset = isa_offset, 471 }; 472 uint32_t phandle; 473 474 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 475 476 phandle = qemu_fdt_alloc_phandle(fdt); 477 assert(phandle > 0); 478 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 479 480 /* 481 * ISA devices are not necessarily parented to the ISA bus so we 482 * can not use object_child_foreach() 483 */ 484 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 485 &args); 486 } 487 488 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 489 { 490 int off; 491 492 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 493 off = fdt_add_subnode(fdt, off, "power-mgt"); 494 495 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 496 } 497 498 static void *pnv_dt_create(MachineState *machine) 499 { 500 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 501 PnvMachineState *pnv = PNV_MACHINE(machine); 502 void *fdt; 503 char *buf; 504 int off; 505 int i; 506 507 fdt = g_malloc0(FDT_MAX_SIZE); 508 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 509 510 /* /qemu node */ 511 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 512 513 /* Root node */ 514 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 515 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 516 _FDT((fdt_setprop_string(fdt, 0, "model", 517 "IBM PowerNV (emulated by qemu)"))); 518 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 519 520 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 521 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 522 if (qemu_uuid_set) { 523 _FDT((fdt_property_string(fdt, "system-id", buf))); 524 } 525 g_free(buf); 526 527 off = fdt_add_subnode(fdt, 0, "chosen"); 528 if (machine->kernel_cmdline) { 529 _FDT((fdt_setprop_string(fdt, off, "bootargs", 530 machine->kernel_cmdline))); 531 } 532 533 if (pnv->initrd_size) { 534 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 535 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 536 537 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 538 &start_prop, sizeof(start_prop)))); 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 540 &end_prop, sizeof(end_prop)))); 541 } 542 543 /* Populate device tree for each chip */ 544 for (i = 0; i < pnv->num_chips; i++) { 545 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 546 } 547 548 /* Populate ISA devices on chip 0 */ 549 pnv_dt_isa(pnv, fdt); 550 551 if (pnv->bmc) { 552 pnv_dt_bmc_sensors(pnv->bmc, fdt); 553 } 554 555 /* Create an extra node for power management on machines that support it */ 556 if (pmc->dt_power_mgt) { 557 pmc->dt_power_mgt(pnv, fdt); 558 } 559 560 return fdt; 561 } 562 563 static void pnv_powerdown_notify(Notifier *n, void *opaque) 564 { 565 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 566 567 if (pnv->bmc) { 568 pnv_bmc_powerdown(pnv->bmc); 569 } 570 } 571 572 static void pnv_reset(MachineState *machine) 573 { 574 void *fdt; 575 576 qemu_devices_reset(); 577 578 fdt = pnv_dt_create(machine); 579 580 /* Pack resulting tree */ 581 _FDT((fdt_pack(fdt))); 582 583 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 584 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 585 586 g_free(fdt); 587 } 588 589 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 590 { 591 Pnv8Chip *chip8 = PNV8_CHIP(chip); 592 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 593 } 594 595 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 596 { 597 Pnv8Chip *chip8 = PNV8_CHIP(chip); 598 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 599 } 600 601 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 602 { 603 Pnv9Chip *chip9 = PNV9_CHIP(chip); 604 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 605 } 606 607 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 608 { 609 Pnv10Chip *chip10 = PNV10_CHIP(chip); 610 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 611 } 612 613 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 614 { 615 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 616 } 617 618 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 619 { 620 Pnv8Chip *chip8 = PNV8_CHIP(chip); 621 int i; 622 623 ics_pic_print_info(&chip8->psi.ics, mon); 624 for (i = 0; i < chip->num_phbs; i++) { 625 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 626 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 627 } 628 } 629 630 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 631 { 632 Pnv9Chip *chip9 = PNV9_CHIP(chip); 633 int i, j; 634 635 pnv_xive_pic_print_info(&chip9->xive, mon); 636 pnv_psi_pic_print_info(&chip9->psi, mon); 637 638 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 639 PnvPhb4PecState *pec = &chip9->pecs[i]; 640 for (j = 0; j < pec->num_stacks; j++) { 641 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 642 } 643 } 644 } 645 646 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 647 uint32_t core_id) 648 { 649 return PNV_XSCOM_EX_BASE(core_id); 650 } 651 652 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 653 uint32_t core_id) 654 { 655 return PNV9_XSCOM_EC_BASE(core_id); 656 } 657 658 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 659 uint32_t core_id) 660 { 661 return PNV10_XSCOM_EC_BASE(core_id); 662 } 663 664 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 665 { 666 PowerPCCPUClass *ppc_default = 667 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 668 PowerPCCPUClass *ppc = 669 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 670 671 return ppc_default->pvr_match(ppc_default, ppc->pvr); 672 } 673 674 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 675 { 676 Object *obj; 677 678 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 679 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 680 object_property_set_int(obj, irq, "irq", &error_fatal); 681 object_property_set_bool(obj, true, "realized", &error_fatal); 682 } 683 684 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 685 { 686 Pnv10Chip *chip10 = PNV10_CHIP(chip); 687 688 pnv_psi_pic_print_info(&chip10->psi, mon); 689 } 690 691 static void pnv_init(MachineState *machine) 692 { 693 PnvMachineState *pnv = PNV_MACHINE(machine); 694 MachineClass *mc = MACHINE_GET_CLASS(machine); 695 MemoryRegion *ram; 696 char *fw_filename; 697 long fw_size; 698 int i; 699 char *chip_typename; 700 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 701 DeviceState *dev; 702 703 /* allocate RAM */ 704 if (machine->ram_size < (1 * GiB)) { 705 warn_report("skiboot may not work with < 1GB of RAM"); 706 } 707 708 ram = g_new(MemoryRegion, 1); 709 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 710 machine->ram_size); 711 memory_region_add_subregion(get_system_memory(), 0, ram); 712 713 /* 714 * Create our simple PNOR device 715 */ 716 dev = qdev_create(NULL, TYPE_PNV_PNOR); 717 if (pnor) { 718 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 719 &error_abort); 720 } 721 qdev_init_nofail(dev); 722 pnv->pnor = PNV_PNOR(dev); 723 724 /* load skiboot firmware */ 725 if (bios_name == NULL) { 726 bios_name = FW_FILE_NAME; 727 } 728 729 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 730 if (!fw_filename) { 731 error_report("Could not find OPAL firmware '%s'", bios_name); 732 exit(1); 733 } 734 735 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 736 if (fw_size < 0) { 737 error_report("Could not load OPAL firmware '%s'", fw_filename); 738 exit(1); 739 } 740 g_free(fw_filename); 741 742 /* load kernel */ 743 if (machine->kernel_filename) { 744 long kernel_size; 745 746 kernel_size = load_image_targphys(machine->kernel_filename, 747 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 748 if (kernel_size < 0) { 749 error_report("Could not load kernel '%s'", 750 machine->kernel_filename); 751 exit(1); 752 } 753 } 754 755 /* load initrd */ 756 if (machine->initrd_filename) { 757 pnv->initrd_base = INITRD_LOAD_ADDR; 758 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 759 pnv->initrd_base, INITRD_MAX_SIZE); 760 if (pnv->initrd_size < 0) { 761 error_report("Could not load initial ram disk '%s'", 762 machine->initrd_filename); 763 exit(1); 764 } 765 } 766 767 /* MSIs are supported on this platform */ 768 msi_nonbroken = true; 769 770 /* 771 * Check compatibility of the specified CPU with the machine 772 * default. 773 */ 774 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 775 error_report("invalid CPU model '%s' for %s machine", 776 machine->cpu_type, mc->name); 777 exit(1); 778 } 779 780 /* Create the processor chips */ 781 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 782 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 783 i, machine->cpu_type); 784 if (!object_class_by_name(chip_typename)) { 785 error_report("invalid chip model '%.*s' for %s machine", 786 i, machine->cpu_type, mc->name); 787 exit(1); 788 } 789 790 pnv->num_chips = 791 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 792 /* 793 * TODO: should we decide on how many chips we can create based 794 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 795 */ 796 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 797 error_report("invalid number of chips: '%d'", pnv->num_chips); 798 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 799 exit(1); 800 } 801 802 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 803 for (i = 0; i < pnv->num_chips; i++) { 804 char chip_name[32]; 805 Object *chip = object_new(chip_typename); 806 807 pnv->chips[i] = PNV_CHIP(chip); 808 809 /* 810 * TODO: put all the memory in one node on chip 0 until we find a 811 * way to specify different ranges for each chip 812 */ 813 if (i == 0) { 814 object_property_set_int(chip, machine->ram_size, "ram-size", 815 &error_fatal); 816 } 817 818 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 819 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 820 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 821 &error_fatal); 822 object_property_set_int(chip, machine->smp.cores, 823 "nr-cores", &error_fatal); 824 object_property_set_int(chip, machine->smp.threads, 825 "nr-threads", &error_fatal); 826 /* 827 * The POWER8 machine use the XICS interrupt interface. 828 * Propagate the XICS fabric to the chip and its controllers. 829 */ 830 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 831 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); 832 } 833 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 834 object_property_set_link(chip, OBJECT(pnv), "xive-fabric", 835 &error_abort); 836 } 837 object_property_set_bool(chip, true, "realized", &error_fatal); 838 } 839 g_free(chip_typename); 840 841 /* Create the machine BMC simulator */ 842 pnv->bmc = pnv_bmc_create(pnv->pnor); 843 844 /* Instantiate ISA bus on chip 0 */ 845 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 846 847 /* Create serial port */ 848 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 849 850 /* Create an RTC ISA device too */ 851 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 852 853 /* Create the IPMI BT device for communication with the BMC */ 854 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 855 856 /* 857 * OpenPOWER systems use a IPMI SEL Event message to notify the 858 * host to powerdown 859 */ 860 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 861 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 862 } 863 864 /* 865 * 0:21 Reserved - Read as zeros 866 * 22:24 Chip ID 867 * 25:28 Core number 868 * 29:31 Thread ID 869 */ 870 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 871 { 872 return (chip->chip_id << 7) | (core_id << 3); 873 } 874 875 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 876 Error **errp) 877 { 878 Pnv8Chip *chip8 = PNV8_CHIP(chip); 879 Error *local_err = NULL; 880 Object *obj; 881 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 882 883 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 884 if (local_err) { 885 error_propagate(errp, local_err); 886 return; 887 } 888 889 pnv_cpu->intc = obj; 890 } 891 892 893 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 894 { 895 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 896 897 icp_reset(ICP(pnv_cpu->intc)); 898 } 899 900 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 901 { 902 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 903 904 icp_destroy(ICP(pnv_cpu->intc)); 905 pnv_cpu->intc = NULL; 906 } 907 908 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 909 Monitor *mon) 910 { 911 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 912 } 913 914 /* 915 * 0:48 Reserved - Read as zeroes 916 * 49:52 Node ID 917 * 53:55 Chip ID 918 * 56 Reserved - Read as zero 919 * 57:61 Core number 920 * 62:63 Thread ID 921 * 922 * We only care about the lower bits. uint32_t is fine for the moment. 923 */ 924 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 925 { 926 return (chip->chip_id << 8) | (core_id << 2); 927 } 928 929 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 930 { 931 return (chip->chip_id << 8) | (core_id << 2); 932 } 933 934 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 935 Error **errp) 936 { 937 Pnv9Chip *chip9 = PNV9_CHIP(chip); 938 Error *local_err = NULL; 939 Object *obj; 940 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 941 942 /* 943 * The core creates its interrupt presenter but the XIVE interrupt 944 * controller object is initialized afterwards. Hopefully, it's 945 * only used at runtime. 946 */ 947 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 948 &local_err); 949 if (local_err) { 950 error_propagate(errp, local_err); 951 return; 952 } 953 954 pnv_cpu->intc = obj; 955 } 956 957 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 958 { 959 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 960 961 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 962 } 963 964 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 965 { 966 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 967 968 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 969 pnv_cpu->intc = NULL; 970 } 971 972 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 973 Monitor *mon) 974 { 975 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 976 } 977 978 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 979 Error **errp) 980 { 981 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 982 983 /* Will be defined when the interrupt controller is */ 984 pnv_cpu->intc = NULL; 985 } 986 987 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 988 { 989 ; 990 } 991 992 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 993 { 994 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 995 996 pnv_cpu->intc = NULL; 997 } 998 999 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1000 Monitor *mon) 1001 { 1002 } 1003 1004 /* 1005 * Allowed core identifiers on a POWER8 Processor Chip : 1006 * 1007 * <EX0 reserved> 1008 * EX1 - Venice only 1009 * EX2 - Venice only 1010 * EX3 - Venice only 1011 * EX4 1012 * EX5 1013 * EX6 1014 * <EX7,8 reserved> <reserved> 1015 * EX9 - Venice only 1016 * EX10 - Venice only 1017 * EX11 - Venice only 1018 * EX12 1019 * EX13 1020 * EX14 1021 * <EX15 reserved> 1022 */ 1023 #define POWER8E_CORE_MASK (0x7070ull) 1024 #define POWER8_CORE_MASK (0x7e7eull) 1025 1026 /* 1027 * POWER9 has 24 cores, ids starting at 0x0 1028 */ 1029 #define POWER9_CORE_MASK (0xffffffffffffffull) 1030 1031 1032 #define POWER10_CORE_MASK (0xffffffffffffffull) 1033 1034 static void pnv_chip_power8_instance_init(Object *obj) 1035 { 1036 PnvChip *chip = PNV_CHIP(obj); 1037 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1038 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1039 int i; 1040 1041 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1042 (Object **)&chip8->xics, 1043 object_property_allow_set_link, 1044 OBJ_PROP_LINK_STRONG, 1045 &error_abort); 1046 1047 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 1048 TYPE_PNV8_PSI, &error_abort, NULL); 1049 1050 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 1051 TYPE_PNV8_LPC, &error_abort, NULL); 1052 1053 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 1054 TYPE_PNV8_OCC, &error_abort, NULL); 1055 1056 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 1057 TYPE_PNV8_HOMER, &error_abort, NULL); 1058 1059 for (i = 0; i < pcc->num_phbs; i++) { 1060 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], 1061 sizeof(chip8->phbs[i]), TYPE_PNV_PHB3, 1062 &error_abort, NULL); 1063 } 1064 1065 /* 1066 * Number of PHBs is the chip default 1067 */ 1068 chip->num_phbs = pcc->num_phbs; 1069 } 1070 1071 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1072 { 1073 PnvChip *chip = PNV_CHIP(chip8); 1074 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1075 int i, j; 1076 char *name; 1077 1078 name = g_strdup_printf("icp-%x", chip->chip_id); 1079 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1080 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1081 g_free(name); 1082 1083 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1084 1085 /* Map the ICP registers for each thread */ 1086 for (i = 0; i < chip->nr_cores; i++) { 1087 PnvCore *pnv_core = chip->cores[i]; 1088 int core_hwid = CPU_CORE(pnv_core)->core_id; 1089 1090 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1091 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1092 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1093 1094 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1095 &icp->mmio); 1096 } 1097 } 1098 } 1099 1100 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1101 { 1102 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1103 PnvChip *chip = PNV_CHIP(dev); 1104 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1105 Pnv8Psi *psi8 = &chip8->psi; 1106 Error *local_err = NULL; 1107 int i; 1108 1109 assert(chip8->xics); 1110 1111 /* XSCOM bridge is first */ 1112 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1113 if (local_err) { 1114 error_propagate(errp, local_err); 1115 return; 1116 } 1117 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1118 1119 pcc->parent_realize(dev, &local_err); 1120 if (local_err) { 1121 error_propagate(errp, local_err); 1122 return; 1123 } 1124 1125 /* Processor Service Interface (PSI) Host Bridge */ 1126 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1127 "bar", &error_fatal); 1128 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), 1129 ICS_PROP_XICS, &error_abort); 1130 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 1131 if (local_err) { 1132 error_propagate(errp, local_err); 1133 return; 1134 } 1135 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1136 &PNV_PSI(psi8)->xscom_regs); 1137 1138 /* Create LPC controller */ 1139 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1140 &error_abort); 1141 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 1142 &error_fatal); 1143 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1144 1145 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1146 (uint64_t) PNV_XSCOM_BASE(chip), 1147 PNV_XSCOM_LPC_BASE); 1148 1149 /* 1150 * Interrupt Management Area. This is the memory region holding 1151 * all the Interrupt Control Presenter (ICP) registers 1152 */ 1153 pnv_chip_icp_realize(chip8, &local_err); 1154 if (local_err) { 1155 error_propagate(errp, local_err); 1156 return; 1157 } 1158 1159 /* Create the simplified OCC model */ 1160 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1161 &error_abort); 1162 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1163 if (local_err) { 1164 error_propagate(errp, local_err); 1165 return; 1166 } 1167 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1168 1169 /* OCC SRAM model */ 1170 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1171 &chip8->occ.sram_regs); 1172 1173 /* HOMER */ 1174 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1175 &error_abort); 1176 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1177 &local_err); 1178 if (local_err) { 1179 error_propagate(errp, local_err); 1180 return; 1181 } 1182 /* Homer Xscom region */ 1183 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1184 1185 /* Homer mmio region */ 1186 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1187 &chip8->homer.regs); 1188 1189 /* PHB3 controllers */ 1190 for (i = 0; i < chip->num_phbs; i++) { 1191 PnvPHB3 *phb = &chip8->phbs[i]; 1192 PnvPBCQState *pbcq = &phb->pbcq; 1193 1194 object_property_set_int(OBJECT(phb), i, "index", &error_fatal); 1195 object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id", 1196 &error_fatal); 1197 object_property_set_bool(OBJECT(phb), true, "realized", &local_err); 1198 if (local_err) { 1199 error_propagate(errp, local_err); 1200 return; 1201 } 1202 qdev_set_parent_bus(DEVICE(phb), sysbus_get_default()); 1203 1204 /* Populate the XSCOM address space. */ 1205 pnv_xscom_add_subregion(chip, 1206 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1207 &pbcq->xscom_nest_regs); 1208 pnv_xscom_add_subregion(chip, 1209 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1210 &pbcq->xscom_pci_regs); 1211 pnv_xscom_add_subregion(chip, 1212 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1213 &pbcq->xscom_spci_regs); 1214 } 1215 } 1216 1217 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1218 { 1219 addr &= (PNV_XSCOM_SIZE - 1); 1220 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1221 } 1222 1223 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1224 { 1225 DeviceClass *dc = DEVICE_CLASS(klass); 1226 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1227 1228 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1229 k->cores_mask = POWER8E_CORE_MASK; 1230 k->num_phbs = 3; 1231 k->core_pir = pnv_chip_core_pir_p8; 1232 k->intc_create = pnv_chip_power8_intc_create; 1233 k->intc_reset = pnv_chip_power8_intc_reset; 1234 k->intc_destroy = pnv_chip_power8_intc_destroy; 1235 k->intc_print_info = pnv_chip_power8_intc_print_info; 1236 k->isa_create = pnv_chip_power8_isa_create; 1237 k->dt_populate = pnv_chip_power8_dt_populate; 1238 k->pic_print_info = pnv_chip_power8_pic_print_info; 1239 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1240 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1241 dc->desc = "PowerNV Chip POWER8E"; 1242 1243 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1244 &k->parent_realize); 1245 } 1246 1247 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1248 { 1249 DeviceClass *dc = DEVICE_CLASS(klass); 1250 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1251 1252 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1253 k->cores_mask = POWER8_CORE_MASK; 1254 k->num_phbs = 3; 1255 k->core_pir = pnv_chip_core_pir_p8; 1256 k->intc_create = pnv_chip_power8_intc_create; 1257 k->intc_reset = pnv_chip_power8_intc_reset; 1258 k->intc_destroy = pnv_chip_power8_intc_destroy; 1259 k->intc_print_info = pnv_chip_power8_intc_print_info; 1260 k->isa_create = pnv_chip_power8_isa_create; 1261 k->dt_populate = pnv_chip_power8_dt_populate; 1262 k->pic_print_info = pnv_chip_power8_pic_print_info; 1263 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1264 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1265 dc->desc = "PowerNV Chip POWER8"; 1266 1267 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1268 &k->parent_realize); 1269 } 1270 1271 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1272 { 1273 DeviceClass *dc = DEVICE_CLASS(klass); 1274 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1275 1276 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1277 k->cores_mask = POWER8_CORE_MASK; 1278 k->num_phbs = 3; 1279 k->core_pir = pnv_chip_core_pir_p8; 1280 k->intc_create = pnv_chip_power8_intc_create; 1281 k->intc_reset = pnv_chip_power8_intc_reset; 1282 k->intc_destroy = pnv_chip_power8_intc_destroy; 1283 k->intc_print_info = pnv_chip_power8_intc_print_info; 1284 k->isa_create = pnv_chip_power8nvl_isa_create; 1285 k->dt_populate = pnv_chip_power8_dt_populate; 1286 k->pic_print_info = pnv_chip_power8_pic_print_info; 1287 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1288 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1289 dc->desc = "PowerNV Chip POWER8NVL"; 1290 1291 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1292 &k->parent_realize); 1293 } 1294 1295 static void pnv_chip_power9_instance_init(Object *obj) 1296 { 1297 PnvChip *chip = PNV_CHIP(obj); 1298 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1299 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1300 int i; 1301 1302 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1303 TYPE_PNV_XIVE, &error_abort, NULL); 1304 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1305 "xive-fabric", &error_abort); 1306 1307 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1308 TYPE_PNV9_PSI, &error_abort, NULL); 1309 1310 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1311 TYPE_PNV9_LPC, &error_abort, NULL); 1312 1313 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1314 TYPE_PNV9_OCC, &error_abort, NULL); 1315 1316 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1317 TYPE_PNV9_HOMER, &error_abort, NULL); 1318 1319 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1320 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1321 sizeof(chip9->pecs[i]), TYPE_PNV_PHB4_PEC, 1322 &error_abort, NULL); 1323 } 1324 1325 /* 1326 * Number of PHBs is the chip default 1327 */ 1328 chip->num_phbs = pcc->num_phbs; 1329 } 1330 1331 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1332 { 1333 PnvChip *chip = PNV_CHIP(chip9); 1334 int i; 1335 1336 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1337 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1338 1339 for (i = 0; i < chip9->nr_quads; i++) { 1340 char eq_name[32]; 1341 PnvQuad *eq = &chip9->quads[i]; 1342 PnvCore *pnv_core = chip->cores[i * 4]; 1343 int core_id = CPU_CORE(pnv_core)->core_id; 1344 1345 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1346 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1347 TYPE_PNV_QUAD, &error_fatal, NULL); 1348 1349 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1350 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1351 1352 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1353 &eq->xscom_regs); 1354 } 1355 } 1356 1357 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1358 { 1359 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1360 Error *local_err = NULL; 1361 int i, j; 1362 int phb_id = 0; 1363 1364 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1365 PnvPhb4PecState *pec = &chip9->pecs[i]; 1366 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1367 uint32_t pec_nest_base; 1368 uint32_t pec_pci_base; 1369 1370 object_property_set_int(OBJECT(pec), i, "index", &error_fatal); 1371 /* 1372 * PEC0 -> 1 stack 1373 * PEC1 -> 2 stacks 1374 * PEC2 -> 3 stacks 1375 */ 1376 object_property_set_int(OBJECT(pec), i + 1, "num-stacks", 1377 &error_fatal); 1378 object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id", 1379 &error_fatal); 1380 object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()), 1381 "system-memory", &error_abort); 1382 object_property_set_bool(OBJECT(pec), true, "realized", &local_err); 1383 if (local_err) { 1384 error_propagate(errp, local_err); 1385 return; 1386 } 1387 1388 pec_nest_base = pecc->xscom_nest_base(pec); 1389 pec_pci_base = pecc->xscom_pci_base(pec); 1390 1391 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1392 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1393 1394 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1395 j++, phb_id++) { 1396 PnvPhb4PecStack *stack = &pec->stacks[j]; 1397 Object *obj = OBJECT(&stack->phb); 1398 1399 object_property_set_int(obj, phb_id, "index", &error_fatal); 1400 object_property_set_int(obj, chip->chip_id, "chip-id", 1401 &error_fatal); 1402 object_property_set_int(obj, PNV_PHB4_VERSION, "version", 1403 &error_fatal); 1404 object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id", 1405 &error_fatal); 1406 object_property_set_link(obj, OBJECT(stack), "stack", &error_abort); 1407 object_property_set_bool(obj, true, "realized", &local_err); 1408 if (local_err) { 1409 error_propagate(errp, local_err); 1410 return; 1411 } 1412 qdev_set_parent_bus(DEVICE(obj), sysbus_get_default()); 1413 1414 /* Populate the XSCOM address space. */ 1415 pnv_xscom_add_subregion(chip, 1416 pec_nest_base + 0x40 * (stack->stack_no + 1), 1417 &stack->nest_regs_mr); 1418 pnv_xscom_add_subregion(chip, 1419 pec_pci_base + 0x40 * (stack->stack_no + 1), 1420 &stack->pci_regs_mr); 1421 pnv_xscom_add_subregion(chip, 1422 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1423 0x40 * stack->stack_no, 1424 &stack->phb_regs_mr); 1425 } 1426 } 1427 } 1428 1429 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1430 { 1431 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1432 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1433 PnvChip *chip = PNV_CHIP(dev); 1434 Pnv9Psi *psi9 = &chip9->psi; 1435 Error *local_err = NULL; 1436 1437 /* XSCOM bridge is first */ 1438 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1439 if (local_err) { 1440 error_propagate(errp, local_err); 1441 return; 1442 } 1443 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1444 1445 pcc->parent_realize(dev, &local_err); 1446 if (local_err) { 1447 error_propagate(errp, local_err); 1448 return; 1449 } 1450 1451 pnv_chip_quad_realize(chip9, &local_err); 1452 if (local_err) { 1453 error_propagate(errp, local_err); 1454 return; 1455 } 1456 1457 /* XIVE interrupt controller (POWER9) */ 1458 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1459 "ic-bar", &error_fatal); 1460 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1461 "vc-bar", &error_fatal); 1462 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1463 "pc-bar", &error_fatal); 1464 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1465 "tm-bar", &error_fatal); 1466 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1467 &error_abort); 1468 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1469 &local_err); 1470 if (local_err) { 1471 error_propagate(errp, local_err); 1472 return; 1473 } 1474 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1475 &chip9->xive.xscom_regs); 1476 1477 /* Processor Service Interface (PSI) Host Bridge */ 1478 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1479 "bar", &error_fatal); 1480 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1481 if (local_err) { 1482 error_propagate(errp, local_err); 1483 return; 1484 } 1485 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1486 &PNV_PSI(psi9)->xscom_regs); 1487 1488 /* LPC */ 1489 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1490 &error_abort); 1491 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1492 if (local_err) { 1493 error_propagate(errp, local_err); 1494 return; 1495 } 1496 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1497 &chip9->lpc.xscom_regs); 1498 1499 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1500 (uint64_t) PNV9_LPCM_BASE(chip)); 1501 1502 /* Create the simplified OCC model */ 1503 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1504 &error_abort); 1505 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1506 if (local_err) { 1507 error_propagate(errp, local_err); 1508 return; 1509 } 1510 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1511 1512 /* OCC SRAM model */ 1513 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1514 &chip9->occ.sram_regs); 1515 1516 /* HOMER */ 1517 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1518 &error_abort); 1519 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1520 &local_err); 1521 if (local_err) { 1522 error_propagate(errp, local_err); 1523 return; 1524 } 1525 /* Homer Xscom region */ 1526 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1527 1528 /* Homer mmio region */ 1529 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1530 &chip9->homer.regs); 1531 1532 /* PHBs */ 1533 pnv_chip_power9_phb_realize(chip, &local_err); 1534 if (local_err) { 1535 error_propagate(errp, local_err); 1536 return; 1537 } 1538 } 1539 1540 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1541 { 1542 addr &= (PNV9_XSCOM_SIZE - 1); 1543 return addr >> 3; 1544 } 1545 1546 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1547 { 1548 DeviceClass *dc = DEVICE_CLASS(klass); 1549 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1550 1551 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1552 k->cores_mask = POWER9_CORE_MASK; 1553 k->core_pir = pnv_chip_core_pir_p9; 1554 k->intc_create = pnv_chip_power9_intc_create; 1555 k->intc_reset = pnv_chip_power9_intc_reset; 1556 k->intc_destroy = pnv_chip_power9_intc_destroy; 1557 k->intc_print_info = pnv_chip_power9_intc_print_info; 1558 k->isa_create = pnv_chip_power9_isa_create; 1559 k->dt_populate = pnv_chip_power9_dt_populate; 1560 k->pic_print_info = pnv_chip_power9_pic_print_info; 1561 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1562 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1563 dc->desc = "PowerNV Chip POWER9"; 1564 k->num_phbs = 6; 1565 1566 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1567 &k->parent_realize); 1568 } 1569 1570 static void pnv_chip_power10_instance_init(Object *obj) 1571 { 1572 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1573 1574 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), 1575 TYPE_PNV10_PSI, &error_abort, NULL); 1576 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), 1577 TYPE_PNV10_LPC, &error_abort, NULL); 1578 } 1579 1580 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1581 { 1582 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1583 PnvChip *chip = PNV_CHIP(dev); 1584 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1585 Error *local_err = NULL; 1586 1587 /* XSCOM bridge is first */ 1588 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1589 if (local_err) { 1590 error_propagate(errp, local_err); 1591 return; 1592 } 1593 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1594 1595 pcc->parent_realize(dev, &local_err); 1596 if (local_err) { 1597 error_propagate(errp, local_err); 1598 return; 1599 } 1600 1601 /* Processor Service Interface (PSI) Host Bridge */ 1602 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1603 "bar", &error_fatal); 1604 object_property_set_bool(OBJECT(&chip10->psi), true, "realized", 1605 &local_err); 1606 if (local_err) { 1607 error_propagate(errp, local_err); 1608 return; 1609 } 1610 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1611 &PNV_PSI(&chip10->psi)->xscom_regs); 1612 1613 /* LPC */ 1614 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1615 &error_abort); 1616 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", 1617 &local_err); 1618 if (local_err) { 1619 error_propagate(errp, local_err); 1620 return; 1621 } 1622 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1623 &chip10->lpc.xscom_regs); 1624 1625 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1626 (uint64_t) PNV10_LPCM_BASE(chip)); 1627 } 1628 1629 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1630 { 1631 addr &= (PNV10_XSCOM_SIZE - 1); 1632 return addr >> 3; 1633 } 1634 1635 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1636 { 1637 DeviceClass *dc = DEVICE_CLASS(klass); 1638 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1639 1640 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1641 k->cores_mask = POWER10_CORE_MASK; 1642 k->core_pir = pnv_chip_core_pir_p10; 1643 k->intc_create = pnv_chip_power10_intc_create; 1644 k->intc_reset = pnv_chip_power10_intc_reset; 1645 k->intc_destroy = pnv_chip_power10_intc_destroy; 1646 k->intc_print_info = pnv_chip_power10_intc_print_info; 1647 k->isa_create = pnv_chip_power10_isa_create; 1648 k->dt_populate = pnv_chip_power10_dt_populate; 1649 k->pic_print_info = pnv_chip_power10_pic_print_info; 1650 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1651 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1652 dc->desc = "PowerNV Chip POWER10"; 1653 1654 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1655 &k->parent_realize); 1656 } 1657 1658 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1659 { 1660 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1661 int cores_max; 1662 1663 /* 1664 * No custom mask for this chip, let's use the default one from * 1665 * the chip class 1666 */ 1667 if (!chip->cores_mask) { 1668 chip->cores_mask = pcc->cores_mask; 1669 } 1670 1671 /* filter alien core ids ! some are reserved */ 1672 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1673 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1674 chip->cores_mask); 1675 return; 1676 } 1677 chip->cores_mask &= pcc->cores_mask; 1678 1679 /* now that we have a sane layout, let check the number of cores */ 1680 cores_max = ctpop64(chip->cores_mask); 1681 if (chip->nr_cores > cores_max) { 1682 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1683 cores_max); 1684 return; 1685 } 1686 } 1687 1688 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1689 { 1690 Error *error = NULL; 1691 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1692 const char *typename = pnv_chip_core_typename(chip); 1693 int i, core_hwid; 1694 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1695 1696 if (!object_class_by_name(typename)) { 1697 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1698 return; 1699 } 1700 1701 /* Cores */ 1702 pnv_chip_core_sanitize(chip, &error); 1703 if (error) { 1704 error_propagate(errp, error); 1705 return; 1706 } 1707 1708 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1709 1710 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1711 && (i < chip->nr_cores); core_hwid++) { 1712 char core_name[32]; 1713 PnvCore *pnv_core; 1714 uint64_t xscom_core_base; 1715 1716 if (!(chip->cores_mask & (1ull << core_hwid))) { 1717 continue; 1718 } 1719 1720 pnv_core = PNV_CORE(object_new(typename)); 1721 1722 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1723 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1724 &error_abort); 1725 chip->cores[i] = pnv_core; 1726 object_property_set_int(OBJECT(pnv_core), chip->nr_threads, 1727 "nr-threads", &error_fatal); 1728 object_property_set_int(OBJECT(pnv_core), core_hwid, 1729 CPU_CORE_PROP_CORE_ID, &error_fatal); 1730 object_property_set_int(OBJECT(pnv_core), 1731 pcc->core_pir(chip, core_hwid), 1732 "pir", &error_fatal); 1733 object_property_set_int(OBJECT(pnv_core), pnv->fw_load_addr, 1734 "hrmor", &error_fatal); 1735 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1736 &error_abort); 1737 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1738 &error_fatal); 1739 1740 /* Each core has an XSCOM MMIO region */ 1741 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1742 1743 pnv_xscom_add_subregion(chip, xscom_core_base, 1744 &pnv_core->xscom_regs); 1745 i++; 1746 } 1747 } 1748 1749 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1750 { 1751 PnvChip *chip = PNV_CHIP(dev); 1752 Error *error = NULL; 1753 1754 /* Cores */ 1755 pnv_chip_core_realize(chip, &error); 1756 if (error) { 1757 error_propagate(errp, error); 1758 return; 1759 } 1760 } 1761 1762 static Property pnv_chip_properties[] = { 1763 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1764 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1765 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1766 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1767 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1768 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1769 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1770 DEFINE_PROP_END_OF_LIST(), 1771 }; 1772 1773 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1774 { 1775 DeviceClass *dc = DEVICE_CLASS(klass); 1776 1777 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1778 dc->realize = pnv_chip_realize; 1779 device_class_set_props(dc, pnv_chip_properties); 1780 dc->desc = "PowerNV Chip"; 1781 } 1782 1783 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1784 { 1785 int i, j; 1786 1787 for (i = 0; i < chip->nr_cores; i++) { 1788 PnvCore *pc = chip->cores[i]; 1789 CPUCore *cc = CPU_CORE(pc); 1790 1791 for (j = 0; j < cc->nr_threads; j++) { 1792 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1793 return pc->threads[j]; 1794 } 1795 } 1796 } 1797 return NULL; 1798 } 1799 1800 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1801 { 1802 PnvMachineState *pnv = PNV_MACHINE(xi); 1803 int i, j; 1804 1805 for (i = 0; i < pnv->num_chips; i++) { 1806 PnvChip *chip = pnv->chips[i]; 1807 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1808 1809 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1810 return &chip8->psi.ics; 1811 } 1812 for (j = 0; j < chip->num_phbs; j++) { 1813 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1814 return &chip8->phbs[j].lsis; 1815 } 1816 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1817 return ICS(&chip8->phbs[j].msis); 1818 } 1819 } 1820 } 1821 return NULL; 1822 } 1823 1824 static void pnv_ics_resend(XICSFabric *xi) 1825 { 1826 PnvMachineState *pnv = PNV_MACHINE(xi); 1827 int i, j; 1828 1829 for (i = 0; i < pnv->num_chips; i++) { 1830 PnvChip *chip = pnv->chips[i]; 1831 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1832 1833 ics_resend(&chip8->psi.ics); 1834 for (j = 0; j < chip->num_phbs; j++) { 1835 ics_resend(&chip8->phbs[j].lsis); 1836 ics_resend(ICS(&chip8->phbs[j].msis)); 1837 } 1838 } 1839 } 1840 1841 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1842 { 1843 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1844 1845 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1846 } 1847 1848 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1849 Monitor *mon) 1850 { 1851 PnvMachineState *pnv = PNV_MACHINE(obj); 1852 int i; 1853 CPUState *cs; 1854 1855 CPU_FOREACH(cs) { 1856 PowerPCCPU *cpu = POWERPC_CPU(cs); 1857 1858 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1859 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1860 mon); 1861 } 1862 1863 for (i = 0; i < pnv->num_chips; i++) { 1864 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1865 } 1866 } 1867 1868 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1869 uint8_t nvt_blk, uint32_t nvt_idx, 1870 bool cam_ignore, uint8_t priority, 1871 uint32_t logic_serv, 1872 XiveTCTXMatch *match) 1873 { 1874 PnvMachineState *pnv = PNV_MACHINE(xfb); 1875 int total_count = 0; 1876 int i; 1877 1878 for (i = 0; i < pnv->num_chips; i++) { 1879 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1880 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1881 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1882 int count; 1883 1884 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1885 priority, logic_serv, match); 1886 1887 if (count < 0) { 1888 return count; 1889 } 1890 1891 total_count += count; 1892 } 1893 1894 return total_count; 1895 } 1896 1897 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1898 { 1899 MachineClass *mc = MACHINE_CLASS(oc); 1900 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1901 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1902 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1903 1904 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1905 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1906 1907 xic->icp_get = pnv_icp_get; 1908 xic->ics_get = pnv_ics_get; 1909 xic->ics_resend = pnv_ics_resend; 1910 1911 pmc->compat = compat; 1912 pmc->compat_size = sizeof(compat); 1913 } 1914 1915 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1916 { 1917 MachineClass *mc = MACHINE_CLASS(oc); 1918 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1919 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1920 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1921 1922 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1923 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1924 xfc->match_nvt = pnv_match_nvt; 1925 1926 mc->alias = "powernv"; 1927 1928 pmc->compat = compat; 1929 pmc->compat_size = sizeof(compat); 1930 pmc->dt_power_mgt = pnv_dt_power_mgt; 1931 } 1932 1933 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1934 { 1935 MachineClass *mc = MACHINE_CLASS(oc); 1936 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1937 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1938 1939 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1940 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1941 1942 pmc->compat = compat; 1943 pmc->compat_size = sizeof(compat); 1944 pmc->dt_power_mgt = pnv_dt_power_mgt; 1945 } 1946 1947 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1948 { 1949 PnvMachineState *pnv = PNV_MACHINE(obj); 1950 1951 return !!pnv->fw_load_addr; 1952 } 1953 1954 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1955 { 1956 PnvMachineState *pnv = PNV_MACHINE(obj); 1957 1958 if (value) { 1959 pnv->fw_load_addr = 0x8000000; 1960 } 1961 } 1962 1963 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1964 { 1965 MachineClass *mc = MACHINE_CLASS(oc); 1966 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1967 1968 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1969 mc->init = pnv_init; 1970 mc->reset = pnv_reset; 1971 mc->max_cpus = MAX_CPUS; 1972 /* Pnv provides a AHCI device for storage */ 1973 mc->block_default_type = IF_IDE; 1974 mc->no_parallel = 1; 1975 mc->default_boot_order = NULL; 1976 /* 1977 * RAM defaults to less than 2048 for 32-bit hosts, and large 1978 * enough to fit the maximum initrd size at it's load address 1979 */ 1980 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1981 ispc->print_info = pnv_pic_print_info; 1982 1983 object_class_property_add_bool(oc, "hb-mode", 1984 pnv_machine_get_hb, pnv_machine_set_hb, 1985 &error_abort); 1986 object_class_property_set_description(oc, "hb-mode", 1987 "Use a hostboot like boot loader", 1988 NULL); 1989 } 1990 1991 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1992 { \ 1993 .name = type, \ 1994 .class_init = class_initfn, \ 1995 .parent = TYPE_PNV8_CHIP, \ 1996 } 1997 1998 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1999 { \ 2000 .name = type, \ 2001 .class_init = class_initfn, \ 2002 .parent = TYPE_PNV9_CHIP, \ 2003 } 2004 2005 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2006 { \ 2007 .name = type, \ 2008 .class_init = class_initfn, \ 2009 .parent = TYPE_PNV10_CHIP, \ 2010 } 2011 2012 static const TypeInfo types[] = { 2013 { 2014 .name = MACHINE_TYPE_NAME("powernv10"), 2015 .parent = TYPE_PNV_MACHINE, 2016 .class_init = pnv_machine_power10_class_init, 2017 }, 2018 { 2019 .name = MACHINE_TYPE_NAME("powernv9"), 2020 .parent = TYPE_PNV_MACHINE, 2021 .class_init = pnv_machine_power9_class_init, 2022 .interfaces = (InterfaceInfo[]) { 2023 { TYPE_XIVE_FABRIC }, 2024 { }, 2025 }, 2026 }, 2027 { 2028 .name = MACHINE_TYPE_NAME("powernv8"), 2029 .parent = TYPE_PNV_MACHINE, 2030 .class_init = pnv_machine_power8_class_init, 2031 .interfaces = (InterfaceInfo[]) { 2032 { TYPE_XICS_FABRIC }, 2033 { }, 2034 }, 2035 }, 2036 { 2037 .name = TYPE_PNV_MACHINE, 2038 .parent = TYPE_MACHINE, 2039 .abstract = true, 2040 .instance_size = sizeof(PnvMachineState), 2041 .class_init = pnv_machine_class_init, 2042 .class_size = sizeof(PnvMachineClass), 2043 .interfaces = (InterfaceInfo[]) { 2044 { TYPE_INTERRUPT_STATS_PROVIDER }, 2045 { }, 2046 }, 2047 }, 2048 { 2049 .name = TYPE_PNV_CHIP, 2050 .parent = TYPE_SYS_BUS_DEVICE, 2051 .class_init = pnv_chip_class_init, 2052 .instance_size = sizeof(PnvChip), 2053 .class_size = sizeof(PnvChipClass), 2054 .abstract = true, 2055 }, 2056 2057 /* 2058 * P10 chip and variants 2059 */ 2060 { 2061 .name = TYPE_PNV10_CHIP, 2062 .parent = TYPE_PNV_CHIP, 2063 .instance_init = pnv_chip_power10_instance_init, 2064 .instance_size = sizeof(Pnv10Chip), 2065 }, 2066 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2067 2068 /* 2069 * P9 chip and variants 2070 */ 2071 { 2072 .name = TYPE_PNV9_CHIP, 2073 .parent = TYPE_PNV_CHIP, 2074 .instance_init = pnv_chip_power9_instance_init, 2075 .instance_size = sizeof(Pnv9Chip), 2076 }, 2077 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2078 2079 /* 2080 * P8 chip and variants 2081 */ 2082 { 2083 .name = TYPE_PNV8_CHIP, 2084 .parent = TYPE_PNV_CHIP, 2085 .instance_init = pnv_chip_power8_instance_init, 2086 .instance_size = sizeof(Pnv8Chip), 2087 }, 2088 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2089 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2090 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2091 pnv_chip_power8nvl_class_init), 2092 }; 2093 2094 DEFINE_TYPES(types) 2095