1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/cpus.h" 28 #include "sysemu/device_tree.h" 29 #include "hw/hw.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 44 #include "hw/ppc/xics.h" 45 #include "hw/ppc/pnv_xscom.h" 46 47 #include "hw/isa/isa.h" 48 #include "hw/char/serial.h" 49 #include "hw/timer/mc146818rtc.h" 50 51 #include <libfdt.h> 52 53 #define FDT_MAX_SIZE (1 * MiB) 54 55 #define FW_FILE_NAME "skiboot.lid" 56 #define FW_LOAD_ADDR 0x0 57 #define FW_MAX_SIZE (4 * MiB) 58 59 #define KERNEL_LOAD_ADDR 0x20000000 60 #define KERNEL_MAX_SIZE (256 * MiB) 61 #define INITRD_LOAD_ADDR 0x60000000 62 #define INITRD_MAX_SIZE (256 * MiB) 63 64 static const char *pnv_chip_core_typename(const PnvChip *o) 65 { 66 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 67 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 68 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 69 const char *core_type = object_class_get_name(object_class_by_name(s)); 70 g_free(s); 71 return core_type; 72 } 73 74 /* 75 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 76 * 4 * 4 sockets * 12 cores * 8 threads = 1536 77 * Let's make it 2^11 78 */ 79 #define MAX_CPUS 2048 80 81 /* 82 * Memory nodes are created by hostboot, one for each range of memory 83 * that has a different "affinity". In practice, it means one range 84 * per chip. 85 */ 86 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 87 { 88 char *mem_name; 89 uint64_t mem_reg_property[2]; 90 int off; 91 92 mem_reg_property[0] = cpu_to_be64(start); 93 mem_reg_property[1] = cpu_to_be64(size); 94 95 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 96 off = fdt_add_subnode(fdt, 0, mem_name); 97 g_free(mem_name); 98 99 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 100 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 101 sizeof(mem_reg_property)))); 102 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 103 } 104 105 static int get_cpus_node(void *fdt) 106 { 107 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 108 109 if (cpus_offset < 0) { 110 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 111 if (cpus_offset) { 112 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 113 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 114 } 115 } 116 _FDT(cpus_offset); 117 return cpus_offset; 118 } 119 120 /* 121 * The PowerNV cores (and threads) need to use real HW ids and not an 122 * incremental index like it has been done on other platforms. This HW 123 * id is stored in the CPU PIR, it is used to create cpu nodes in the 124 * device tree, used in XSCOM to address cores and in interrupt 125 * servers. 126 */ 127 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 128 { 129 PowerPCCPU *cpu = pc->threads[0]; 130 CPUState *cs = CPU(cpu); 131 DeviceClass *dc = DEVICE_GET_CLASS(cs); 132 int smt_threads = CPU_CORE(pc)->nr_threads; 133 CPUPPCState *env = &cpu->env; 134 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 135 uint32_t servers_prop[smt_threads]; 136 int i; 137 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 138 0xffffffff, 0xffffffff}; 139 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 140 uint32_t cpufreq = 1000000000; 141 uint32_t page_sizes_prop[64]; 142 size_t page_sizes_prop_size; 143 const uint8_t pa_features[] = { 24, 0, 144 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 145 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 146 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 147 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 148 int offset; 149 char *nodename; 150 int cpus_offset = get_cpus_node(fdt); 151 152 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 153 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 154 _FDT(offset); 155 g_free(nodename); 156 157 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 158 159 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 161 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 164 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 165 env->dcache_line_size))); 166 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 167 env->dcache_line_size))); 168 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 169 env->icache_line_size))); 170 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 171 env->icache_line_size))); 172 173 if (pcc->l1_dcache_size) { 174 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 175 pcc->l1_dcache_size))); 176 } else { 177 warn_report("Unknown L1 dcache size for cpu"); 178 } 179 if (pcc->l1_icache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 181 pcc->l1_icache_size))); 182 } else { 183 warn_report("Unknown L1 icache size for cpu"); 184 } 185 186 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 187 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 188 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 189 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 190 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 191 192 if (env->spr_cb[SPR_PURR].oea_read) { 193 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 194 } 195 196 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 197 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 198 segs, sizeof(segs)))); 199 } 200 201 /* Advertise VMX/VSX (vector extensions) if available 202 * 0 / no property == no vector extensions 203 * 1 == VMX / Altivec available 204 * 2 == VSX available */ 205 if (env->insns_flags & PPC_ALTIVEC) { 206 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 207 208 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 209 } 210 211 /* Advertise DFP (Decimal Floating Point) if available 212 * 0 / no property == no DFP 213 * 1 == DFP available */ 214 if (env->insns_flags2 & PPC2_DFP) { 215 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 216 } 217 218 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 219 sizeof(page_sizes_prop)); 220 if (page_sizes_prop_size) { 221 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 222 page_sizes_prop, page_sizes_prop_size))); 223 } 224 225 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 226 pa_features, sizeof(pa_features)))); 227 228 /* Build interrupt servers properties */ 229 for (i = 0; i < smt_threads; i++) { 230 servers_prop[i] = cpu_to_be32(pc->pir + i); 231 } 232 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 233 servers_prop, sizeof(servers_prop)))); 234 } 235 236 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 237 uint32_t nr_threads) 238 { 239 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 240 char *name; 241 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 242 uint32_t irange[2], i, rsize; 243 uint64_t *reg; 244 int offset; 245 246 irange[0] = cpu_to_be32(pir); 247 irange[1] = cpu_to_be32(nr_threads); 248 249 rsize = sizeof(uint64_t) * 2 * nr_threads; 250 reg = g_malloc(rsize); 251 for (i = 0; i < nr_threads; i++) { 252 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 253 reg[i * 2 + 1] = cpu_to_be64(0x1000); 254 } 255 256 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 257 offset = fdt_add_subnode(fdt, 0, name); 258 _FDT(offset); 259 g_free(name); 260 261 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 262 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 263 _FDT((fdt_setprop_string(fdt, offset, "device_type", 264 "PowerPC-External-Interrupt-Presentation"))); 265 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 266 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 267 irange, sizeof(irange)))); 268 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 269 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 270 g_free(reg); 271 } 272 273 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 274 { 275 const char *typename = pnv_chip_core_typename(chip); 276 size_t typesize = object_type_get_instance_size(typename); 277 int i; 278 279 pnv_dt_xscom(chip, fdt, 0); 280 281 for (i = 0; i < chip->nr_cores; i++) { 282 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 283 284 pnv_dt_core(chip, pnv_core, fdt); 285 286 /* Interrupt Control Presenters (ICP). One per core. */ 287 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 288 } 289 290 if (chip->ram_size) { 291 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 292 } 293 } 294 295 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 296 { 297 const char *typename = pnv_chip_core_typename(chip); 298 size_t typesize = object_type_get_instance_size(typename); 299 int i; 300 301 pnv_dt_xscom(chip, fdt, 0); 302 303 for (i = 0; i < chip->nr_cores; i++) { 304 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 305 306 pnv_dt_core(chip, pnv_core, fdt); 307 } 308 309 if (chip->ram_size) { 310 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 311 } 312 313 pnv_dt_lpc(chip, fdt, 0); 314 } 315 316 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 317 { 318 uint32_t io_base = d->ioport_id; 319 uint32_t io_regs[] = { 320 cpu_to_be32(1), 321 cpu_to_be32(io_base), 322 cpu_to_be32(2) 323 }; 324 char *name; 325 int node; 326 327 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 328 node = fdt_add_subnode(fdt, lpc_off, name); 329 _FDT(node); 330 g_free(name); 331 332 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 333 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 334 } 335 336 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 337 { 338 const char compatible[] = "ns16550\0pnpPNP,501"; 339 uint32_t io_base = d->ioport_id; 340 uint32_t io_regs[] = { 341 cpu_to_be32(1), 342 cpu_to_be32(io_base), 343 cpu_to_be32(8) 344 }; 345 char *name; 346 int node; 347 348 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 349 node = fdt_add_subnode(fdt, lpc_off, name); 350 _FDT(node); 351 g_free(name); 352 353 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 354 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 355 sizeof(compatible)))); 356 357 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 358 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 359 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 360 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 361 fdt_get_phandle(fdt, lpc_off)))); 362 363 /* This is needed by Linux */ 364 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 365 } 366 367 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 368 { 369 const char compatible[] = "bt\0ipmi-bt"; 370 uint32_t io_base; 371 uint32_t io_regs[] = { 372 cpu_to_be32(1), 373 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 374 cpu_to_be32(3) 375 }; 376 uint32_t irq; 377 char *name; 378 int node; 379 380 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 381 io_regs[1] = cpu_to_be32(io_base); 382 383 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 384 385 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 386 node = fdt_add_subnode(fdt, lpc_off, name); 387 _FDT(node); 388 g_free(name); 389 390 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 391 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 392 sizeof(compatible)))); 393 394 /* Mark it as reserved to avoid Linux trying to claim it */ 395 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 396 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 397 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 398 fdt_get_phandle(fdt, lpc_off)))); 399 } 400 401 typedef struct ForeachPopulateArgs { 402 void *fdt; 403 int offset; 404 } ForeachPopulateArgs; 405 406 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 407 { 408 ForeachPopulateArgs *args = opaque; 409 ISADevice *d = ISA_DEVICE(dev); 410 411 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 412 pnv_dt_rtc(d, args->fdt, args->offset); 413 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 414 pnv_dt_serial(d, args->fdt, args->offset); 415 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 416 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 417 } else { 418 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 419 d->ioport_id); 420 } 421 422 return 0; 423 } 424 425 /* The default LPC bus of a multichip system is on chip 0. It's 426 * recognized by the firmware (skiboot) using a "primary" property. 427 */ 428 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 429 { 430 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 431 ForeachPopulateArgs args = { 432 .fdt = fdt, 433 .offset = isa_offset, 434 }; 435 436 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 437 438 /* ISA devices are not necessarily parented to the ISA bus so we 439 * can not use object_child_foreach() */ 440 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 441 &args); 442 } 443 444 static void pnv_dt_power_mgt(void *fdt) 445 { 446 int off; 447 448 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 449 off = fdt_add_subnode(fdt, off, "power-mgt"); 450 451 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 452 } 453 454 static void *pnv_dt_create(MachineState *machine) 455 { 456 const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 457 const char plat_compat9[] = "qemu,powernv9\0ibm,powernv"; 458 PnvMachineState *pnv = PNV_MACHINE(machine); 459 void *fdt; 460 char *buf; 461 int off; 462 int i; 463 464 fdt = g_malloc0(FDT_MAX_SIZE); 465 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 466 467 /* Root node */ 468 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 469 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 470 _FDT((fdt_setprop_string(fdt, 0, "model", 471 "IBM PowerNV (emulated by qemu)"))); 472 if (pnv_is_power9(pnv)) { 473 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, 474 sizeof(plat_compat9)))); 475 } else { 476 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8, 477 sizeof(plat_compat8)))); 478 } 479 480 481 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 482 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 483 if (qemu_uuid_set) { 484 _FDT((fdt_property_string(fdt, "system-id", buf))); 485 } 486 g_free(buf); 487 488 off = fdt_add_subnode(fdt, 0, "chosen"); 489 if (machine->kernel_cmdline) { 490 _FDT((fdt_setprop_string(fdt, off, "bootargs", 491 machine->kernel_cmdline))); 492 } 493 494 if (pnv->initrd_size) { 495 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 496 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 497 498 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 499 &start_prop, sizeof(start_prop)))); 500 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 501 &end_prop, sizeof(end_prop)))); 502 } 503 504 /* Populate device tree for each chip */ 505 for (i = 0; i < pnv->num_chips; i++) { 506 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 507 } 508 509 /* Populate ISA devices on chip 0 */ 510 pnv_dt_isa(pnv, fdt); 511 512 if (pnv->bmc) { 513 pnv_dt_bmc_sensors(pnv->bmc, fdt); 514 } 515 516 /* Create an extra node for power management on Power9 */ 517 if (pnv_is_power9(pnv)) { 518 pnv_dt_power_mgt(fdt); 519 } 520 521 return fdt; 522 } 523 524 static void pnv_powerdown_notify(Notifier *n, void *opaque) 525 { 526 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 527 528 if (pnv->bmc) { 529 pnv_bmc_powerdown(pnv->bmc); 530 } 531 } 532 533 static void pnv_reset(MachineState *machine) 534 { 535 PnvMachineState *pnv = PNV_MACHINE(machine); 536 void *fdt; 537 Object *obj; 538 539 qemu_devices_reset(); 540 541 /* OpenPOWER systems have a BMC, which can be defined on the 542 * command line with: 543 * 544 * -device ipmi-bmc-sim,id=bmc0 545 * 546 * This is the internal simulator but it could also be an external 547 * BMC. 548 */ 549 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); 550 if (obj) { 551 pnv->bmc = IPMI_BMC(obj); 552 } 553 554 fdt = pnv_dt_create(machine); 555 556 /* Pack resulting tree */ 557 _FDT((fdt_pack(fdt))); 558 559 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 560 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 561 } 562 563 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 564 { 565 Pnv8Chip *chip8 = PNV8_CHIP(chip); 566 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 567 } 568 569 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 570 { 571 Pnv8Chip *chip8 = PNV8_CHIP(chip); 572 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 573 } 574 575 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 576 { 577 Pnv9Chip *chip9 = PNV9_CHIP(chip); 578 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 579 } 580 581 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 582 { 583 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 584 } 585 586 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 587 { 588 Pnv8Chip *chip8 = PNV8_CHIP(chip); 589 590 ics_pic_print_info(&chip8->psi.ics, mon); 591 } 592 593 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 594 { 595 Pnv9Chip *chip9 = PNV9_CHIP(chip); 596 597 pnv_xive_pic_print_info(&chip9->xive, mon); 598 pnv_psi_pic_print_info(&chip9->psi, mon); 599 } 600 601 static void pnv_init(MachineState *machine) 602 { 603 PnvMachineState *pnv = PNV_MACHINE(machine); 604 MemoryRegion *ram; 605 char *fw_filename; 606 long fw_size; 607 int i; 608 char *chip_typename; 609 610 /* allocate RAM */ 611 if (machine->ram_size < (1 * GiB)) { 612 warn_report("skiboot may not work with < 1GB of RAM"); 613 } 614 615 ram = g_new(MemoryRegion, 1); 616 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 617 machine->ram_size); 618 memory_region_add_subregion(get_system_memory(), 0, ram); 619 620 /* load skiboot firmware */ 621 if (bios_name == NULL) { 622 bios_name = FW_FILE_NAME; 623 } 624 625 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 626 if (!fw_filename) { 627 error_report("Could not find OPAL firmware '%s'", bios_name); 628 exit(1); 629 } 630 631 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 632 if (fw_size < 0) { 633 error_report("Could not load OPAL firmware '%s'", fw_filename); 634 exit(1); 635 } 636 g_free(fw_filename); 637 638 /* load kernel */ 639 if (machine->kernel_filename) { 640 long kernel_size; 641 642 kernel_size = load_image_targphys(machine->kernel_filename, 643 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 644 if (kernel_size < 0) { 645 error_report("Could not load kernel '%s'", 646 machine->kernel_filename); 647 exit(1); 648 } 649 } 650 651 /* load initrd */ 652 if (machine->initrd_filename) { 653 pnv->initrd_base = INITRD_LOAD_ADDR; 654 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 655 pnv->initrd_base, INITRD_MAX_SIZE); 656 if (pnv->initrd_size < 0) { 657 error_report("Could not load initial ram disk '%s'", 658 machine->initrd_filename); 659 exit(1); 660 } 661 } 662 663 /* Create the processor chips */ 664 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 665 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 666 i, machine->cpu_type); 667 if (!object_class_by_name(chip_typename)) { 668 error_report("invalid CPU model '%.*s' for %s machine", 669 i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name); 670 exit(1); 671 } 672 673 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 674 for (i = 0; i < pnv->num_chips; i++) { 675 char chip_name[32]; 676 Object *chip = object_new(chip_typename); 677 678 pnv->chips[i] = PNV_CHIP(chip); 679 680 /* TODO: put all the memory in one node on chip 0 until we find a 681 * way to specify different ranges for each chip 682 */ 683 if (i == 0) { 684 object_property_set_int(chip, machine->ram_size, "ram-size", 685 &error_fatal); 686 } 687 688 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 689 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 690 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 691 &error_fatal); 692 object_property_set_int(chip, machine->smp.cores, 693 "nr-cores", &error_fatal); 694 object_property_set_bool(chip, true, "realized", &error_fatal); 695 } 696 g_free(chip_typename); 697 698 /* Instantiate ISA bus on chip 0 */ 699 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 700 701 /* Create serial port */ 702 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 703 704 /* Create an RTC ISA device too */ 705 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 706 707 /* OpenPOWER systems use a IPMI SEL Event message to notify the 708 * host to powerdown */ 709 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 710 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 711 } 712 713 /* 714 * 0:21 Reserved - Read as zeros 715 * 22:24 Chip ID 716 * 25:28 Core number 717 * 29:31 Thread ID 718 */ 719 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 720 { 721 return (chip->chip_id << 7) | (core_id << 3); 722 } 723 724 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 725 Error **errp) 726 { 727 Error *local_err = NULL; 728 Object *obj; 729 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 730 731 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 732 &local_err); 733 if (local_err) { 734 error_propagate(errp, local_err); 735 return; 736 } 737 738 pnv_cpu->intc = obj; 739 } 740 741 /* 742 * 0:48 Reserved - Read as zeroes 743 * 49:52 Node ID 744 * 53:55 Chip ID 745 * 56 Reserved - Read as zero 746 * 57:61 Core number 747 * 62:63 Thread ID 748 * 749 * We only care about the lower bits. uint32_t is fine for the moment. 750 */ 751 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 752 { 753 return (chip->chip_id << 8) | (core_id << 2); 754 } 755 756 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 757 Error **errp) 758 { 759 Pnv9Chip *chip9 = PNV9_CHIP(chip); 760 Error *local_err = NULL; 761 Object *obj; 762 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 763 764 /* 765 * The core creates its interrupt presenter but the XIVE interrupt 766 * controller object is initialized afterwards. Hopefully, it's 767 * only used at runtime. 768 */ 769 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); 770 if (local_err) { 771 error_propagate(errp, local_err); 772 return; 773 } 774 775 pnv_cpu->intc = obj; 776 } 777 778 /* Allowed core identifiers on a POWER8 Processor Chip : 779 * 780 * <EX0 reserved> 781 * EX1 - Venice only 782 * EX2 - Venice only 783 * EX3 - Venice only 784 * EX4 785 * EX5 786 * EX6 787 * <EX7,8 reserved> <reserved> 788 * EX9 - Venice only 789 * EX10 - Venice only 790 * EX11 - Venice only 791 * EX12 792 * EX13 793 * EX14 794 * <EX15 reserved> 795 */ 796 #define POWER8E_CORE_MASK (0x7070ull) 797 #define POWER8_CORE_MASK (0x7e7eull) 798 799 /* 800 * POWER9 has 24 cores, ids starting at 0x0 801 */ 802 #define POWER9_CORE_MASK (0xffffffffffffffull) 803 804 static void pnv_chip_power8_instance_init(Object *obj) 805 { 806 Pnv8Chip *chip8 = PNV8_CHIP(obj); 807 808 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 809 TYPE_PNV8_PSI, &error_abort, NULL); 810 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 811 OBJECT(qdev_get_machine()), &error_abort); 812 813 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 814 TYPE_PNV8_LPC, &error_abort, NULL); 815 object_property_add_const_link(OBJECT(&chip8->lpc), "psi", 816 OBJECT(&chip8->psi), &error_abort); 817 818 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 819 TYPE_PNV8_OCC, &error_abort, NULL); 820 object_property_add_const_link(OBJECT(&chip8->occ), "psi", 821 OBJECT(&chip8->psi), &error_abort); 822 } 823 824 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 825 { 826 PnvChip *chip = PNV_CHIP(chip8); 827 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 828 const char *typename = pnv_chip_core_typename(chip); 829 size_t typesize = object_type_get_instance_size(typename); 830 int i, j; 831 char *name; 832 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 833 834 name = g_strdup_printf("icp-%x", chip->chip_id); 835 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 836 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 837 g_free(name); 838 839 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 840 841 /* Map the ICP registers for each thread */ 842 for (i = 0; i < chip->nr_cores; i++) { 843 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 844 int core_hwid = CPU_CORE(pnv_core)->core_id; 845 846 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 847 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 848 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 849 850 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 851 &icp->mmio); 852 } 853 } 854 } 855 856 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 857 { 858 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 859 PnvChip *chip = PNV_CHIP(dev); 860 Pnv8Chip *chip8 = PNV8_CHIP(dev); 861 Pnv8Psi *psi8 = &chip8->psi; 862 Error *local_err = NULL; 863 864 /* XSCOM bridge is first */ 865 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 866 if (local_err) { 867 error_propagate(errp, local_err); 868 return; 869 } 870 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 871 872 pcc->parent_realize(dev, &local_err); 873 if (local_err) { 874 error_propagate(errp, local_err); 875 return; 876 } 877 878 /* Processor Service Interface (PSI) Host Bridge */ 879 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 880 "bar", &error_fatal); 881 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 882 if (local_err) { 883 error_propagate(errp, local_err); 884 return; 885 } 886 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 887 &PNV_PSI(psi8)->xscom_regs); 888 889 /* Create LPC controller */ 890 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 891 &error_fatal); 892 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 893 894 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 895 (uint64_t) PNV_XSCOM_BASE(chip), 896 PNV_XSCOM_LPC_BASE); 897 898 /* Interrupt Management Area. This is the memory region holding 899 * all the Interrupt Control Presenter (ICP) registers */ 900 pnv_chip_icp_realize(chip8, &local_err); 901 if (local_err) { 902 error_propagate(errp, local_err); 903 return; 904 } 905 906 /* Create the simplified OCC model */ 907 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 908 if (local_err) { 909 error_propagate(errp, local_err); 910 return; 911 } 912 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 913 } 914 915 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 916 { 917 DeviceClass *dc = DEVICE_CLASS(klass); 918 PnvChipClass *k = PNV_CHIP_CLASS(klass); 919 920 k->chip_type = PNV_CHIP_POWER8E; 921 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 922 k->cores_mask = POWER8E_CORE_MASK; 923 k->core_pir = pnv_chip_core_pir_p8; 924 k->intc_create = pnv_chip_power8_intc_create; 925 k->isa_create = pnv_chip_power8_isa_create; 926 k->dt_populate = pnv_chip_power8_dt_populate; 927 k->pic_print_info = pnv_chip_power8_pic_print_info; 928 dc->desc = "PowerNV Chip POWER8E"; 929 930 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 931 &k->parent_realize); 932 } 933 934 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 935 { 936 DeviceClass *dc = DEVICE_CLASS(klass); 937 PnvChipClass *k = PNV_CHIP_CLASS(klass); 938 939 k->chip_type = PNV_CHIP_POWER8; 940 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 941 k->cores_mask = POWER8_CORE_MASK; 942 k->core_pir = pnv_chip_core_pir_p8; 943 k->intc_create = pnv_chip_power8_intc_create; 944 k->isa_create = pnv_chip_power8_isa_create; 945 k->dt_populate = pnv_chip_power8_dt_populate; 946 k->pic_print_info = pnv_chip_power8_pic_print_info; 947 dc->desc = "PowerNV Chip POWER8"; 948 949 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 950 &k->parent_realize); 951 } 952 953 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 954 { 955 DeviceClass *dc = DEVICE_CLASS(klass); 956 PnvChipClass *k = PNV_CHIP_CLASS(klass); 957 958 k->chip_type = PNV_CHIP_POWER8NVL; 959 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 960 k->cores_mask = POWER8_CORE_MASK; 961 k->core_pir = pnv_chip_core_pir_p8; 962 k->intc_create = pnv_chip_power8_intc_create; 963 k->isa_create = pnv_chip_power8nvl_isa_create; 964 k->dt_populate = pnv_chip_power8_dt_populate; 965 k->pic_print_info = pnv_chip_power8_pic_print_info; 966 dc->desc = "PowerNV Chip POWER8NVL"; 967 968 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 969 &k->parent_realize); 970 } 971 972 static void pnv_chip_power9_instance_init(Object *obj) 973 { 974 Pnv9Chip *chip9 = PNV9_CHIP(obj); 975 976 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 977 TYPE_PNV_XIVE, &error_abort, NULL); 978 object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj, 979 &error_abort); 980 981 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 982 TYPE_PNV9_PSI, &error_abort, NULL); 983 object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj, 984 &error_abort); 985 986 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 987 TYPE_PNV9_LPC, &error_abort, NULL); 988 object_property_add_const_link(OBJECT(&chip9->lpc), "psi", 989 OBJECT(&chip9->psi), &error_abort); 990 991 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 992 TYPE_PNV9_OCC, &error_abort, NULL); 993 object_property_add_const_link(OBJECT(&chip9->occ), "psi", 994 OBJECT(&chip9->psi), &error_abort); 995 } 996 997 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 998 { 999 PnvChip *chip = PNV_CHIP(chip9); 1000 const char *typename = pnv_chip_core_typename(chip); 1001 size_t typesize = object_type_get_instance_size(typename); 1002 int i; 1003 1004 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1005 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1006 1007 for (i = 0; i < chip9->nr_quads; i++) { 1008 char eq_name[32]; 1009 PnvQuad *eq = &chip9->quads[i]; 1010 PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize); 1011 int core_id = CPU_CORE(pnv_core)->core_id; 1012 1013 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1014 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1015 TYPE_PNV_QUAD, &error_fatal, NULL); 1016 1017 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1018 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1019 1020 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1021 &eq->xscom_regs); 1022 } 1023 } 1024 1025 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1026 { 1027 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1028 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1029 PnvChip *chip = PNV_CHIP(dev); 1030 Pnv9Psi *psi9 = &chip9->psi; 1031 Error *local_err = NULL; 1032 1033 /* XSCOM bridge is first */ 1034 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1035 if (local_err) { 1036 error_propagate(errp, local_err); 1037 return; 1038 } 1039 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1040 1041 pcc->parent_realize(dev, &local_err); 1042 if (local_err) { 1043 error_propagate(errp, local_err); 1044 return; 1045 } 1046 1047 pnv_chip_quad_realize(chip9, &local_err); 1048 if (local_err) { 1049 error_propagate(errp, local_err); 1050 return; 1051 } 1052 1053 /* XIVE interrupt controller (POWER9) */ 1054 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1055 "ic-bar", &error_fatal); 1056 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1057 "vc-bar", &error_fatal); 1058 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1059 "pc-bar", &error_fatal); 1060 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1061 "tm-bar", &error_fatal); 1062 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1063 &local_err); 1064 if (local_err) { 1065 error_propagate(errp, local_err); 1066 return; 1067 } 1068 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1069 &chip9->xive.xscom_regs); 1070 1071 /* Processor Service Interface (PSI) Host Bridge */ 1072 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1073 "bar", &error_fatal); 1074 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1075 if (local_err) { 1076 error_propagate(errp, local_err); 1077 return; 1078 } 1079 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1080 &PNV_PSI(psi9)->xscom_regs); 1081 1082 /* LPC */ 1083 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1084 if (local_err) { 1085 error_propagate(errp, local_err); 1086 return; 1087 } 1088 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1089 &chip9->lpc.xscom_regs); 1090 1091 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1092 (uint64_t) PNV9_LPCM_BASE(chip)); 1093 1094 /* Create the simplified OCC model */ 1095 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1096 if (local_err) { 1097 error_propagate(errp, local_err); 1098 return; 1099 } 1100 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1101 } 1102 1103 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1104 { 1105 DeviceClass *dc = DEVICE_CLASS(klass); 1106 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1107 1108 k->chip_type = PNV_CHIP_POWER9; 1109 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1110 k->cores_mask = POWER9_CORE_MASK; 1111 k->core_pir = pnv_chip_core_pir_p9; 1112 k->intc_create = pnv_chip_power9_intc_create; 1113 k->isa_create = pnv_chip_power9_isa_create; 1114 k->dt_populate = pnv_chip_power9_dt_populate; 1115 k->pic_print_info = pnv_chip_power9_pic_print_info; 1116 dc->desc = "PowerNV Chip POWER9"; 1117 1118 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1119 &k->parent_realize); 1120 } 1121 1122 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1123 { 1124 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1125 int cores_max; 1126 1127 /* 1128 * No custom mask for this chip, let's use the default one from * 1129 * the chip class 1130 */ 1131 if (!chip->cores_mask) { 1132 chip->cores_mask = pcc->cores_mask; 1133 } 1134 1135 /* filter alien core ids ! some are reserved */ 1136 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1137 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1138 chip->cores_mask); 1139 return; 1140 } 1141 chip->cores_mask &= pcc->cores_mask; 1142 1143 /* now that we have a sane layout, let check the number of cores */ 1144 cores_max = ctpop64(chip->cores_mask); 1145 if (chip->nr_cores > cores_max) { 1146 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1147 cores_max); 1148 return; 1149 } 1150 } 1151 1152 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1153 { 1154 MachineState *ms = MACHINE(qdev_get_machine()); 1155 Error *error = NULL; 1156 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1157 const char *typename = pnv_chip_core_typename(chip); 1158 size_t typesize = object_type_get_instance_size(typename); 1159 int i, core_hwid; 1160 1161 if (!object_class_by_name(typename)) { 1162 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1163 return; 1164 } 1165 1166 /* Cores */ 1167 pnv_chip_core_sanitize(chip, &error); 1168 if (error) { 1169 error_propagate(errp, error); 1170 return; 1171 } 1172 1173 chip->cores = g_malloc0(typesize * chip->nr_cores); 1174 1175 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1176 && (i < chip->nr_cores); core_hwid++) { 1177 char core_name[32]; 1178 void *pnv_core = chip->cores + i * typesize; 1179 uint64_t xscom_core_base; 1180 1181 if (!(chip->cores_mask & (1ull << core_hwid))) { 1182 continue; 1183 } 1184 1185 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1186 object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize, 1187 typename, &error_fatal, NULL); 1188 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", 1189 &error_fatal); 1190 object_property_set_int(OBJECT(pnv_core), core_hwid, 1191 CPU_CORE_PROP_CORE_ID, &error_fatal); 1192 object_property_set_int(OBJECT(pnv_core), 1193 pcc->core_pir(chip, core_hwid), 1194 "pir", &error_fatal); 1195 object_property_add_const_link(OBJECT(pnv_core), "chip", 1196 OBJECT(chip), &error_fatal); 1197 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1198 &error_fatal); 1199 1200 /* Each core has an XSCOM MMIO region */ 1201 if (!pnv_chip_is_power9(chip)) { 1202 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); 1203 } else { 1204 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); 1205 } 1206 1207 pnv_xscom_add_subregion(chip, xscom_core_base, 1208 &PNV_CORE(pnv_core)->xscom_regs); 1209 i++; 1210 } 1211 } 1212 1213 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1214 { 1215 PnvChip *chip = PNV_CHIP(dev); 1216 Error *error = NULL; 1217 1218 /* Cores */ 1219 pnv_chip_core_realize(chip, &error); 1220 if (error) { 1221 error_propagate(errp, error); 1222 return; 1223 } 1224 } 1225 1226 static Property pnv_chip_properties[] = { 1227 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1228 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1229 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1230 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1231 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1232 DEFINE_PROP_END_OF_LIST(), 1233 }; 1234 1235 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1236 { 1237 DeviceClass *dc = DEVICE_CLASS(klass); 1238 1239 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1240 dc->realize = pnv_chip_realize; 1241 dc->props = pnv_chip_properties; 1242 dc->desc = "PowerNV Chip"; 1243 } 1244 1245 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1246 { 1247 PnvMachineState *pnv = PNV_MACHINE(xi); 1248 int i; 1249 1250 for (i = 0; i < pnv->num_chips; i++) { 1251 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1252 1253 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1254 return &chip8->psi.ics; 1255 } 1256 } 1257 return NULL; 1258 } 1259 1260 static void pnv_ics_resend(XICSFabric *xi) 1261 { 1262 PnvMachineState *pnv = PNV_MACHINE(xi); 1263 int i; 1264 1265 for (i = 0; i < pnv->num_chips; i++) { 1266 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1267 ics_resend(&chip8->psi.ics); 1268 } 1269 } 1270 1271 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1272 { 1273 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1274 1275 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1276 } 1277 1278 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1279 Monitor *mon) 1280 { 1281 PnvMachineState *pnv = PNV_MACHINE(obj); 1282 int i; 1283 CPUState *cs; 1284 1285 CPU_FOREACH(cs) { 1286 PowerPCCPU *cpu = POWERPC_CPU(cs); 1287 1288 if (pnv_chip_is_power9(pnv->chips[0])) { 1289 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1290 } else { 1291 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1292 } 1293 } 1294 1295 for (i = 0; i < pnv->num_chips; i++) { 1296 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1297 } 1298 } 1299 1300 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1301 void *opaque, Error **errp) 1302 { 1303 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1304 } 1305 1306 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1307 void *opaque, Error **errp) 1308 { 1309 PnvMachineState *pnv = PNV_MACHINE(obj); 1310 uint32_t num_chips; 1311 Error *local_err = NULL; 1312 1313 visit_type_uint32(v, name, &num_chips, &local_err); 1314 if (local_err) { 1315 error_propagate(errp, local_err); 1316 return; 1317 } 1318 1319 /* 1320 * TODO: should we decide on how many chips we can create based 1321 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1322 */ 1323 if (!is_power_of_2(num_chips) || num_chips > 4) { 1324 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1325 return; 1326 } 1327 1328 pnv->num_chips = num_chips; 1329 } 1330 1331 static void pnv_machine_instance_init(Object *obj) 1332 { 1333 PnvMachineState *pnv = PNV_MACHINE(obj); 1334 pnv->num_chips = 1; 1335 } 1336 1337 static void pnv_machine_class_props_init(ObjectClass *oc) 1338 { 1339 object_class_property_add(oc, "num-chips", "uint32", 1340 pnv_get_num_chips, pnv_set_num_chips, 1341 NULL, NULL, NULL); 1342 object_class_property_set_description(oc, "num-chips", 1343 "Specifies the number of processor chips", 1344 NULL); 1345 } 1346 1347 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1348 { 1349 MachineClass *mc = MACHINE_CLASS(oc); 1350 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1351 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1352 1353 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1354 mc->init = pnv_init; 1355 mc->reset = pnv_reset; 1356 mc->max_cpus = MAX_CPUS; 1357 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1358 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for 1359 * storage */ 1360 mc->no_parallel = 1; 1361 mc->default_boot_order = NULL; 1362 mc->default_ram_size = 1 * GiB; 1363 xic->icp_get = pnv_icp_get; 1364 xic->ics_get = pnv_ics_get; 1365 xic->ics_resend = pnv_ics_resend; 1366 ispc->print_info = pnv_pic_print_info; 1367 1368 pnv_machine_class_props_init(oc); 1369 } 1370 1371 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1372 { \ 1373 .name = type, \ 1374 .class_init = class_initfn, \ 1375 .parent = TYPE_PNV8_CHIP, \ 1376 } 1377 1378 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1379 { \ 1380 .name = type, \ 1381 .class_init = class_initfn, \ 1382 .parent = TYPE_PNV9_CHIP, \ 1383 } 1384 1385 static const TypeInfo types[] = { 1386 { 1387 .name = TYPE_PNV_MACHINE, 1388 .parent = TYPE_MACHINE, 1389 .instance_size = sizeof(PnvMachineState), 1390 .instance_init = pnv_machine_instance_init, 1391 .class_init = pnv_machine_class_init, 1392 .interfaces = (InterfaceInfo[]) { 1393 { TYPE_XICS_FABRIC }, 1394 { TYPE_INTERRUPT_STATS_PROVIDER }, 1395 { }, 1396 }, 1397 }, 1398 { 1399 .name = TYPE_PNV_CHIP, 1400 .parent = TYPE_SYS_BUS_DEVICE, 1401 .class_init = pnv_chip_class_init, 1402 .instance_size = sizeof(PnvChip), 1403 .class_size = sizeof(PnvChipClass), 1404 .abstract = true, 1405 }, 1406 1407 /* 1408 * P9 chip and variants 1409 */ 1410 { 1411 .name = TYPE_PNV9_CHIP, 1412 .parent = TYPE_PNV_CHIP, 1413 .instance_init = pnv_chip_power9_instance_init, 1414 .instance_size = sizeof(Pnv9Chip), 1415 }, 1416 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1417 1418 /* 1419 * P8 chip and variants 1420 */ 1421 { 1422 .name = TYPE_PNV8_CHIP, 1423 .parent = TYPE_PNV_CHIP, 1424 .instance_init = pnv_chip_power8_instance_init, 1425 .instance_size = sizeof(Pnv8Chip), 1426 }, 1427 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1428 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1429 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1430 pnv_chip_power8nvl_class_init), 1431 }; 1432 1433 DEFINE_TYPES(types) 1434