1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "sysemu/hw_accel.h" 31 #include "target/ppc/cpu.h" 32 #include "qemu/log.h" 33 #include "hw/ppc/fdt.h" 34 #include "hw/ppc/ppc.h" 35 #include "hw/ppc/pnv.h" 36 #include "hw/ppc/pnv_core.h" 37 #include "hw/loader.h" 38 #include "hw/nmi.h" 39 #include "exec/address-spaces.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 47 #include "hw/ppc/xics.h" 48 #include "hw/qdev-properties.h" 49 #include "hw/ppc/pnv_xscom.h" 50 #include "hw/ppc/pnv_pnor.h" 51 52 #include "hw/isa/isa.h" 53 #include "hw/boards.h" 54 #include "hw/char/serial.h" 55 #include "hw/rtc/mc146818rtc.h" 56 57 #include <libfdt.h> 58 59 #define FDT_MAX_SIZE (1 * MiB) 60 61 #define FW_FILE_NAME "skiboot.lid" 62 #define FW_LOAD_ADDR 0x0 63 #define FW_MAX_SIZE (4 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x20000000 66 #define KERNEL_MAX_SIZE (256 * MiB) 67 #define INITRD_LOAD_ADDR 0x60000000 68 #define INITRD_MAX_SIZE (256 * MiB) 69 70 static const char *pnv_chip_core_typename(const PnvChip *o) 71 { 72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 75 const char *core_type = object_class_get_name(object_class_by_name(s)); 76 g_free(s); 77 return core_type; 78 } 79 80 /* 81 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 82 * 4 * 4 sockets * 12 cores * 8 threads = 1536 83 * Let's make it 2^11 84 */ 85 #define MAX_CPUS 2048 86 87 /* 88 * Memory nodes are created by hostboot, one for each range of memory 89 * that has a different "affinity". In practice, it means one range 90 * per chip. 91 */ 92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 93 { 94 char *mem_name; 95 uint64_t mem_reg_property[2]; 96 int off; 97 98 mem_reg_property[0] = cpu_to_be64(start); 99 mem_reg_property[1] = cpu_to_be64(size); 100 101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 102 off = fdt_add_subnode(fdt, 0, mem_name); 103 g_free(mem_name); 104 105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 107 sizeof(mem_reg_property)))); 108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 109 } 110 111 static int get_cpus_node(void *fdt) 112 { 113 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 114 115 if (cpus_offset < 0) { 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 117 if (cpus_offset) { 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 120 } 121 } 122 _FDT(cpus_offset); 123 return cpus_offset; 124 } 125 126 /* 127 * The PowerNV cores (and threads) need to use real HW ids and not an 128 * incremental index like it has been done on other platforms. This HW 129 * id is stored in the CPU PIR, it is used to create cpu nodes in the 130 * device tree, used in XSCOM to address cores and in interrupt 131 * servers. 132 */ 133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 134 { 135 PowerPCCPU *cpu = pc->threads[0]; 136 CPUState *cs = CPU(cpu); 137 DeviceClass *dc = DEVICE_GET_CLASS(cs); 138 int smt_threads = CPU_CORE(pc)->nr_threads; 139 CPUPPCState *env = &cpu->env; 140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 141 uint32_t servers_prop[smt_threads]; 142 int i; 143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 144 0xffffffff, 0xffffffff}; 145 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 146 uint32_t cpufreq = 1000000000; 147 uint32_t page_sizes_prop[64]; 148 size_t page_sizes_prop_size; 149 const uint8_t pa_features[] = { 24, 0, 150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 154 int offset; 155 char *nodename; 156 int cpus_offset = get_cpus_node(fdt); 157 158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 159 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 160 _FDT(offset); 161 g_free(nodename); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 175 env->icache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 177 env->icache_line_size))); 178 179 if (pcc->l1_dcache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 181 pcc->l1_dcache_size))); 182 } else { 183 warn_report("Unknown L1 dcache size for cpu"); 184 } 185 if (pcc->l1_icache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 187 pcc->l1_icache_size))); 188 } else { 189 warn_report("Unknown L1 icache size for cpu"); 190 } 191 192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 195 cpu->hash64_opts->slb_size))); 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 198 199 if (env->spr_cb[SPR_PURR].oea_read) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 201 } 202 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 205 segs, sizeof(segs)))); 206 } 207 208 /* 209 * Advertise VMX/VSX (vector extensions) if available 210 * 0 / no property == no vector extensions 211 * 1 == VMX / Altivec available 212 * 2 == VSX available 213 */ 214 if (env->insns_flags & PPC_ALTIVEC) { 215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 216 217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 218 } 219 220 /* 221 * Advertise DFP (Decimal Floating Point) if available 222 * 0 / no property == no DFP 223 * 1 == DFP available 224 */ 225 if (env->insns_flags2 & PPC2_DFP) { 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 227 } 228 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 230 sizeof(page_sizes_prop)); 231 if (page_sizes_prop_size) { 232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 233 page_sizes_prop, page_sizes_prop_size))); 234 } 235 236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 237 pa_features, sizeof(pa_features)))); 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pc->pir + i); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(servers_prop)))); 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 248 uint32_t nr_threads) 249 { 250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 251 char *name; 252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 253 uint32_t irange[2], i, rsize; 254 uint64_t *reg; 255 int offset; 256 257 irange[0] = cpu_to_be32(pir); 258 irange[1] = cpu_to_be32(nr_threads); 259 260 rsize = sizeof(uint64_t) * 2 * nr_threads; 261 reg = g_malloc(rsize); 262 for (i = 0; i < nr_threads; i++) { 263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 264 reg[i * 2 + 1] = cpu_to_be64(0x1000); 265 } 266 267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 268 offset = fdt_add_subnode(fdt, 0, name); 269 _FDT(offset); 270 g_free(name); 271 272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 274 _FDT((fdt_setprop_string(fdt, offset, "device_type", 275 "PowerPC-External-Interrupt-Presentation"))); 276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 278 irange, sizeof(irange)))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 281 g_free(reg); 282 } 283 284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 285 { 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 287 int i; 288 289 pnv_dt_xscom(chip, fdt, 0, 290 cpu_to_be64(PNV_XSCOM_BASE(chip)), 291 cpu_to_be64(PNV_XSCOM_SIZE), 292 compat, sizeof(compat)); 293 294 for (i = 0; i < chip->nr_cores; i++) { 295 PnvCore *pnv_core = chip->cores[i]; 296 297 pnv_dt_core(chip, pnv_core, fdt); 298 299 /* Interrupt Control Presenters (ICP). One per core. */ 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 301 } 302 303 if (chip->ram_size) { 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 305 } 306 } 307 308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 309 { 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 311 int i; 312 313 pnv_dt_xscom(chip, fdt, 0, 314 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 315 cpu_to_be64(PNV9_XSCOM_SIZE), 316 compat, sizeof(compat)); 317 318 for (i = 0; i < chip->nr_cores; i++) { 319 PnvCore *pnv_core = chip->cores[i]; 320 321 pnv_dt_core(chip, pnv_core, fdt); 322 } 323 324 if (chip->ram_size) { 325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 326 } 327 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 329 } 330 331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 332 { 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 334 int i; 335 336 pnv_dt_xscom(chip, fdt, 0, 337 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 338 cpu_to_be64(PNV10_XSCOM_SIZE), 339 compat, sizeof(compat)); 340 341 for (i = 0; i < chip->nr_cores; i++) { 342 PnvCore *pnv_core = chip->cores[i]; 343 344 pnv_dt_core(chip, pnv_core, fdt); 345 } 346 347 if (chip->ram_size) { 348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 349 } 350 351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 352 } 353 354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 355 { 356 uint32_t io_base = d->ioport_id; 357 uint32_t io_regs[] = { 358 cpu_to_be32(1), 359 cpu_to_be32(io_base), 360 cpu_to_be32(2) 361 }; 362 char *name; 363 int node; 364 365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 366 node = fdt_add_subnode(fdt, lpc_off, name); 367 _FDT(node); 368 g_free(name); 369 370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 372 } 373 374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 375 { 376 const char compatible[] = "ns16550\0pnpPNP,501"; 377 uint32_t io_base = d->ioport_id; 378 uint32_t io_regs[] = { 379 cpu_to_be32(1), 380 cpu_to_be32(io_base), 381 cpu_to_be32(8) 382 }; 383 char *name; 384 int node; 385 386 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 387 node = fdt_add_subnode(fdt, lpc_off, name); 388 _FDT(node); 389 g_free(name); 390 391 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 392 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 393 sizeof(compatible)))); 394 395 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 396 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 397 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 398 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 399 fdt_get_phandle(fdt, lpc_off)))); 400 401 /* This is needed by Linux */ 402 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 403 } 404 405 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 406 { 407 const char compatible[] = "bt\0ipmi-bt"; 408 uint32_t io_base; 409 uint32_t io_regs[] = { 410 cpu_to_be32(1), 411 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 412 cpu_to_be32(3) 413 }; 414 uint32_t irq; 415 char *name; 416 int node; 417 418 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 419 io_regs[1] = cpu_to_be32(io_base); 420 421 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 422 423 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 424 node = fdt_add_subnode(fdt, lpc_off, name); 425 _FDT(node); 426 g_free(name); 427 428 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 429 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 430 sizeof(compatible)))); 431 432 /* Mark it as reserved to avoid Linux trying to claim it */ 433 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 434 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 435 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 436 fdt_get_phandle(fdt, lpc_off)))); 437 } 438 439 typedef struct ForeachPopulateArgs { 440 void *fdt; 441 int offset; 442 } ForeachPopulateArgs; 443 444 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 445 { 446 ForeachPopulateArgs *args = opaque; 447 ISADevice *d = ISA_DEVICE(dev); 448 449 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 450 pnv_dt_rtc(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 452 pnv_dt_serial(d, args->fdt, args->offset); 453 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 454 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 455 } else { 456 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 457 d->ioport_id); 458 } 459 460 return 0; 461 } 462 463 /* 464 * The default LPC bus of a multichip system is on chip 0. It's 465 * recognized by the firmware (skiboot) using a "primary" property. 466 */ 467 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 468 { 469 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 470 ForeachPopulateArgs args = { 471 .fdt = fdt, 472 .offset = isa_offset, 473 }; 474 uint32_t phandle; 475 476 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 477 478 phandle = qemu_fdt_alloc_phandle(fdt); 479 assert(phandle > 0); 480 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 481 482 /* 483 * ISA devices are not necessarily parented to the ISA bus so we 484 * can not use object_child_foreach() 485 */ 486 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 487 &args); 488 } 489 490 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 491 { 492 int off; 493 494 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 495 off = fdt_add_subnode(fdt, off, "power-mgt"); 496 497 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 498 } 499 500 static void *pnv_dt_create(MachineState *machine) 501 { 502 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 503 PnvMachineState *pnv = PNV_MACHINE(machine); 504 void *fdt; 505 char *buf; 506 int off; 507 int i; 508 509 fdt = g_malloc0(FDT_MAX_SIZE); 510 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 511 512 /* /qemu node */ 513 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 514 515 /* Root node */ 516 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 517 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 518 _FDT((fdt_setprop_string(fdt, 0, "model", 519 "IBM PowerNV (emulated by qemu)"))); 520 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 521 522 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 523 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 524 if (qemu_uuid_set) { 525 _FDT((fdt_property_string(fdt, "system-id", buf))); 526 } 527 g_free(buf); 528 529 off = fdt_add_subnode(fdt, 0, "chosen"); 530 if (machine->kernel_cmdline) { 531 _FDT((fdt_setprop_string(fdt, off, "bootargs", 532 machine->kernel_cmdline))); 533 } 534 535 if (pnv->initrd_size) { 536 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 537 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 538 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 540 &start_prop, sizeof(start_prop)))); 541 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 542 &end_prop, sizeof(end_prop)))); 543 } 544 545 /* Populate device tree for each chip */ 546 for (i = 0; i < pnv->num_chips; i++) { 547 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 548 } 549 550 /* Populate ISA devices on chip 0 */ 551 pnv_dt_isa(pnv, fdt); 552 553 if (pnv->bmc) { 554 pnv_dt_bmc_sensors(pnv->bmc, fdt); 555 } 556 557 /* Create an extra node for power management on machines that support it */ 558 if (pmc->dt_power_mgt) { 559 pmc->dt_power_mgt(pnv, fdt); 560 } 561 562 return fdt; 563 } 564 565 static void pnv_powerdown_notify(Notifier *n, void *opaque) 566 { 567 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 568 569 if (pnv->bmc) { 570 pnv_bmc_powerdown(pnv->bmc); 571 } 572 } 573 574 static void pnv_reset(MachineState *machine) 575 { 576 PnvMachineState *pnv = PNV_MACHINE(machine); 577 IPMIBmc *bmc; 578 void *fdt; 579 580 qemu_devices_reset(); 581 582 /* 583 * The machine should provide by default an internal BMC simulator. 584 * If not, try to use the BMC device that was provided on the command 585 * line. 586 */ 587 bmc = pnv_bmc_find(&error_fatal); 588 if (!pnv->bmc) { 589 if (!bmc) { 590 warn_report("machine has no BMC device. Use '-device " 591 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 592 "to define one"); 593 } else { 594 pnv_bmc_set_pnor(bmc, pnv->pnor); 595 pnv->bmc = bmc; 596 } 597 } 598 599 fdt = pnv_dt_create(machine); 600 601 /* Pack resulting tree */ 602 _FDT((fdt_pack(fdt))); 603 604 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 605 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 606 607 g_free(fdt); 608 } 609 610 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 611 { 612 Pnv8Chip *chip8 = PNV8_CHIP(chip); 613 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 614 } 615 616 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 617 { 618 Pnv8Chip *chip8 = PNV8_CHIP(chip); 619 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 620 } 621 622 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 623 { 624 Pnv9Chip *chip9 = PNV9_CHIP(chip); 625 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 626 } 627 628 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 629 { 630 Pnv10Chip *chip10 = PNV10_CHIP(chip); 631 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 632 } 633 634 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 635 { 636 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 637 } 638 639 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 640 { 641 Pnv8Chip *chip8 = PNV8_CHIP(chip); 642 int i; 643 644 ics_pic_print_info(&chip8->psi.ics, mon); 645 for (i = 0; i < chip->num_phbs; i++) { 646 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 647 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 648 } 649 } 650 651 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 652 { 653 Pnv9Chip *chip9 = PNV9_CHIP(chip); 654 int i, j; 655 656 pnv_xive_pic_print_info(&chip9->xive, mon); 657 pnv_psi_pic_print_info(&chip9->psi, mon); 658 659 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 660 PnvPhb4PecState *pec = &chip9->pecs[i]; 661 for (j = 0; j < pec->num_stacks; j++) { 662 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 663 } 664 } 665 } 666 667 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 668 uint32_t core_id) 669 { 670 return PNV_XSCOM_EX_BASE(core_id); 671 } 672 673 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 674 uint32_t core_id) 675 { 676 return PNV9_XSCOM_EC_BASE(core_id); 677 } 678 679 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 680 uint32_t core_id) 681 { 682 return PNV10_XSCOM_EC_BASE(core_id); 683 } 684 685 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 686 { 687 PowerPCCPUClass *ppc_default = 688 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 689 PowerPCCPUClass *ppc = 690 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 691 692 return ppc_default->pvr_match(ppc_default, ppc->pvr); 693 } 694 695 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 696 { 697 ISADevice *dev = isa_new("isa-ipmi-bt"); 698 699 object_property_set_link(OBJECT(dev), OBJECT(bmc), "bmc", &error_fatal); 700 object_property_set_int(OBJECT(dev), irq, "irq", &error_fatal); 701 isa_realize_and_unref(dev, bus, &error_fatal); 702 } 703 704 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 705 { 706 Pnv10Chip *chip10 = PNV10_CHIP(chip); 707 708 pnv_psi_pic_print_info(&chip10->psi, mon); 709 } 710 711 static void pnv_init(MachineState *machine) 712 { 713 PnvMachineState *pnv = PNV_MACHINE(machine); 714 MachineClass *mc = MACHINE_GET_CLASS(machine); 715 char *fw_filename; 716 long fw_size; 717 int i; 718 char *chip_typename; 719 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 720 DeviceState *dev; 721 722 /* allocate RAM */ 723 if (machine->ram_size < (1 * GiB)) { 724 warn_report("skiboot may not work with < 1GB of RAM"); 725 } 726 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 727 728 /* 729 * Create our simple PNOR device 730 */ 731 dev = qdev_new(TYPE_PNV_PNOR); 732 if (pnor) { 733 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 734 } 735 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 736 pnv->pnor = PNV_PNOR(dev); 737 738 /* load skiboot firmware */ 739 if (bios_name == NULL) { 740 bios_name = FW_FILE_NAME; 741 } 742 743 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 744 if (!fw_filename) { 745 error_report("Could not find OPAL firmware '%s'", bios_name); 746 exit(1); 747 } 748 749 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 750 if (fw_size < 0) { 751 error_report("Could not load OPAL firmware '%s'", fw_filename); 752 exit(1); 753 } 754 g_free(fw_filename); 755 756 /* load kernel */ 757 if (machine->kernel_filename) { 758 long kernel_size; 759 760 kernel_size = load_image_targphys(machine->kernel_filename, 761 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 762 if (kernel_size < 0) { 763 error_report("Could not load kernel '%s'", 764 machine->kernel_filename); 765 exit(1); 766 } 767 } 768 769 /* load initrd */ 770 if (machine->initrd_filename) { 771 pnv->initrd_base = INITRD_LOAD_ADDR; 772 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 773 pnv->initrd_base, INITRD_MAX_SIZE); 774 if (pnv->initrd_size < 0) { 775 error_report("Could not load initial ram disk '%s'", 776 machine->initrd_filename); 777 exit(1); 778 } 779 } 780 781 /* MSIs are supported on this platform */ 782 msi_nonbroken = true; 783 784 /* 785 * Check compatibility of the specified CPU with the machine 786 * default. 787 */ 788 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 789 error_report("invalid CPU model '%s' for %s machine", 790 machine->cpu_type, mc->name); 791 exit(1); 792 } 793 794 /* Create the processor chips */ 795 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 796 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 797 i, machine->cpu_type); 798 if (!object_class_by_name(chip_typename)) { 799 error_report("invalid chip model '%.*s' for %s machine", 800 i, machine->cpu_type, mc->name); 801 exit(1); 802 } 803 804 pnv->num_chips = 805 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 806 /* 807 * TODO: should we decide on how many chips we can create based 808 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 809 */ 810 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 811 error_report("invalid number of chips: '%d'", pnv->num_chips); 812 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 813 exit(1); 814 } 815 816 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 817 for (i = 0; i < pnv->num_chips; i++) { 818 char chip_name[32]; 819 Object *chip = OBJECT(qdev_new(chip_typename)); 820 821 pnv->chips[i] = PNV_CHIP(chip); 822 823 /* 824 * TODO: put all the memory in one node on chip 0 until we find a 825 * way to specify different ranges for each chip 826 */ 827 if (i == 0) { 828 object_property_set_int(chip, machine->ram_size, "ram-size", 829 &error_fatal); 830 } 831 832 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 833 object_property_add_child(OBJECT(pnv), chip_name, chip); 834 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 835 &error_fatal); 836 object_property_set_int(chip, machine->smp.cores, 837 "nr-cores", &error_fatal); 838 object_property_set_int(chip, machine->smp.threads, 839 "nr-threads", &error_fatal); 840 /* 841 * The POWER8 machine use the XICS interrupt interface. 842 * Propagate the XICS fabric to the chip and its controllers. 843 */ 844 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 845 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); 846 } 847 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 848 object_property_set_link(chip, OBJECT(pnv), "xive-fabric", 849 &error_abort); 850 } 851 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 852 } 853 g_free(chip_typename); 854 855 /* Instantiate ISA bus on chip 0 */ 856 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 857 858 /* Create serial port */ 859 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 860 861 /* Create an RTC ISA device too */ 862 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 863 864 /* 865 * Create the machine BMC simulator and the IPMI BT device for 866 * communication with the BMC 867 */ 868 if (defaults_enabled()) { 869 pnv->bmc = pnv_bmc_create(pnv->pnor); 870 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 871 } 872 873 /* 874 * OpenPOWER systems use a IPMI SEL Event message to notify the 875 * host to powerdown 876 */ 877 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 878 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 879 } 880 881 /* 882 * 0:21 Reserved - Read as zeros 883 * 22:24 Chip ID 884 * 25:28 Core number 885 * 29:31 Thread ID 886 */ 887 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 888 { 889 return (chip->chip_id << 7) | (core_id << 3); 890 } 891 892 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 893 Error **errp) 894 { 895 Pnv8Chip *chip8 = PNV8_CHIP(chip); 896 Error *local_err = NULL; 897 Object *obj; 898 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 899 900 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 901 if (local_err) { 902 error_propagate(errp, local_err); 903 return; 904 } 905 906 pnv_cpu->intc = obj; 907 } 908 909 910 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 911 { 912 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 913 914 icp_reset(ICP(pnv_cpu->intc)); 915 } 916 917 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 918 { 919 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 920 921 icp_destroy(ICP(pnv_cpu->intc)); 922 pnv_cpu->intc = NULL; 923 } 924 925 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 926 Monitor *mon) 927 { 928 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 929 } 930 931 /* 932 * 0:48 Reserved - Read as zeroes 933 * 49:52 Node ID 934 * 53:55 Chip ID 935 * 56 Reserved - Read as zero 936 * 57:61 Core number 937 * 62:63 Thread ID 938 * 939 * We only care about the lower bits. uint32_t is fine for the moment. 940 */ 941 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 942 { 943 return (chip->chip_id << 8) | (core_id << 2); 944 } 945 946 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 947 { 948 return (chip->chip_id << 8) | (core_id << 2); 949 } 950 951 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 952 Error **errp) 953 { 954 Pnv9Chip *chip9 = PNV9_CHIP(chip); 955 Error *local_err = NULL; 956 Object *obj; 957 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 958 959 /* 960 * The core creates its interrupt presenter but the XIVE interrupt 961 * controller object is initialized afterwards. Hopefully, it's 962 * only used at runtime. 963 */ 964 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 965 &local_err); 966 if (local_err) { 967 error_propagate(errp, local_err); 968 return; 969 } 970 971 pnv_cpu->intc = obj; 972 } 973 974 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 975 { 976 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 977 978 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 979 } 980 981 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 982 { 983 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 984 985 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 986 pnv_cpu->intc = NULL; 987 } 988 989 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 990 Monitor *mon) 991 { 992 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 993 } 994 995 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 996 Error **errp) 997 { 998 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 999 1000 /* Will be defined when the interrupt controller is */ 1001 pnv_cpu->intc = NULL; 1002 } 1003 1004 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1005 { 1006 ; 1007 } 1008 1009 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1010 { 1011 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1012 1013 pnv_cpu->intc = NULL; 1014 } 1015 1016 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1017 Monitor *mon) 1018 { 1019 } 1020 1021 /* 1022 * Allowed core identifiers on a POWER8 Processor Chip : 1023 * 1024 * <EX0 reserved> 1025 * EX1 - Venice only 1026 * EX2 - Venice only 1027 * EX3 - Venice only 1028 * EX4 1029 * EX5 1030 * EX6 1031 * <EX7,8 reserved> <reserved> 1032 * EX9 - Venice only 1033 * EX10 - Venice only 1034 * EX11 - Venice only 1035 * EX12 1036 * EX13 1037 * EX14 1038 * <EX15 reserved> 1039 */ 1040 #define POWER8E_CORE_MASK (0x7070ull) 1041 #define POWER8_CORE_MASK (0x7e7eull) 1042 1043 /* 1044 * POWER9 has 24 cores, ids starting at 0x0 1045 */ 1046 #define POWER9_CORE_MASK (0xffffffffffffffull) 1047 1048 1049 #define POWER10_CORE_MASK (0xffffffffffffffull) 1050 1051 static void pnv_chip_power8_instance_init(Object *obj) 1052 { 1053 PnvChip *chip = PNV_CHIP(obj); 1054 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1055 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1056 int i; 1057 1058 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1059 (Object **)&chip8->xics, 1060 object_property_allow_set_link, 1061 OBJ_PROP_LINK_STRONG); 1062 1063 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1064 1065 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1066 1067 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1068 1069 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1070 1071 for (i = 0; i < pcc->num_phbs; i++) { 1072 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1073 } 1074 1075 /* 1076 * Number of PHBs is the chip default 1077 */ 1078 chip->num_phbs = pcc->num_phbs; 1079 } 1080 1081 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1082 { 1083 PnvChip *chip = PNV_CHIP(chip8); 1084 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1085 int i, j; 1086 char *name; 1087 1088 name = g_strdup_printf("icp-%x", chip->chip_id); 1089 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1090 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1091 g_free(name); 1092 1093 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1094 1095 /* Map the ICP registers for each thread */ 1096 for (i = 0; i < chip->nr_cores; i++) { 1097 PnvCore *pnv_core = chip->cores[i]; 1098 int core_hwid = CPU_CORE(pnv_core)->core_id; 1099 1100 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1101 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1102 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1103 1104 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1105 &icp->mmio); 1106 } 1107 } 1108 } 1109 1110 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1111 { 1112 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1113 PnvChip *chip = PNV_CHIP(dev); 1114 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1115 Pnv8Psi *psi8 = &chip8->psi; 1116 Error *local_err = NULL; 1117 int i; 1118 1119 assert(chip8->xics); 1120 1121 /* XSCOM bridge is first */ 1122 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1123 if (local_err) { 1124 error_propagate(errp, local_err); 1125 return; 1126 } 1127 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1128 1129 pcc->parent_realize(dev, &local_err); 1130 if (local_err) { 1131 error_propagate(errp, local_err); 1132 return; 1133 } 1134 1135 /* Processor Service Interface (PSI) Host Bridge */ 1136 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1137 "bar", &error_fatal); 1138 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), 1139 ICS_PROP_XICS, &error_abort); 1140 qdev_realize(DEVICE(&chip8->psi), NULL, &local_err); 1141 if (local_err) { 1142 error_propagate(errp, local_err); 1143 return; 1144 } 1145 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1146 &PNV_PSI(psi8)->xscom_regs); 1147 1148 /* Create LPC controller */ 1149 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1150 &error_abort); 1151 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1152 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1153 1154 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1155 (uint64_t) PNV_XSCOM_BASE(chip), 1156 PNV_XSCOM_LPC_BASE); 1157 1158 /* 1159 * Interrupt Management Area. This is the memory region holding 1160 * all the Interrupt Control Presenter (ICP) registers 1161 */ 1162 pnv_chip_icp_realize(chip8, &local_err); 1163 if (local_err) { 1164 error_propagate(errp, local_err); 1165 return; 1166 } 1167 1168 /* Create the simplified OCC model */ 1169 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1170 &error_abort); 1171 qdev_realize(DEVICE(&chip8->occ), NULL, &local_err); 1172 if (local_err) { 1173 error_propagate(errp, local_err); 1174 return; 1175 } 1176 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1177 1178 /* OCC SRAM model */ 1179 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1180 &chip8->occ.sram_regs); 1181 1182 /* HOMER */ 1183 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1184 &error_abort); 1185 qdev_realize(DEVICE(&chip8->homer), NULL, &local_err); 1186 if (local_err) { 1187 error_propagate(errp, local_err); 1188 return; 1189 } 1190 /* Homer Xscom region */ 1191 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1192 1193 /* Homer mmio region */ 1194 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1195 &chip8->homer.regs); 1196 1197 /* PHB3 controllers */ 1198 for (i = 0; i < chip->num_phbs; i++) { 1199 PnvPHB3 *phb = &chip8->phbs[i]; 1200 PnvPBCQState *pbcq = &phb->pbcq; 1201 1202 object_property_set_int(OBJECT(phb), i, "index", &error_fatal); 1203 object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id", 1204 &error_fatal); 1205 sysbus_realize(SYS_BUS_DEVICE(phb), &local_err); 1206 if (local_err) { 1207 error_propagate(errp, local_err); 1208 return; 1209 } 1210 1211 /* Populate the XSCOM address space. */ 1212 pnv_xscom_add_subregion(chip, 1213 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1214 &pbcq->xscom_nest_regs); 1215 pnv_xscom_add_subregion(chip, 1216 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1217 &pbcq->xscom_pci_regs); 1218 pnv_xscom_add_subregion(chip, 1219 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1220 &pbcq->xscom_spci_regs); 1221 } 1222 } 1223 1224 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1225 { 1226 addr &= (PNV_XSCOM_SIZE - 1); 1227 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1228 } 1229 1230 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1231 { 1232 DeviceClass *dc = DEVICE_CLASS(klass); 1233 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1234 1235 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1236 k->cores_mask = POWER8E_CORE_MASK; 1237 k->num_phbs = 3; 1238 k->core_pir = pnv_chip_core_pir_p8; 1239 k->intc_create = pnv_chip_power8_intc_create; 1240 k->intc_reset = pnv_chip_power8_intc_reset; 1241 k->intc_destroy = pnv_chip_power8_intc_destroy; 1242 k->intc_print_info = pnv_chip_power8_intc_print_info; 1243 k->isa_create = pnv_chip_power8_isa_create; 1244 k->dt_populate = pnv_chip_power8_dt_populate; 1245 k->pic_print_info = pnv_chip_power8_pic_print_info; 1246 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1247 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1248 dc->desc = "PowerNV Chip POWER8E"; 1249 1250 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1251 &k->parent_realize); 1252 } 1253 1254 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1255 { 1256 DeviceClass *dc = DEVICE_CLASS(klass); 1257 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1258 1259 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1260 k->cores_mask = POWER8_CORE_MASK; 1261 k->num_phbs = 3; 1262 k->core_pir = pnv_chip_core_pir_p8; 1263 k->intc_create = pnv_chip_power8_intc_create; 1264 k->intc_reset = pnv_chip_power8_intc_reset; 1265 k->intc_destroy = pnv_chip_power8_intc_destroy; 1266 k->intc_print_info = pnv_chip_power8_intc_print_info; 1267 k->isa_create = pnv_chip_power8_isa_create; 1268 k->dt_populate = pnv_chip_power8_dt_populate; 1269 k->pic_print_info = pnv_chip_power8_pic_print_info; 1270 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1271 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1272 dc->desc = "PowerNV Chip POWER8"; 1273 1274 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1275 &k->parent_realize); 1276 } 1277 1278 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1279 { 1280 DeviceClass *dc = DEVICE_CLASS(klass); 1281 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1282 1283 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1284 k->cores_mask = POWER8_CORE_MASK; 1285 k->num_phbs = 3; 1286 k->core_pir = pnv_chip_core_pir_p8; 1287 k->intc_create = pnv_chip_power8_intc_create; 1288 k->intc_reset = pnv_chip_power8_intc_reset; 1289 k->intc_destroy = pnv_chip_power8_intc_destroy; 1290 k->intc_print_info = pnv_chip_power8_intc_print_info; 1291 k->isa_create = pnv_chip_power8nvl_isa_create; 1292 k->dt_populate = pnv_chip_power8_dt_populate; 1293 k->pic_print_info = pnv_chip_power8_pic_print_info; 1294 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1295 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1296 dc->desc = "PowerNV Chip POWER8NVL"; 1297 1298 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1299 &k->parent_realize); 1300 } 1301 1302 static void pnv_chip_power9_instance_init(Object *obj) 1303 { 1304 PnvChip *chip = PNV_CHIP(obj); 1305 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1306 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1307 int i; 1308 1309 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1310 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1311 "xive-fabric"); 1312 1313 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1314 1315 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1316 1317 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1318 1319 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1320 1321 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1322 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1323 TYPE_PNV_PHB4_PEC); 1324 } 1325 1326 /* 1327 * Number of PHBs is the chip default 1328 */ 1329 chip->num_phbs = pcc->num_phbs; 1330 } 1331 1332 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1333 { 1334 PnvChip *chip = PNV_CHIP(chip9); 1335 int i; 1336 1337 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1338 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1339 1340 for (i = 0; i < chip9->nr_quads; i++) { 1341 char eq_name[32]; 1342 PnvQuad *eq = &chip9->quads[i]; 1343 PnvCore *pnv_core = chip->cores[i * 4]; 1344 int core_id = CPU_CORE(pnv_core)->core_id; 1345 1346 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1347 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1348 sizeof(*eq), TYPE_PNV_QUAD, 1349 &error_fatal, NULL); 1350 1351 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1352 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1353 1354 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1355 &eq->xscom_regs); 1356 } 1357 } 1358 1359 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1360 { 1361 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1362 Error *local_err = NULL; 1363 int i, j; 1364 int phb_id = 0; 1365 1366 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1367 PnvPhb4PecState *pec = &chip9->pecs[i]; 1368 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1369 uint32_t pec_nest_base; 1370 uint32_t pec_pci_base; 1371 1372 object_property_set_int(OBJECT(pec), i, "index", &error_fatal); 1373 /* 1374 * PEC0 -> 1 stack 1375 * PEC1 -> 2 stacks 1376 * PEC2 -> 3 stacks 1377 */ 1378 object_property_set_int(OBJECT(pec), i + 1, "num-stacks", 1379 &error_fatal); 1380 object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id", 1381 &error_fatal); 1382 object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()), 1383 "system-memory", &error_abort); 1384 qdev_realize(DEVICE(pec), NULL, &local_err); 1385 if (local_err) { 1386 error_propagate(errp, local_err); 1387 return; 1388 } 1389 1390 pec_nest_base = pecc->xscom_nest_base(pec); 1391 pec_pci_base = pecc->xscom_pci_base(pec); 1392 1393 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1394 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1395 1396 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1397 j++, phb_id++) { 1398 PnvPhb4PecStack *stack = &pec->stacks[j]; 1399 Object *obj = OBJECT(&stack->phb); 1400 1401 object_property_set_int(obj, phb_id, "index", &error_fatal); 1402 object_property_set_int(obj, chip->chip_id, "chip-id", 1403 &error_fatal); 1404 object_property_set_int(obj, PNV_PHB4_VERSION, "version", 1405 &error_fatal); 1406 object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id", 1407 &error_fatal); 1408 object_property_set_link(obj, OBJECT(stack), "stack", &error_abort); 1409 sysbus_realize(SYS_BUS_DEVICE(obj), &local_err); 1410 if (local_err) { 1411 error_propagate(errp, local_err); 1412 return; 1413 } 1414 1415 /* Populate the XSCOM address space. */ 1416 pnv_xscom_add_subregion(chip, 1417 pec_nest_base + 0x40 * (stack->stack_no + 1), 1418 &stack->nest_regs_mr); 1419 pnv_xscom_add_subregion(chip, 1420 pec_pci_base + 0x40 * (stack->stack_no + 1), 1421 &stack->pci_regs_mr); 1422 pnv_xscom_add_subregion(chip, 1423 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1424 0x40 * stack->stack_no, 1425 &stack->phb_regs_mr); 1426 } 1427 } 1428 } 1429 1430 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1431 { 1432 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1433 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1434 PnvChip *chip = PNV_CHIP(dev); 1435 Pnv9Psi *psi9 = &chip9->psi; 1436 Error *local_err = NULL; 1437 1438 /* XSCOM bridge is first */ 1439 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1440 if (local_err) { 1441 error_propagate(errp, local_err); 1442 return; 1443 } 1444 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1445 1446 pcc->parent_realize(dev, &local_err); 1447 if (local_err) { 1448 error_propagate(errp, local_err); 1449 return; 1450 } 1451 1452 pnv_chip_quad_realize(chip9, &local_err); 1453 if (local_err) { 1454 error_propagate(errp, local_err); 1455 return; 1456 } 1457 1458 /* XIVE interrupt controller (POWER9) */ 1459 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1460 "ic-bar", &error_fatal); 1461 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1462 "vc-bar", &error_fatal); 1463 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1464 "pc-bar", &error_fatal); 1465 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1466 "tm-bar", &error_fatal); 1467 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1468 &error_abort); 1469 sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), &local_err); 1470 if (local_err) { 1471 error_propagate(errp, local_err); 1472 return; 1473 } 1474 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1475 &chip9->xive.xscom_regs); 1476 1477 /* Processor Service Interface (PSI) Host Bridge */ 1478 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1479 "bar", &error_fatal); 1480 qdev_realize(DEVICE(&chip9->psi), NULL, &local_err); 1481 if (local_err) { 1482 error_propagate(errp, local_err); 1483 return; 1484 } 1485 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1486 &PNV_PSI(psi9)->xscom_regs); 1487 1488 /* LPC */ 1489 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1490 &error_abort); 1491 qdev_realize(DEVICE(&chip9->lpc), NULL, &local_err); 1492 if (local_err) { 1493 error_propagate(errp, local_err); 1494 return; 1495 } 1496 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1497 &chip9->lpc.xscom_regs); 1498 1499 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1500 (uint64_t) PNV9_LPCM_BASE(chip)); 1501 1502 /* Create the simplified OCC model */ 1503 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1504 &error_abort); 1505 qdev_realize(DEVICE(&chip9->occ), NULL, &local_err); 1506 if (local_err) { 1507 error_propagate(errp, local_err); 1508 return; 1509 } 1510 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1511 1512 /* OCC SRAM model */ 1513 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1514 &chip9->occ.sram_regs); 1515 1516 /* HOMER */ 1517 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1518 &error_abort); 1519 qdev_realize(DEVICE(&chip9->homer), NULL, &local_err); 1520 if (local_err) { 1521 error_propagate(errp, local_err); 1522 return; 1523 } 1524 /* Homer Xscom region */ 1525 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1526 1527 /* Homer mmio region */ 1528 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1529 &chip9->homer.regs); 1530 1531 /* PHBs */ 1532 pnv_chip_power9_phb_realize(chip, &local_err); 1533 if (local_err) { 1534 error_propagate(errp, local_err); 1535 return; 1536 } 1537 } 1538 1539 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1540 { 1541 addr &= (PNV9_XSCOM_SIZE - 1); 1542 return addr >> 3; 1543 } 1544 1545 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1546 { 1547 DeviceClass *dc = DEVICE_CLASS(klass); 1548 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1549 1550 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1551 k->cores_mask = POWER9_CORE_MASK; 1552 k->core_pir = pnv_chip_core_pir_p9; 1553 k->intc_create = pnv_chip_power9_intc_create; 1554 k->intc_reset = pnv_chip_power9_intc_reset; 1555 k->intc_destroy = pnv_chip_power9_intc_destroy; 1556 k->intc_print_info = pnv_chip_power9_intc_print_info; 1557 k->isa_create = pnv_chip_power9_isa_create; 1558 k->dt_populate = pnv_chip_power9_dt_populate; 1559 k->pic_print_info = pnv_chip_power9_pic_print_info; 1560 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1561 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1562 dc->desc = "PowerNV Chip POWER9"; 1563 k->num_phbs = 6; 1564 1565 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1566 &k->parent_realize); 1567 } 1568 1569 static void pnv_chip_power10_instance_init(Object *obj) 1570 { 1571 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1572 1573 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1574 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1575 } 1576 1577 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1578 { 1579 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1580 PnvChip *chip = PNV_CHIP(dev); 1581 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1582 Error *local_err = NULL; 1583 1584 /* XSCOM bridge is first */ 1585 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1586 if (local_err) { 1587 error_propagate(errp, local_err); 1588 return; 1589 } 1590 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1591 1592 pcc->parent_realize(dev, &local_err); 1593 if (local_err) { 1594 error_propagate(errp, local_err); 1595 return; 1596 } 1597 1598 /* Processor Service Interface (PSI) Host Bridge */ 1599 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1600 "bar", &error_fatal); 1601 qdev_realize(DEVICE(&chip10->psi), NULL, &local_err); 1602 if (local_err) { 1603 error_propagate(errp, local_err); 1604 return; 1605 } 1606 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1607 &PNV_PSI(&chip10->psi)->xscom_regs); 1608 1609 /* LPC */ 1610 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1611 &error_abort); 1612 qdev_realize(DEVICE(&chip10->lpc), NULL, &local_err); 1613 if (local_err) { 1614 error_propagate(errp, local_err); 1615 return; 1616 } 1617 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1618 &chip10->lpc.xscom_regs); 1619 1620 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1621 (uint64_t) PNV10_LPCM_BASE(chip)); 1622 } 1623 1624 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1625 { 1626 addr &= (PNV10_XSCOM_SIZE - 1); 1627 return addr >> 3; 1628 } 1629 1630 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1631 { 1632 DeviceClass *dc = DEVICE_CLASS(klass); 1633 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1634 1635 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1636 k->cores_mask = POWER10_CORE_MASK; 1637 k->core_pir = pnv_chip_core_pir_p10; 1638 k->intc_create = pnv_chip_power10_intc_create; 1639 k->intc_reset = pnv_chip_power10_intc_reset; 1640 k->intc_destroy = pnv_chip_power10_intc_destroy; 1641 k->intc_print_info = pnv_chip_power10_intc_print_info; 1642 k->isa_create = pnv_chip_power10_isa_create; 1643 k->dt_populate = pnv_chip_power10_dt_populate; 1644 k->pic_print_info = pnv_chip_power10_pic_print_info; 1645 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1646 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1647 dc->desc = "PowerNV Chip POWER10"; 1648 1649 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1650 &k->parent_realize); 1651 } 1652 1653 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1654 { 1655 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1656 int cores_max; 1657 1658 /* 1659 * No custom mask for this chip, let's use the default one from * 1660 * the chip class 1661 */ 1662 if (!chip->cores_mask) { 1663 chip->cores_mask = pcc->cores_mask; 1664 } 1665 1666 /* filter alien core ids ! some are reserved */ 1667 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1668 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1669 chip->cores_mask); 1670 return; 1671 } 1672 chip->cores_mask &= pcc->cores_mask; 1673 1674 /* now that we have a sane layout, let check the number of cores */ 1675 cores_max = ctpop64(chip->cores_mask); 1676 if (chip->nr_cores > cores_max) { 1677 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1678 cores_max); 1679 return; 1680 } 1681 } 1682 1683 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1684 { 1685 Error *error = NULL; 1686 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1687 const char *typename = pnv_chip_core_typename(chip); 1688 int i, core_hwid; 1689 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1690 1691 if (!object_class_by_name(typename)) { 1692 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1693 return; 1694 } 1695 1696 /* Cores */ 1697 pnv_chip_core_sanitize(chip, &error); 1698 if (error) { 1699 error_propagate(errp, error); 1700 return; 1701 } 1702 1703 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1704 1705 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1706 && (i < chip->nr_cores); core_hwid++) { 1707 char core_name[32]; 1708 PnvCore *pnv_core; 1709 uint64_t xscom_core_base; 1710 1711 if (!(chip->cores_mask & (1ull << core_hwid))) { 1712 continue; 1713 } 1714 1715 pnv_core = PNV_CORE(object_new(typename)); 1716 1717 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1718 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1719 chip->cores[i] = pnv_core; 1720 object_property_set_int(OBJECT(pnv_core), chip->nr_threads, 1721 "nr-threads", &error_fatal); 1722 object_property_set_int(OBJECT(pnv_core), core_hwid, 1723 CPU_CORE_PROP_CORE_ID, &error_fatal); 1724 object_property_set_int(OBJECT(pnv_core), 1725 pcc->core_pir(chip, core_hwid), 1726 "pir", &error_fatal); 1727 object_property_set_int(OBJECT(pnv_core), pnv->fw_load_addr, 1728 "hrmor", &error_fatal); 1729 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1730 &error_abort); 1731 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1732 1733 /* Each core has an XSCOM MMIO region */ 1734 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1735 1736 pnv_xscom_add_subregion(chip, xscom_core_base, 1737 &pnv_core->xscom_regs); 1738 i++; 1739 } 1740 } 1741 1742 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1743 { 1744 PnvChip *chip = PNV_CHIP(dev); 1745 Error *error = NULL; 1746 1747 /* Cores */ 1748 pnv_chip_core_realize(chip, &error); 1749 if (error) { 1750 error_propagate(errp, error); 1751 return; 1752 } 1753 } 1754 1755 static Property pnv_chip_properties[] = { 1756 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1757 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1758 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1759 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1760 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1761 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1762 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1763 DEFINE_PROP_END_OF_LIST(), 1764 }; 1765 1766 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1767 { 1768 DeviceClass *dc = DEVICE_CLASS(klass); 1769 1770 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1771 dc->realize = pnv_chip_realize; 1772 device_class_set_props(dc, pnv_chip_properties); 1773 dc->desc = "PowerNV Chip"; 1774 } 1775 1776 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1777 { 1778 int i, j; 1779 1780 for (i = 0; i < chip->nr_cores; i++) { 1781 PnvCore *pc = chip->cores[i]; 1782 CPUCore *cc = CPU_CORE(pc); 1783 1784 for (j = 0; j < cc->nr_threads; j++) { 1785 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1786 return pc->threads[j]; 1787 } 1788 } 1789 } 1790 return NULL; 1791 } 1792 1793 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1794 { 1795 PnvMachineState *pnv = PNV_MACHINE(xi); 1796 int i, j; 1797 1798 for (i = 0; i < pnv->num_chips; i++) { 1799 PnvChip *chip = pnv->chips[i]; 1800 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1801 1802 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1803 return &chip8->psi.ics; 1804 } 1805 for (j = 0; j < chip->num_phbs; j++) { 1806 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1807 return &chip8->phbs[j].lsis; 1808 } 1809 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1810 return ICS(&chip8->phbs[j].msis); 1811 } 1812 } 1813 } 1814 return NULL; 1815 } 1816 1817 static void pnv_ics_resend(XICSFabric *xi) 1818 { 1819 PnvMachineState *pnv = PNV_MACHINE(xi); 1820 int i, j; 1821 1822 for (i = 0; i < pnv->num_chips; i++) { 1823 PnvChip *chip = pnv->chips[i]; 1824 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1825 1826 ics_resend(&chip8->psi.ics); 1827 for (j = 0; j < chip->num_phbs; j++) { 1828 ics_resend(&chip8->phbs[j].lsis); 1829 ics_resend(ICS(&chip8->phbs[j].msis)); 1830 } 1831 } 1832 } 1833 1834 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1835 { 1836 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1837 1838 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1839 } 1840 1841 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1842 Monitor *mon) 1843 { 1844 PnvMachineState *pnv = PNV_MACHINE(obj); 1845 int i; 1846 CPUState *cs; 1847 1848 CPU_FOREACH(cs) { 1849 PowerPCCPU *cpu = POWERPC_CPU(cs); 1850 1851 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1852 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1853 mon); 1854 } 1855 1856 for (i = 0; i < pnv->num_chips; i++) { 1857 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1858 } 1859 } 1860 1861 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1862 uint8_t nvt_blk, uint32_t nvt_idx, 1863 bool cam_ignore, uint8_t priority, 1864 uint32_t logic_serv, 1865 XiveTCTXMatch *match) 1866 { 1867 PnvMachineState *pnv = PNV_MACHINE(xfb); 1868 int total_count = 0; 1869 int i; 1870 1871 for (i = 0; i < pnv->num_chips; i++) { 1872 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1873 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1874 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1875 int count; 1876 1877 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1878 priority, logic_serv, match); 1879 1880 if (count < 0) { 1881 return count; 1882 } 1883 1884 total_count += count; 1885 } 1886 1887 return total_count; 1888 } 1889 1890 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1891 { 1892 MachineClass *mc = MACHINE_CLASS(oc); 1893 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1894 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1895 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1896 1897 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1898 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1899 1900 xic->icp_get = pnv_icp_get; 1901 xic->ics_get = pnv_ics_get; 1902 xic->ics_resend = pnv_ics_resend; 1903 1904 pmc->compat = compat; 1905 pmc->compat_size = sizeof(compat); 1906 } 1907 1908 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1909 { 1910 MachineClass *mc = MACHINE_CLASS(oc); 1911 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1912 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1913 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1914 1915 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1916 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1917 xfc->match_nvt = pnv_match_nvt; 1918 1919 mc->alias = "powernv"; 1920 1921 pmc->compat = compat; 1922 pmc->compat_size = sizeof(compat); 1923 pmc->dt_power_mgt = pnv_dt_power_mgt; 1924 } 1925 1926 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1927 { 1928 MachineClass *mc = MACHINE_CLASS(oc); 1929 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1930 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1931 1932 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1933 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1934 1935 pmc->compat = compat; 1936 pmc->compat_size = sizeof(compat); 1937 pmc->dt_power_mgt = pnv_dt_power_mgt; 1938 } 1939 1940 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1941 { 1942 PnvMachineState *pnv = PNV_MACHINE(obj); 1943 1944 return !!pnv->fw_load_addr; 1945 } 1946 1947 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1948 { 1949 PnvMachineState *pnv = PNV_MACHINE(obj); 1950 1951 if (value) { 1952 pnv->fw_load_addr = 0x8000000; 1953 } 1954 } 1955 1956 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 1957 { 1958 PowerPCCPU *cpu = POWERPC_CPU(cs); 1959 CPUPPCState *env = &cpu->env; 1960 1961 cpu_synchronize_state(cs); 1962 ppc_cpu_do_system_reset(cs); 1963 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 1964 /* 1965 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 1966 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 1967 * (PPC_BIT(43)). 1968 */ 1969 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 1970 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 1971 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 1972 } 1973 } else { 1974 /* 1975 * For non-powersave system resets, SRR1[42:45] are defined to be 1976 * implementation-dependent. The POWER9 User Manual specifies that 1977 * an external (SCOM driven, which may come from a BMC nmi command or 1978 * another CPU requesting a NMI IPI) system reset exception should be 1979 * 0b0010 (PPC_BIT(44)). 1980 */ 1981 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 1982 } 1983 } 1984 1985 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 1986 { 1987 CPUState *cs; 1988 1989 CPU_FOREACH(cs) { 1990 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 1991 } 1992 } 1993 1994 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1995 { 1996 MachineClass *mc = MACHINE_CLASS(oc); 1997 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1998 NMIClass *nc = NMI_CLASS(oc); 1999 2000 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2001 mc->init = pnv_init; 2002 mc->reset = pnv_reset; 2003 mc->max_cpus = MAX_CPUS; 2004 /* Pnv provides a AHCI device for storage */ 2005 mc->block_default_type = IF_IDE; 2006 mc->no_parallel = 1; 2007 mc->default_boot_order = NULL; 2008 /* 2009 * RAM defaults to less than 2048 for 32-bit hosts, and large 2010 * enough to fit the maximum initrd size at it's load address 2011 */ 2012 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 2013 mc->default_ram_id = "pnv.ram"; 2014 ispc->print_info = pnv_pic_print_info; 2015 nc->nmi_monitor_handler = pnv_nmi; 2016 2017 object_class_property_add_bool(oc, "hb-mode", 2018 pnv_machine_get_hb, pnv_machine_set_hb); 2019 object_class_property_set_description(oc, "hb-mode", 2020 "Use a hostboot like boot loader"); 2021 } 2022 2023 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2024 { \ 2025 .name = type, \ 2026 .class_init = class_initfn, \ 2027 .parent = TYPE_PNV8_CHIP, \ 2028 } 2029 2030 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2031 { \ 2032 .name = type, \ 2033 .class_init = class_initfn, \ 2034 .parent = TYPE_PNV9_CHIP, \ 2035 } 2036 2037 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2038 { \ 2039 .name = type, \ 2040 .class_init = class_initfn, \ 2041 .parent = TYPE_PNV10_CHIP, \ 2042 } 2043 2044 static const TypeInfo types[] = { 2045 { 2046 .name = MACHINE_TYPE_NAME("powernv10"), 2047 .parent = TYPE_PNV_MACHINE, 2048 .class_init = pnv_machine_power10_class_init, 2049 }, 2050 { 2051 .name = MACHINE_TYPE_NAME("powernv9"), 2052 .parent = TYPE_PNV_MACHINE, 2053 .class_init = pnv_machine_power9_class_init, 2054 .interfaces = (InterfaceInfo[]) { 2055 { TYPE_XIVE_FABRIC }, 2056 { }, 2057 }, 2058 }, 2059 { 2060 .name = MACHINE_TYPE_NAME("powernv8"), 2061 .parent = TYPE_PNV_MACHINE, 2062 .class_init = pnv_machine_power8_class_init, 2063 .interfaces = (InterfaceInfo[]) { 2064 { TYPE_XICS_FABRIC }, 2065 { }, 2066 }, 2067 }, 2068 { 2069 .name = TYPE_PNV_MACHINE, 2070 .parent = TYPE_MACHINE, 2071 .abstract = true, 2072 .instance_size = sizeof(PnvMachineState), 2073 .class_init = pnv_machine_class_init, 2074 .class_size = sizeof(PnvMachineClass), 2075 .interfaces = (InterfaceInfo[]) { 2076 { TYPE_INTERRUPT_STATS_PROVIDER }, 2077 { TYPE_NMI }, 2078 { }, 2079 }, 2080 }, 2081 { 2082 .name = TYPE_PNV_CHIP, 2083 .parent = TYPE_SYS_BUS_DEVICE, 2084 .class_init = pnv_chip_class_init, 2085 .instance_size = sizeof(PnvChip), 2086 .class_size = sizeof(PnvChipClass), 2087 .abstract = true, 2088 }, 2089 2090 /* 2091 * P10 chip and variants 2092 */ 2093 { 2094 .name = TYPE_PNV10_CHIP, 2095 .parent = TYPE_PNV_CHIP, 2096 .instance_init = pnv_chip_power10_instance_init, 2097 .instance_size = sizeof(Pnv10Chip), 2098 }, 2099 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2100 2101 /* 2102 * P9 chip and variants 2103 */ 2104 { 2105 .name = TYPE_PNV9_CHIP, 2106 .parent = TYPE_PNV_CHIP, 2107 .instance_init = pnv_chip_power9_instance_init, 2108 .instance_size = sizeof(Pnv9Chip), 2109 }, 2110 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2111 2112 /* 2113 * P8 chip and variants 2114 */ 2115 { 2116 .name = TYPE_PNV8_CHIP, 2117 .parent = TYPE_PNV_CHIP, 2118 .instance_init = pnv_chip_power8_instance_init, 2119 .instance_size = sizeof(Pnv8Chip), 2120 }, 2121 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2122 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2123 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2124 pnv_chip_power8nvl_class_init), 2125 }; 2126 2127 DEFINE_TYPES(types) 2128