1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qemu/units.h" 24 #include "qemu/cutils.h" 25 #include "qapi/error.h" 26 #include "sysemu/qtest.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/reset.h" 30 #include "sysemu/runstate.h" 31 #include "sysemu/cpus.h" 32 #include "sysemu/device_tree.h" 33 #include "sysemu/hw_accel.h" 34 #include "target/ppc/cpu.h" 35 #include "hw/ppc/fdt.h" 36 #include "hw/ppc/ppc.h" 37 #include "hw/ppc/pnv.h" 38 #include "hw/ppc/pnv_core.h" 39 #include "hw/loader.h" 40 #include "hw/nmi.h" 41 #include "qapi/visitor.h" 42 #include "monitor/monitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 48 #include "hw/ppc/xics.h" 49 #include "hw/qdev-properties.h" 50 #include "hw/ppc/pnv_xscom.h" 51 #include "hw/ppc/pnv_pnor.h" 52 53 #include "hw/isa/isa.h" 54 #include "hw/char/serial.h" 55 #include "hw/rtc/mc146818rtc.h" 56 57 #include <libfdt.h> 58 59 #define FDT_MAX_SIZE (1 * MiB) 60 61 #define FW_FILE_NAME "skiboot.lid" 62 #define FW_LOAD_ADDR 0x0 63 #define FW_MAX_SIZE (16 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x20000000 66 #define KERNEL_MAX_SIZE (128 * MiB) 67 #define INITRD_LOAD_ADDR 0x28000000 68 #define INITRD_MAX_SIZE (128 * MiB) 69 70 static const char *pnv_chip_core_typename(const PnvChip *o) 71 { 72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 75 const char *core_type = object_class_get_name(object_class_by_name(s)); 76 g_free(s); 77 return core_type; 78 } 79 80 /* 81 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 82 * 4 * 4 sockets * 12 cores * 8 threads = 1536 83 * Let's make it 2^11 84 */ 85 #define MAX_CPUS 2048 86 87 /* 88 * Memory nodes are created by hostboot, one for each range of memory 89 * that has a different "affinity". In practice, it means one range 90 * per chip. 91 */ 92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 93 { 94 char *mem_name; 95 uint64_t mem_reg_property[2]; 96 int off; 97 98 mem_reg_property[0] = cpu_to_be64(start); 99 mem_reg_property[1] = cpu_to_be64(size); 100 101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 102 off = fdt_add_subnode(fdt, 0, mem_name); 103 g_free(mem_name); 104 105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 107 sizeof(mem_reg_property)))); 108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 109 } 110 111 static int get_cpus_node(void *fdt) 112 { 113 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 114 115 if (cpus_offset < 0) { 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 117 if (cpus_offset) { 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 120 } 121 } 122 _FDT(cpus_offset); 123 return cpus_offset; 124 } 125 126 /* 127 * The PowerNV cores (and threads) need to use real HW ids and not an 128 * incremental index like it has been done on other platforms. This HW 129 * id is stored in the CPU PIR, it is used to create cpu nodes in the 130 * device tree, used in XSCOM to address cores and in interrupt 131 * servers. 132 */ 133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 134 { 135 PowerPCCPU *cpu = pc->threads[0]; 136 CPUState *cs = CPU(cpu); 137 DeviceClass *dc = DEVICE_GET_CLASS(cs); 138 int smt_threads = CPU_CORE(pc)->nr_threads; 139 CPUPPCState *env = &cpu->env; 140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 141 uint32_t servers_prop[smt_threads]; 142 int i; 143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 144 0xffffffff, 0xffffffff}; 145 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 146 uint32_t cpufreq = 1000000000; 147 uint32_t page_sizes_prop[64]; 148 size_t page_sizes_prop_size; 149 const uint8_t pa_features[] = { 24, 0, 150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 154 int offset; 155 char *nodename; 156 int cpus_offset = get_cpus_node(fdt); 157 158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 159 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 160 _FDT(offset); 161 g_free(nodename); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 175 env->icache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 177 env->icache_line_size))); 178 179 if (pcc->l1_dcache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 181 pcc->l1_dcache_size))); 182 } else { 183 warn_report("Unknown L1 dcache size for cpu"); 184 } 185 if (pcc->l1_icache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 187 pcc->l1_icache_size))); 188 } else { 189 warn_report("Unknown L1 icache size for cpu"); 190 } 191 192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 195 cpu->hash64_opts->slb_size))); 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 198 199 if (ppc_has_spr(cpu, SPR_PURR)) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 201 } 202 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 205 segs, sizeof(segs)))); 206 } 207 208 /* 209 * Advertise VMX/VSX (vector extensions) if available 210 * 0 / no property == no vector extensions 211 * 1 == VMX / Altivec available 212 * 2 == VSX available 213 */ 214 if (env->insns_flags & PPC_ALTIVEC) { 215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 216 217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 218 } 219 220 /* 221 * Advertise DFP (Decimal Floating Point) if available 222 * 0 / no property == no DFP 223 * 1 == DFP available 224 */ 225 if (env->insns_flags2 & PPC2_DFP) { 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 227 } 228 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 230 sizeof(page_sizes_prop)); 231 if (page_sizes_prop_size) { 232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 233 page_sizes_prop, page_sizes_prop_size))); 234 } 235 236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 237 pa_features, sizeof(pa_features)))); 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pc->pir + i); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(servers_prop)))); 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 248 uint32_t nr_threads) 249 { 250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 251 char *name; 252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 253 uint32_t irange[2], i, rsize; 254 uint64_t *reg; 255 int offset; 256 257 irange[0] = cpu_to_be32(pir); 258 irange[1] = cpu_to_be32(nr_threads); 259 260 rsize = sizeof(uint64_t) * 2 * nr_threads; 261 reg = g_malloc(rsize); 262 for (i = 0; i < nr_threads; i++) { 263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 264 reg[i * 2 + 1] = cpu_to_be64(0x1000); 265 } 266 267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 268 offset = fdt_add_subnode(fdt, 0, name); 269 _FDT(offset); 270 g_free(name); 271 272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 274 _FDT((fdt_setprop_string(fdt, offset, "device_type", 275 "PowerPC-External-Interrupt-Presentation"))); 276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 278 irange, sizeof(irange)))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 281 g_free(reg); 282 } 283 284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 285 { 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 287 int i; 288 289 pnv_dt_xscom(chip, fdt, 0, 290 cpu_to_be64(PNV_XSCOM_BASE(chip)), 291 cpu_to_be64(PNV_XSCOM_SIZE), 292 compat, sizeof(compat)); 293 294 for (i = 0; i < chip->nr_cores; i++) { 295 PnvCore *pnv_core = chip->cores[i]; 296 297 pnv_dt_core(chip, pnv_core, fdt); 298 299 /* Interrupt Control Presenters (ICP). One per core. */ 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 301 } 302 303 if (chip->ram_size) { 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 305 } 306 } 307 308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 309 { 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 311 int i; 312 313 pnv_dt_xscom(chip, fdt, 0, 314 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 315 cpu_to_be64(PNV9_XSCOM_SIZE), 316 compat, sizeof(compat)); 317 318 for (i = 0; i < chip->nr_cores; i++) { 319 PnvCore *pnv_core = chip->cores[i]; 320 321 pnv_dt_core(chip, pnv_core, fdt); 322 } 323 324 if (chip->ram_size) { 325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 326 } 327 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 329 } 330 331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 332 { 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 334 int i; 335 336 pnv_dt_xscom(chip, fdt, 0, 337 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 338 cpu_to_be64(PNV10_XSCOM_SIZE), 339 compat, sizeof(compat)); 340 341 for (i = 0; i < chip->nr_cores; i++) { 342 PnvCore *pnv_core = chip->cores[i]; 343 344 pnv_dt_core(chip, pnv_core, fdt); 345 } 346 347 if (chip->ram_size) { 348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 349 } 350 351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 352 } 353 354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 355 { 356 uint32_t io_base = d->ioport_id; 357 uint32_t io_regs[] = { 358 cpu_to_be32(1), 359 cpu_to_be32(io_base), 360 cpu_to_be32(2) 361 }; 362 char *name; 363 int node; 364 365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 366 node = fdt_add_subnode(fdt, lpc_off, name); 367 _FDT(node); 368 g_free(name); 369 370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 372 } 373 374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 375 { 376 const char compatible[] = "ns16550\0pnpPNP,501"; 377 uint32_t io_base = d->ioport_id; 378 uint32_t io_regs[] = { 379 cpu_to_be32(1), 380 cpu_to_be32(io_base), 381 cpu_to_be32(8) 382 }; 383 char *name; 384 int node; 385 386 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 387 node = fdt_add_subnode(fdt, lpc_off, name); 388 _FDT(node); 389 g_free(name); 390 391 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 392 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 393 sizeof(compatible)))); 394 395 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 396 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 397 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 398 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 399 fdt_get_phandle(fdt, lpc_off)))); 400 401 /* This is needed by Linux */ 402 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 403 } 404 405 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 406 { 407 const char compatible[] = "bt\0ipmi-bt"; 408 uint32_t io_base; 409 uint32_t io_regs[] = { 410 cpu_to_be32(1), 411 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 412 cpu_to_be32(3) 413 }; 414 uint32_t irq; 415 char *name; 416 int node; 417 418 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 419 io_regs[1] = cpu_to_be32(io_base); 420 421 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 422 423 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 424 node = fdt_add_subnode(fdt, lpc_off, name); 425 _FDT(node); 426 g_free(name); 427 428 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 429 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 430 sizeof(compatible)))); 431 432 /* Mark it as reserved to avoid Linux trying to claim it */ 433 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 434 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 435 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 436 fdt_get_phandle(fdt, lpc_off)))); 437 } 438 439 typedef struct ForeachPopulateArgs { 440 void *fdt; 441 int offset; 442 } ForeachPopulateArgs; 443 444 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 445 { 446 ForeachPopulateArgs *args = opaque; 447 ISADevice *d = ISA_DEVICE(dev); 448 449 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 450 pnv_dt_rtc(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 452 pnv_dt_serial(d, args->fdt, args->offset); 453 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 454 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 455 } else { 456 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 457 d->ioport_id); 458 } 459 460 return 0; 461 } 462 463 /* 464 * The default LPC bus of a multichip system is on chip 0. It's 465 * recognized by the firmware (skiboot) using a "primary" property. 466 */ 467 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 468 { 469 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 470 ForeachPopulateArgs args = { 471 .fdt = fdt, 472 .offset = isa_offset, 473 }; 474 uint32_t phandle; 475 476 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 477 478 phandle = qemu_fdt_alloc_phandle(fdt); 479 assert(phandle > 0); 480 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 481 482 /* 483 * ISA devices are not necessarily parented to the ISA bus so we 484 * can not use object_child_foreach() 485 */ 486 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 487 &args); 488 } 489 490 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 491 { 492 int off; 493 494 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 495 off = fdt_add_subnode(fdt, off, "power-mgt"); 496 497 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 498 } 499 500 static void *pnv_dt_create(MachineState *machine) 501 { 502 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 503 PnvMachineState *pnv = PNV_MACHINE(machine); 504 void *fdt; 505 char *buf; 506 int off; 507 int i; 508 509 fdt = g_malloc0(FDT_MAX_SIZE); 510 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 511 512 /* /qemu node */ 513 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 514 515 /* Root node */ 516 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 517 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 518 _FDT((fdt_setprop_string(fdt, 0, "model", 519 "IBM PowerNV (emulated by qemu)"))); 520 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 521 522 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 523 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 524 if (qemu_uuid_set) { 525 _FDT((fdt_property_string(fdt, "system-id", buf))); 526 } 527 g_free(buf); 528 529 off = fdt_add_subnode(fdt, 0, "chosen"); 530 if (machine->kernel_cmdline) { 531 _FDT((fdt_setprop_string(fdt, off, "bootargs", 532 machine->kernel_cmdline))); 533 } 534 535 if (pnv->initrd_size) { 536 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 537 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 538 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 540 &start_prop, sizeof(start_prop)))); 541 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 542 &end_prop, sizeof(end_prop)))); 543 } 544 545 /* Populate device tree for each chip */ 546 for (i = 0; i < pnv->num_chips; i++) { 547 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 548 } 549 550 /* Populate ISA devices on chip 0 */ 551 pnv_dt_isa(pnv, fdt); 552 553 if (pnv->bmc) { 554 pnv_dt_bmc_sensors(pnv->bmc, fdt); 555 } 556 557 /* Create an extra node for power management on machines that support it */ 558 if (pmc->dt_power_mgt) { 559 pmc->dt_power_mgt(pnv, fdt); 560 } 561 562 return fdt; 563 } 564 565 static void pnv_powerdown_notify(Notifier *n, void *opaque) 566 { 567 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 568 569 if (pnv->bmc) { 570 pnv_bmc_powerdown(pnv->bmc); 571 } 572 } 573 574 static void pnv_reset(MachineState *machine) 575 { 576 PnvMachineState *pnv = PNV_MACHINE(machine); 577 IPMIBmc *bmc; 578 void *fdt; 579 580 qemu_devices_reset(); 581 582 /* 583 * The machine should provide by default an internal BMC simulator. 584 * If not, try to use the BMC device that was provided on the command 585 * line. 586 */ 587 bmc = pnv_bmc_find(&error_fatal); 588 if (!pnv->bmc) { 589 if (!bmc) { 590 if (!qtest_enabled()) { 591 warn_report("machine has no BMC device. Use '-device " 592 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 593 "to define one"); 594 } 595 } else { 596 pnv_bmc_set_pnor(bmc, pnv->pnor); 597 pnv->bmc = bmc; 598 } 599 } 600 601 fdt = pnv_dt_create(machine); 602 603 /* Pack resulting tree */ 604 _FDT((fdt_pack(fdt))); 605 606 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 607 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 608 609 g_free(fdt); 610 } 611 612 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 613 { 614 Pnv8Chip *chip8 = PNV8_CHIP(chip); 615 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 616 } 617 618 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 619 { 620 Pnv8Chip *chip8 = PNV8_CHIP(chip); 621 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 622 } 623 624 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 625 { 626 Pnv9Chip *chip9 = PNV9_CHIP(chip); 627 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 628 } 629 630 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 631 { 632 Pnv10Chip *chip10 = PNV10_CHIP(chip); 633 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 634 } 635 636 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 637 { 638 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 639 } 640 641 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 642 { 643 Pnv8Chip *chip8 = PNV8_CHIP(chip); 644 int i; 645 646 ics_pic_print_info(&chip8->psi.ics, mon); 647 for (i = 0; i < chip->num_phbs; i++) { 648 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 649 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 650 } 651 } 652 653 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 654 { 655 Pnv9Chip *chip9 = PNV9_CHIP(chip); 656 int i, j; 657 658 pnv_xive_pic_print_info(&chip9->xive, mon); 659 pnv_psi_pic_print_info(&chip9->psi, mon); 660 661 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 662 PnvPhb4PecState *pec = &chip9->pecs[i]; 663 for (j = 0; j < pec->num_stacks; j++) { 664 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 665 } 666 } 667 } 668 669 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 670 uint32_t core_id) 671 { 672 return PNV_XSCOM_EX_BASE(core_id); 673 } 674 675 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 676 uint32_t core_id) 677 { 678 return PNV9_XSCOM_EC_BASE(core_id); 679 } 680 681 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 682 uint32_t core_id) 683 { 684 return PNV10_XSCOM_EC_BASE(core_id); 685 } 686 687 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 688 { 689 PowerPCCPUClass *ppc_default = 690 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 691 PowerPCCPUClass *ppc = 692 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 693 694 return ppc_default->pvr_match(ppc_default, ppc->pvr); 695 } 696 697 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 698 { 699 ISADevice *dev = isa_new("isa-ipmi-bt"); 700 701 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 702 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 703 isa_realize_and_unref(dev, bus, &error_fatal); 704 } 705 706 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 707 { 708 Pnv10Chip *chip10 = PNV10_CHIP(chip); 709 710 pnv_psi_pic_print_info(&chip10->psi, mon); 711 } 712 713 /* Always give the first 1GB to chip 0 else we won't boot */ 714 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 715 { 716 MachineState *machine = MACHINE(pnv); 717 uint64_t ram_per_chip; 718 719 assert(machine->ram_size >= 1 * GiB); 720 721 ram_per_chip = machine->ram_size / pnv->num_chips; 722 if (ram_per_chip >= 1 * GiB) { 723 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 724 } 725 726 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 727 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 728 } 729 730 static void pnv_init(MachineState *machine) 731 { 732 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 733 PnvMachineState *pnv = PNV_MACHINE(machine); 734 MachineClass *mc = MACHINE_GET_CLASS(machine); 735 char *fw_filename; 736 long fw_size; 737 uint64_t chip_ram_start = 0; 738 int i; 739 char *chip_typename; 740 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 741 DeviceState *dev; 742 743 /* allocate RAM */ 744 if (machine->ram_size < mc->default_ram_size) { 745 char *sz = size_to_str(mc->default_ram_size); 746 error_report("Invalid RAM size, should be bigger than %s", sz); 747 g_free(sz); 748 exit(EXIT_FAILURE); 749 } 750 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 751 752 /* 753 * Create our simple PNOR device 754 */ 755 dev = qdev_new(TYPE_PNV_PNOR); 756 if (pnor) { 757 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 758 } 759 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 760 pnv->pnor = PNV_PNOR(dev); 761 762 /* load skiboot firmware */ 763 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 764 if (!fw_filename) { 765 error_report("Could not find OPAL firmware '%s'", bios_name); 766 exit(1); 767 } 768 769 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 770 if (fw_size < 0) { 771 error_report("Could not load OPAL firmware '%s'", fw_filename); 772 exit(1); 773 } 774 g_free(fw_filename); 775 776 /* load kernel */ 777 if (machine->kernel_filename) { 778 long kernel_size; 779 780 kernel_size = load_image_targphys(machine->kernel_filename, 781 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 782 if (kernel_size < 0) { 783 error_report("Could not load kernel '%s'", 784 machine->kernel_filename); 785 exit(1); 786 } 787 } 788 789 /* load initrd */ 790 if (machine->initrd_filename) { 791 pnv->initrd_base = INITRD_LOAD_ADDR; 792 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 793 pnv->initrd_base, INITRD_MAX_SIZE); 794 if (pnv->initrd_size < 0) { 795 error_report("Could not load initial ram disk '%s'", 796 machine->initrd_filename); 797 exit(1); 798 } 799 } 800 801 /* MSIs are supported on this platform */ 802 msi_nonbroken = true; 803 804 /* 805 * Check compatibility of the specified CPU with the machine 806 * default. 807 */ 808 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 809 error_report("invalid CPU model '%s' for %s machine", 810 machine->cpu_type, mc->name); 811 exit(1); 812 } 813 814 /* Create the processor chips */ 815 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 816 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 817 i, machine->cpu_type); 818 if (!object_class_by_name(chip_typename)) { 819 error_report("invalid chip model '%.*s' for %s machine", 820 i, machine->cpu_type, mc->name); 821 exit(1); 822 } 823 824 pnv->num_chips = 825 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 826 /* 827 * TODO: should we decide on how many chips we can create based 828 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 829 */ 830 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 831 error_report("invalid number of chips: '%d'", pnv->num_chips); 832 error_printf( 833 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 834 exit(1); 835 } 836 837 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 838 for (i = 0; i < pnv->num_chips; i++) { 839 char chip_name[32]; 840 Object *chip = OBJECT(qdev_new(chip_typename)); 841 int chip_id = i; 842 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, chip_id); 843 844 pnv->chips[i] = PNV_CHIP(chip); 845 846 /* Distribute RAM among the chips */ 847 object_property_set_int(chip, "ram-start", chip_ram_start, 848 &error_fatal); 849 object_property_set_int(chip, "ram-size", chip_ram_size, 850 &error_fatal); 851 chip_ram_start += chip_ram_size; 852 853 snprintf(chip_name, sizeof(chip_name), "chip[%d]", chip_id); 854 object_property_add_child(OBJECT(pnv), chip_name, chip); 855 object_property_set_int(chip, "chip-id", chip_id, &error_fatal); 856 object_property_set_int(chip, "nr-cores", machine->smp.cores, 857 &error_fatal); 858 object_property_set_int(chip, "nr-threads", machine->smp.threads, 859 &error_fatal); 860 /* 861 * The POWER8 machine use the XICS interrupt interface. 862 * Propagate the XICS fabric to the chip and its controllers. 863 */ 864 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 865 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 866 } 867 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 868 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 869 &error_abort); 870 } 871 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 872 } 873 g_free(chip_typename); 874 875 /* Instantiate ISA bus on chip 0 */ 876 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 877 878 /* Create serial port */ 879 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 880 881 /* Create an RTC ISA device too */ 882 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 883 884 /* 885 * Create the machine BMC simulator and the IPMI BT device for 886 * communication with the BMC 887 */ 888 if (defaults_enabled()) { 889 pnv->bmc = pnv_bmc_create(pnv->pnor); 890 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 891 } 892 893 /* 894 * The PNOR is mapped on the LPC FW address space by the BMC. 895 * Since we can not reach the remote BMC machine with LPC memops, 896 * map it always for now. 897 */ 898 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 899 &pnv->pnor->mmio); 900 901 /* 902 * OpenPOWER systems use a IPMI SEL Event message to notify the 903 * host to powerdown 904 */ 905 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 906 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 907 } 908 909 /* 910 * 0:21 Reserved - Read as zeros 911 * 22:24 Chip ID 912 * 25:28 Core number 913 * 29:31 Thread ID 914 */ 915 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 916 { 917 return (chip->chip_id << 7) | (core_id << 3); 918 } 919 920 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 921 Error **errp) 922 { 923 Pnv8Chip *chip8 = PNV8_CHIP(chip); 924 Error *local_err = NULL; 925 Object *obj; 926 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 927 928 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 929 if (local_err) { 930 error_propagate(errp, local_err); 931 return; 932 } 933 934 pnv_cpu->intc = obj; 935 } 936 937 938 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 939 { 940 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 941 942 icp_reset(ICP(pnv_cpu->intc)); 943 } 944 945 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 946 { 947 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 948 949 icp_destroy(ICP(pnv_cpu->intc)); 950 pnv_cpu->intc = NULL; 951 } 952 953 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 954 Monitor *mon) 955 { 956 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 957 } 958 959 /* 960 * 0:48 Reserved - Read as zeroes 961 * 49:52 Node ID 962 * 53:55 Chip ID 963 * 56 Reserved - Read as zero 964 * 57:61 Core number 965 * 62:63 Thread ID 966 * 967 * We only care about the lower bits. uint32_t is fine for the moment. 968 */ 969 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 970 { 971 return (chip->chip_id << 8) | (core_id << 2); 972 } 973 974 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 975 { 976 return (chip->chip_id << 8) | (core_id << 2); 977 } 978 979 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 980 Error **errp) 981 { 982 Pnv9Chip *chip9 = PNV9_CHIP(chip); 983 Error *local_err = NULL; 984 Object *obj; 985 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 986 987 /* 988 * The core creates its interrupt presenter but the XIVE interrupt 989 * controller object is initialized afterwards. Hopefully, it's 990 * only used at runtime. 991 */ 992 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 993 &local_err); 994 if (local_err) { 995 error_propagate(errp, local_err); 996 return; 997 } 998 999 pnv_cpu->intc = obj; 1000 } 1001 1002 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1003 { 1004 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1005 1006 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1007 } 1008 1009 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1010 { 1011 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1012 1013 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1014 pnv_cpu->intc = NULL; 1015 } 1016 1017 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1018 Monitor *mon) 1019 { 1020 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1021 } 1022 1023 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1024 Error **errp) 1025 { 1026 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1027 1028 /* Will be defined when the interrupt controller is */ 1029 pnv_cpu->intc = NULL; 1030 } 1031 1032 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1033 { 1034 ; 1035 } 1036 1037 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1038 { 1039 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1040 1041 pnv_cpu->intc = NULL; 1042 } 1043 1044 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1045 Monitor *mon) 1046 { 1047 } 1048 1049 /* 1050 * Allowed core identifiers on a POWER8 Processor Chip : 1051 * 1052 * <EX0 reserved> 1053 * EX1 - Venice only 1054 * EX2 - Venice only 1055 * EX3 - Venice only 1056 * EX4 1057 * EX5 1058 * EX6 1059 * <EX7,8 reserved> <reserved> 1060 * EX9 - Venice only 1061 * EX10 - Venice only 1062 * EX11 - Venice only 1063 * EX12 1064 * EX13 1065 * EX14 1066 * <EX15 reserved> 1067 */ 1068 #define POWER8E_CORE_MASK (0x7070ull) 1069 #define POWER8_CORE_MASK (0x7e7eull) 1070 1071 /* 1072 * POWER9 has 24 cores, ids starting at 0x0 1073 */ 1074 #define POWER9_CORE_MASK (0xffffffffffffffull) 1075 1076 1077 #define POWER10_CORE_MASK (0xffffffffffffffull) 1078 1079 static void pnv_chip_power8_instance_init(Object *obj) 1080 { 1081 PnvChip *chip = PNV_CHIP(obj); 1082 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1083 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1084 int i; 1085 1086 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1087 (Object **)&chip8->xics, 1088 object_property_allow_set_link, 1089 OBJ_PROP_LINK_STRONG); 1090 1091 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1092 1093 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1094 1095 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1096 1097 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1098 1099 for (i = 0; i < pcc->num_phbs; i++) { 1100 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1101 } 1102 1103 /* 1104 * Number of PHBs is the chip default 1105 */ 1106 chip->num_phbs = pcc->num_phbs; 1107 } 1108 1109 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1110 { 1111 PnvChip *chip = PNV_CHIP(chip8); 1112 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1113 int i, j; 1114 char *name; 1115 1116 name = g_strdup_printf("icp-%x", chip->chip_id); 1117 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1118 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1119 g_free(name); 1120 1121 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1122 1123 /* Map the ICP registers for each thread */ 1124 for (i = 0; i < chip->nr_cores; i++) { 1125 PnvCore *pnv_core = chip->cores[i]; 1126 int core_hwid = CPU_CORE(pnv_core)->core_id; 1127 1128 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1129 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1130 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1131 1132 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1133 &icp->mmio); 1134 } 1135 } 1136 } 1137 1138 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1139 { 1140 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1141 PnvChip *chip = PNV_CHIP(dev); 1142 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1143 Pnv8Psi *psi8 = &chip8->psi; 1144 Error *local_err = NULL; 1145 int i; 1146 1147 assert(chip8->xics); 1148 1149 /* XSCOM bridge is first */ 1150 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1151 if (local_err) { 1152 error_propagate(errp, local_err); 1153 return; 1154 } 1155 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1156 1157 pcc->parent_realize(dev, &local_err); 1158 if (local_err) { 1159 error_propagate(errp, local_err); 1160 return; 1161 } 1162 1163 /* Processor Service Interface (PSI) Host Bridge */ 1164 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1165 &error_fatal); 1166 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1167 OBJECT(chip8->xics), &error_abort); 1168 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1169 return; 1170 } 1171 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1172 &PNV_PSI(psi8)->xscom_regs); 1173 1174 /* Create LPC controller */ 1175 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi), 1176 &error_abort); 1177 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1178 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1179 1180 chip->fw_mr = &chip8->lpc.isa_fw; 1181 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1182 (uint64_t) PNV_XSCOM_BASE(chip), 1183 PNV_XSCOM_LPC_BASE); 1184 1185 /* 1186 * Interrupt Management Area. This is the memory region holding 1187 * all the Interrupt Control Presenter (ICP) registers 1188 */ 1189 pnv_chip_icp_realize(chip8, &local_err); 1190 if (local_err) { 1191 error_propagate(errp, local_err); 1192 return; 1193 } 1194 1195 /* Create the simplified OCC model */ 1196 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi), 1197 &error_abort); 1198 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1199 return; 1200 } 1201 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1202 1203 /* OCC SRAM model */ 1204 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1205 &chip8->occ.sram_regs); 1206 1207 /* HOMER */ 1208 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1209 &error_abort); 1210 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1211 return; 1212 } 1213 /* Homer Xscom region */ 1214 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1215 1216 /* Homer mmio region */ 1217 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1218 &chip8->homer.regs); 1219 1220 /* PHB3 controllers */ 1221 for (i = 0; i < chip->num_phbs; i++) { 1222 PnvPHB3 *phb = &chip8->phbs[i]; 1223 PnvPBCQState *pbcq = &phb->pbcq; 1224 1225 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1226 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1227 &error_fatal); 1228 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1229 return; 1230 } 1231 1232 /* Populate the XSCOM address space. */ 1233 pnv_xscom_add_subregion(chip, 1234 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1235 &pbcq->xscom_nest_regs); 1236 pnv_xscom_add_subregion(chip, 1237 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1238 &pbcq->xscom_pci_regs); 1239 pnv_xscom_add_subregion(chip, 1240 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1241 &pbcq->xscom_spci_regs); 1242 } 1243 } 1244 1245 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1246 { 1247 addr &= (PNV_XSCOM_SIZE - 1); 1248 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1249 } 1250 1251 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1252 { 1253 DeviceClass *dc = DEVICE_CLASS(klass); 1254 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1255 1256 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1257 k->cores_mask = POWER8E_CORE_MASK; 1258 k->num_phbs = 3; 1259 k->core_pir = pnv_chip_core_pir_p8; 1260 k->intc_create = pnv_chip_power8_intc_create; 1261 k->intc_reset = pnv_chip_power8_intc_reset; 1262 k->intc_destroy = pnv_chip_power8_intc_destroy; 1263 k->intc_print_info = pnv_chip_power8_intc_print_info; 1264 k->isa_create = pnv_chip_power8_isa_create; 1265 k->dt_populate = pnv_chip_power8_dt_populate; 1266 k->pic_print_info = pnv_chip_power8_pic_print_info; 1267 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1268 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1269 dc->desc = "PowerNV Chip POWER8E"; 1270 1271 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1272 &k->parent_realize); 1273 } 1274 1275 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1276 { 1277 DeviceClass *dc = DEVICE_CLASS(klass); 1278 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1279 1280 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1281 k->cores_mask = POWER8_CORE_MASK; 1282 k->num_phbs = 3; 1283 k->core_pir = pnv_chip_core_pir_p8; 1284 k->intc_create = pnv_chip_power8_intc_create; 1285 k->intc_reset = pnv_chip_power8_intc_reset; 1286 k->intc_destroy = pnv_chip_power8_intc_destroy; 1287 k->intc_print_info = pnv_chip_power8_intc_print_info; 1288 k->isa_create = pnv_chip_power8_isa_create; 1289 k->dt_populate = pnv_chip_power8_dt_populate; 1290 k->pic_print_info = pnv_chip_power8_pic_print_info; 1291 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1292 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1293 dc->desc = "PowerNV Chip POWER8"; 1294 1295 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1296 &k->parent_realize); 1297 } 1298 1299 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1300 { 1301 DeviceClass *dc = DEVICE_CLASS(klass); 1302 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1303 1304 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1305 k->cores_mask = POWER8_CORE_MASK; 1306 k->num_phbs = 3; 1307 k->core_pir = pnv_chip_core_pir_p8; 1308 k->intc_create = pnv_chip_power8_intc_create; 1309 k->intc_reset = pnv_chip_power8_intc_reset; 1310 k->intc_destroy = pnv_chip_power8_intc_destroy; 1311 k->intc_print_info = pnv_chip_power8_intc_print_info; 1312 k->isa_create = pnv_chip_power8nvl_isa_create; 1313 k->dt_populate = pnv_chip_power8_dt_populate; 1314 k->pic_print_info = pnv_chip_power8_pic_print_info; 1315 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1316 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1317 dc->desc = "PowerNV Chip POWER8NVL"; 1318 1319 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1320 &k->parent_realize); 1321 } 1322 1323 static void pnv_chip_power9_instance_init(Object *obj) 1324 { 1325 PnvChip *chip = PNV_CHIP(obj); 1326 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1327 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1328 int i; 1329 1330 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1331 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1332 "xive-fabric"); 1333 1334 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1335 1336 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1337 1338 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1339 1340 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1341 1342 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1343 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1344 TYPE_PNV_PHB4_PEC); 1345 } 1346 1347 /* 1348 * Number of PHBs is the chip default 1349 */ 1350 chip->num_phbs = pcc->num_phbs; 1351 } 1352 1353 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1354 { 1355 PnvChip *chip = PNV_CHIP(chip9); 1356 int i; 1357 1358 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1359 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1360 1361 for (i = 0; i < chip9->nr_quads; i++) { 1362 char eq_name[32]; 1363 PnvQuad *eq = &chip9->quads[i]; 1364 PnvCore *pnv_core = chip->cores[i * 4]; 1365 int core_id = CPU_CORE(pnv_core)->core_id; 1366 1367 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1368 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1369 sizeof(*eq), TYPE_PNV_QUAD, 1370 &error_fatal, NULL); 1371 1372 object_property_set_int(OBJECT(eq), "id", core_id, &error_fatal); 1373 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1374 1375 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1376 &eq->xscom_regs); 1377 } 1378 } 1379 1380 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1381 { 1382 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1383 int i, j; 1384 int phb_id = 0; 1385 1386 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1387 PnvPhb4PecState *pec = &chip9->pecs[i]; 1388 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1389 uint32_t pec_nest_base; 1390 uint32_t pec_pci_base; 1391 1392 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1393 /* 1394 * PEC0 -> 1 stack 1395 * PEC1 -> 2 stacks 1396 * PEC2 -> 3 stacks 1397 */ 1398 object_property_set_int(OBJECT(pec), "num-stacks", i + 1, 1399 &error_fatal); 1400 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1401 &error_fatal); 1402 object_property_set_link(OBJECT(pec), "system-memory", 1403 OBJECT(get_system_memory()), &error_abort); 1404 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1405 return; 1406 } 1407 1408 pec_nest_base = pecc->xscom_nest_base(pec); 1409 pec_pci_base = pecc->xscom_pci_base(pec); 1410 1411 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1412 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1413 1414 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1415 j++, phb_id++) { 1416 PnvPhb4PecStack *stack = &pec->stacks[j]; 1417 Object *obj = OBJECT(&stack->phb); 1418 1419 object_property_set_int(obj, "index", phb_id, &error_fatal); 1420 object_property_set_int(obj, "chip-id", chip->chip_id, 1421 &error_fatal); 1422 object_property_set_int(obj, "version", PNV_PHB4_VERSION, 1423 &error_fatal); 1424 object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID, 1425 &error_fatal); 1426 object_property_set_link(obj, "stack", OBJECT(stack), 1427 &error_abort); 1428 if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) { 1429 return; 1430 } 1431 1432 /* Populate the XSCOM address space. */ 1433 pnv_xscom_add_subregion(chip, 1434 pec_nest_base + 0x40 * (stack->stack_no + 1), 1435 &stack->nest_regs_mr); 1436 pnv_xscom_add_subregion(chip, 1437 pec_pci_base + 0x40 * (stack->stack_no + 1), 1438 &stack->pci_regs_mr); 1439 pnv_xscom_add_subregion(chip, 1440 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1441 0x40 * stack->stack_no, 1442 &stack->phb_regs_mr); 1443 } 1444 } 1445 } 1446 1447 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1448 { 1449 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1450 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1451 PnvChip *chip = PNV_CHIP(dev); 1452 Pnv9Psi *psi9 = &chip9->psi; 1453 Error *local_err = NULL; 1454 1455 /* XSCOM bridge is first */ 1456 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1457 if (local_err) { 1458 error_propagate(errp, local_err); 1459 return; 1460 } 1461 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1462 1463 pcc->parent_realize(dev, &local_err); 1464 if (local_err) { 1465 error_propagate(errp, local_err); 1466 return; 1467 } 1468 1469 pnv_chip_quad_realize(chip9, &local_err); 1470 if (local_err) { 1471 error_propagate(errp, local_err); 1472 return; 1473 } 1474 1475 /* XIVE interrupt controller (POWER9) */ 1476 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1477 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1478 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1479 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1480 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1481 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1482 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1483 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1484 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1485 &error_abort); 1486 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1487 return; 1488 } 1489 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1490 &chip9->xive.xscom_regs); 1491 1492 /* Processor Service Interface (PSI) Host Bridge */ 1493 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1494 &error_fatal); 1495 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1496 return; 1497 } 1498 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1499 &PNV_PSI(psi9)->xscom_regs); 1500 1501 /* LPC */ 1502 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi), 1503 &error_abort); 1504 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1505 return; 1506 } 1507 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1508 &chip9->lpc.xscom_regs); 1509 1510 chip->fw_mr = &chip9->lpc.isa_fw; 1511 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1512 (uint64_t) PNV9_LPCM_BASE(chip)); 1513 1514 /* Create the simplified OCC model */ 1515 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi), 1516 &error_abort); 1517 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1518 return; 1519 } 1520 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1521 1522 /* OCC SRAM model */ 1523 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1524 &chip9->occ.sram_regs); 1525 1526 /* HOMER */ 1527 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1528 &error_abort); 1529 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1530 return; 1531 } 1532 /* Homer Xscom region */ 1533 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1534 1535 /* Homer mmio region */ 1536 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1537 &chip9->homer.regs); 1538 1539 /* PHBs */ 1540 pnv_chip_power9_phb_realize(chip, &local_err); 1541 if (local_err) { 1542 error_propagate(errp, local_err); 1543 return; 1544 } 1545 } 1546 1547 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1548 { 1549 addr &= (PNV9_XSCOM_SIZE - 1); 1550 return addr >> 3; 1551 } 1552 1553 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1554 { 1555 DeviceClass *dc = DEVICE_CLASS(klass); 1556 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1557 1558 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1559 k->cores_mask = POWER9_CORE_MASK; 1560 k->core_pir = pnv_chip_core_pir_p9; 1561 k->intc_create = pnv_chip_power9_intc_create; 1562 k->intc_reset = pnv_chip_power9_intc_reset; 1563 k->intc_destroy = pnv_chip_power9_intc_destroy; 1564 k->intc_print_info = pnv_chip_power9_intc_print_info; 1565 k->isa_create = pnv_chip_power9_isa_create; 1566 k->dt_populate = pnv_chip_power9_dt_populate; 1567 k->pic_print_info = pnv_chip_power9_pic_print_info; 1568 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1569 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1570 dc->desc = "PowerNV Chip POWER9"; 1571 k->num_phbs = 6; 1572 1573 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1574 &k->parent_realize); 1575 } 1576 1577 static void pnv_chip_power10_instance_init(Object *obj) 1578 { 1579 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1580 1581 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1582 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1583 } 1584 1585 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1586 { 1587 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1588 PnvChip *chip = PNV_CHIP(dev); 1589 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1590 Error *local_err = NULL; 1591 1592 /* XSCOM bridge is first */ 1593 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1594 if (local_err) { 1595 error_propagate(errp, local_err); 1596 return; 1597 } 1598 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1599 1600 pcc->parent_realize(dev, &local_err); 1601 if (local_err) { 1602 error_propagate(errp, local_err); 1603 return; 1604 } 1605 1606 /* Processor Service Interface (PSI) Host Bridge */ 1607 object_property_set_int(OBJECT(&chip10->psi), "bar", 1608 PNV10_PSIHB_BASE(chip), &error_fatal); 1609 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1610 return; 1611 } 1612 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1613 &PNV_PSI(&chip10->psi)->xscom_regs); 1614 1615 /* LPC */ 1616 object_property_set_link(OBJECT(&chip10->lpc), "psi", 1617 OBJECT(&chip10->psi), &error_abort); 1618 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1619 return; 1620 } 1621 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1622 &chip10->lpc.xscom_regs); 1623 1624 chip->fw_mr = &chip10->lpc.isa_fw; 1625 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1626 (uint64_t) PNV10_LPCM_BASE(chip)); 1627 } 1628 1629 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1630 { 1631 addr &= (PNV10_XSCOM_SIZE - 1); 1632 return addr >> 3; 1633 } 1634 1635 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1636 { 1637 DeviceClass *dc = DEVICE_CLASS(klass); 1638 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1639 1640 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1641 k->cores_mask = POWER10_CORE_MASK; 1642 k->core_pir = pnv_chip_core_pir_p10; 1643 k->intc_create = pnv_chip_power10_intc_create; 1644 k->intc_reset = pnv_chip_power10_intc_reset; 1645 k->intc_destroy = pnv_chip_power10_intc_destroy; 1646 k->intc_print_info = pnv_chip_power10_intc_print_info; 1647 k->isa_create = pnv_chip_power10_isa_create; 1648 k->dt_populate = pnv_chip_power10_dt_populate; 1649 k->pic_print_info = pnv_chip_power10_pic_print_info; 1650 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1651 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1652 dc->desc = "PowerNV Chip POWER10"; 1653 1654 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1655 &k->parent_realize); 1656 } 1657 1658 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1659 { 1660 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1661 int cores_max; 1662 1663 /* 1664 * No custom mask for this chip, let's use the default one from * 1665 * the chip class 1666 */ 1667 if (!chip->cores_mask) { 1668 chip->cores_mask = pcc->cores_mask; 1669 } 1670 1671 /* filter alien core ids ! some are reserved */ 1672 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1673 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1674 chip->cores_mask); 1675 return; 1676 } 1677 chip->cores_mask &= pcc->cores_mask; 1678 1679 /* now that we have a sane layout, let check the number of cores */ 1680 cores_max = ctpop64(chip->cores_mask); 1681 if (chip->nr_cores > cores_max) { 1682 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1683 cores_max); 1684 return; 1685 } 1686 } 1687 1688 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1689 { 1690 Error *error = NULL; 1691 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1692 const char *typename = pnv_chip_core_typename(chip); 1693 int i, core_hwid; 1694 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1695 1696 if (!object_class_by_name(typename)) { 1697 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1698 return; 1699 } 1700 1701 /* Cores */ 1702 pnv_chip_core_sanitize(chip, &error); 1703 if (error) { 1704 error_propagate(errp, error); 1705 return; 1706 } 1707 1708 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1709 1710 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1711 && (i < chip->nr_cores); core_hwid++) { 1712 char core_name[32]; 1713 PnvCore *pnv_core; 1714 uint64_t xscom_core_base; 1715 1716 if (!(chip->cores_mask & (1ull << core_hwid))) { 1717 continue; 1718 } 1719 1720 pnv_core = PNV_CORE(object_new(typename)); 1721 1722 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1723 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1724 chip->cores[i] = pnv_core; 1725 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1726 chip->nr_threads, &error_fatal); 1727 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1728 core_hwid, &error_fatal); 1729 object_property_set_int(OBJECT(pnv_core), "pir", 1730 pcc->core_pir(chip, core_hwid), &error_fatal); 1731 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1732 &error_fatal); 1733 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1734 &error_abort); 1735 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1736 1737 /* Each core has an XSCOM MMIO region */ 1738 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1739 1740 pnv_xscom_add_subregion(chip, xscom_core_base, 1741 &pnv_core->xscom_regs); 1742 i++; 1743 } 1744 } 1745 1746 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1747 { 1748 PnvChip *chip = PNV_CHIP(dev); 1749 Error *error = NULL; 1750 1751 /* Cores */ 1752 pnv_chip_core_realize(chip, &error); 1753 if (error) { 1754 error_propagate(errp, error); 1755 return; 1756 } 1757 } 1758 1759 static Property pnv_chip_properties[] = { 1760 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1761 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1762 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1763 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1764 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1765 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1766 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1767 DEFINE_PROP_END_OF_LIST(), 1768 }; 1769 1770 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1771 { 1772 DeviceClass *dc = DEVICE_CLASS(klass); 1773 1774 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1775 dc->realize = pnv_chip_realize; 1776 device_class_set_props(dc, pnv_chip_properties); 1777 dc->desc = "PowerNV Chip"; 1778 } 1779 1780 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1781 { 1782 int i, j; 1783 1784 for (i = 0; i < chip->nr_cores; i++) { 1785 PnvCore *pc = chip->cores[i]; 1786 CPUCore *cc = CPU_CORE(pc); 1787 1788 for (j = 0; j < cc->nr_threads; j++) { 1789 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1790 return pc->threads[j]; 1791 } 1792 } 1793 } 1794 return NULL; 1795 } 1796 1797 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1798 { 1799 PnvMachineState *pnv = PNV_MACHINE(xi); 1800 int i, j; 1801 1802 for (i = 0; i < pnv->num_chips; i++) { 1803 PnvChip *chip = pnv->chips[i]; 1804 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1805 1806 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1807 return &chip8->psi.ics; 1808 } 1809 for (j = 0; j < chip->num_phbs; j++) { 1810 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1811 return &chip8->phbs[j].lsis; 1812 } 1813 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1814 return ICS(&chip8->phbs[j].msis); 1815 } 1816 } 1817 } 1818 return NULL; 1819 } 1820 1821 static void pnv_ics_resend(XICSFabric *xi) 1822 { 1823 PnvMachineState *pnv = PNV_MACHINE(xi); 1824 int i, j; 1825 1826 for (i = 0; i < pnv->num_chips; i++) { 1827 PnvChip *chip = pnv->chips[i]; 1828 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1829 1830 ics_resend(&chip8->psi.ics); 1831 for (j = 0; j < chip->num_phbs; j++) { 1832 ics_resend(&chip8->phbs[j].lsis); 1833 ics_resend(ICS(&chip8->phbs[j].msis)); 1834 } 1835 } 1836 } 1837 1838 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1839 { 1840 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1841 1842 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1843 } 1844 1845 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1846 Monitor *mon) 1847 { 1848 PnvMachineState *pnv = PNV_MACHINE(obj); 1849 int i; 1850 CPUState *cs; 1851 1852 CPU_FOREACH(cs) { 1853 PowerPCCPU *cpu = POWERPC_CPU(cs); 1854 1855 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1856 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1857 mon); 1858 } 1859 1860 for (i = 0; i < pnv->num_chips; i++) { 1861 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1862 } 1863 } 1864 1865 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1866 uint8_t nvt_blk, uint32_t nvt_idx, 1867 bool cam_ignore, uint8_t priority, 1868 uint32_t logic_serv, 1869 XiveTCTXMatch *match) 1870 { 1871 PnvMachineState *pnv = PNV_MACHINE(xfb); 1872 int total_count = 0; 1873 int i; 1874 1875 for (i = 0; i < pnv->num_chips; i++) { 1876 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1877 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1878 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1879 int count; 1880 1881 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1882 priority, logic_serv, match); 1883 1884 if (count < 0) { 1885 return count; 1886 } 1887 1888 total_count += count; 1889 } 1890 1891 return total_count; 1892 } 1893 1894 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1895 { 1896 MachineClass *mc = MACHINE_CLASS(oc); 1897 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1898 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1899 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1900 1901 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1902 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1903 1904 xic->icp_get = pnv_icp_get; 1905 xic->ics_get = pnv_ics_get; 1906 xic->ics_resend = pnv_ics_resend; 1907 1908 pmc->compat = compat; 1909 pmc->compat_size = sizeof(compat); 1910 } 1911 1912 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1913 { 1914 MachineClass *mc = MACHINE_CLASS(oc); 1915 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1916 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1917 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1918 1919 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1920 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1921 xfc->match_nvt = pnv_match_nvt; 1922 1923 mc->alias = "powernv"; 1924 1925 pmc->compat = compat; 1926 pmc->compat_size = sizeof(compat); 1927 pmc->dt_power_mgt = pnv_dt_power_mgt; 1928 } 1929 1930 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1931 { 1932 MachineClass *mc = MACHINE_CLASS(oc); 1933 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1934 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1935 1936 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1937 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 1938 1939 pmc->compat = compat; 1940 pmc->compat_size = sizeof(compat); 1941 pmc->dt_power_mgt = pnv_dt_power_mgt; 1942 } 1943 1944 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1945 { 1946 PnvMachineState *pnv = PNV_MACHINE(obj); 1947 1948 return !!pnv->fw_load_addr; 1949 } 1950 1951 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1952 { 1953 PnvMachineState *pnv = PNV_MACHINE(obj); 1954 1955 if (value) { 1956 pnv->fw_load_addr = 0x8000000; 1957 } 1958 } 1959 1960 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 1961 { 1962 PowerPCCPU *cpu = POWERPC_CPU(cs); 1963 CPUPPCState *env = &cpu->env; 1964 1965 cpu_synchronize_state(cs); 1966 ppc_cpu_do_system_reset(cs); 1967 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 1968 /* 1969 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 1970 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 1971 * (PPC_BIT(43)). 1972 */ 1973 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 1974 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 1975 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 1976 } 1977 } else { 1978 /* 1979 * For non-powersave system resets, SRR1[42:45] are defined to be 1980 * implementation-dependent. The POWER9 User Manual specifies that 1981 * an external (SCOM driven, which may come from a BMC nmi command or 1982 * another CPU requesting a NMI IPI) system reset exception should be 1983 * 0b0010 (PPC_BIT(44)). 1984 */ 1985 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 1986 } 1987 } 1988 1989 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 1990 { 1991 CPUState *cs; 1992 1993 CPU_FOREACH(cs) { 1994 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 1995 } 1996 } 1997 1998 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1999 { 2000 MachineClass *mc = MACHINE_CLASS(oc); 2001 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2002 NMIClass *nc = NMI_CLASS(oc); 2003 2004 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2005 mc->init = pnv_init; 2006 mc->reset = pnv_reset; 2007 mc->max_cpus = MAX_CPUS; 2008 /* Pnv provides a AHCI device for storage */ 2009 mc->block_default_type = IF_IDE; 2010 mc->no_parallel = 1; 2011 mc->default_boot_order = NULL; 2012 /* 2013 * RAM defaults to less than 2048 for 32-bit hosts, and large 2014 * enough to fit the maximum initrd size at it's load address 2015 */ 2016 mc->default_ram_size = 1 * GiB; 2017 mc->default_ram_id = "pnv.ram"; 2018 ispc->print_info = pnv_pic_print_info; 2019 nc->nmi_monitor_handler = pnv_nmi; 2020 2021 object_class_property_add_bool(oc, "hb-mode", 2022 pnv_machine_get_hb, pnv_machine_set_hb); 2023 object_class_property_set_description(oc, "hb-mode", 2024 "Use a hostboot like boot loader"); 2025 } 2026 2027 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2028 { \ 2029 .name = type, \ 2030 .class_init = class_initfn, \ 2031 .parent = TYPE_PNV8_CHIP, \ 2032 } 2033 2034 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2035 { \ 2036 .name = type, \ 2037 .class_init = class_initfn, \ 2038 .parent = TYPE_PNV9_CHIP, \ 2039 } 2040 2041 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2042 { \ 2043 .name = type, \ 2044 .class_init = class_initfn, \ 2045 .parent = TYPE_PNV10_CHIP, \ 2046 } 2047 2048 static const TypeInfo types[] = { 2049 { 2050 .name = MACHINE_TYPE_NAME("powernv10"), 2051 .parent = TYPE_PNV_MACHINE, 2052 .class_init = pnv_machine_power10_class_init, 2053 }, 2054 { 2055 .name = MACHINE_TYPE_NAME("powernv9"), 2056 .parent = TYPE_PNV_MACHINE, 2057 .class_init = pnv_machine_power9_class_init, 2058 .interfaces = (InterfaceInfo[]) { 2059 { TYPE_XIVE_FABRIC }, 2060 { }, 2061 }, 2062 }, 2063 { 2064 .name = MACHINE_TYPE_NAME("powernv8"), 2065 .parent = TYPE_PNV_MACHINE, 2066 .class_init = pnv_machine_power8_class_init, 2067 .interfaces = (InterfaceInfo[]) { 2068 { TYPE_XICS_FABRIC }, 2069 { }, 2070 }, 2071 }, 2072 { 2073 .name = TYPE_PNV_MACHINE, 2074 .parent = TYPE_MACHINE, 2075 .abstract = true, 2076 .instance_size = sizeof(PnvMachineState), 2077 .class_init = pnv_machine_class_init, 2078 .class_size = sizeof(PnvMachineClass), 2079 .interfaces = (InterfaceInfo[]) { 2080 { TYPE_INTERRUPT_STATS_PROVIDER }, 2081 { TYPE_NMI }, 2082 { }, 2083 }, 2084 }, 2085 { 2086 .name = TYPE_PNV_CHIP, 2087 .parent = TYPE_SYS_BUS_DEVICE, 2088 .class_init = pnv_chip_class_init, 2089 .instance_size = sizeof(PnvChip), 2090 .class_size = sizeof(PnvChipClass), 2091 .abstract = true, 2092 }, 2093 2094 /* 2095 * P10 chip and variants 2096 */ 2097 { 2098 .name = TYPE_PNV10_CHIP, 2099 .parent = TYPE_PNV_CHIP, 2100 .instance_init = pnv_chip_power10_instance_init, 2101 .instance_size = sizeof(Pnv10Chip), 2102 }, 2103 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2104 2105 /* 2106 * P9 chip and variants 2107 */ 2108 { 2109 .name = TYPE_PNV9_CHIP, 2110 .parent = TYPE_PNV_CHIP, 2111 .instance_init = pnv_chip_power9_instance_init, 2112 .instance_size = sizeof(Pnv9Chip), 2113 }, 2114 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2115 2116 /* 2117 * P8 chip and variants 2118 */ 2119 { 2120 .name = TYPE_PNV8_CHIP, 2121 .parent = TYPE_PNV_CHIP, 2122 .instance_init = pnv_chip_power8_instance_init, 2123 .instance_size = sizeof(Pnv8Chip), 2124 }, 2125 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2126 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2127 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2128 pnv_chip_power8nvl_class_init), 2129 }; 2130 2131 DEFINE_TYPES(types) 2132