1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/cpus.h" 27 #include "sysemu/device_tree.h" 28 #include "hw/hw.h" 29 #include "target/ppc/cpu.h" 30 #include "qemu/log.h" 31 #include "hw/ppc/fdt.h" 32 #include "hw/ppc/ppc.h" 33 #include "hw/ppc/pnv.h" 34 #include "hw/ppc/pnv_core.h" 35 #include "hw/loader.h" 36 #include "exec/address-spaces.h" 37 #include "qapi/visitor.h" 38 #include "monitor/monitor.h" 39 #include "hw/intc/intc.h" 40 #include "hw/ipmi/ipmi.h" 41 #include "target/ppc/mmu-hash64.h" 42 43 #include "hw/ppc/xics.h" 44 #include "hw/ppc/pnv_xscom.h" 45 46 #include "hw/isa/isa.h" 47 #include "hw/char/serial.h" 48 #include "hw/timer/mc146818rtc.h" 49 50 #include <libfdt.h> 51 52 #define FDT_MAX_SIZE (1 * MiB) 53 54 #define FW_FILE_NAME "skiboot.lid" 55 #define FW_LOAD_ADDR 0x0 56 #define FW_MAX_SIZE (4 * MiB) 57 58 #define KERNEL_LOAD_ADDR 0x20000000 59 #define KERNEL_MAX_SIZE (256 * MiB) 60 #define INITRD_LOAD_ADDR 0x60000000 61 #define INITRD_MAX_SIZE (256 * MiB) 62 63 static const char *pnv_chip_core_typename(const PnvChip *o) 64 { 65 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 66 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 67 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 68 const char *core_type = object_class_get_name(object_class_by_name(s)); 69 g_free(s); 70 return core_type; 71 } 72 73 /* 74 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 75 * 4 * 4 sockets * 12 cores * 8 threads = 1536 76 * Let's make it 2^11 77 */ 78 #define MAX_CPUS 2048 79 80 /* 81 * Memory nodes are created by hostboot, one for each range of memory 82 * that has a different "affinity". In practice, it means one range 83 * per chip. 84 */ 85 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 86 { 87 char *mem_name; 88 uint64_t mem_reg_property[2]; 89 int off; 90 91 mem_reg_property[0] = cpu_to_be64(start); 92 mem_reg_property[1] = cpu_to_be64(size); 93 94 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 95 off = fdt_add_subnode(fdt, 0, mem_name); 96 g_free(mem_name); 97 98 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 99 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 100 sizeof(mem_reg_property)))); 101 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 102 } 103 104 static int get_cpus_node(void *fdt) 105 { 106 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 107 108 if (cpus_offset < 0) { 109 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 110 if (cpus_offset) { 111 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 112 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 113 } 114 } 115 _FDT(cpus_offset); 116 return cpus_offset; 117 } 118 119 /* 120 * The PowerNV cores (and threads) need to use real HW ids and not an 121 * incremental index like it has been done on other platforms. This HW 122 * id is stored in the CPU PIR, it is used to create cpu nodes in the 123 * device tree, used in XSCOM to address cores and in interrupt 124 * servers. 125 */ 126 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 127 { 128 PowerPCCPU *cpu = pc->threads[0]; 129 CPUState *cs = CPU(cpu); 130 DeviceClass *dc = DEVICE_GET_CLASS(cs); 131 int smt_threads = CPU_CORE(pc)->nr_threads; 132 CPUPPCState *env = &cpu->env; 133 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 134 uint32_t servers_prop[smt_threads]; 135 int i; 136 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 137 0xffffffff, 0xffffffff}; 138 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 139 uint32_t cpufreq = 1000000000; 140 uint32_t page_sizes_prop[64]; 141 size_t page_sizes_prop_size; 142 const uint8_t pa_features[] = { 24, 0, 143 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 144 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 145 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 146 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 147 int offset; 148 char *nodename; 149 int cpus_offset = get_cpus_node(fdt); 150 151 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 152 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 153 _FDT(offset); 154 g_free(nodename); 155 156 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 157 158 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 159 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 160 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 161 162 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 163 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 164 env->dcache_line_size))); 165 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 166 env->dcache_line_size))); 167 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 168 env->icache_line_size))); 169 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 170 env->icache_line_size))); 171 172 if (pcc->l1_dcache_size) { 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 174 pcc->l1_dcache_size))); 175 } else { 176 warn_report("Unknown L1 dcache size for cpu"); 177 } 178 if (pcc->l1_icache_size) { 179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 180 pcc->l1_icache_size))); 181 } else { 182 warn_report("Unknown L1 icache size for cpu"); 183 } 184 185 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 186 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 187 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 188 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 189 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 190 191 if (env->spr_cb[SPR_PURR].oea_read) { 192 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 193 } 194 195 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 196 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 197 segs, sizeof(segs)))); 198 } 199 200 /* Advertise VMX/VSX (vector extensions) if available 201 * 0 / no property == no vector extensions 202 * 1 == VMX / Altivec available 203 * 2 == VSX available */ 204 if (env->insns_flags & PPC_ALTIVEC) { 205 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 206 207 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 208 } 209 210 /* Advertise DFP (Decimal Floating Point) if available 211 * 0 / no property == no DFP 212 * 1 == DFP available */ 213 if (env->insns_flags2 & PPC2_DFP) { 214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 215 } 216 217 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 218 sizeof(page_sizes_prop)); 219 if (page_sizes_prop_size) { 220 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 221 page_sizes_prop, page_sizes_prop_size))); 222 } 223 224 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 225 pa_features, sizeof(pa_features)))); 226 227 /* Build interrupt servers properties */ 228 for (i = 0; i < smt_threads; i++) { 229 servers_prop[i] = cpu_to_be32(pc->pir + i); 230 } 231 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 232 servers_prop, sizeof(servers_prop)))); 233 } 234 235 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 236 uint32_t nr_threads) 237 { 238 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 239 char *name; 240 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 241 uint32_t irange[2], i, rsize; 242 uint64_t *reg; 243 int offset; 244 245 irange[0] = cpu_to_be32(pir); 246 irange[1] = cpu_to_be32(nr_threads); 247 248 rsize = sizeof(uint64_t) * 2 * nr_threads; 249 reg = g_malloc(rsize); 250 for (i = 0; i < nr_threads; i++) { 251 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 252 reg[i * 2 + 1] = cpu_to_be64(0x1000); 253 } 254 255 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 256 offset = fdt_add_subnode(fdt, 0, name); 257 _FDT(offset); 258 g_free(name); 259 260 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 261 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 262 _FDT((fdt_setprop_string(fdt, offset, "device_type", 263 "PowerPC-External-Interrupt-Presentation"))); 264 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 265 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 266 irange, sizeof(irange)))); 267 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 268 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 269 g_free(reg); 270 } 271 272 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 273 { 274 const char *typename = pnv_chip_core_typename(chip); 275 size_t typesize = object_type_get_instance_size(typename); 276 int i; 277 278 pnv_dt_xscom(chip, fdt, 0); 279 280 for (i = 0; i < chip->nr_cores; i++) { 281 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 282 283 pnv_dt_core(chip, pnv_core, fdt); 284 285 /* Interrupt Control Presenters (ICP). One per core. */ 286 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 287 } 288 289 if (chip->ram_size) { 290 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 291 } 292 } 293 294 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 295 { 296 const char *typename = pnv_chip_core_typename(chip); 297 size_t typesize = object_type_get_instance_size(typename); 298 int i; 299 300 pnv_dt_xscom(chip, fdt, 0); 301 302 for (i = 0; i < chip->nr_cores; i++) { 303 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 304 305 pnv_dt_core(chip, pnv_core, fdt); 306 } 307 308 if (chip->ram_size) { 309 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 310 } 311 312 pnv_dt_lpc(chip, fdt, 0); 313 } 314 315 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 316 { 317 uint32_t io_base = d->ioport_id; 318 uint32_t io_regs[] = { 319 cpu_to_be32(1), 320 cpu_to_be32(io_base), 321 cpu_to_be32(2) 322 }; 323 char *name; 324 int node; 325 326 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 327 node = fdt_add_subnode(fdt, lpc_off, name); 328 _FDT(node); 329 g_free(name); 330 331 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 332 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 333 } 334 335 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 336 { 337 const char compatible[] = "ns16550\0pnpPNP,501"; 338 uint32_t io_base = d->ioport_id; 339 uint32_t io_regs[] = { 340 cpu_to_be32(1), 341 cpu_to_be32(io_base), 342 cpu_to_be32(8) 343 }; 344 char *name; 345 int node; 346 347 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 348 node = fdt_add_subnode(fdt, lpc_off, name); 349 _FDT(node); 350 g_free(name); 351 352 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 353 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 354 sizeof(compatible)))); 355 356 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 357 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 358 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 359 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 360 fdt_get_phandle(fdt, lpc_off)))); 361 362 /* This is needed by Linux */ 363 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 364 } 365 366 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 367 { 368 const char compatible[] = "bt\0ipmi-bt"; 369 uint32_t io_base; 370 uint32_t io_regs[] = { 371 cpu_to_be32(1), 372 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 373 cpu_to_be32(3) 374 }; 375 uint32_t irq; 376 char *name; 377 int node; 378 379 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 380 io_regs[1] = cpu_to_be32(io_base); 381 382 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 383 384 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 385 node = fdt_add_subnode(fdt, lpc_off, name); 386 _FDT(node); 387 g_free(name); 388 389 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 390 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 391 sizeof(compatible)))); 392 393 /* Mark it as reserved to avoid Linux trying to claim it */ 394 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 395 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 396 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 397 fdt_get_phandle(fdt, lpc_off)))); 398 } 399 400 typedef struct ForeachPopulateArgs { 401 void *fdt; 402 int offset; 403 } ForeachPopulateArgs; 404 405 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 406 { 407 ForeachPopulateArgs *args = opaque; 408 ISADevice *d = ISA_DEVICE(dev); 409 410 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 411 pnv_dt_rtc(d, args->fdt, args->offset); 412 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 413 pnv_dt_serial(d, args->fdt, args->offset); 414 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 415 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 416 } else { 417 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 418 d->ioport_id); 419 } 420 421 return 0; 422 } 423 424 /* The default LPC bus of a multichip system is on chip 0. It's 425 * recognized by the firmware (skiboot) using a "primary" property. 426 */ 427 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 428 { 429 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 430 ForeachPopulateArgs args = { 431 .fdt = fdt, 432 .offset = isa_offset, 433 }; 434 435 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 436 437 /* ISA devices are not necessarily parented to the ISA bus so we 438 * can not use object_child_foreach() */ 439 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 440 &args); 441 } 442 443 static void pnv_dt_power_mgt(void *fdt) 444 { 445 int off; 446 447 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 448 off = fdt_add_subnode(fdt, off, "power-mgt"); 449 450 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 451 } 452 453 static void *pnv_dt_create(MachineState *machine) 454 { 455 const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 456 const char plat_compat9[] = "qemu,powernv9\0ibm,powernv"; 457 PnvMachineState *pnv = PNV_MACHINE(machine); 458 void *fdt; 459 char *buf; 460 int off; 461 int i; 462 463 fdt = g_malloc0(FDT_MAX_SIZE); 464 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 465 466 /* Root node */ 467 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 468 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 469 _FDT((fdt_setprop_string(fdt, 0, "model", 470 "IBM PowerNV (emulated by qemu)"))); 471 if (pnv_is_power9(pnv)) { 472 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, 473 sizeof(plat_compat9)))); 474 } else { 475 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8, 476 sizeof(plat_compat8)))); 477 } 478 479 480 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 481 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 482 if (qemu_uuid_set) { 483 _FDT((fdt_property_string(fdt, "system-id", buf))); 484 } 485 g_free(buf); 486 487 off = fdt_add_subnode(fdt, 0, "chosen"); 488 if (machine->kernel_cmdline) { 489 _FDT((fdt_setprop_string(fdt, off, "bootargs", 490 machine->kernel_cmdline))); 491 } 492 493 if (pnv->initrd_size) { 494 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 495 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 496 497 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 498 &start_prop, sizeof(start_prop)))); 499 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 500 &end_prop, sizeof(end_prop)))); 501 } 502 503 /* Populate device tree for each chip */ 504 for (i = 0; i < pnv->num_chips; i++) { 505 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 506 } 507 508 /* Populate ISA devices on chip 0 */ 509 pnv_dt_isa(pnv, fdt); 510 511 if (pnv->bmc) { 512 pnv_dt_bmc_sensors(pnv->bmc, fdt); 513 } 514 515 /* Create an extra node for power management on Power9 */ 516 if (pnv_is_power9(pnv)) { 517 pnv_dt_power_mgt(fdt); 518 } 519 520 return fdt; 521 } 522 523 static void pnv_powerdown_notify(Notifier *n, void *opaque) 524 { 525 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 526 527 if (pnv->bmc) { 528 pnv_bmc_powerdown(pnv->bmc); 529 } 530 } 531 532 static void pnv_reset(MachineState *machine) 533 { 534 PnvMachineState *pnv = PNV_MACHINE(machine); 535 void *fdt; 536 Object *obj; 537 538 qemu_devices_reset(); 539 540 /* OpenPOWER systems have a BMC, which can be defined on the 541 * command line with: 542 * 543 * -device ipmi-bmc-sim,id=bmc0 544 * 545 * This is the internal simulator but it could also be an external 546 * BMC. 547 */ 548 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); 549 if (obj) { 550 pnv->bmc = IPMI_BMC(obj); 551 } 552 553 fdt = pnv_dt_create(machine); 554 555 /* Pack resulting tree */ 556 _FDT((fdt_pack(fdt))); 557 558 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 559 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 560 } 561 562 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 563 { 564 Pnv8Chip *chip8 = PNV8_CHIP(chip); 565 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 566 } 567 568 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 569 { 570 Pnv8Chip *chip8 = PNV8_CHIP(chip); 571 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 572 } 573 574 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 575 { 576 Pnv9Chip *chip9 = PNV9_CHIP(chip); 577 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 578 } 579 580 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 581 { 582 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 583 } 584 585 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 586 { 587 Pnv8Chip *chip8 = PNV8_CHIP(chip); 588 589 ics_pic_print_info(&chip8->psi.ics, mon); 590 } 591 592 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 593 { 594 Pnv9Chip *chip9 = PNV9_CHIP(chip); 595 596 pnv_xive_pic_print_info(&chip9->xive, mon); 597 pnv_psi_pic_print_info(&chip9->psi, mon); 598 } 599 600 static void pnv_init(MachineState *machine) 601 { 602 PnvMachineState *pnv = PNV_MACHINE(machine); 603 MemoryRegion *ram; 604 char *fw_filename; 605 long fw_size; 606 int i; 607 char *chip_typename; 608 609 /* allocate RAM */ 610 if (machine->ram_size < (1 * GiB)) { 611 warn_report("skiboot may not work with < 1GB of RAM"); 612 } 613 614 ram = g_new(MemoryRegion, 1); 615 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 616 machine->ram_size); 617 memory_region_add_subregion(get_system_memory(), 0, ram); 618 619 /* load skiboot firmware */ 620 if (bios_name == NULL) { 621 bios_name = FW_FILE_NAME; 622 } 623 624 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 625 if (!fw_filename) { 626 error_report("Could not find OPAL firmware '%s'", bios_name); 627 exit(1); 628 } 629 630 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 631 if (fw_size < 0) { 632 error_report("Could not load OPAL firmware '%s'", fw_filename); 633 exit(1); 634 } 635 g_free(fw_filename); 636 637 /* load kernel */ 638 if (machine->kernel_filename) { 639 long kernel_size; 640 641 kernel_size = load_image_targphys(machine->kernel_filename, 642 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 643 if (kernel_size < 0) { 644 error_report("Could not load kernel '%s'", 645 machine->kernel_filename); 646 exit(1); 647 } 648 } 649 650 /* load initrd */ 651 if (machine->initrd_filename) { 652 pnv->initrd_base = INITRD_LOAD_ADDR; 653 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 654 pnv->initrd_base, INITRD_MAX_SIZE); 655 if (pnv->initrd_size < 0) { 656 error_report("Could not load initial ram disk '%s'", 657 machine->initrd_filename); 658 exit(1); 659 } 660 } 661 662 /* Create the processor chips */ 663 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 664 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 665 i, machine->cpu_type); 666 if (!object_class_by_name(chip_typename)) { 667 error_report("invalid CPU model '%.*s' for %s machine", 668 i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name); 669 exit(1); 670 } 671 672 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 673 for (i = 0; i < pnv->num_chips; i++) { 674 char chip_name[32]; 675 Object *chip = object_new(chip_typename); 676 677 pnv->chips[i] = PNV_CHIP(chip); 678 679 /* TODO: put all the memory in one node on chip 0 until we find a 680 * way to specify different ranges for each chip 681 */ 682 if (i == 0) { 683 object_property_set_int(chip, machine->ram_size, "ram-size", 684 &error_fatal); 685 } 686 687 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 688 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 689 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 690 &error_fatal); 691 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal); 692 object_property_set_bool(chip, true, "realized", &error_fatal); 693 } 694 g_free(chip_typename); 695 696 /* Instantiate ISA bus on chip 0 */ 697 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 698 699 /* Create serial port */ 700 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 701 702 /* Create an RTC ISA device too */ 703 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 704 705 /* OpenPOWER systems use a IPMI SEL Event message to notify the 706 * host to powerdown */ 707 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 708 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 709 } 710 711 /* 712 * 0:21 Reserved - Read as zeros 713 * 22:24 Chip ID 714 * 25:28 Core number 715 * 29:31 Thread ID 716 */ 717 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 718 { 719 return (chip->chip_id << 7) | (core_id << 3); 720 } 721 722 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 723 Error **errp) 724 { 725 Error *local_err = NULL; 726 Object *obj; 727 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 728 729 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 730 &local_err); 731 if (local_err) { 732 error_propagate(errp, local_err); 733 return; 734 } 735 736 pnv_cpu->intc = obj; 737 } 738 739 /* 740 * 0:48 Reserved - Read as zeroes 741 * 49:52 Node ID 742 * 53:55 Chip ID 743 * 56 Reserved - Read as zero 744 * 57:61 Core number 745 * 62:63 Thread ID 746 * 747 * We only care about the lower bits. uint32_t is fine for the moment. 748 */ 749 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 750 { 751 return (chip->chip_id << 8) | (core_id << 2); 752 } 753 754 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 755 Error **errp) 756 { 757 Pnv9Chip *chip9 = PNV9_CHIP(chip); 758 Error *local_err = NULL; 759 Object *obj; 760 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 761 762 /* 763 * The core creates its interrupt presenter but the XIVE interrupt 764 * controller object is initialized afterwards. Hopefully, it's 765 * only used at runtime. 766 */ 767 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); 768 if (local_err) { 769 error_propagate(errp, local_err); 770 return; 771 } 772 773 pnv_cpu->intc = obj; 774 } 775 776 /* Allowed core identifiers on a POWER8 Processor Chip : 777 * 778 * <EX0 reserved> 779 * EX1 - Venice only 780 * EX2 - Venice only 781 * EX3 - Venice only 782 * EX4 783 * EX5 784 * EX6 785 * <EX7,8 reserved> <reserved> 786 * EX9 - Venice only 787 * EX10 - Venice only 788 * EX11 - Venice only 789 * EX12 790 * EX13 791 * EX14 792 * <EX15 reserved> 793 */ 794 #define POWER8E_CORE_MASK (0x7070ull) 795 #define POWER8_CORE_MASK (0x7e7eull) 796 797 /* 798 * POWER9 has 24 cores, ids starting at 0x0 799 */ 800 #define POWER9_CORE_MASK (0xffffffffffffffull) 801 802 static void pnv_chip_power8_instance_init(Object *obj) 803 { 804 Pnv8Chip *chip8 = PNV8_CHIP(obj); 805 806 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 807 TYPE_PNV8_PSI, &error_abort, NULL); 808 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 809 OBJECT(qdev_get_machine()), &error_abort); 810 811 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 812 TYPE_PNV8_LPC, &error_abort, NULL); 813 object_property_add_const_link(OBJECT(&chip8->lpc), "psi", 814 OBJECT(&chip8->psi), &error_abort); 815 816 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 817 TYPE_PNV8_OCC, &error_abort, NULL); 818 object_property_add_const_link(OBJECT(&chip8->occ), "psi", 819 OBJECT(&chip8->psi), &error_abort); 820 } 821 822 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 823 { 824 PnvChip *chip = PNV_CHIP(chip8); 825 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 826 const char *typename = pnv_chip_core_typename(chip); 827 size_t typesize = object_type_get_instance_size(typename); 828 int i, j; 829 char *name; 830 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 831 832 name = g_strdup_printf("icp-%x", chip->chip_id); 833 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 834 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 835 g_free(name); 836 837 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 838 839 /* Map the ICP registers for each thread */ 840 for (i = 0; i < chip->nr_cores; i++) { 841 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 842 int core_hwid = CPU_CORE(pnv_core)->core_id; 843 844 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 845 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 846 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 847 848 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 849 &icp->mmio); 850 } 851 } 852 } 853 854 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 855 { 856 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 857 PnvChip *chip = PNV_CHIP(dev); 858 Pnv8Chip *chip8 = PNV8_CHIP(dev); 859 Pnv8Psi *psi8 = &chip8->psi; 860 Error *local_err = NULL; 861 862 /* XSCOM bridge is first */ 863 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 864 if (local_err) { 865 error_propagate(errp, local_err); 866 return; 867 } 868 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 869 870 pcc->parent_realize(dev, &local_err); 871 if (local_err) { 872 error_propagate(errp, local_err); 873 return; 874 } 875 876 /* Processor Service Interface (PSI) Host Bridge */ 877 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 878 "bar", &error_fatal); 879 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 880 if (local_err) { 881 error_propagate(errp, local_err); 882 return; 883 } 884 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 885 &PNV_PSI(psi8)->xscom_regs); 886 887 /* Create LPC controller */ 888 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 889 &error_fatal); 890 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 891 892 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 893 (uint64_t) PNV_XSCOM_BASE(chip), 894 PNV_XSCOM_LPC_BASE); 895 896 /* Interrupt Management Area. This is the memory region holding 897 * all the Interrupt Control Presenter (ICP) registers */ 898 pnv_chip_icp_realize(chip8, &local_err); 899 if (local_err) { 900 error_propagate(errp, local_err); 901 return; 902 } 903 904 /* Create the simplified OCC model */ 905 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 906 if (local_err) { 907 error_propagate(errp, local_err); 908 return; 909 } 910 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 911 } 912 913 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 914 { 915 DeviceClass *dc = DEVICE_CLASS(klass); 916 PnvChipClass *k = PNV_CHIP_CLASS(klass); 917 918 k->chip_type = PNV_CHIP_POWER8E; 919 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 920 k->cores_mask = POWER8E_CORE_MASK; 921 k->core_pir = pnv_chip_core_pir_p8; 922 k->intc_create = pnv_chip_power8_intc_create; 923 k->isa_create = pnv_chip_power8_isa_create; 924 k->dt_populate = pnv_chip_power8_dt_populate; 925 k->pic_print_info = pnv_chip_power8_pic_print_info; 926 dc->desc = "PowerNV Chip POWER8E"; 927 928 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 929 &k->parent_realize); 930 } 931 932 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 933 { 934 DeviceClass *dc = DEVICE_CLASS(klass); 935 PnvChipClass *k = PNV_CHIP_CLASS(klass); 936 937 k->chip_type = PNV_CHIP_POWER8; 938 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 939 k->cores_mask = POWER8_CORE_MASK; 940 k->core_pir = pnv_chip_core_pir_p8; 941 k->intc_create = pnv_chip_power8_intc_create; 942 k->isa_create = pnv_chip_power8_isa_create; 943 k->dt_populate = pnv_chip_power8_dt_populate; 944 k->pic_print_info = pnv_chip_power8_pic_print_info; 945 dc->desc = "PowerNV Chip POWER8"; 946 947 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 948 &k->parent_realize); 949 } 950 951 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 952 { 953 DeviceClass *dc = DEVICE_CLASS(klass); 954 PnvChipClass *k = PNV_CHIP_CLASS(klass); 955 956 k->chip_type = PNV_CHIP_POWER8NVL; 957 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 958 k->cores_mask = POWER8_CORE_MASK; 959 k->core_pir = pnv_chip_core_pir_p8; 960 k->intc_create = pnv_chip_power8_intc_create; 961 k->isa_create = pnv_chip_power8nvl_isa_create; 962 k->dt_populate = pnv_chip_power8_dt_populate; 963 k->pic_print_info = pnv_chip_power8_pic_print_info; 964 dc->desc = "PowerNV Chip POWER8NVL"; 965 966 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 967 &k->parent_realize); 968 } 969 970 static void pnv_chip_power9_instance_init(Object *obj) 971 { 972 Pnv9Chip *chip9 = PNV9_CHIP(obj); 973 974 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 975 TYPE_PNV_XIVE, &error_abort, NULL); 976 object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj, 977 &error_abort); 978 979 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 980 TYPE_PNV9_PSI, &error_abort, NULL); 981 object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj, 982 &error_abort); 983 984 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 985 TYPE_PNV9_LPC, &error_abort, NULL); 986 object_property_add_const_link(OBJECT(&chip9->lpc), "psi", 987 OBJECT(&chip9->psi), &error_abort); 988 989 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 990 TYPE_PNV9_OCC, &error_abort, NULL); 991 object_property_add_const_link(OBJECT(&chip9->occ), "psi", 992 OBJECT(&chip9->psi), &error_abort); 993 } 994 995 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 996 { 997 PnvChip *chip = PNV_CHIP(chip9); 998 const char *typename = pnv_chip_core_typename(chip); 999 size_t typesize = object_type_get_instance_size(typename); 1000 int i; 1001 1002 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1003 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1004 1005 for (i = 0; i < chip9->nr_quads; i++) { 1006 char eq_name[32]; 1007 PnvQuad *eq = &chip9->quads[i]; 1008 PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize); 1009 int core_id = CPU_CORE(pnv_core)->core_id; 1010 1011 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1012 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1013 TYPE_PNV_QUAD, &error_fatal, NULL); 1014 1015 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1016 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1017 1018 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1019 &eq->xscom_regs); 1020 } 1021 } 1022 1023 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1024 { 1025 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1026 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1027 PnvChip *chip = PNV_CHIP(dev); 1028 Pnv9Psi *psi9 = &chip9->psi; 1029 Error *local_err = NULL; 1030 1031 /* XSCOM bridge is first */ 1032 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1033 if (local_err) { 1034 error_propagate(errp, local_err); 1035 return; 1036 } 1037 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1038 1039 pcc->parent_realize(dev, &local_err); 1040 if (local_err) { 1041 error_propagate(errp, local_err); 1042 return; 1043 } 1044 1045 pnv_chip_quad_realize(chip9, &local_err); 1046 if (local_err) { 1047 error_propagate(errp, local_err); 1048 return; 1049 } 1050 1051 /* XIVE interrupt controller (POWER9) */ 1052 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1053 "ic-bar", &error_fatal); 1054 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1055 "vc-bar", &error_fatal); 1056 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1057 "pc-bar", &error_fatal); 1058 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1059 "tm-bar", &error_fatal); 1060 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1061 &local_err); 1062 if (local_err) { 1063 error_propagate(errp, local_err); 1064 return; 1065 } 1066 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1067 &chip9->xive.xscom_regs); 1068 1069 /* Processor Service Interface (PSI) Host Bridge */ 1070 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1071 "bar", &error_fatal); 1072 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1073 if (local_err) { 1074 error_propagate(errp, local_err); 1075 return; 1076 } 1077 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1078 &PNV_PSI(psi9)->xscom_regs); 1079 1080 /* LPC */ 1081 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1082 if (local_err) { 1083 error_propagate(errp, local_err); 1084 return; 1085 } 1086 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1087 &chip9->lpc.xscom_regs); 1088 1089 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1090 (uint64_t) PNV9_LPCM_BASE(chip)); 1091 1092 /* Create the simplified OCC model */ 1093 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1094 if (local_err) { 1095 error_propagate(errp, local_err); 1096 return; 1097 } 1098 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1099 } 1100 1101 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1102 { 1103 DeviceClass *dc = DEVICE_CLASS(klass); 1104 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1105 1106 k->chip_type = PNV_CHIP_POWER9; 1107 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1108 k->cores_mask = POWER9_CORE_MASK; 1109 k->core_pir = pnv_chip_core_pir_p9; 1110 k->intc_create = pnv_chip_power9_intc_create; 1111 k->isa_create = pnv_chip_power9_isa_create; 1112 k->dt_populate = pnv_chip_power9_dt_populate; 1113 k->pic_print_info = pnv_chip_power9_pic_print_info; 1114 dc->desc = "PowerNV Chip POWER9"; 1115 1116 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1117 &k->parent_realize); 1118 } 1119 1120 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1121 { 1122 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1123 int cores_max; 1124 1125 /* 1126 * No custom mask for this chip, let's use the default one from * 1127 * the chip class 1128 */ 1129 if (!chip->cores_mask) { 1130 chip->cores_mask = pcc->cores_mask; 1131 } 1132 1133 /* filter alien core ids ! some are reserved */ 1134 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1135 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1136 chip->cores_mask); 1137 return; 1138 } 1139 chip->cores_mask &= pcc->cores_mask; 1140 1141 /* now that we have a sane layout, let check the number of cores */ 1142 cores_max = ctpop64(chip->cores_mask); 1143 if (chip->nr_cores > cores_max) { 1144 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1145 cores_max); 1146 return; 1147 } 1148 } 1149 1150 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1151 { 1152 Error *error = NULL; 1153 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1154 const char *typename = pnv_chip_core_typename(chip); 1155 size_t typesize = object_type_get_instance_size(typename); 1156 int i, core_hwid; 1157 1158 if (!object_class_by_name(typename)) { 1159 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1160 return; 1161 } 1162 1163 /* Cores */ 1164 pnv_chip_core_sanitize(chip, &error); 1165 if (error) { 1166 error_propagate(errp, error); 1167 return; 1168 } 1169 1170 chip->cores = g_malloc0(typesize * chip->nr_cores); 1171 1172 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1173 && (i < chip->nr_cores); core_hwid++) { 1174 char core_name[32]; 1175 void *pnv_core = chip->cores + i * typesize; 1176 uint64_t xscom_core_base; 1177 1178 if (!(chip->cores_mask & (1ull << core_hwid))) { 1179 continue; 1180 } 1181 1182 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1183 object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize, 1184 typename, &error_fatal, NULL); 1185 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads", 1186 &error_fatal); 1187 object_property_set_int(OBJECT(pnv_core), core_hwid, 1188 CPU_CORE_PROP_CORE_ID, &error_fatal); 1189 object_property_set_int(OBJECT(pnv_core), 1190 pcc->core_pir(chip, core_hwid), 1191 "pir", &error_fatal); 1192 object_property_add_const_link(OBJECT(pnv_core), "chip", 1193 OBJECT(chip), &error_fatal); 1194 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1195 &error_fatal); 1196 1197 /* Each core has an XSCOM MMIO region */ 1198 if (!pnv_chip_is_power9(chip)) { 1199 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); 1200 } else { 1201 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); 1202 } 1203 1204 pnv_xscom_add_subregion(chip, xscom_core_base, 1205 &PNV_CORE(pnv_core)->xscom_regs); 1206 i++; 1207 } 1208 } 1209 1210 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1211 { 1212 PnvChip *chip = PNV_CHIP(dev); 1213 Error *error = NULL; 1214 1215 /* Cores */ 1216 pnv_chip_core_realize(chip, &error); 1217 if (error) { 1218 error_propagate(errp, error); 1219 return; 1220 } 1221 } 1222 1223 static Property pnv_chip_properties[] = { 1224 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1225 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1226 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1227 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1228 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1229 DEFINE_PROP_END_OF_LIST(), 1230 }; 1231 1232 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1233 { 1234 DeviceClass *dc = DEVICE_CLASS(klass); 1235 1236 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1237 dc->realize = pnv_chip_realize; 1238 dc->props = pnv_chip_properties; 1239 dc->desc = "PowerNV Chip"; 1240 } 1241 1242 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1243 { 1244 PnvMachineState *pnv = PNV_MACHINE(xi); 1245 int i; 1246 1247 for (i = 0; i < pnv->num_chips; i++) { 1248 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1249 1250 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1251 return &chip8->psi.ics; 1252 } 1253 } 1254 return NULL; 1255 } 1256 1257 static void pnv_ics_resend(XICSFabric *xi) 1258 { 1259 PnvMachineState *pnv = PNV_MACHINE(xi); 1260 int i; 1261 1262 for (i = 0; i < pnv->num_chips; i++) { 1263 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1264 ics_resend(&chip8->psi.ics); 1265 } 1266 } 1267 1268 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1269 { 1270 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1271 1272 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1273 } 1274 1275 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1276 Monitor *mon) 1277 { 1278 PnvMachineState *pnv = PNV_MACHINE(obj); 1279 int i; 1280 CPUState *cs; 1281 1282 CPU_FOREACH(cs) { 1283 PowerPCCPU *cpu = POWERPC_CPU(cs); 1284 1285 if (pnv_chip_is_power9(pnv->chips[0])) { 1286 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1287 } else { 1288 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1289 } 1290 } 1291 1292 for (i = 0; i < pnv->num_chips; i++) { 1293 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1294 } 1295 } 1296 1297 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1298 void *opaque, Error **errp) 1299 { 1300 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1301 } 1302 1303 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1304 void *opaque, Error **errp) 1305 { 1306 PnvMachineState *pnv = PNV_MACHINE(obj); 1307 uint32_t num_chips; 1308 Error *local_err = NULL; 1309 1310 visit_type_uint32(v, name, &num_chips, &local_err); 1311 if (local_err) { 1312 error_propagate(errp, local_err); 1313 return; 1314 } 1315 1316 /* 1317 * TODO: should we decide on how many chips we can create based 1318 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1319 */ 1320 if (!is_power_of_2(num_chips) || num_chips > 4) { 1321 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1322 return; 1323 } 1324 1325 pnv->num_chips = num_chips; 1326 } 1327 1328 static void pnv_machine_instance_init(Object *obj) 1329 { 1330 PnvMachineState *pnv = PNV_MACHINE(obj); 1331 pnv->num_chips = 1; 1332 } 1333 1334 static void pnv_machine_class_props_init(ObjectClass *oc) 1335 { 1336 object_class_property_add(oc, "num-chips", "uint32", 1337 pnv_get_num_chips, pnv_set_num_chips, 1338 NULL, NULL, NULL); 1339 object_class_property_set_description(oc, "num-chips", 1340 "Specifies the number of processor chips", 1341 NULL); 1342 } 1343 1344 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1345 { 1346 MachineClass *mc = MACHINE_CLASS(oc); 1347 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1348 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1349 1350 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1351 mc->init = pnv_init; 1352 mc->reset = pnv_reset; 1353 mc->max_cpus = MAX_CPUS; 1354 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1355 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for 1356 * storage */ 1357 mc->no_parallel = 1; 1358 mc->default_boot_order = NULL; 1359 mc->default_ram_size = 1 * GiB; 1360 xic->icp_get = pnv_icp_get; 1361 xic->ics_get = pnv_ics_get; 1362 xic->ics_resend = pnv_ics_resend; 1363 ispc->print_info = pnv_pic_print_info; 1364 1365 pnv_machine_class_props_init(oc); 1366 } 1367 1368 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1369 { \ 1370 .name = type, \ 1371 .class_init = class_initfn, \ 1372 .parent = TYPE_PNV8_CHIP, \ 1373 } 1374 1375 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1376 { \ 1377 .name = type, \ 1378 .class_init = class_initfn, \ 1379 .parent = TYPE_PNV9_CHIP, \ 1380 } 1381 1382 static const TypeInfo types[] = { 1383 { 1384 .name = TYPE_PNV_MACHINE, 1385 .parent = TYPE_MACHINE, 1386 .instance_size = sizeof(PnvMachineState), 1387 .instance_init = pnv_machine_instance_init, 1388 .class_init = pnv_machine_class_init, 1389 .interfaces = (InterfaceInfo[]) { 1390 { TYPE_XICS_FABRIC }, 1391 { TYPE_INTERRUPT_STATS_PROVIDER }, 1392 { }, 1393 }, 1394 }, 1395 { 1396 .name = TYPE_PNV_CHIP, 1397 .parent = TYPE_SYS_BUS_DEVICE, 1398 .class_init = pnv_chip_class_init, 1399 .instance_size = sizeof(PnvChip), 1400 .class_size = sizeof(PnvChipClass), 1401 .abstract = true, 1402 }, 1403 1404 /* 1405 * P9 chip and variants 1406 */ 1407 { 1408 .name = TYPE_PNV9_CHIP, 1409 .parent = TYPE_PNV_CHIP, 1410 .instance_init = pnv_chip_power9_instance_init, 1411 .instance_size = sizeof(Pnv9Chip), 1412 }, 1413 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1414 1415 /* 1416 * P8 chip and variants 1417 */ 1418 { 1419 .name = TYPE_PNV8_CHIP, 1420 .parent = TYPE_PNV_CHIP, 1421 .instance_init = pnv_chip_power8_instance_init, 1422 .instance_size = sizeof(Pnv8Chip), 1423 }, 1424 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1425 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1426 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1427 pnv_chip_power8nvl_class_init), 1428 }; 1429 1430 DEFINE_TYPES(types) 1431