1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "hw/intc/intc.h" 42 #include "hw/ipmi/ipmi.h" 43 #include "target/ppc/mmu-hash64.h" 44 #include "hw/pci/msi.h" 45 #include "hw/pci-host/pnv_phb.h" 46 #include "hw/pci-host/pnv_phb3.h" 47 #include "hw/pci-host/pnv_phb4.h" 48 49 #include "hw/ppc/xics.h" 50 #include "hw/qdev-properties.h" 51 #include "hw/ppc/pnv_chip.h" 52 #include "hw/ppc/pnv_xscom.h" 53 #include "hw/ppc/pnv_pnor.h" 54 55 #include "hw/isa/isa.h" 56 #include "hw/char/serial.h" 57 #include "hw/rtc/mc146818rtc.h" 58 59 #include <libfdt.h> 60 61 #define FDT_MAX_SIZE (1 * MiB) 62 63 #define FW_FILE_NAME "skiboot.lid" 64 #define FW_LOAD_ADDR 0x0 65 #define FW_MAX_SIZE (16 * MiB) 66 67 #define KERNEL_LOAD_ADDR 0x20000000 68 #define KERNEL_MAX_SIZE (128 * MiB) 69 #define INITRD_LOAD_ADDR 0x28000000 70 #define INITRD_MAX_SIZE (128 * MiB) 71 72 static const char *pnv_chip_core_typename(const PnvChip *o) 73 { 74 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 75 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 76 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 77 const char *core_type = object_class_get_name(object_class_by_name(s)); 78 g_free(s); 79 return core_type; 80 } 81 82 /* 83 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 84 * 4 * 4 sockets * 12 cores * 8 threads = 1536 85 * Let's make it 2^11 86 */ 87 #define MAX_CPUS 2048 88 89 /* 90 * Memory nodes are created by hostboot, one for each range of memory 91 * that has a different "affinity". In practice, it means one range 92 * per chip. 93 */ 94 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 95 { 96 char *mem_name; 97 uint64_t mem_reg_property[2]; 98 int off; 99 100 mem_reg_property[0] = cpu_to_be64(start); 101 mem_reg_property[1] = cpu_to_be64(size); 102 103 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 104 off = fdt_add_subnode(fdt, 0, mem_name); 105 g_free(mem_name); 106 107 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 108 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 109 sizeof(mem_reg_property)))); 110 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 111 } 112 113 static int get_cpus_node(void *fdt) 114 { 115 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 116 117 if (cpus_offset < 0) { 118 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 119 if (cpus_offset) { 120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 122 } 123 } 124 _FDT(cpus_offset); 125 return cpus_offset; 126 } 127 128 /* 129 * The PowerNV cores (and threads) need to use real HW ids and not an 130 * incremental index like it has been done on other platforms. This HW 131 * id is stored in the CPU PIR, it is used to create cpu nodes in the 132 * device tree, used in XSCOM to address cores and in interrupt 133 * servers. 134 */ 135 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 136 { 137 PowerPCCPU *cpu = pc->threads[0]; 138 CPUState *cs = CPU(cpu); 139 DeviceClass *dc = DEVICE_GET_CLASS(cs); 140 int smt_threads = CPU_CORE(pc)->nr_threads; 141 CPUPPCState *env = &cpu->env; 142 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 143 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 145 int i; 146 uint32_t pir; 147 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 148 0xffffffff, 0xffffffff}; 149 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 150 uint32_t cpufreq = 1000000000; 151 uint32_t page_sizes_prop[64]; 152 size_t page_sizes_prop_size; 153 int offset; 154 char *nodename; 155 int cpus_offset = get_cpus_node(fdt); 156 157 pir = pnv_cc->chip_pir(chip, pc->hwid, 0); 158 159 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 160 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 161 _FDT(offset); 162 g_free(nodename); 163 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 167 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 168 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 169 170 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 172 env->dcache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 176 env->icache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 178 env->icache_line_size))); 179 180 if (pcc->l1_dcache_size) { 181 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 182 pcc->l1_dcache_size))); 183 } else { 184 warn_report("Unknown L1 dcache size for cpu"); 185 } 186 if (pcc->l1_icache_size) { 187 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 188 pcc->l1_icache_size))); 189 } else { 190 warn_report("Unknown L1 icache size for cpu"); 191 } 192 193 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 195 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 196 cpu->hash64_opts->slb_size))); 197 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 198 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 199 200 if (ppc_has_spr(cpu, SPR_PURR)) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 202 } 203 204 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 205 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 206 segs, sizeof(segs)))); 207 } 208 209 /* 210 * Advertise VMX/VSX (vector extensions) if available 211 * 0 / no property == no vector extensions 212 * 1 == VMX / Altivec available 213 * 2 == VSX available 214 */ 215 if (env->insns_flags & PPC_ALTIVEC) { 216 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 217 218 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 219 } 220 221 /* 222 * Advertise DFP (Decimal Floating Point) if available 223 * 0 / no property == no DFP 224 * 1 == DFP available 225 */ 226 if (env->insns_flags2 & PPC2_DFP) { 227 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 228 } 229 230 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 231 sizeof(page_sizes_prop)); 232 if (page_sizes_prop_size) { 233 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 234 page_sizes_prop, page_sizes_prop_size))); 235 } 236 237 /* Build interrupt servers properties */ 238 for (i = 0; i < smt_threads; i++) { 239 servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i)); 240 } 241 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 242 servers_prop, sizeof(*servers_prop) * smt_threads))); 243 244 return offset; 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 248 uint32_t nr_threads) 249 { 250 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 251 uint32_t pir = pcc->chip_pir(chip, hwid, 0); 252 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 253 char *name; 254 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 255 uint32_t irange[2], i, rsize; 256 uint64_t *reg; 257 int offset; 258 259 irange[0] = cpu_to_be32(pir); 260 irange[1] = cpu_to_be32(nr_threads); 261 262 rsize = sizeof(uint64_t) * 2 * nr_threads; 263 reg = g_malloc(rsize); 264 for (i = 0; i < nr_threads; i++) { 265 /* We know P8 PIR is linear with thread id */ 266 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 267 reg[i * 2 + 1] = cpu_to_be64(0x1000); 268 } 269 270 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 271 offset = fdt_add_subnode(fdt, 0, name); 272 _FDT(offset); 273 g_free(name); 274 275 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 276 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 277 _FDT((fdt_setprop_string(fdt, offset, "device_type", 278 "PowerPC-External-Interrupt-Presentation"))); 279 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 280 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 281 irange, sizeof(irange)))); 282 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 283 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 284 g_free(reg); 285 } 286 287 /* 288 * Adds a PnvPHB to the chip on P8. 289 * Implemented here, like for defaults PHBs 290 */ 291 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 292 { 293 Pnv8Chip *chip8 = PNV8_CHIP(chip); 294 295 phb->chip = chip; 296 297 chip8->phbs[chip8->num_phbs] = phb; 298 chip8->num_phbs++; 299 return chip; 300 } 301 302 /* 303 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 304 * HTM is always enabled because TCG does implement HTM, it's just a 305 * degenerate implementation. 306 */ 307 static const uint8_t pa_features_207[] = { 24, 0, 308 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 309 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 310 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 311 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 312 313 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 314 { 315 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 316 int i; 317 318 pnv_dt_xscom(chip, fdt, 0, 319 cpu_to_be64(PNV_XSCOM_BASE(chip)), 320 cpu_to_be64(PNV_XSCOM_SIZE), 321 compat, sizeof(compat)); 322 323 for (i = 0; i < chip->nr_cores; i++) { 324 PnvCore *pnv_core = chip->cores[i]; 325 int offset; 326 327 offset = pnv_dt_core(chip, pnv_core, fdt); 328 329 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 330 pa_features_207, sizeof(pa_features_207)))); 331 332 /* Interrupt Control Presenters (ICP). One per core. */ 333 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 334 } 335 336 if (chip->ram_size) { 337 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 338 } 339 } 340 341 /* 342 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 343 */ 344 static const uint8_t pa_features_300[] = { 66, 0, 345 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 346 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 347 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 348 /* 6: DS207 */ 349 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 350 /* 16: Vector */ 351 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 352 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 353 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 354 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 355 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 356 /* 32: LE atomic, 34: EBB + ext EBB */ 357 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 358 /* 40: Radix MMU */ 359 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 360 /* 42: PM, 44: PC RA, 46: SC vec'd */ 361 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 362 /* 48: SIMD, 50: QP BFP, 52: String */ 363 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 364 /* 54: DecFP, 56: DecI, 58: SHA */ 365 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 366 /* 60: NM atomic, 62: RNG */ 367 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 368 }; 369 370 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 371 { 372 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 373 int i; 374 375 pnv_dt_xscom(chip, fdt, 0, 376 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 377 cpu_to_be64(PNV9_XSCOM_SIZE), 378 compat, sizeof(compat)); 379 380 for (i = 0; i < chip->nr_cores; i++) { 381 PnvCore *pnv_core = chip->cores[i]; 382 int offset; 383 384 offset = pnv_dt_core(chip, pnv_core, fdt); 385 386 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 387 pa_features_300, sizeof(pa_features_300)))); 388 } 389 390 if (chip->ram_size) { 391 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 392 } 393 394 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 395 } 396 397 /* 398 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 399 * always disables copy/paste. 400 */ 401 static const uint8_t pa_features_31[] = { 74, 0, 402 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 403 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 404 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 405 /* 6: DS207 */ 406 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 407 /* 16: Vector */ 408 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 409 /* 18: Vec. Scalar, 20: Vec. XOR */ 410 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 411 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 412 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 413 /* 32: LE atomic, 34: EBB + ext EBB */ 414 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 415 /* 40: Radix MMU */ 416 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 417 /* 42: PM, 44: PC RA, 46: SC vec'd */ 418 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 419 /* 48: SIMD, 50: QP BFP, 52: String */ 420 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 421 /* 54: DecFP, 56: DecI, 58: SHA */ 422 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 423 /* 60: NM atomic, 62: RNG */ 424 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 425 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 426 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 427 /* 72: [P]HASHST/[P]HASHCHK */ 428 0x80, 0x00, /* 72 - 73 */ 429 }; 430 431 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 432 { 433 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 434 int i; 435 436 pnv_dt_xscom(chip, fdt, 0, 437 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 438 cpu_to_be64(PNV10_XSCOM_SIZE), 439 compat, sizeof(compat)); 440 441 for (i = 0; i < chip->nr_cores; i++) { 442 PnvCore *pnv_core = chip->cores[i]; 443 int offset; 444 445 offset = pnv_dt_core(chip, pnv_core, fdt); 446 447 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 448 pa_features_31, sizeof(pa_features_31)))); 449 } 450 451 if (chip->ram_size) { 452 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 453 } 454 455 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 456 } 457 458 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 459 { 460 uint32_t io_base = d->ioport_id; 461 uint32_t io_regs[] = { 462 cpu_to_be32(1), 463 cpu_to_be32(io_base), 464 cpu_to_be32(2) 465 }; 466 char *name; 467 int node; 468 469 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 470 node = fdt_add_subnode(fdt, lpc_off, name); 471 _FDT(node); 472 g_free(name); 473 474 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 475 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 476 } 477 478 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 479 { 480 const char compatible[] = "ns16550\0pnpPNP,501"; 481 uint32_t io_base = d->ioport_id; 482 uint32_t io_regs[] = { 483 cpu_to_be32(1), 484 cpu_to_be32(io_base), 485 cpu_to_be32(8) 486 }; 487 uint32_t irq; 488 char *name; 489 int node; 490 491 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 492 493 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 494 node = fdt_add_subnode(fdt, lpc_off, name); 495 _FDT(node); 496 g_free(name); 497 498 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 499 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 500 sizeof(compatible)))); 501 502 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 503 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 504 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 505 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 506 fdt_get_phandle(fdt, lpc_off)))); 507 508 /* This is needed by Linux */ 509 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 510 } 511 512 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 513 { 514 const char compatible[] = "bt\0ipmi-bt"; 515 uint32_t io_base; 516 uint32_t io_regs[] = { 517 cpu_to_be32(1), 518 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 519 cpu_to_be32(3) 520 }; 521 uint32_t irq; 522 char *name; 523 int node; 524 525 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 526 io_regs[1] = cpu_to_be32(io_base); 527 528 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 529 530 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 531 node = fdt_add_subnode(fdt, lpc_off, name); 532 _FDT(node); 533 g_free(name); 534 535 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 536 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 537 sizeof(compatible)))); 538 539 /* Mark it as reserved to avoid Linux trying to claim it */ 540 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 541 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 542 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 543 fdt_get_phandle(fdt, lpc_off)))); 544 } 545 546 typedef struct ForeachPopulateArgs { 547 void *fdt; 548 int offset; 549 } ForeachPopulateArgs; 550 551 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 552 { 553 ForeachPopulateArgs *args = opaque; 554 ISADevice *d = ISA_DEVICE(dev); 555 556 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 557 pnv_dt_rtc(d, args->fdt, args->offset); 558 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 559 pnv_dt_serial(d, args->fdt, args->offset); 560 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 561 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 562 } else { 563 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 564 d->ioport_id); 565 } 566 567 return 0; 568 } 569 570 /* 571 * The default LPC bus of a multichip system is on chip 0. It's 572 * recognized by the firmware (skiboot) using a "primary" property. 573 */ 574 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 575 { 576 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 577 ForeachPopulateArgs args = { 578 .fdt = fdt, 579 .offset = isa_offset, 580 }; 581 uint32_t phandle; 582 583 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 584 585 phandle = qemu_fdt_alloc_phandle(fdt); 586 assert(phandle > 0); 587 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 588 589 /* 590 * ISA devices are not necessarily parented to the ISA bus so we 591 * can not use object_child_foreach() 592 */ 593 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 594 &args); 595 } 596 597 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 598 { 599 int off; 600 601 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 602 off = fdt_add_subnode(fdt, off, "power-mgt"); 603 604 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 605 } 606 607 static void *pnv_dt_create(MachineState *machine) 608 { 609 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 610 PnvMachineState *pnv = PNV_MACHINE(machine); 611 void *fdt; 612 char *buf; 613 int off; 614 int i; 615 616 fdt = g_malloc0(FDT_MAX_SIZE); 617 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 618 619 /* /qemu node */ 620 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 621 622 /* Root node */ 623 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 624 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 625 _FDT((fdt_setprop_string(fdt, 0, "model", 626 "IBM PowerNV (emulated by qemu)"))); 627 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 628 629 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 630 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 631 if (qemu_uuid_set) { 632 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 633 } 634 g_free(buf); 635 636 off = fdt_add_subnode(fdt, 0, "chosen"); 637 if (machine->kernel_cmdline) { 638 _FDT((fdt_setprop_string(fdt, off, "bootargs", 639 machine->kernel_cmdline))); 640 } 641 642 if (pnv->initrd_size) { 643 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 644 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 645 646 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 647 &start_prop, sizeof(start_prop)))); 648 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 649 &end_prop, sizeof(end_prop)))); 650 } 651 652 /* Populate device tree for each chip */ 653 for (i = 0; i < pnv->num_chips; i++) { 654 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 655 } 656 657 /* Populate ISA devices on chip 0 */ 658 pnv_dt_isa(pnv, fdt); 659 660 if (pnv->bmc) { 661 pnv_dt_bmc_sensors(pnv->bmc, fdt); 662 } 663 664 /* Create an extra node for power management on machines that support it */ 665 if (pmc->dt_power_mgt) { 666 pmc->dt_power_mgt(pnv, fdt); 667 } 668 669 return fdt; 670 } 671 672 static void pnv_powerdown_notify(Notifier *n, void *opaque) 673 { 674 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 675 676 if (pnv->bmc) { 677 pnv_bmc_powerdown(pnv->bmc); 678 } 679 } 680 681 static void pnv_reset(MachineState *machine, ShutdownCause reason) 682 { 683 PnvMachineState *pnv = PNV_MACHINE(machine); 684 IPMIBmc *bmc; 685 void *fdt; 686 687 qemu_devices_reset(reason); 688 689 /* 690 * The machine should provide by default an internal BMC simulator. 691 * If not, try to use the BMC device that was provided on the command 692 * line. 693 */ 694 bmc = pnv_bmc_find(&error_fatal); 695 if (!pnv->bmc) { 696 if (!bmc) { 697 if (!qtest_enabled()) { 698 warn_report("machine has no BMC device. Use '-device " 699 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 700 "to define one"); 701 } 702 } else { 703 pnv_bmc_set_pnor(bmc, pnv->pnor); 704 pnv->bmc = bmc; 705 } 706 } 707 708 fdt = pnv_dt_create(machine); 709 710 /* Pack resulting tree */ 711 _FDT((fdt_pack(fdt))); 712 713 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 714 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 715 716 /* 717 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 718 * the existing machine->fdt to avoid leaking it during 719 * a reset. 720 */ 721 g_free(machine->fdt); 722 machine->fdt = fdt; 723 } 724 725 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 726 { 727 Pnv8Chip *chip8 = PNV8_CHIP(chip); 728 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 729 730 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 731 732 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 733 } 734 735 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 736 { 737 Pnv8Chip *chip8 = PNV8_CHIP(chip); 738 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 739 740 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 741 742 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 743 } 744 745 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 746 { 747 Pnv9Chip *chip9 = PNV9_CHIP(chip); 748 qemu_irq irq; 749 750 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 751 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq); 752 753 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0); 754 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); 755 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1); 756 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); 757 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2); 758 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); 759 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3); 760 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); 761 762 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 763 } 764 765 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 766 { 767 Pnv10Chip *chip10 = PNV10_CHIP(chip); 768 qemu_irq irq; 769 770 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 771 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq); 772 773 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0); 774 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); 775 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1); 776 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); 777 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2); 778 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); 779 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3); 780 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); 781 782 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 783 } 784 785 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 786 { 787 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 788 } 789 790 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf) 791 { 792 Pnv8Chip *chip8 = PNV8_CHIP(chip); 793 int i; 794 795 ics_pic_print_info(&chip8->psi.ics, buf); 796 797 for (i = 0; i < chip8->num_phbs; i++) { 798 PnvPHB *phb = chip8->phbs[i]; 799 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 800 801 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 802 ics_pic_print_info(&phb3->lsis, buf); 803 } 804 } 805 806 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 807 { 808 GString *buf = opaque; 809 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 810 811 if (!phb) { 812 return 0; 813 } 814 815 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 816 817 return 0; 818 } 819 820 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf) 821 { 822 Pnv9Chip *chip9 = PNV9_CHIP(chip); 823 824 pnv_xive_pic_print_info(&chip9->xive, buf); 825 pnv_psi_pic_print_info(&chip9->psi, buf); 826 object_child_foreach_recursive(OBJECT(chip), 827 pnv_chip_power9_pic_print_info_child, buf); 828 } 829 830 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 831 uint32_t core_id) 832 { 833 return PNV_XSCOM_EX_BASE(core_id); 834 } 835 836 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 837 uint32_t core_id) 838 { 839 return PNV9_XSCOM_EC_BASE(core_id); 840 } 841 842 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 843 uint32_t core_id) 844 { 845 return PNV10_XSCOM_EC_BASE(core_id); 846 } 847 848 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 849 { 850 PowerPCCPUClass *ppc_default = 851 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 852 PowerPCCPUClass *ppc = 853 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 854 855 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 856 } 857 858 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 859 { 860 ISADevice *dev = isa_new("isa-ipmi-bt"); 861 862 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 863 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 864 isa_realize_and_unref(dev, bus, &error_fatal); 865 } 866 867 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf) 868 { 869 Pnv10Chip *chip10 = PNV10_CHIP(chip); 870 871 pnv_xive2_pic_print_info(&chip10->xive, buf); 872 pnv_psi_pic_print_info(&chip10->psi, buf); 873 object_child_foreach_recursive(OBJECT(chip), 874 pnv_chip_power9_pic_print_info_child, buf); 875 } 876 877 /* Always give the first 1GB to chip 0 else we won't boot */ 878 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 879 { 880 MachineState *machine = MACHINE(pnv); 881 uint64_t ram_per_chip; 882 883 assert(machine->ram_size >= 1 * GiB); 884 885 ram_per_chip = machine->ram_size / pnv->num_chips; 886 if (ram_per_chip >= 1 * GiB) { 887 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 888 } 889 890 assert(pnv->num_chips > 1); 891 892 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 893 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 894 } 895 896 static void pnv_init(MachineState *machine) 897 { 898 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 899 PnvMachineState *pnv = PNV_MACHINE(machine); 900 MachineClass *mc = MACHINE_GET_CLASS(machine); 901 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 902 char *fw_filename; 903 long fw_size; 904 uint64_t chip_ram_start = 0; 905 int i; 906 char *chip_typename; 907 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 908 DeviceState *dev; 909 910 if (kvm_enabled()) { 911 error_report("machine %s does not support the KVM accelerator", 912 mc->name); 913 exit(EXIT_FAILURE); 914 } 915 916 /* allocate RAM */ 917 if (machine->ram_size < mc->default_ram_size) { 918 char *sz = size_to_str(mc->default_ram_size); 919 error_report("Invalid RAM size, should be bigger than %s", sz); 920 g_free(sz); 921 exit(EXIT_FAILURE); 922 } 923 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 924 925 /* 926 * Create our simple PNOR device 927 */ 928 dev = qdev_new(TYPE_PNV_PNOR); 929 if (pnor) { 930 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 931 } 932 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 933 pnv->pnor = PNV_PNOR(dev); 934 935 /* load skiboot firmware */ 936 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 937 if (!fw_filename) { 938 error_report("Could not find OPAL firmware '%s'", bios_name); 939 exit(1); 940 } 941 942 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 943 if (fw_size < 0) { 944 error_report("Could not load OPAL firmware '%s'", fw_filename); 945 exit(1); 946 } 947 g_free(fw_filename); 948 949 /* load kernel */ 950 if (machine->kernel_filename) { 951 long kernel_size; 952 953 kernel_size = load_image_targphys(machine->kernel_filename, 954 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 955 if (kernel_size < 0) { 956 error_report("Could not load kernel '%s'", 957 machine->kernel_filename); 958 exit(1); 959 } 960 } 961 962 /* load initrd */ 963 if (machine->initrd_filename) { 964 pnv->initrd_base = INITRD_LOAD_ADDR; 965 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 966 pnv->initrd_base, INITRD_MAX_SIZE); 967 if (pnv->initrd_size < 0) { 968 error_report("Could not load initial ram disk '%s'", 969 machine->initrd_filename); 970 exit(1); 971 } 972 } 973 974 /* MSIs are supported on this platform */ 975 msi_nonbroken = true; 976 977 /* 978 * Check compatibility of the specified CPU with the machine 979 * default. 980 */ 981 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 982 error_report("invalid CPU model '%s' for %s machine", 983 machine->cpu_type, mc->name); 984 exit(1); 985 } 986 987 /* Create the processor chips */ 988 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 989 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 990 i, machine->cpu_type); 991 if (!object_class_by_name(chip_typename)) { 992 error_report("invalid chip model '%.*s' for %s machine", 993 i, machine->cpu_type, mc->name); 994 exit(1); 995 } 996 997 pnv->num_chips = 998 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 999 1000 if (machine->smp.threads > 8) { 1001 error_report("Cannot support more than 8 threads/core " 1002 "on a powernv machine"); 1003 exit(1); 1004 } 1005 if (!is_power_of_2(machine->smp.threads)) { 1006 error_report("Cannot support %d threads/core on a powernv" 1007 "machine because it must be a power of 2", 1008 machine->smp.threads); 1009 exit(1); 1010 } 1011 /* 1012 * TODO: should we decide on how many chips we can create based 1013 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1014 */ 1015 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1016 error_report("invalid number of chips: '%d'", pnv->num_chips); 1017 error_printf( 1018 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1019 exit(1); 1020 } 1021 1022 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1023 for (i = 0; i < pnv->num_chips; i++) { 1024 char chip_name[32]; 1025 Object *chip = OBJECT(qdev_new(chip_typename)); 1026 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1027 1028 pnv->chips[i] = PNV_CHIP(chip); 1029 1030 /* Distribute RAM among the chips */ 1031 object_property_set_int(chip, "ram-start", chip_ram_start, 1032 &error_fatal); 1033 object_property_set_int(chip, "ram-size", chip_ram_size, 1034 &error_fatal); 1035 chip_ram_start += chip_ram_size; 1036 1037 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1038 object_property_add_child(OBJECT(pnv), chip_name, chip); 1039 object_property_set_int(chip, "chip-id", i, &error_fatal); 1040 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1041 &error_fatal); 1042 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1043 &error_fatal); 1044 /* 1045 * The POWER8 machine use the XICS interrupt interface. 1046 * Propagate the XICS fabric to the chip and its controllers. 1047 */ 1048 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1049 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1050 } 1051 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1052 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1053 &error_abort); 1054 } 1055 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1056 } 1057 g_free(chip_typename); 1058 1059 /* Instantiate ISA bus on chip 0 */ 1060 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1061 1062 /* Create serial port */ 1063 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1064 1065 /* Create an RTC ISA device too */ 1066 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1067 1068 /* 1069 * Create the machine BMC simulator and the IPMI BT device for 1070 * communication with the BMC 1071 */ 1072 if (defaults_enabled()) { 1073 pnv->bmc = pnv_bmc_create(pnv->pnor); 1074 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1075 } 1076 1077 /* 1078 * The PNOR is mapped on the LPC FW address space by the BMC. 1079 * Since we can not reach the remote BMC machine with LPC memops, 1080 * map it always for now. 1081 */ 1082 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1083 &pnv->pnor->mmio); 1084 1085 /* 1086 * OpenPOWER systems use a IPMI SEL Event message to notify the 1087 * host to powerdown 1088 */ 1089 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1090 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1091 1092 /* 1093 * Create/Connect any machine-specific I2C devices 1094 */ 1095 if (pmc->i2c_init) { 1096 pmc->i2c_init(pnv); 1097 } 1098 } 1099 1100 /* 1101 * 0:21 Reserved - Read as zeros 1102 * 22:24 Chip ID 1103 * 25:28 Core number 1104 * 29:31 Thread ID 1105 */ 1106 static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id, 1107 uint32_t thread_id) 1108 { 1109 return (chip->chip_id << 7) | (core_id << 3) | thread_id; 1110 } 1111 1112 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1113 Error **errp) 1114 { 1115 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1116 Error *local_err = NULL; 1117 Object *obj; 1118 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1119 1120 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1121 if (local_err) { 1122 error_propagate(errp, local_err); 1123 return; 1124 } 1125 1126 pnv_cpu->intc = obj; 1127 } 1128 1129 1130 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1131 { 1132 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1133 1134 icp_reset(ICP(pnv_cpu->intc)); 1135 } 1136 1137 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1138 { 1139 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1140 1141 icp_destroy(ICP(pnv_cpu->intc)); 1142 pnv_cpu->intc = NULL; 1143 } 1144 1145 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1146 GString *buf) 1147 { 1148 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1149 } 1150 1151 /* 1152 * 0:48 Reserved - Read as zeroes 1153 * 49:52 Node ID 1154 * 53:55 Chip ID 1155 * 56 Reserved - Read as zero 1156 * 57:61 Core number 1157 * 62:63 Thread ID 1158 * 1159 * We only care about the lower bits. uint32_t is fine for the moment. 1160 */ 1161 static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id, 1162 uint32_t thread_id) 1163 { 1164 if (chip->nr_threads == 8) { 1165 return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) | 1166 (thread_id >> 1); 1167 } else { 1168 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1169 } 1170 } 1171 1172 /* 1173 * 0:48 Reserved - Read as zeroes 1174 * 49:52 Node ID 1175 * 53:55 Chip ID 1176 * 56 Reserved - Read as zero 1177 * 57:59 Quad ID 1178 * 60 Core Chiplet Pair ID 1179 * 61:63 Thread/Core Chiplet ID t0-t2 1180 * 1181 * We only care about the lower bits. uint32_t is fine for the moment. 1182 */ 1183 static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id, 1184 uint32_t thread_id) 1185 { 1186 if (chip->nr_threads == 8) { 1187 return (chip->chip_id << 8) | ((core_id / 4) << 4) | 1188 ((core_id % 2) << 3) | thread_id; 1189 } else { 1190 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1191 } 1192 } 1193 1194 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1195 Error **errp) 1196 { 1197 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1198 Error *local_err = NULL; 1199 Object *obj; 1200 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1201 1202 /* 1203 * The core creates its interrupt presenter but the XIVE interrupt 1204 * controller object is initialized afterwards. Hopefully, it's 1205 * only used at runtime. 1206 */ 1207 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1208 &local_err); 1209 if (local_err) { 1210 error_propagate(errp, local_err); 1211 return; 1212 } 1213 1214 pnv_cpu->intc = obj; 1215 } 1216 1217 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1218 { 1219 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1220 1221 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1222 } 1223 1224 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1225 { 1226 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1227 1228 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1229 pnv_cpu->intc = NULL; 1230 } 1231 1232 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1233 GString *buf) 1234 { 1235 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1236 } 1237 1238 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1239 Error **errp) 1240 { 1241 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1242 Error *local_err = NULL; 1243 Object *obj; 1244 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1245 1246 /* 1247 * The core creates its interrupt presenter but the XIVE2 interrupt 1248 * controller object is initialized afterwards. Hopefully, it's 1249 * only used at runtime. 1250 */ 1251 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1252 &local_err); 1253 if (local_err) { 1254 error_propagate(errp, local_err); 1255 return; 1256 } 1257 1258 pnv_cpu->intc = obj; 1259 } 1260 1261 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1262 { 1263 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1264 1265 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1266 } 1267 1268 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1269 { 1270 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1271 1272 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1273 pnv_cpu->intc = NULL; 1274 } 1275 1276 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1277 GString *buf) 1278 { 1279 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1280 } 1281 1282 /* 1283 * Allowed core identifiers on a POWER8 Processor Chip : 1284 * 1285 * <EX0 reserved> 1286 * EX1 - Venice only 1287 * EX2 - Venice only 1288 * EX3 - Venice only 1289 * EX4 1290 * EX5 1291 * EX6 1292 * <EX7,8 reserved> <reserved> 1293 * EX9 - Venice only 1294 * EX10 - Venice only 1295 * EX11 - Venice only 1296 * EX12 1297 * EX13 1298 * EX14 1299 * <EX15 reserved> 1300 */ 1301 #define POWER8E_CORE_MASK (0x7070ull) 1302 #define POWER8_CORE_MASK (0x7e7eull) 1303 1304 /* 1305 * POWER9 has 24 cores, ids starting at 0x0 1306 */ 1307 #define POWER9_CORE_MASK (0xffffffffffffffull) 1308 1309 1310 #define POWER10_CORE_MASK (0xffffffffffffffull) 1311 1312 static void pnv_chip_power8_instance_init(Object *obj) 1313 { 1314 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1315 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1316 int i; 1317 1318 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1319 (Object **)&chip8->xics, 1320 object_property_allow_set_link, 1321 OBJ_PROP_LINK_STRONG); 1322 1323 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1324 1325 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1326 1327 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1328 1329 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1330 1331 if (defaults_enabled()) { 1332 chip8->num_phbs = pcc->num_phbs; 1333 1334 for (i = 0; i < chip8->num_phbs; i++) { 1335 Object *phb = object_new(TYPE_PNV_PHB); 1336 1337 /* 1338 * We need the chip to parent the PHB to allow the DT 1339 * to build correctly (via pnv_xscom_dt()). 1340 * 1341 * TODO: the PHB should be parented by a PEC device that, at 1342 * this moment, is not modelled powernv8/phb3. 1343 */ 1344 object_property_add_child(obj, "phb[*]", phb); 1345 chip8->phbs[i] = PNV_PHB(phb); 1346 } 1347 } 1348 1349 } 1350 1351 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1352 { 1353 PnvChip *chip = PNV_CHIP(chip8); 1354 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1355 int i, j; 1356 char *name; 1357 1358 name = g_strdup_printf("icp-%x", chip->chip_id); 1359 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1360 g_free(name); 1361 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1362 &chip8->icp_mmio); 1363 1364 /* Map the ICP registers for each thread */ 1365 for (i = 0; i < chip->nr_cores; i++) { 1366 PnvCore *pnv_core = chip->cores[i]; 1367 int core_hwid = CPU_CORE(pnv_core)->core_id; 1368 1369 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1370 uint32_t pir = pcc->chip_pir(chip, core_hwid, j); 1371 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1372 1373 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1374 &icp->mmio); 1375 } 1376 } 1377 } 1378 1379 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1380 { 1381 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1382 PnvChip *chip = PNV_CHIP(dev); 1383 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1384 Pnv8Psi *psi8 = &chip8->psi; 1385 Error *local_err = NULL; 1386 int i; 1387 1388 assert(chip8->xics); 1389 1390 /* XSCOM bridge is first */ 1391 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1392 1393 pcc->parent_realize(dev, &local_err); 1394 if (local_err) { 1395 error_propagate(errp, local_err); 1396 return; 1397 } 1398 1399 /* Processor Service Interface (PSI) Host Bridge */ 1400 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1401 &error_fatal); 1402 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1403 OBJECT(chip8->xics), &error_abort); 1404 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1405 return; 1406 } 1407 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1408 &PNV_PSI(psi8)->xscom_regs); 1409 1410 /* Create LPC controller */ 1411 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1412 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1413 1414 chip->fw_mr = &chip8->lpc.isa_fw; 1415 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1416 (uint64_t) PNV_XSCOM_BASE(chip), 1417 PNV_XSCOM_LPC_BASE); 1418 1419 /* 1420 * Interrupt Management Area. This is the memory region holding 1421 * all the Interrupt Control Presenter (ICP) registers 1422 */ 1423 pnv_chip_icp_realize(chip8, &local_err); 1424 if (local_err) { 1425 error_propagate(errp, local_err); 1426 return; 1427 } 1428 1429 /* Create the simplified OCC model */ 1430 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1431 return; 1432 } 1433 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1434 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1435 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1436 1437 /* OCC SRAM model */ 1438 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1439 &chip8->occ.sram_regs); 1440 1441 /* HOMER */ 1442 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1443 &error_abort); 1444 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1445 return; 1446 } 1447 /* Homer Xscom region */ 1448 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1449 1450 /* Homer mmio region */ 1451 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1452 &chip8->homer.regs); 1453 1454 /* PHB controllers */ 1455 for (i = 0; i < chip8->num_phbs; i++) { 1456 PnvPHB *phb = chip8->phbs[i]; 1457 1458 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1459 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1460 &error_fatal); 1461 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1462 &error_fatal); 1463 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1464 return; 1465 } 1466 } 1467 } 1468 1469 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1470 { 1471 addr &= (PNV_XSCOM_SIZE - 1); 1472 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1473 } 1474 1475 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1476 { 1477 DeviceClass *dc = DEVICE_CLASS(klass); 1478 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1479 1480 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1481 k->cores_mask = POWER8E_CORE_MASK; 1482 k->num_phbs = 3; 1483 k->chip_pir = pnv_chip_pir_p8; 1484 k->intc_create = pnv_chip_power8_intc_create; 1485 k->intc_reset = pnv_chip_power8_intc_reset; 1486 k->intc_destroy = pnv_chip_power8_intc_destroy; 1487 k->intc_print_info = pnv_chip_power8_intc_print_info; 1488 k->isa_create = pnv_chip_power8_isa_create; 1489 k->dt_populate = pnv_chip_power8_dt_populate; 1490 k->pic_print_info = pnv_chip_power8_pic_print_info; 1491 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1492 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1493 dc->desc = "PowerNV Chip POWER8E"; 1494 1495 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1496 &k->parent_realize); 1497 } 1498 1499 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1500 { 1501 DeviceClass *dc = DEVICE_CLASS(klass); 1502 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1503 1504 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1505 k->cores_mask = POWER8_CORE_MASK; 1506 k->num_phbs = 3; 1507 k->chip_pir = pnv_chip_pir_p8; 1508 k->intc_create = pnv_chip_power8_intc_create; 1509 k->intc_reset = pnv_chip_power8_intc_reset; 1510 k->intc_destroy = pnv_chip_power8_intc_destroy; 1511 k->intc_print_info = pnv_chip_power8_intc_print_info; 1512 k->isa_create = pnv_chip_power8_isa_create; 1513 k->dt_populate = pnv_chip_power8_dt_populate; 1514 k->pic_print_info = pnv_chip_power8_pic_print_info; 1515 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1516 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1517 dc->desc = "PowerNV Chip POWER8"; 1518 1519 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1520 &k->parent_realize); 1521 } 1522 1523 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1524 { 1525 DeviceClass *dc = DEVICE_CLASS(klass); 1526 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1527 1528 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1529 k->cores_mask = POWER8_CORE_MASK; 1530 k->num_phbs = 4; 1531 k->chip_pir = pnv_chip_pir_p8; 1532 k->intc_create = pnv_chip_power8_intc_create; 1533 k->intc_reset = pnv_chip_power8_intc_reset; 1534 k->intc_destroy = pnv_chip_power8_intc_destroy; 1535 k->intc_print_info = pnv_chip_power8_intc_print_info; 1536 k->isa_create = pnv_chip_power8nvl_isa_create; 1537 k->dt_populate = pnv_chip_power8_dt_populate; 1538 k->pic_print_info = pnv_chip_power8_pic_print_info; 1539 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1540 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1541 dc->desc = "PowerNV Chip POWER8NVL"; 1542 1543 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1544 &k->parent_realize); 1545 } 1546 1547 static void pnv_chip_power9_instance_init(Object *obj) 1548 { 1549 PnvChip *chip = PNV_CHIP(obj); 1550 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1551 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1552 int i; 1553 1554 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU); 1555 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1556 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1557 "xive-fabric"); 1558 1559 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1560 1561 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1562 1563 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1564 1565 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1566 1567 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1568 1569 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1570 1571 /* Number of PECs is the chip default */ 1572 chip->num_pecs = pcc->num_pecs; 1573 1574 for (i = 0; i < chip->num_pecs; i++) { 1575 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1576 TYPE_PNV_PHB4_PEC); 1577 } 1578 1579 for (i = 0; i < pcc->i2c_num_engines; i++) { 1580 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1581 } 1582 } 1583 1584 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1585 PnvCore *pnv_core, 1586 const char *type) 1587 { 1588 char eq_name[32]; 1589 int core_id = CPU_CORE(pnv_core)->core_id; 1590 1591 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1592 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1593 sizeof(*eq), type, 1594 &error_fatal, NULL); 1595 1596 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1597 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1598 } 1599 1600 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1601 { 1602 PnvChip *chip = PNV_CHIP(chip9); 1603 int i; 1604 1605 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1606 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1607 1608 for (i = 0; i < chip9->nr_quads; i++) { 1609 PnvQuad *eq = &chip9->quads[i]; 1610 1611 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1612 PNV_QUAD_TYPE_NAME("power9")); 1613 1614 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1615 &eq->xscom_regs); 1616 } 1617 } 1618 1619 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1620 { 1621 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1622 int i; 1623 1624 for (i = 0; i < chip->num_pecs; i++) { 1625 PnvPhb4PecState *pec = &chip9->pecs[i]; 1626 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1627 uint32_t pec_nest_base; 1628 uint32_t pec_pci_base; 1629 1630 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1631 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1632 &error_fatal); 1633 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1634 &error_fatal); 1635 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1636 return; 1637 } 1638 1639 pec_nest_base = pecc->xscom_nest_base(pec); 1640 pec_pci_base = pecc->xscom_pci_base(pec); 1641 1642 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1643 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1644 } 1645 } 1646 1647 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1648 { 1649 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1650 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1651 PnvChip *chip = PNV_CHIP(dev); 1652 Pnv9Psi *psi9 = &chip9->psi; 1653 Error *local_err = NULL; 1654 int i; 1655 1656 /* XSCOM bridge is first */ 1657 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1658 1659 pcc->parent_realize(dev, &local_err); 1660 if (local_err) { 1661 error_propagate(errp, local_err); 1662 return; 1663 } 1664 1665 /* ADU */ 1666 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { 1667 return; 1668 } 1669 pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE, 1670 &chip9->adu.xscom_regs); 1671 1672 pnv_chip_quad_realize(chip9, &local_err); 1673 if (local_err) { 1674 error_propagate(errp, local_err); 1675 return; 1676 } 1677 1678 /* XIVE interrupt controller (POWER9) */ 1679 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1680 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1681 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1682 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1683 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1684 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1685 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1686 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1687 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1688 &error_abort); 1689 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1690 return; 1691 } 1692 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1693 &chip9->xive.xscom_regs); 1694 1695 /* Processor Service Interface (PSI) Host Bridge */ 1696 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1697 &error_fatal); 1698 /* This is the only device with 4k ESB pages */ 1699 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1700 &error_fatal); 1701 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1702 return; 1703 } 1704 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1705 &PNV_PSI(psi9)->xscom_regs); 1706 1707 /* LPC */ 1708 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1709 return; 1710 } 1711 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1712 &chip9->lpc.xscom_regs); 1713 1714 chip->fw_mr = &chip9->lpc.isa_fw; 1715 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1716 (uint64_t) PNV9_LPCM_BASE(chip)); 1717 1718 /* ChipTOD */ 1719 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1720 chip->chip_id == 0, &error_abort); 1721 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1722 chip->chip_id == 1, &error_abort); 1723 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1724 &error_abort); 1725 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1726 return; 1727 } 1728 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1729 &chip9->chiptod.xscom_regs); 1730 1731 /* Create the simplified OCC model */ 1732 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1733 return; 1734 } 1735 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1736 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1737 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1738 1739 /* OCC SRAM model */ 1740 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1741 &chip9->occ.sram_regs); 1742 1743 /* SBE */ 1744 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1745 return; 1746 } 1747 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1748 &chip9->sbe.xscom_ctrl_regs); 1749 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1750 &chip9->sbe.xscom_mbox_regs); 1751 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1752 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1753 1754 /* HOMER */ 1755 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1756 &error_abort); 1757 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1758 return; 1759 } 1760 /* Homer Xscom region */ 1761 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1762 1763 /* Homer mmio region */ 1764 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1765 &chip9->homer.regs); 1766 1767 /* PEC PHBs */ 1768 pnv_chip_power9_pec_realize(chip, &local_err); 1769 if (local_err) { 1770 error_propagate(errp, local_err); 1771 return; 1772 } 1773 1774 /* 1775 * I2C 1776 */ 1777 for (i = 0; i < pcc->i2c_num_engines; i++) { 1778 Object *obj = OBJECT(&chip9->i2c[i]); 1779 1780 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1781 object_property_set_int(obj, "num-busses", 1782 pcc->i2c_ports_per_engine[i], 1783 &error_fatal); 1784 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1785 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1786 return; 1787 } 1788 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1789 (chip9->i2c[i].engine - 1) * 1790 PNV9_XSCOM_I2CM_SIZE, 1791 &chip9->i2c[i].xscom_regs); 1792 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1793 qdev_get_gpio_in(DEVICE(psi9), 1794 PSIHB9_IRQ_SBE_I2C)); 1795 } 1796 } 1797 1798 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1799 { 1800 addr &= (PNV9_XSCOM_SIZE - 1); 1801 return addr >> 3; 1802 } 1803 1804 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1805 { 1806 DeviceClass *dc = DEVICE_CLASS(klass); 1807 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1808 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1809 1810 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1811 k->cores_mask = POWER9_CORE_MASK; 1812 k->chip_pir = pnv_chip_pir_p9; 1813 k->intc_create = pnv_chip_power9_intc_create; 1814 k->intc_reset = pnv_chip_power9_intc_reset; 1815 k->intc_destroy = pnv_chip_power9_intc_destroy; 1816 k->intc_print_info = pnv_chip_power9_intc_print_info; 1817 k->isa_create = pnv_chip_power9_isa_create; 1818 k->dt_populate = pnv_chip_power9_dt_populate; 1819 k->pic_print_info = pnv_chip_power9_pic_print_info; 1820 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1821 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1822 dc->desc = "PowerNV Chip POWER9"; 1823 k->num_pecs = PNV9_CHIP_MAX_PEC; 1824 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1825 k->i2c_ports_per_engine = i2c_ports_per_engine; 1826 1827 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1828 &k->parent_realize); 1829 } 1830 1831 static void pnv_chip_power10_instance_init(Object *obj) 1832 { 1833 PnvChip *chip = PNV_CHIP(obj); 1834 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1835 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1836 int i; 1837 1838 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); 1839 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1840 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1841 "xive-fabric"); 1842 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1843 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1844 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1845 TYPE_PNV10_CHIPTOD); 1846 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1847 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1848 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1849 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1850 TYPE_PNV_N1_CHIPLET); 1851 1852 chip->num_pecs = pcc->num_pecs; 1853 1854 for (i = 0; i < chip->num_pecs; i++) { 1855 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1856 TYPE_PNV_PHB5_PEC); 1857 } 1858 1859 for (i = 0; i < pcc->i2c_num_engines; i++) { 1860 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1861 } 1862 } 1863 1864 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1865 { 1866 PnvChip *chip = PNV_CHIP(chip10); 1867 int i; 1868 1869 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1870 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1871 1872 for (i = 0; i < chip10->nr_quads; i++) { 1873 PnvQuad *eq = &chip10->quads[i]; 1874 1875 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1876 PNV_QUAD_TYPE_NAME("power10")); 1877 1878 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1879 &eq->xscom_regs); 1880 1881 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1882 &eq->xscom_qme_regs); 1883 } 1884 } 1885 1886 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1887 { 1888 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1889 int i; 1890 1891 for (i = 0; i < chip->num_pecs; i++) { 1892 PnvPhb4PecState *pec = &chip10->pecs[i]; 1893 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1894 uint32_t pec_nest_base; 1895 uint32_t pec_pci_base; 1896 1897 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1898 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1899 &error_fatal); 1900 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1901 &error_fatal); 1902 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1903 return; 1904 } 1905 1906 pec_nest_base = pecc->xscom_nest_base(pec); 1907 pec_pci_base = pecc->xscom_pci_base(pec); 1908 1909 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1910 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1911 } 1912 } 1913 1914 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1915 { 1916 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1917 PnvChip *chip = PNV_CHIP(dev); 1918 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1919 Error *local_err = NULL; 1920 int i; 1921 1922 /* XSCOM bridge is first */ 1923 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 1924 1925 pcc->parent_realize(dev, &local_err); 1926 if (local_err) { 1927 error_propagate(errp, local_err); 1928 return; 1929 } 1930 1931 /* ADU */ 1932 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { 1933 return; 1934 } 1935 pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE, 1936 &chip10->adu.xscom_regs); 1937 1938 pnv_chip_power10_quad_realize(chip10, &local_err); 1939 if (local_err) { 1940 error_propagate(errp, local_err); 1941 return; 1942 } 1943 1944 /* XIVE2 interrupt controller (POWER10) */ 1945 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1946 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1947 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1948 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1949 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1950 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1951 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1952 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1953 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1954 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1955 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1956 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1957 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1958 &error_abort); 1959 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1960 return; 1961 } 1962 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1963 &chip10->xive.xscom_regs); 1964 1965 /* Processor Service Interface (PSI) Host Bridge */ 1966 object_property_set_int(OBJECT(&chip10->psi), "bar", 1967 PNV10_PSIHB_BASE(chip), &error_fatal); 1968 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1969 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1970 &error_fatal); 1971 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1972 return; 1973 } 1974 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1975 &PNV_PSI(&chip10->psi)->xscom_regs); 1976 1977 /* LPC */ 1978 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1979 return; 1980 } 1981 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1982 &chip10->lpc.xscom_regs); 1983 1984 chip->fw_mr = &chip10->lpc.isa_fw; 1985 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1986 (uint64_t) PNV10_LPCM_BASE(chip)); 1987 1988 /* ChipTOD */ 1989 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 1990 chip->chip_id == 0, &error_abort); 1991 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 1992 chip->chip_id == 1, &error_abort); 1993 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 1994 &error_abort); 1995 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 1996 return; 1997 } 1998 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 1999 &chip10->chiptod.xscom_regs); 2000 2001 /* Create the simplified OCC model */ 2002 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 2003 return; 2004 } 2005 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 2006 &chip10->occ.xscom_regs); 2007 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 2008 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 2009 2010 /* OCC SRAM model */ 2011 memory_region_add_subregion(get_system_memory(), 2012 PNV10_OCC_SENSOR_BASE(chip), 2013 &chip10->occ.sram_regs); 2014 2015 /* SBE */ 2016 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 2017 return; 2018 } 2019 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2020 &chip10->sbe.xscom_ctrl_regs); 2021 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2022 &chip10->sbe.xscom_mbox_regs); 2023 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2024 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2025 2026 /* HOMER */ 2027 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2028 &error_abort); 2029 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2030 return; 2031 } 2032 /* Homer Xscom region */ 2033 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2034 &chip10->homer.pba_regs); 2035 2036 /* Homer mmio region */ 2037 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 2038 &chip10->homer.regs); 2039 2040 /* N1 chiplet */ 2041 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2042 return; 2043 } 2044 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2045 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2046 2047 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2048 &chip10->n1_chiplet.xscom_pb_eq_mr); 2049 2050 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2051 &chip10->n1_chiplet.xscom_pb_es_mr); 2052 2053 /* PHBs */ 2054 pnv_chip_power10_phb_realize(chip, &local_err); 2055 if (local_err) { 2056 error_propagate(errp, local_err); 2057 return; 2058 } 2059 2060 2061 /* 2062 * I2C 2063 */ 2064 for (i = 0; i < pcc->i2c_num_engines; i++) { 2065 Object *obj = OBJECT(&chip10->i2c[i]); 2066 2067 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2068 object_property_set_int(obj, "num-busses", 2069 pcc->i2c_ports_per_engine[i], 2070 &error_fatal); 2071 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2072 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2073 return; 2074 } 2075 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2076 (chip10->i2c[i].engine - 1) * 2077 PNV10_XSCOM_I2CM_SIZE, 2078 &chip10->i2c[i].xscom_regs); 2079 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2080 qdev_get_gpio_in(DEVICE(&chip10->psi), 2081 PSIHB9_IRQ_SBE_I2C)); 2082 } 2083 2084 } 2085 2086 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2087 { 2088 int i; 2089 for (i = 0; i < pnv->num_chips; i++) { 2090 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2091 2092 /* 2093 * Add a PCA9552 I2C device for PCIe hotplug control 2094 * to engine 2, bus 1, address 0x63 2095 */ 2096 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2097 "pca9552", 0x63); 2098 2099 /* 2100 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2101 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2102 * after hypervisor code sets a SLOTx_EN pin high. 2103 */ 2104 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2105 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2106 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2107 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2108 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2109 2110 /* 2111 * Add a PCA9554 I2C device for cable card presence detection 2112 * to engine 2, bus 1, address 0x25 2113 */ 2114 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2115 } 2116 } 2117 2118 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2119 { 2120 addr &= (PNV10_XSCOM_SIZE - 1); 2121 return addr >> 3; 2122 } 2123 2124 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2125 { 2126 DeviceClass *dc = DEVICE_CLASS(klass); 2127 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2128 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2129 2130 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */ 2131 k->cores_mask = POWER10_CORE_MASK; 2132 k->chip_pir = pnv_chip_pir_p10; 2133 k->intc_create = pnv_chip_power10_intc_create; 2134 k->intc_reset = pnv_chip_power10_intc_reset; 2135 k->intc_destroy = pnv_chip_power10_intc_destroy; 2136 k->intc_print_info = pnv_chip_power10_intc_print_info; 2137 k->isa_create = pnv_chip_power10_isa_create; 2138 k->dt_populate = pnv_chip_power10_dt_populate; 2139 k->pic_print_info = pnv_chip_power10_pic_print_info; 2140 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2141 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2142 dc->desc = "PowerNV Chip POWER10"; 2143 k->num_pecs = PNV10_CHIP_MAX_PEC; 2144 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2145 k->i2c_ports_per_engine = i2c_ports_per_engine; 2146 2147 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2148 &k->parent_realize); 2149 } 2150 2151 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 2152 { 2153 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2154 int cores_max; 2155 2156 /* 2157 * No custom mask for this chip, let's use the default one from * 2158 * the chip class 2159 */ 2160 if (!chip->cores_mask) { 2161 chip->cores_mask = pcc->cores_mask; 2162 } 2163 2164 /* filter alien core ids ! some are reserved */ 2165 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2166 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2167 chip->cores_mask); 2168 return; 2169 } 2170 chip->cores_mask &= pcc->cores_mask; 2171 2172 /* now that we have a sane layout, let check the number of cores */ 2173 cores_max = ctpop64(chip->cores_mask); 2174 if (chip->nr_cores > cores_max) { 2175 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2176 cores_max); 2177 return; 2178 } 2179 } 2180 2181 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2182 { 2183 Error *error = NULL; 2184 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2185 const char *typename = pnv_chip_core_typename(chip); 2186 int i, core_hwid; 2187 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2188 2189 if (!object_class_by_name(typename)) { 2190 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2191 return; 2192 } 2193 2194 /* Cores */ 2195 pnv_chip_core_sanitize(chip, &error); 2196 if (error) { 2197 error_propagate(errp, error); 2198 return; 2199 } 2200 2201 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2202 2203 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2204 && (i < chip->nr_cores); core_hwid++) { 2205 char core_name[32]; 2206 PnvCore *pnv_core; 2207 uint64_t xscom_core_base; 2208 2209 if (!(chip->cores_mask & (1ull << core_hwid))) { 2210 continue; 2211 } 2212 2213 pnv_core = PNV_CORE(object_new(typename)); 2214 2215 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2216 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2217 chip->cores[i] = pnv_core; 2218 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2219 chip->nr_threads, &error_fatal); 2220 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2221 core_hwid, &error_fatal); 2222 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2223 &error_fatal); 2224 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2225 &error_fatal); 2226 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2227 &error_abort); 2228 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2229 2230 /* Each core has an XSCOM MMIO region */ 2231 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2232 2233 pnv_xscom_add_subregion(chip, xscom_core_base, 2234 &pnv_core->xscom_regs); 2235 i++; 2236 } 2237 } 2238 2239 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2240 { 2241 PnvChip *chip = PNV_CHIP(dev); 2242 Error *error = NULL; 2243 2244 /* Cores */ 2245 pnv_chip_core_realize(chip, &error); 2246 if (error) { 2247 error_propagate(errp, error); 2248 return; 2249 } 2250 } 2251 2252 static Property pnv_chip_properties[] = { 2253 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2254 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2255 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2256 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2257 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2258 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2259 DEFINE_PROP_END_OF_LIST(), 2260 }; 2261 2262 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2263 { 2264 DeviceClass *dc = DEVICE_CLASS(klass); 2265 2266 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2267 dc->realize = pnv_chip_realize; 2268 device_class_set_props(dc, pnv_chip_properties); 2269 dc->desc = "PowerNV Chip"; 2270 } 2271 2272 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2273 { 2274 int i; 2275 2276 for (i = 0; i < chip->nr_cores; i++) { 2277 PnvCore *pc = chip->cores[i]; 2278 CPUCore *cc = CPU_CORE(pc); 2279 2280 if (cc->core_id == core_id) { 2281 return pc; 2282 } 2283 } 2284 return NULL; 2285 } 2286 2287 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2288 { 2289 int i, j; 2290 2291 for (i = 0; i < chip->nr_cores; i++) { 2292 PnvCore *pc = chip->cores[i]; 2293 CPUCore *cc = CPU_CORE(pc); 2294 2295 for (j = 0; j < cc->nr_threads; j++) { 2296 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2297 return pc->threads[j]; 2298 } 2299 } 2300 } 2301 return NULL; 2302 } 2303 2304 static void pnv_chip_foreach_cpu(PnvChip *chip, 2305 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque), 2306 void *opaque) 2307 { 2308 int i, j; 2309 2310 for (i = 0; i < chip->nr_cores; i++) { 2311 PnvCore *pc = chip->cores[i]; 2312 2313 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) { 2314 fn(chip, pc->threads[j], opaque); 2315 } 2316 } 2317 } 2318 2319 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2320 { 2321 PnvMachineState *pnv = PNV_MACHINE(xi); 2322 int i, j; 2323 2324 for (i = 0; i < pnv->num_chips; i++) { 2325 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2326 2327 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2328 return &chip8->psi.ics; 2329 } 2330 2331 for (j = 0; j < chip8->num_phbs; j++) { 2332 PnvPHB *phb = chip8->phbs[j]; 2333 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2334 2335 if (ics_valid_irq(&phb3->lsis, irq)) { 2336 return &phb3->lsis; 2337 } 2338 2339 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2340 return ICS(&phb3->msis); 2341 } 2342 } 2343 } 2344 return NULL; 2345 } 2346 2347 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2348 { 2349 int i; 2350 2351 for (i = 0; i < pnv->num_chips; i++) { 2352 PnvChip *chip = pnv->chips[i]; 2353 if (chip->chip_id == chip_id) { 2354 return chip; 2355 } 2356 } 2357 return NULL; 2358 } 2359 2360 static void pnv_ics_resend(XICSFabric *xi) 2361 { 2362 PnvMachineState *pnv = PNV_MACHINE(xi); 2363 int i, j; 2364 2365 for (i = 0; i < pnv->num_chips; i++) { 2366 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2367 2368 ics_resend(&chip8->psi.ics); 2369 2370 for (j = 0; j < chip8->num_phbs; j++) { 2371 PnvPHB *phb = chip8->phbs[j]; 2372 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2373 2374 ics_resend(&phb3->lsis); 2375 ics_resend(ICS(&phb3->msis)); 2376 } 2377 } 2378 } 2379 2380 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2381 { 2382 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2383 2384 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2385 } 2386 2387 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 2388 void *opaque) 2389 { 2390 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); 2391 } 2392 2393 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf) 2394 { 2395 PnvMachineState *pnv = PNV_MACHINE(obj); 2396 int i; 2397 2398 for (i = 0; i < pnv->num_chips; i++) { 2399 PnvChip *chip = pnv->chips[i]; 2400 2401 /* First CPU presenters */ 2402 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf); 2403 2404 /* Then other devices, PHB, PSI, XIVE */ 2405 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); 2406 } 2407 } 2408 2409 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2410 uint8_t nvt_blk, uint32_t nvt_idx, 2411 bool cam_ignore, uint8_t priority, 2412 uint32_t logic_serv, 2413 XiveTCTXMatch *match) 2414 { 2415 PnvMachineState *pnv = PNV_MACHINE(xfb); 2416 int total_count = 0; 2417 int i; 2418 2419 for (i = 0; i < pnv->num_chips; i++) { 2420 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2421 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2422 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2423 int count; 2424 2425 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2426 priority, logic_serv, match); 2427 2428 if (count < 0) { 2429 return count; 2430 } 2431 2432 total_count += count; 2433 } 2434 2435 return total_count; 2436 } 2437 2438 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2439 uint8_t nvt_blk, uint32_t nvt_idx, 2440 bool cam_ignore, uint8_t priority, 2441 uint32_t logic_serv, 2442 XiveTCTXMatch *match) 2443 { 2444 PnvMachineState *pnv = PNV_MACHINE(xfb); 2445 int total_count = 0; 2446 int i; 2447 2448 for (i = 0; i < pnv->num_chips; i++) { 2449 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2450 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2451 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2452 int count; 2453 2454 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2455 priority, logic_serv, match); 2456 2457 if (count < 0) { 2458 return count; 2459 } 2460 2461 total_count += count; 2462 } 2463 2464 return total_count; 2465 } 2466 2467 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2468 { 2469 MachineClass *mc = MACHINE_CLASS(oc); 2470 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2471 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2472 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2473 2474 static GlobalProperty phb_compat[] = { 2475 { TYPE_PNV_PHB, "version", "3" }, 2476 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2477 }; 2478 2479 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2480 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2481 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2482 2483 xic->icp_get = pnv_icp_get; 2484 xic->ics_get = pnv_ics_get; 2485 xic->ics_resend = pnv_ics_resend; 2486 2487 pmc->compat = compat; 2488 pmc->compat_size = sizeof(compat); 2489 2490 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2491 } 2492 2493 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2494 { 2495 MachineClass *mc = MACHINE_CLASS(oc); 2496 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2497 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2498 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2499 2500 static GlobalProperty phb_compat[] = { 2501 { TYPE_PNV_PHB, "version", "4" }, 2502 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2503 }; 2504 2505 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2506 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2507 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2508 2509 xfc->match_nvt = pnv_match_nvt; 2510 2511 pmc->compat = compat; 2512 pmc->compat_size = sizeof(compat); 2513 pmc->dt_power_mgt = pnv_dt_power_mgt; 2514 2515 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2516 } 2517 2518 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2519 { 2520 MachineClass *mc = MACHINE_CLASS(oc); 2521 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2522 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2523 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2524 2525 static GlobalProperty phb_compat[] = { 2526 { TYPE_PNV_PHB, "version", "5" }, 2527 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2528 }; 2529 2530 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2531 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2532 2533 mc->alias = "powernv"; 2534 2535 pmc->compat = compat; 2536 pmc->compat_size = sizeof(compat); 2537 pmc->dt_power_mgt = pnv_dt_power_mgt; 2538 2539 xfc->match_nvt = pnv10_xive_match_nvt; 2540 2541 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2542 } 2543 2544 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2545 { 2546 MachineClass *mc = MACHINE_CLASS(oc); 2547 2548 pnv_machine_p10_common_class_init(oc, data); 2549 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2550 } 2551 2552 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2553 { 2554 MachineClass *mc = MACHINE_CLASS(oc); 2555 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2556 2557 pnv_machine_p10_common_class_init(oc, data); 2558 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2559 pmc->i2c_init = pnv_rainier_i2c_init; 2560 } 2561 2562 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2563 { 2564 PnvMachineState *pnv = PNV_MACHINE(obj); 2565 2566 return !!pnv->fw_load_addr; 2567 } 2568 2569 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2570 { 2571 PnvMachineState *pnv = PNV_MACHINE(obj); 2572 2573 if (value) { 2574 pnv->fw_load_addr = 0x8000000; 2575 } 2576 } 2577 2578 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2579 { 2580 CPUPPCState *env = cpu_env(cs); 2581 2582 cpu_synchronize_state(cs); 2583 ppc_cpu_do_system_reset(cs); 2584 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2585 /* 2586 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2587 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2588 * (PPC_BIT(43)). 2589 */ 2590 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2591 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2592 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2593 } 2594 } else { 2595 /* 2596 * For non-powersave system resets, SRR1[42:45] are defined to be 2597 * implementation-dependent. The POWER9 User Manual specifies that 2598 * an external (SCOM driven, which may come from a BMC nmi command or 2599 * another CPU requesting a NMI IPI) system reset exception should be 2600 * 0b0010 (PPC_BIT(44)). 2601 */ 2602 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2603 } 2604 } 2605 2606 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque) 2607 { 2608 async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2609 } 2610 2611 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2612 { 2613 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2614 int i; 2615 2616 for (i = 0; i < pnv->num_chips; i++) { 2617 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL); 2618 } 2619 } 2620 2621 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2622 { 2623 MachineClass *mc = MACHINE_CLASS(oc); 2624 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2625 NMIClass *nc = NMI_CLASS(oc); 2626 2627 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2628 mc->init = pnv_init; 2629 mc->reset = pnv_reset; 2630 mc->max_cpus = MAX_CPUS; 2631 /* Pnv provides a AHCI device for storage */ 2632 mc->block_default_type = IF_IDE; 2633 mc->no_parallel = 1; 2634 mc->default_boot_order = NULL; 2635 /* 2636 * RAM defaults to less than 2048 for 32-bit hosts, and large 2637 * enough to fit the maximum initrd size at it's load address 2638 */ 2639 mc->default_ram_size = 1 * GiB; 2640 mc->default_ram_id = "pnv.ram"; 2641 ispc->print_info = pnv_pic_print_info; 2642 nc->nmi_monitor_handler = pnv_nmi; 2643 2644 object_class_property_add_bool(oc, "hb-mode", 2645 pnv_machine_get_hb, pnv_machine_set_hb); 2646 object_class_property_set_description(oc, "hb-mode", 2647 "Use a hostboot like boot loader"); 2648 } 2649 2650 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2651 { \ 2652 .name = type, \ 2653 .class_init = class_initfn, \ 2654 .parent = TYPE_PNV8_CHIP, \ 2655 } 2656 2657 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2658 { \ 2659 .name = type, \ 2660 .class_init = class_initfn, \ 2661 .parent = TYPE_PNV9_CHIP, \ 2662 } 2663 2664 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2665 { \ 2666 .name = type, \ 2667 .class_init = class_initfn, \ 2668 .parent = TYPE_PNV10_CHIP, \ 2669 } 2670 2671 static const TypeInfo types[] = { 2672 { 2673 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2674 .parent = MACHINE_TYPE_NAME("powernv10"), 2675 .class_init = pnv_machine_p10_rainier_class_init, 2676 }, 2677 { 2678 .name = MACHINE_TYPE_NAME("powernv10"), 2679 .parent = TYPE_PNV_MACHINE, 2680 .class_init = pnv_machine_power10_class_init, 2681 .interfaces = (InterfaceInfo[]) { 2682 { TYPE_XIVE_FABRIC }, 2683 { }, 2684 }, 2685 }, 2686 { 2687 .name = MACHINE_TYPE_NAME("powernv9"), 2688 .parent = TYPE_PNV_MACHINE, 2689 .class_init = pnv_machine_power9_class_init, 2690 .interfaces = (InterfaceInfo[]) { 2691 { TYPE_XIVE_FABRIC }, 2692 { }, 2693 }, 2694 }, 2695 { 2696 .name = MACHINE_TYPE_NAME("powernv8"), 2697 .parent = TYPE_PNV_MACHINE, 2698 .class_init = pnv_machine_power8_class_init, 2699 .interfaces = (InterfaceInfo[]) { 2700 { TYPE_XICS_FABRIC }, 2701 { }, 2702 }, 2703 }, 2704 { 2705 .name = TYPE_PNV_MACHINE, 2706 .parent = TYPE_MACHINE, 2707 .abstract = true, 2708 .instance_size = sizeof(PnvMachineState), 2709 .class_init = pnv_machine_class_init, 2710 .class_size = sizeof(PnvMachineClass), 2711 .interfaces = (InterfaceInfo[]) { 2712 { TYPE_INTERRUPT_STATS_PROVIDER }, 2713 { TYPE_NMI }, 2714 { }, 2715 }, 2716 }, 2717 { 2718 .name = TYPE_PNV_CHIP, 2719 .parent = TYPE_SYS_BUS_DEVICE, 2720 .class_init = pnv_chip_class_init, 2721 .instance_size = sizeof(PnvChip), 2722 .class_size = sizeof(PnvChipClass), 2723 .abstract = true, 2724 }, 2725 2726 /* 2727 * P10 chip and variants 2728 */ 2729 { 2730 .name = TYPE_PNV10_CHIP, 2731 .parent = TYPE_PNV_CHIP, 2732 .instance_init = pnv_chip_power10_instance_init, 2733 .instance_size = sizeof(Pnv10Chip), 2734 }, 2735 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2736 2737 /* 2738 * P9 chip and variants 2739 */ 2740 { 2741 .name = TYPE_PNV9_CHIP, 2742 .parent = TYPE_PNV_CHIP, 2743 .instance_init = pnv_chip_power9_instance_init, 2744 .instance_size = sizeof(Pnv9Chip), 2745 }, 2746 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2747 2748 /* 2749 * P8 chip and variants 2750 */ 2751 { 2752 .name = TYPE_PNV8_CHIP, 2753 .parent = TYPE_PNV_CHIP, 2754 .instance_init = pnv_chip_power8_instance_init, 2755 .instance_size = sizeof(Pnv8Chip), 2756 }, 2757 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2758 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2759 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2760 pnv_chip_power8nvl_class_init), 2761 }; 2762 2763 DEFINE_TYPES(types) 2764