1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 #include "hw/pci/msi.h" 44 45 #include "hw/ppc/xics.h" 46 #include "hw/qdev-properties.h" 47 #include "hw/ppc/pnv_xscom.h" 48 #include "hw/ppc/pnv_pnor.h" 49 50 #include "hw/isa/isa.h" 51 #include "hw/boards.h" 52 #include "hw/char/serial.h" 53 #include "hw/rtc/mc146818rtc.h" 54 55 #include <libfdt.h> 56 57 #define FDT_MAX_SIZE (1 * MiB) 58 59 #define FW_FILE_NAME "skiboot.lid" 60 #define FW_LOAD_ADDR 0x0 61 #define FW_MAX_SIZE (4 * MiB) 62 63 #define KERNEL_LOAD_ADDR 0x20000000 64 #define KERNEL_MAX_SIZE (256 * MiB) 65 #define INITRD_LOAD_ADDR 0x60000000 66 #define INITRD_MAX_SIZE (256 * MiB) 67 68 static const char *pnv_chip_core_typename(const PnvChip *o) 69 { 70 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 71 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 72 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 73 const char *core_type = object_class_get_name(object_class_by_name(s)); 74 g_free(s); 75 return core_type; 76 } 77 78 /* 79 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 80 * 4 * 4 sockets * 12 cores * 8 threads = 1536 81 * Let's make it 2^11 82 */ 83 #define MAX_CPUS 2048 84 85 /* 86 * Memory nodes are created by hostboot, one for each range of memory 87 * that has a different "affinity". In practice, it means one range 88 * per chip. 89 */ 90 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 91 { 92 char *mem_name; 93 uint64_t mem_reg_property[2]; 94 int off; 95 96 mem_reg_property[0] = cpu_to_be64(start); 97 mem_reg_property[1] = cpu_to_be64(size); 98 99 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 100 off = fdt_add_subnode(fdt, 0, mem_name); 101 g_free(mem_name); 102 103 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 104 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 105 sizeof(mem_reg_property)))); 106 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 107 } 108 109 static int get_cpus_node(void *fdt) 110 { 111 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 112 113 if (cpus_offset < 0) { 114 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 115 if (cpus_offset) { 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 117 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 118 } 119 } 120 _FDT(cpus_offset); 121 return cpus_offset; 122 } 123 124 /* 125 * The PowerNV cores (and threads) need to use real HW ids and not an 126 * incremental index like it has been done on other platforms. This HW 127 * id is stored in the CPU PIR, it is used to create cpu nodes in the 128 * device tree, used in XSCOM to address cores and in interrupt 129 * servers. 130 */ 131 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 132 { 133 PowerPCCPU *cpu = pc->threads[0]; 134 CPUState *cs = CPU(cpu); 135 DeviceClass *dc = DEVICE_GET_CLASS(cs); 136 int smt_threads = CPU_CORE(pc)->nr_threads; 137 CPUPPCState *env = &cpu->env; 138 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 139 uint32_t servers_prop[smt_threads]; 140 int i; 141 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 142 0xffffffff, 0xffffffff}; 143 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 144 uint32_t cpufreq = 1000000000; 145 uint32_t page_sizes_prop[64]; 146 size_t page_sizes_prop_size; 147 const uint8_t pa_features[] = { 24, 0, 148 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 149 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 150 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 151 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 152 int offset; 153 char *nodename; 154 int cpus_offset = get_cpus_node(fdt); 155 156 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 157 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 158 _FDT(offset); 159 g_free(nodename); 160 161 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 165 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 166 167 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 168 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 169 env->dcache_line_size))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 173 env->icache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 175 env->icache_line_size))); 176 177 if (pcc->l1_dcache_size) { 178 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 179 pcc->l1_dcache_size))); 180 } else { 181 warn_report("Unknown L1 dcache size for cpu"); 182 } 183 if (pcc->l1_icache_size) { 184 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 185 pcc->l1_icache_size))); 186 } else { 187 warn_report("Unknown L1 icache size for cpu"); 188 } 189 190 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 192 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 193 cpu->hash64_opts->slb_size))); 194 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 195 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 196 197 if (env->spr_cb[SPR_PURR].oea_read) { 198 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 199 } 200 201 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 202 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 203 segs, sizeof(segs)))); 204 } 205 206 /* 207 * Advertise VMX/VSX (vector extensions) if available 208 * 0 / no property == no vector extensions 209 * 1 == VMX / Altivec available 210 * 2 == VSX available 211 */ 212 if (env->insns_flags & PPC_ALTIVEC) { 213 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 214 215 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 216 } 217 218 /* 219 * Advertise DFP (Decimal Floating Point) if available 220 * 0 / no property == no DFP 221 * 1 == DFP available 222 */ 223 if (env->insns_flags2 & PPC2_DFP) { 224 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 225 } 226 227 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 228 sizeof(page_sizes_prop)); 229 if (page_sizes_prop_size) { 230 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 231 page_sizes_prop, page_sizes_prop_size))); 232 } 233 234 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 235 pa_features, sizeof(pa_features)))); 236 237 /* Build interrupt servers properties */ 238 for (i = 0; i < smt_threads; i++) { 239 servers_prop[i] = cpu_to_be32(pc->pir + i); 240 } 241 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 242 servers_prop, sizeof(servers_prop)))); 243 } 244 245 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 246 uint32_t nr_threads) 247 { 248 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 249 char *name; 250 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 251 uint32_t irange[2], i, rsize; 252 uint64_t *reg; 253 int offset; 254 255 irange[0] = cpu_to_be32(pir); 256 irange[1] = cpu_to_be32(nr_threads); 257 258 rsize = sizeof(uint64_t) * 2 * nr_threads; 259 reg = g_malloc(rsize); 260 for (i = 0; i < nr_threads; i++) { 261 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 262 reg[i * 2 + 1] = cpu_to_be64(0x1000); 263 } 264 265 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 266 offset = fdt_add_subnode(fdt, 0, name); 267 _FDT(offset); 268 g_free(name); 269 270 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 271 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 272 _FDT((fdt_setprop_string(fdt, offset, "device_type", 273 "PowerPC-External-Interrupt-Presentation"))); 274 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 275 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 276 irange, sizeof(irange)))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 278 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 279 g_free(reg); 280 } 281 282 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 283 { 284 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 285 int i; 286 287 pnv_dt_xscom(chip, fdt, 0, 288 cpu_to_be64(PNV_XSCOM_BASE(chip)), 289 cpu_to_be64(PNV_XSCOM_SIZE), 290 compat, sizeof(compat)); 291 292 for (i = 0; i < chip->nr_cores; i++) { 293 PnvCore *pnv_core = chip->cores[i]; 294 295 pnv_dt_core(chip, pnv_core, fdt); 296 297 /* Interrupt Control Presenters (ICP). One per core. */ 298 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 299 } 300 301 if (chip->ram_size) { 302 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 303 } 304 } 305 306 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 307 { 308 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 309 int i; 310 311 pnv_dt_xscom(chip, fdt, 0, 312 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 313 cpu_to_be64(PNV9_XSCOM_SIZE), 314 compat, sizeof(compat)); 315 316 for (i = 0; i < chip->nr_cores; i++) { 317 PnvCore *pnv_core = chip->cores[i]; 318 319 pnv_dt_core(chip, pnv_core, fdt); 320 } 321 322 if (chip->ram_size) { 323 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 324 } 325 326 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 327 } 328 329 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 330 { 331 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 332 int i; 333 334 pnv_dt_xscom(chip, fdt, 0, 335 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 336 cpu_to_be64(PNV10_XSCOM_SIZE), 337 compat, sizeof(compat)); 338 339 for (i = 0; i < chip->nr_cores; i++) { 340 PnvCore *pnv_core = chip->cores[i]; 341 342 pnv_dt_core(chip, pnv_core, fdt); 343 } 344 345 if (chip->ram_size) { 346 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 347 } 348 349 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 350 } 351 352 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 353 { 354 uint32_t io_base = d->ioport_id; 355 uint32_t io_regs[] = { 356 cpu_to_be32(1), 357 cpu_to_be32(io_base), 358 cpu_to_be32(2) 359 }; 360 char *name; 361 int node; 362 363 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 364 node = fdt_add_subnode(fdt, lpc_off, name); 365 _FDT(node); 366 g_free(name); 367 368 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 369 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 370 } 371 372 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 373 { 374 const char compatible[] = "ns16550\0pnpPNP,501"; 375 uint32_t io_base = d->ioport_id; 376 uint32_t io_regs[] = { 377 cpu_to_be32(1), 378 cpu_to_be32(io_base), 379 cpu_to_be32(8) 380 }; 381 char *name; 382 int node; 383 384 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 385 node = fdt_add_subnode(fdt, lpc_off, name); 386 _FDT(node); 387 g_free(name); 388 389 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 390 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 391 sizeof(compatible)))); 392 393 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 394 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 395 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 396 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 397 fdt_get_phandle(fdt, lpc_off)))); 398 399 /* This is needed by Linux */ 400 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 401 } 402 403 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 404 { 405 const char compatible[] = "bt\0ipmi-bt"; 406 uint32_t io_base; 407 uint32_t io_regs[] = { 408 cpu_to_be32(1), 409 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 410 cpu_to_be32(3) 411 }; 412 uint32_t irq; 413 char *name; 414 int node; 415 416 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 417 io_regs[1] = cpu_to_be32(io_base); 418 419 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 420 421 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 422 node = fdt_add_subnode(fdt, lpc_off, name); 423 _FDT(node); 424 g_free(name); 425 426 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 427 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 428 sizeof(compatible)))); 429 430 /* Mark it as reserved to avoid Linux trying to claim it */ 431 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 432 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 433 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 434 fdt_get_phandle(fdt, lpc_off)))); 435 } 436 437 typedef struct ForeachPopulateArgs { 438 void *fdt; 439 int offset; 440 } ForeachPopulateArgs; 441 442 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 443 { 444 ForeachPopulateArgs *args = opaque; 445 ISADevice *d = ISA_DEVICE(dev); 446 447 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 448 pnv_dt_rtc(d, args->fdt, args->offset); 449 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 450 pnv_dt_serial(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 452 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 453 } else { 454 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 455 d->ioport_id); 456 } 457 458 return 0; 459 } 460 461 /* 462 * The default LPC bus of a multichip system is on chip 0. It's 463 * recognized by the firmware (skiboot) using a "primary" property. 464 */ 465 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 466 { 467 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 468 ForeachPopulateArgs args = { 469 .fdt = fdt, 470 .offset = isa_offset, 471 }; 472 uint32_t phandle; 473 474 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 475 476 phandle = qemu_fdt_alloc_phandle(fdt); 477 assert(phandle > 0); 478 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 479 480 /* 481 * ISA devices are not necessarily parented to the ISA bus so we 482 * can not use object_child_foreach() 483 */ 484 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 485 &args); 486 } 487 488 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 489 { 490 int off; 491 492 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 493 off = fdt_add_subnode(fdt, off, "power-mgt"); 494 495 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 496 } 497 498 static void *pnv_dt_create(MachineState *machine) 499 { 500 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 501 PnvMachineState *pnv = PNV_MACHINE(machine); 502 void *fdt; 503 char *buf; 504 int off; 505 int i; 506 507 fdt = g_malloc0(FDT_MAX_SIZE); 508 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 509 510 /* /qemu node */ 511 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 512 513 /* Root node */ 514 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 515 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 516 _FDT((fdt_setprop_string(fdt, 0, "model", 517 "IBM PowerNV (emulated by qemu)"))); 518 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 519 520 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 521 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 522 if (qemu_uuid_set) { 523 _FDT((fdt_property_string(fdt, "system-id", buf))); 524 } 525 g_free(buf); 526 527 off = fdt_add_subnode(fdt, 0, "chosen"); 528 if (machine->kernel_cmdline) { 529 _FDT((fdt_setprop_string(fdt, off, "bootargs", 530 machine->kernel_cmdline))); 531 } 532 533 if (pnv->initrd_size) { 534 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 535 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 536 537 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 538 &start_prop, sizeof(start_prop)))); 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 540 &end_prop, sizeof(end_prop)))); 541 } 542 543 /* Populate device tree for each chip */ 544 for (i = 0; i < pnv->num_chips; i++) { 545 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 546 } 547 548 /* Populate ISA devices on chip 0 */ 549 pnv_dt_isa(pnv, fdt); 550 551 if (pnv->bmc) { 552 pnv_dt_bmc_sensors(pnv->bmc, fdt); 553 } 554 555 /* Create an extra node for power management on machines that support it */ 556 if (pmc->dt_power_mgt) { 557 pmc->dt_power_mgt(pnv, fdt); 558 } 559 560 return fdt; 561 } 562 563 static void pnv_powerdown_notify(Notifier *n, void *opaque) 564 { 565 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 566 567 if (pnv->bmc) { 568 pnv_bmc_powerdown(pnv->bmc); 569 } 570 } 571 572 static void pnv_reset(MachineState *machine) 573 { 574 void *fdt; 575 576 qemu_devices_reset(); 577 578 fdt = pnv_dt_create(machine); 579 580 /* Pack resulting tree */ 581 _FDT((fdt_pack(fdt))); 582 583 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 584 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 585 } 586 587 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 588 { 589 Pnv8Chip *chip8 = PNV8_CHIP(chip); 590 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 591 } 592 593 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 594 { 595 Pnv8Chip *chip8 = PNV8_CHIP(chip); 596 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 597 } 598 599 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 600 { 601 Pnv9Chip *chip9 = PNV9_CHIP(chip); 602 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 603 } 604 605 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 606 { 607 Pnv10Chip *chip10 = PNV10_CHIP(chip); 608 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 609 } 610 611 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 612 { 613 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 614 } 615 616 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 617 { 618 Pnv8Chip *chip8 = PNV8_CHIP(chip); 619 620 ics_pic_print_info(&chip8->psi.ics, mon); 621 } 622 623 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 624 { 625 Pnv9Chip *chip9 = PNV9_CHIP(chip); 626 int i, j; 627 628 pnv_xive_pic_print_info(&chip9->xive, mon); 629 pnv_psi_pic_print_info(&chip9->psi, mon); 630 631 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 632 PnvPhb4PecState *pec = &chip9->pecs[i]; 633 for (j = 0; j < pec->num_stacks; j++) { 634 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 635 } 636 } 637 } 638 639 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 640 uint32_t core_id) 641 { 642 return PNV_XSCOM_EX_BASE(core_id); 643 } 644 645 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 646 uint32_t core_id) 647 { 648 return PNV9_XSCOM_EC_BASE(core_id); 649 } 650 651 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 652 uint32_t core_id) 653 { 654 return PNV10_XSCOM_EC_BASE(core_id); 655 } 656 657 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 658 { 659 PowerPCCPUClass *ppc_default = 660 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 661 PowerPCCPUClass *ppc = 662 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 663 664 return ppc_default->pvr_match(ppc_default, ppc->pvr); 665 } 666 667 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 668 { 669 Object *obj; 670 671 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 672 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 673 object_property_set_int(obj, irq, "irq", &error_fatal); 674 object_property_set_bool(obj, true, "realized", &error_fatal); 675 } 676 677 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 678 { 679 Pnv10Chip *chip10 = PNV10_CHIP(chip); 680 681 pnv_psi_pic_print_info(&chip10->psi, mon); 682 } 683 684 static void pnv_init(MachineState *machine) 685 { 686 PnvMachineState *pnv = PNV_MACHINE(machine); 687 MachineClass *mc = MACHINE_GET_CLASS(machine); 688 MemoryRegion *ram; 689 char *fw_filename; 690 long fw_size; 691 int i; 692 char *chip_typename; 693 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 694 DeviceState *dev; 695 696 /* allocate RAM */ 697 if (machine->ram_size < (1 * GiB)) { 698 warn_report("skiboot may not work with < 1GB of RAM"); 699 } 700 701 ram = g_new(MemoryRegion, 1); 702 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 703 machine->ram_size); 704 memory_region_add_subregion(get_system_memory(), 0, ram); 705 706 /* 707 * Create our simple PNOR device 708 */ 709 dev = qdev_create(NULL, TYPE_PNV_PNOR); 710 if (pnor) { 711 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 712 &error_abort); 713 } 714 qdev_init_nofail(dev); 715 pnv->pnor = PNV_PNOR(dev); 716 717 /* load skiboot firmware */ 718 if (bios_name == NULL) { 719 bios_name = FW_FILE_NAME; 720 } 721 722 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 723 if (!fw_filename) { 724 error_report("Could not find OPAL firmware '%s'", bios_name); 725 exit(1); 726 } 727 728 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 729 if (fw_size < 0) { 730 error_report("Could not load OPAL firmware '%s'", fw_filename); 731 exit(1); 732 } 733 g_free(fw_filename); 734 735 /* load kernel */ 736 if (machine->kernel_filename) { 737 long kernel_size; 738 739 kernel_size = load_image_targphys(machine->kernel_filename, 740 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 741 if (kernel_size < 0) { 742 error_report("Could not load kernel '%s'", 743 machine->kernel_filename); 744 exit(1); 745 } 746 } 747 748 /* load initrd */ 749 if (machine->initrd_filename) { 750 pnv->initrd_base = INITRD_LOAD_ADDR; 751 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 752 pnv->initrd_base, INITRD_MAX_SIZE); 753 if (pnv->initrd_size < 0) { 754 error_report("Could not load initial ram disk '%s'", 755 machine->initrd_filename); 756 exit(1); 757 } 758 } 759 760 /* MSIs are supported on this platform */ 761 msi_nonbroken = true; 762 763 /* 764 * Check compatibility of the specified CPU with the machine 765 * default. 766 */ 767 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 768 error_report("invalid CPU model '%s' for %s machine", 769 machine->cpu_type, mc->name); 770 exit(1); 771 } 772 773 /* Create the processor chips */ 774 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 775 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 776 i, machine->cpu_type); 777 if (!object_class_by_name(chip_typename)) { 778 error_report("invalid chip model '%.*s' for %s machine", 779 i, machine->cpu_type, mc->name); 780 exit(1); 781 } 782 783 pnv->num_chips = 784 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 785 /* 786 * TODO: should we decide on how many chips we can create based 787 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 788 */ 789 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 790 error_report("invalid number of chips: '%d'", pnv->num_chips); 791 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 792 exit(1); 793 } 794 795 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 796 for (i = 0; i < pnv->num_chips; i++) { 797 char chip_name[32]; 798 Object *chip = object_new(chip_typename); 799 800 pnv->chips[i] = PNV_CHIP(chip); 801 802 /* 803 * TODO: put all the memory in one node on chip 0 until we find a 804 * way to specify different ranges for each chip 805 */ 806 if (i == 0) { 807 object_property_set_int(chip, machine->ram_size, "ram-size", 808 &error_fatal); 809 } 810 811 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 812 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 813 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 814 &error_fatal); 815 object_property_set_int(chip, machine->smp.cores, 816 "nr-cores", &error_fatal); 817 object_property_set_int(chip, machine->smp.threads, 818 "nr-threads", &error_fatal); 819 /* 820 * The POWER8 machine use the XICS interrupt interface. 821 * Propagate the XICS fabric to the chip and its controllers. 822 */ 823 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 824 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); 825 } 826 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 827 object_property_set_link(chip, OBJECT(pnv), "xive-fabric", 828 &error_abort); 829 } 830 object_property_set_bool(chip, true, "realized", &error_fatal); 831 } 832 g_free(chip_typename); 833 834 /* Create the machine BMC simulator */ 835 pnv->bmc = pnv_bmc_create(pnv->pnor); 836 837 /* Instantiate ISA bus on chip 0 */ 838 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 839 840 /* Create serial port */ 841 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 842 843 /* Create an RTC ISA device too */ 844 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 845 846 /* Create the IPMI BT device for communication with the BMC */ 847 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 848 849 /* 850 * OpenPOWER systems use a IPMI SEL Event message to notify the 851 * host to powerdown 852 */ 853 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 854 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 855 } 856 857 /* 858 * 0:21 Reserved - Read as zeros 859 * 22:24 Chip ID 860 * 25:28 Core number 861 * 29:31 Thread ID 862 */ 863 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 864 { 865 return (chip->chip_id << 7) | (core_id << 3); 866 } 867 868 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 869 Error **errp) 870 { 871 Pnv8Chip *chip8 = PNV8_CHIP(chip); 872 Error *local_err = NULL; 873 Object *obj; 874 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 875 876 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 877 if (local_err) { 878 error_propagate(errp, local_err); 879 return; 880 } 881 882 pnv_cpu->intc = obj; 883 } 884 885 886 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 887 { 888 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 889 890 icp_reset(ICP(pnv_cpu->intc)); 891 } 892 893 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 894 { 895 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 896 897 icp_destroy(ICP(pnv_cpu->intc)); 898 pnv_cpu->intc = NULL; 899 } 900 901 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 902 Monitor *mon) 903 { 904 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 905 } 906 907 /* 908 * 0:48 Reserved - Read as zeroes 909 * 49:52 Node ID 910 * 53:55 Chip ID 911 * 56 Reserved - Read as zero 912 * 57:61 Core number 913 * 62:63 Thread ID 914 * 915 * We only care about the lower bits. uint32_t is fine for the moment. 916 */ 917 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 918 { 919 return (chip->chip_id << 8) | (core_id << 2); 920 } 921 922 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 923 { 924 return (chip->chip_id << 8) | (core_id << 2); 925 } 926 927 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 928 Error **errp) 929 { 930 Pnv9Chip *chip9 = PNV9_CHIP(chip); 931 Error *local_err = NULL; 932 Object *obj; 933 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 934 935 /* 936 * The core creates its interrupt presenter but the XIVE interrupt 937 * controller object is initialized afterwards. Hopefully, it's 938 * only used at runtime. 939 */ 940 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 941 &local_err); 942 if (local_err) { 943 error_propagate(errp, local_err); 944 return; 945 } 946 947 pnv_cpu->intc = obj; 948 } 949 950 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 951 { 952 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 953 954 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 955 } 956 957 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 958 { 959 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 960 961 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 962 pnv_cpu->intc = NULL; 963 } 964 965 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 966 Monitor *mon) 967 { 968 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 969 } 970 971 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 972 Error **errp) 973 { 974 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 975 976 /* Will be defined when the interrupt controller is */ 977 pnv_cpu->intc = NULL; 978 } 979 980 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 981 { 982 ; 983 } 984 985 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 986 { 987 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 988 989 pnv_cpu->intc = NULL; 990 } 991 992 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 993 Monitor *mon) 994 { 995 } 996 997 /* 998 * Allowed core identifiers on a POWER8 Processor Chip : 999 * 1000 * <EX0 reserved> 1001 * EX1 - Venice only 1002 * EX2 - Venice only 1003 * EX3 - Venice only 1004 * EX4 1005 * EX5 1006 * EX6 1007 * <EX7,8 reserved> <reserved> 1008 * EX9 - Venice only 1009 * EX10 - Venice only 1010 * EX11 - Venice only 1011 * EX12 1012 * EX13 1013 * EX14 1014 * <EX15 reserved> 1015 */ 1016 #define POWER8E_CORE_MASK (0x7070ull) 1017 #define POWER8_CORE_MASK (0x7e7eull) 1018 1019 /* 1020 * POWER9 has 24 cores, ids starting at 0x0 1021 */ 1022 #define POWER9_CORE_MASK (0xffffffffffffffull) 1023 1024 1025 #define POWER10_CORE_MASK (0xffffffffffffffull) 1026 1027 static void pnv_chip_power8_instance_init(Object *obj) 1028 { 1029 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1030 1031 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1032 (Object **)&chip8->xics, 1033 object_property_allow_set_link, 1034 OBJ_PROP_LINK_STRONG, 1035 &error_abort); 1036 1037 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 1038 TYPE_PNV8_PSI, &error_abort, NULL); 1039 1040 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 1041 TYPE_PNV8_LPC, &error_abort, NULL); 1042 1043 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 1044 TYPE_PNV8_OCC, &error_abort, NULL); 1045 1046 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 1047 TYPE_PNV8_HOMER, &error_abort, NULL); 1048 } 1049 1050 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1051 { 1052 PnvChip *chip = PNV_CHIP(chip8); 1053 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1054 int i, j; 1055 char *name; 1056 1057 name = g_strdup_printf("icp-%x", chip->chip_id); 1058 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1059 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1060 g_free(name); 1061 1062 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1063 1064 /* Map the ICP registers for each thread */ 1065 for (i = 0; i < chip->nr_cores; i++) { 1066 PnvCore *pnv_core = chip->cores[i]; 1067 int core_hwid = CPU_CORE(pnv_core)->core_id; 1068 1069 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1070 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1071 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1072 1073 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1074 &icp->mmio); 1075 } 1076 } 1077 } 1078 1079 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1080 { 1081 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1082 PnvChip *chip = PNV_CHIP(dev); 1083 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1084 Pnv8Psi *psi8 = &chip8->psi; 1085 Error *local_err = NULL; 1086 1087 assert(chip8->xics); 1088 1089 /* XSCOM bridge is first */ 1090 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1091 if (local_err) { 1092 error_propagate(errp, local_err); 1093 return; 1094 } 1095 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1096 1097 pcc->parent_realize(dev, &local_err); 1098 if (local_err) { 1099 error_propagate(errp, local_err); 1100 return; 1101 } 1102 1103 /* Processor Service Interface (PSI) Host Bridge */ 1104 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1105 "bar", &error_fatal); 1106 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), 1107 ICS_PROP_XICS, &error_abort); 1108 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 1109 if (local_err) { 1110 error_propagate(errp, local_err); 1111 return; 1112 } 1113 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1114 &PNV_PSI(psi8)->xscom_regs); 1115 1116 /* Create LPC controller */ 1117 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1118 &error_abort); 1119 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 1120 &error_fatal); 1121 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1122 1123 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1124 (uint64_t) PNV_XSCOM_BASE(chip), 1125 PNV_XSCOM_LPC_BASE); 1126 1127 /* 1128 * Interrupt Management Area. This is the memory region holding 1129 * all the Interrupt Control Presenter (ICP) registers 1130 */ 1131 pnv_chip_icp_realize(chip8, &local_err); 1132 if (local_err) { 1133 error_propagate(errp, local_err); 1134 return; 1135 } 1136 1137 /* Create the simplified OCC model */ 1138 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1139 &error_abort); 1140 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1141 if (local_err) { 1142 error_propagate(errp, local_err); 1143 return; 1144 } 1145 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1146 1147 /* OCC SRAM model */ 1148 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1149 &chip8->occ.sram_regs); 1150 1151 /* HOMER */ 1152 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1153 &error_abort); 1154 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1155 &local_err); 1156 if (local_err) { 1157 error_propagate(errp, local_err); 1158 return; 1159 } 1160 /* Homer Xscom region */ 1161 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1162 1163 /* Homer mmio region */ 1164 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1165 &chip8->homer.regs); 1166 } 1167 1168 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1169 { 1170 addr &= (PNV_XSCOM_SIZE - 1); 1171 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1172 } 1173 1174 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1175 { 1176 DeviceClass *dc = DEVICE_CLASS(klass); 1177 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1178 1179 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1180 k->cores_mask = POWER8E_CORE_MASK; 1181 k->core_pir = pnv_chip_core_pir_p8; 1182 k->intc_create = pnv_chip_power8_intc_create; 1183 k->intc_reset = pnv_chip_power8_intc_reset; 1184 k->intc_destroy = pnv_chip_power8_intc_destroy; 1185 k->intc_print_info = pnv_chip_power8_intc_print_info; 1186 k->isa_create = pnv_chip_power8_isa_create; 1187 k->dt_populate = pnv_chip_power8_dt_populate; 1188 k->pic_print_info = pnv_chip_power8_pic_print_info; 1189 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1190 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1191 dc->desc = "PowerNV Chip POWER8E"; 1192 1193 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1194 &k->parent_realize); 1195 } 1196 1197 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1198 { 1199 DeviceClass *dc = DEVICE_CLASS(klass); 1200 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1201 1202 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1203 k->cores_mask = POWER8_CORE_MASK; 1204 k->core_pir = pnv_chip_core_pir_p8; 1205 k->intc_create = pnv_chip_power8_intc_create; 1206 k->intc_reset = pnv_chip_power8_intc_reset; 1207 k->intc_destroy = pnv_chip_power8_intc_destroy; 1208 k->intc_print_info = pnv_chip_power8_intc_print_info; 1209 k->isa_create = pnv_chip_power8_isa_create; 1210 k->dt_populate = pnv_chip_power8_dt_populate; 1211 k->pic_print_info = pnv_chip_power8_pic_print_info; 1212 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1213 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1214 dc->desc = "PowerNV Chip POWER8"; 1215 1216 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1217 &k->parent_realize); 1218 } 1219 1220 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1221 { 1222 DeviceClass *dc = DEVICE_CLASS(klass); 1223 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1224 1225 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1226 k->cores_mask = POWER8_CORE_MASK; 1227 k->core_pir = pnv_chip_core_pir_p8; 1228 k->intc_create = pnv_chip_power8_intc_create; 1229 k->intc_reset = pnv_chip_power8_intc_reset; 1230 k->intc_destroy = pnv_chip_power8_intc_destroy; 1231 k->intc_print_info = pnv_chip_power8_intc_print_info; 1232 k->isa_create = pnv_chip_power8nvl_isa_create; 1233 k->dt_populate = pnv_chip_power8_dt_populate; 1234 k->pic_print_info = pnv_chip_power8_pic_print_info; 1235 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1236 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1237 dc->desc = "PowerNV Chip POWER8NVL"; 1238 1239 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1240 &k->parent_realize); 1241 } 1242 1243 static void pnv_chip_power9_instance_init(Object *obj) 1244 { 1245 PnvChip *chip = PNV_CHIP(obj); 1246 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1247 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1248 int i; 1249 1250 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1251 TYPE_PNV_XIVE, &error_abort, NULL); 1252 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1253 "xive-fabric", &error_abort); 1254 1255 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1256 TYPE_PNV9_PSI, &error_abort, NULL); 1257 1258 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1259 TYPE_PNV9_LPC, &error_abort, NULL); 1260 1261 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1262 TYPE_PNV9_OCC, &error_abort, NULL); 1263 1264 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1265 TYPE_PNV9_HOMER, &error_abort, NULL); 1266 1267 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1268 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1269 sizeof(chip9->pecs[i]), TYPE_PNV_PHB4_PEC, 1270 &error_abort, NULL); 1271 } 1272 1273 /* 1274 * Number of PHBs is the chip default 1275 */ 1276 chip->num_phbs = pcc->num_phbs; 1277 } 1278 1279 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1280 { 1281 PnvChip *chip = PNV_CHIP(chip9); 1282 int i; 1283 1284 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1285 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1286 1287 for (i = 0; i < chip9->nr_quads; i++) { 1288 char eq_name[32]; 1289 PnvQuad *eq = &chip9->quads[i]; 1290 PnvCore *pnv_core = chip->cores[i * 4]; 1291 int core_id = CPU_CORE(pnv_core)->core_id; 1292 1293 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1294 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1295 TYPE_PNV_QUAD, &error_fatal, NULL); 1296 1297 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1298 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1299 1300 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1301 &eq->xscom_regs); 1302 } 1303 } 1304 1305 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1306 { 1307 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1308 Error *local_err = NULL; 1309 int i, j; 1310 int phb_id = 0; 1311 1312 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1313 PnvPhb4PecState *pec = &chip9->pecs[i]; 1314 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1315 uint32_t pec_nest_base; 1316 uint32_t pec_pci_base; 1317 1318 object_property_set_int(OBJECT(pec), i, "index", &error_fatal); 1319 /* 1320 * PEC0 -> 1 stack 1321 * PEC1 -> 2 stacks 1322 * PEC2 -> 3 stacks 1323 */ 1324 object_property_set_int(OBJECT(pec), i + 1, "num-stacks", 1325 &error_fatal); 1326 object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id", 1327 &error_fatal); 1328 object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()), 1329 "system-memory", &error_abort); 1330 object_property_set_bool(OBJECT(pec), true, "realized", &local_err); 1331 if (local_err) { 1332 error_propagate(errp, local_err); 1333 return; 1334 } 1335 1336 pec_nest_base = pecc->xscom_nest_base(pec); 1337 pec_pci_base = pecc->xscom_pci_base(pec); 1338 1339 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1340 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1341 1342 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1343 j++, phb_id++) { 1344 PnvPhb4PecStack *stack = &pec->stacks[j]; 1345 Object *obj = OBJECT(&stack->phb); 1346 1347 object_property_set_int(obj, phb_id, "index", &error_fatal); 1348 object_property_set_int(obj, chip->chip_id, "chip-id", 1349 &error_fatal); 1350 object_property_set_int(obj, PNV_PHB4_VERSION, "version", 1351 &error_fatal); 1352 object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id", 1353 &error_fatal); 1354 object_property_set_link(obj, OBJECT(stack), "stack", &error_abort); 1355 object_property_set_bool(obj, true, "realized", &local_err); 1356 if (local_err) { 1357 error_propagate(errp, local_err); 1358 return; 1359 } 1360 qdev_set_parent_bus(DEVICE(obj), sysbus_get_default()); 1361 1362 /* Populate the XSCOM address space. */ 1363 pnv_xscom_add_subregion(chip, 1364 pec_nest_base + 0x40 * (stack->stack_no + 1), 1365 &stack->nest_regs_mr); 1366 pnv_xscom_add_subregion(chip, 1367 pec_pci_base + 0x40 * (stack->stack_no + 1), 1368 &stack->pci_regs_mr); 1369 pnv_xscom_add_subregion(chip, 1370 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1371 0x40 * stack->stack_no, 1372 &stack->phb_regs_mr); 1373 } 1374 } 1375 } 1376 1377 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1378 { 1379 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1380 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1381 PnvChip *chip = PNV_CHIP(dev); 1382 Pnv9Psi *psi9 = &chip9->psi; 1383 Error *local_err = NULL; 1384 1385 /* XSCOM bridge is first */ 1386 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1387 if (local_err) { 1388 error_propagate(errp, local_err); 1389 return; 1390 } 1391 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1392 1393 pcc->parent_realize(dev, &local_err); 1394 if (local_err) { 1395 error_propagate(errp, local_err); 1396 return; 1397 } 1398 1399 pnv_chip_quad_realize(chip9, &local_err); 1400 if (local_err) { 1401 error_propagate(errp, local_err); 1402 return; 1403 } 1404 1405 /* XIVE interrupt controller (POWER9) */ 1406 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1407 "ic-bar", &error_fatal); 1408 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1409 "vc-bar", &error_fatal); 1410 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1411 "pc-bar", &error_fatal); 1412 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1413 "tm-bar", &error_fatal); 1414 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1415 &error_abort); 1416 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1417 &local_err); 1418 if (local_err) { 1419 error_propagate(errp, local_err); 1420 return; 1421 } 1422 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1423 &chip9->xive.xscom_regs); 1424 1425 /* Processor Service Interface (PSI) Host Bridge */ 1426 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1427 "bar", &error_fatal); 1428 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1429 if (local_err) { 1430 error_propagate(errp, local_err); 1431 return; 1432 } 1433 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1434 &PNV_PSI(psi9)->xscom_regs); 1435 1436 /* LPC */ 1437 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1438 &error_abort); 1439 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1440 if (local_err) { 1441 error_propagate(errp, local_err); 1442 return; 1443 } 1444 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1445 &chip9->lpc.xscom_regs); 1446 1447 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1448 (uint64_t) PNV9_LPCM_BASE(chip)); 1449 1450 /* Create the simplified OCC model */ 1451 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1452 &error_abort); 1453 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1454 if (local_err) { 1455 error_propagate(errp, local_err); 1456 return; 1457 } 1458 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1459 1460 /* OCC SRAM model */ 1461 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1462 &chip9->occ.sram_regs); 1463 1464 /* HOMER */ 1465 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1466 &error_abort); 1467 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1468 &local_err); 1469 if (local_err) { 1470 error_propagate(errp, local_err); 1471 return; 1472 } 1473 /* Homer Xscom region */ 1474 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1475 1476 /* Homer mmio region */ 1477 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1478 &chip9->homer.regs); 1479 1480 /* PHBs */ 1481 pnv_chip_power9_phb_realize(chip, &local_err); 1482 if (local_err) { 1483 error_propagate(errp, local_err); 1484 return; 1485 } 1486 } 1487 1488 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1489 { 1490 addr &= (PNV9_XSCOM_SIZE - 1); 1491 return addr >> 3; 1492 } 1493 1494 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1495 { 1496 DeviceClass *dc = DEVICE_CLASS(klass); 1497 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1498 1499 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1500 k->cores_mask = POWER9_CORE_MASK; 1501 k->core_pir = pnv_chip_core_pir_p9; 1502 k->intc_create = pnv_chip_power9_intc_create; 1503 k->intc_reset = pnv_chip_power9_intc_reset; 1504 k->intc_destroy = pnv_chip_power9_intc_destroy; 1505 k->intc_print_info = pnv_chip_power9_intc_print_info; 1506 k->isa_create = pnv_chip_power9_isa_create; 1507 k->dt_populate = pnv_chip_power9_dt_populate; 1508 k->pic_print_info = pnv_chip_power9_pic_print_info; 1509 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1510 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1511 dc->desc = "PowerNV Chip POWER9"; 1512 k->num_phbs = 6; 1513 1514 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1515 &k->parent_realize); 1516 } 1517 1518 static void pnv_chip_power10_instance_init(Object *obj) 1519 { 1520 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1521 1522 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), 1523 TYPE_PNV10_PSI, &error_abort, NULL); 1524 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), 1525 TYPE_PNV10_LPC, &error_abort, NULL); 1526 } 1527 1528 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1529 { 1530 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1531 PnvChip *chip = PNV_CHIP(dev); 1532 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1533 Error *local_err = NULL; 1534 1535 /* XSCOM bridge is first */ 1536 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1537 if (local_err) { 1538 error_propagate(errp, local_err); 1539 return; 1540 } 1541 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1542 1543 pcc->parent_realize(dev, &local_err); 1544 if (local_err) { 1545 error_propagate(errp, local_err); 1546 return; 1547 } 1548 1549 /* Processor Service Interface (PSI) Host Bridge */ 1550 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1551 "bar", &error_fatal); 1552 object_property_set_bool(OBJECT(&chip10->psi), true, "realized", 1553 &local_err); 1554 if (local_err) { 1555 error_propagate(errp, local_err); 1556 return; 1557 } 1558 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1559 &PNV_PSI(&chip10->psi)->xscom_regs); 1560 1561 /* LPC */ 1562 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1563 &error_abort); 1564 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", 1565 &local_err); 1566 if (local_err) { 1567 error_propagate(errp, local_err); 1568 return; 1569 } 1570 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1571 &chip10->lpc.xscom_regs); 1572 1573 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1574 (uint64_t) PNV10_LPCM_BASE(chip)); 1575 } 1576 1577 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1578 { 1579 addr &= (PNV10_XSCOM_SIZE - 1); 1580 return addr >> 3; 1581 } 1582 1583 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1584 { 1585 DeviceClass *dc = DEVICE_CLASS(klass); 1586 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1587 1588 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1589 k->cores_mask = POWER10_CORE_MASK; 1590 k->core_pir = pnv_chip_core_pir_p10; 1591 k->intc_create = pnv_chip_power10_intc_create; 1592 k->intc_reset = pnv_chip_power10_intc_reset; 1593 k->intc_destroy = pnv_chip_power10_intc_destroy; 1594 k->intc_print_info = pnv_chip_power10_intc_print_info; 1595 k->isa_create = pnv_chip_power10_isa_create; 1596 k->dt_populate = pnv_chip_power10_dt_populate; 1597 k->pic_print_info = pnv_chip_power10_pic_print_info; 1598 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1599 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1600 dc->desc = "PowerNV Chip POWER10"; 1601 1602 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1603 &k->parent_realize); 1604 } 1605 1606 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1607 { 1608 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1609 int cores_max; 1610 1611 /* 1612 * No custom mask for this chip, let's use the default one from * 1613 * the chip class 1614 */ 1615 if (!chip->cores_mask) { 1616 chip->cores_mask = pcc->cores_mask; 1617 } 1618 1619 /* filter alien core ids ! some are reserved */ 1620 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1621 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1622 chip->cores_mask); 1623 return; 1624 } 1625 chip->cores_mask &= pcc->cores_mask; 1626 1627 /* now that we have a sane layout, let check the number of cores */ 1628 cores_max = ctpop64(chip->cores_mask); 1629 if (chip->nr_cores > cores_max) { 1630 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1631 cores_max); 1632 return; 1633 } 1634 } 1635 1636 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1637 { 1638 Error *error = NULL; 1639 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1640 const char *typename = pnv_chip_core_typename(chip); 1641 int i, core_hwid; 1642 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1643 1644 if (!object_class_by_name(typename)) { 1645 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1646 return; 1647 } 1648 1649 /* Cores */ 1650 pnv_chip_core_sanitize(chip, &error); 1651 if (error) { 1652 error_propagate(errp, error); 1653 return; 1654 } 1655 1656 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1657 1658 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1659 && (i < chip->nr_cores); core_hwid++) { 1660 char core_name[32]; 1661 PnvCore *pnv_core; 1662 uint64_t xscom_core_base; 1663 1664 if (!(chip->cores_mask & (1ull << core_hwid))) { 1665 continue; 1666 } 1667 1668 pnv_core = PNV_CORE(object_new(typename)); 1669 1670 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1671 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1672 &error_abort); 1673 chip->cores[i] = pnv_core; 1674 object_property_set_int(OBJECT(pnv_core), chip->nr_threads, 1675 "nr-threads", &error_fatal); 1676 object_property_set_int(OBJECT(pnv_core), core_hwid, 1677 CPU_CORE_PROP_CORE_ID, &error_fatal); 1678 object_property_set_int(OBJECT(pnv_core), 1679 pcc->core_pir(chip, core_hwid), 1680 "pir", &error_fatal); 1681 object_property_set_int(OBJECT(pnv_core), pnv->fw_load_addr, 1682 "hrmor", &error_fatal); 1683 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1684 &error_abort); 1685 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1686 &error_fatal); 1687 1688 /* Each core has an XSCOM MMIO region */ 1689 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1690 1691 pnv_xscom_add_subregion(chip, xscom_core_base, 1692 &pnv_core->xscom_regs); 1693 i++; 1694 } 1695 } 1696 1697 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1698 { 1699 PnvChip *chip = PNV_CHIP(dev); 1700 Error *error = NULL; 1701 1702 /* Cores */ 1703 pnv_chip_core_realize(chip, &error); 1704 if (error) { 1705 error_propagate(errp, error); 1706 return; 1707 } 1708 } 1709 1710 static Property pnv_chip_properties[] = { 1711 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1712 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1713 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1714 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1715 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1716 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1717 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1718 DEFINE_PROP_END_OF_LIST(), 1719 }; 1720 1721 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1722 { 1723 DeviceClass *dc = DEVICE_CLASS(klass); 1724 1725 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1726 dc->realize = pnv_chip_realize; 1727 device_class_set_props(dc, pnv_chip_properties); 1728 dc->desc = "PowerNV Chip"; 1729 } 1730 1731 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1732 { 1733 int i, j; 1734 1735 for (i = 0; i < chip->nr_cores; i++) { 1736 PnvCore *pc = chip->cores[i]; 1737 CPUCore *cc = CPU_CORE(pc); 1738 1739 for (j = 0; j < cc->nr_threads; j++) { 1740 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1741 return pc->threads[j]; 1742 } 1743 } 1744 } 1745 return NULL; 1746 } 1747 1748 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1749 { 1750 PnvMachineState *pnv = PNV_MACHINE(xi); 1751 int i; 1752 1753 for (i = 0; i < pnv->num_chips; i++) { 1754 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1755 1756 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1757 return &chip8->psi.ics; 1758 } 1759 } 1760 return NULL; 1761 } 1762 1763 static void pnv_ics_resend(XICSFabric *xi) 1764 { 1765 PnvMachineState *pnv = PNV_MACHINE(xi); 1766 int i; 1767 1768 for (i = 0; i < pnv->num_chips; i++) { 1769 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1770 ics_resend(&chip8->psi.ics); 1771 } 1772 } 1773 1774 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1775 { 1776 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1777 1778 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1779 } 1780 1781 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1782 Monitor *mon) 1783 { 1784 PnvMachineState *pnv = PNV_MACHINE(obj); 1785 int i; 1786 CPUState *cs; 1787 1788 CPU_FOREACH(cs) { 1789 PowerPCCPU *cpu = POWERPC_CPU(cs); 1790 1791 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1792 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1793 mon); 1794 } 1795 1796 for (i = 0; i < pnv->num_chips; i++) { 1797 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1798 } 1799 } 1800 1801 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1802 uint8_t nvt_blk, uint32_t nvt_idx, 1803 bool cam_ignore, uint8_t priority, 1804 uint32_t logic_serv, 1805 XiveTCTXMatch *match) 1806 { 1807 PnvMachineState *pnv = PNV_MACHINE(xfb); 1808 int total_count = 0; 1809 int i; 1810 1811 for (i = 0; i < pnv->num_chips; i++) { 1812 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1813 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1814 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1815 int count; 1816 1817 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1818 priority, logic_serv, match); 1819 1820 if (count < 0) { 1821 return count; 1822 } 1823 1824 total_count += count; 1825 } 1826 1827 return total_count; 1828 } 1829 1830 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1831 { 1832 MachineClass *mc = MACHINE_CLASS(oc); 1833 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1834 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1835 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1836 1837 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1838 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1839 1840 xic->icp_get = pnv_icp_get; 1841 xic->ics_get = pnv_ics_get; 1842 xic->ics_resend = pnv_ics_resend; 1843 1844 pmc->compat = compat; 1845 pmc->compat_size = sizeof(compat); 1846 } 1847 1848 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1849 { 1850 MachineClass *mc = MACHINE_CLASS(oc); 1851 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1852 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1853 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1854 1855 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1856 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1857 xfc->match_nvt = pnv_match_nvt; 1858 1859 mc->alias = "powernv"; 1860 1861 pmc->compat = compat; 1862 pmc->compat_size = sizeof(compat); 1863 pmc->dt_power_mgt = pnv_dt_power_mgt; 1864 } 1865 1866 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1867 { 1868 MachineClass *mc = MACHINE_CLASS(oc); 1869 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1870 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1871 1872 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1873 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1874 1875 pmc->compat = compat; 1876 pmc->compat_size = sizeof(compat); 1877 pmc->dt_power_mgt = pnv_dt_power_mgt; 1878 } 1879 1880 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1881 { 1882 PnvMachineState *pnv = PNV_MACHINE(obj); 1883 1884 return !!pnv->fw_load_addr; 1885 } 1886 1887 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1888 { 1889 PnvMachineState *pnv = PNV_MACHINE(obj); 1890 1891 if (value) { 1892 pnv->fw_load_addr = 0x8000000; 1893 } 1894 } 1895 1896 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1897 { 1898 MachineClass *mc = MACHINE_CLASS(oc); 1899 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1900 1901 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1902 mc->init = pnv_init; 1903 mc->reset = pnv_reset; 1904 mc->max_cpus = MAX_CPUS; 1905 /* Pnv provides a AHCI device for storage */ 1906 mc->block_default_type = IF_IDE; 1907 mc->no_parallel = 1; 1908 mc->default_boot_order = NULL; 1909 /* 1910 * RAM defaults to less than 2048 for 32-bit hosts, and large 1911 * enough to fit the maximum initrd size at it's load address 1912 */ 1913 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1914 ispc->print_info = pnv_pic_print_info; 1915 1916 object_class_property_add_bool(oc, "hb-mode", 1917 pnv_machine_get_hb, pnv_machine_set_hb, 1918 &error_abort); 1919 object_class_property_set_description(oc, "hb-mode", 1920 "Use a hostboot like boot loader", 1921 NULL); 1922 } 1923 1924 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1925 { \ 1926 .name = type, \ 1927 .class_init = class_initfn, \ 1928 .parent = TYPE_PNV8_CHIP, \ 1929 } 1930 1931 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1932 { \ 1933 .name = type, \ 1934 .class_init = class_initfn, \ 1935 .parent = TYPE_PNV9_CHIP, \ 1936 } 1937 1938 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 1939 { \ 1940 .name = type, \ 1941 .class_init = class_initfn, \ 1942 .parent = TYPE_PNV10_CHIP, \ 1943 } 1944 1945 static const TypeInfo types[] = { 1946 { 1947 .name = MACHINE_TYPE_NAME("powernv10"), 1948 .parent = TYPE_PNV_MACHINE, 1949 .class_init = pnv_machine_power10_class_init, 1950 }, 1951 { 1952 .name = MACHINE_TYPE_NAME("powernv9"), 1953 .parent = TYPE_PNV_MACHINE, 1954 .class_init = pnv_machine_power9_class_init, 1955 .interfaces = (InterfaceInfo[]) { 1956 { TYPE_XIVE_FABRIC }, 1957 { }, 1958 }, 1959 }, 1960 { 1961 .name = MACHINE_TYPE_NAME("powernv8"), 1962 .parent = TYPE_PNV_MACHINE, 1963 .class_init = pnv_machine_power8_class_init, 1964 .interfaces = (InterfaceInfo[]) { 1965 { TYPE_XICS_FABRIC }, 1966 { }, 1967 }, 1968 }, 1969 { 1970 .name = TYPE_PNV_MACHINE, 1971 .parent = TYPE_MACHINE, 1972 .abstract = true, 1973 .instance_size = sizeof(PnvMachineState), 1974 .class_init = pnv_machine_class_init, 1975 .class_size = sizeof(PnvMachineClass), 1976 .interfaces = (InterfaceInfo[]) { 1977 { TYPE_INTERRUPT_STATS_PROVIDER }, 1978 { }, 1979 }, 1980 }, 1981 { 1982 .name = TYPE_PNV_CHIP, 1983 .parent = TYPE_SYS_BUS_DEVICE, 1984 .class_init = pnv_chip_class_init, 1985 .instance_size = sizeof(PnvChip), 1986 .class_size = sizeof(PnvChipClass), 1987 .abstract = true, 1988 }, 1989 1990 /* 1991 * P10 chip and variants 1992 */ 1993 { 1994 .name = TYPE_PNV10_CHIP, 1995 .parent = TYPE_PNV_CHIP, 1996 .instance_init = pnv_chip_power10_instance_init, 1997 .instance_size = sizeof(Pnv10Chip), 1998 }, 1999 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2000 2001 /* 2002 * P9 chip and variants 2003 */ 2004 { 2005 .name = TYPE_PNV9_CHIP, 2006 .parent = TYPE_PNV_CHIP, 2007 .instance_init = pnv_chip_power9_instance_init, 2008 .instance_size = sizeof(Pnv9Chip), 2009 }, 2010 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2011 2012 /* 2013 * P8 chip and variants 2014 */ 2015 { 2016 .name = TYPE_PNV8_CHIP, 2017 .parent = TYPE_PNV_CHIP, 2018 .instance_init = pnv_chip_power8_instance_init, 2019 .instance_size = sizeof(Pnv8Chip), 2020 }, 2021 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2022 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2023 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2024 pnv_chip_power8nvl_class_init), 2025 }; 2026 2027 DEFINE_TYPES(types) 2028