1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qapi/error.h" 23 #include "sysemu/sysemu.h" 24 #include "sysemu/numa.h" 25 #include "sysemu/cpus.h" 26 #include "hw/hw.h" 27 #include "target/ppc/cpu.h" 28 #include "qemu/log.h" 29 #include "hw/ppc/fdt.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/ppc/pnv.h" 32 #include "hw/ppc/pnv_core.h" 33 #include "hw/loader.h" 34 #include "exec/address-spaces.h" 35 #include "qapi/visitor.h" 36 #include "monitor/monitor.h" 37 #include "hw/intc/intc.h" 38 #include "hw/ipmi/ipmi.h" 39 #include "target/ppc/mmu-hash64.h" 40 41 #include "hw/ppc/xics.h" 42 #include "hw/ppc/pnv_xscom.h" 43 44 #include "hw/isa/isa.h" 45 #include "hw/char/serial.h" 46 #include "hw/timer/mc146818rtc.h" 47 48 #include <libfdt.h> 49 50 #define FDT_MAX_SIZE (1 * MiB) 51 52 #define FW_FILE_NAME "skiboot.lid" 53 #define FW_LOAD_ADDR 0x0 54 #define FW_MAX_SIZE (4 * MiB) 55 56 #define KERNEL_LOAD_ADDR 0x20000000 57 #define KERNEL_MAX_SIZE (256 * MiB) 58 #define INITRD_LOAD_ADDR 0x60000000 59 #define INITRD_MAX_SIZE (256 * MiB) 60 61 static const char *pnv_chip_core_typename(const PnvChip *o) 62 { 63 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 64 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 65 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 66 const char *core_type = object_class_get_name(object_class_by_name(s)); 67 g_free(s); 68 return core_type; 69 } 70 71 /* 72 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 73 * 4 * 4 sockets * 12 cores * 8 threads = 1536 74 * Let's make it 2^11 75 */ 76 #define MAX_CPUS 2048 77 78 /* 79 * Memory nodes are created by hostboot, one for each range of memory 80 * that has a different "affinity". In practice, it means one range 81 * per chip. 82 */ 83 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 84 { 85 char *mem_name; 86 uint64_t mem_reg_property[2]; 87 int off; 88 89 mem_reg_property[0] = cpu_to_be64(start); 90 mem_reg_property[1] = cpu_to_be64(size); 91 92 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 93 off = fdt_add_subnode(fdt, 0, mem_name); 94 g_free(mem_name); 95 96 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 97 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 98 sizeof(mem_reg_property)))); 99 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 100 } 101 102 static int get_cpus_node(void *fdt) 103 { 104 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 105 106 if (cpus_offset < 0) { 107 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 108 if (cpus_offset) { 109 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 110 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 111 } 112 } 113 _FDT(cpus_offset); 114 return cpus_offset; 115 } 116 117 /* 118 * The PowerNV cores (and threads) need to use real HW ids and not an 119 * incremental index like it has been done on other platforms. This HW 120 * id is stored in the CPU PIR, it is used to create cpu nodes in the 121 * device tree, used in XSCOM to address cores and in interrupt 122 * servers. 123 */ 124 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 125 { 126 PowerPCCPU *cpu = pc->threads[0]; 127 CPUState *cs = CPU(cpu); 128 DeviceClass *dc = DEVICE_GET_CLASS(cs); 129 int smt_threads = CPU_CORE(pc)->nr_threads; 130 CPUPPCState *env = &cpu->env; 131 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 132 uint32_t servers_prop[smt_threads]; 133 int i; 134 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 135 0xffffffff, 0xffffffff}; 136 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 137 uint32_t cpufreq = 1000000000; 138 uint32_t page_sizes_prop[64]; 139 size_t page_sizes_prop_size; 140 const uint8_t pa_features[] = { 24, 0, 141 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 142 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 143 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 144 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 145 int offset; 146 char *nodename; 147 int cpus_offset = get_cpus_node(fdt); 148 149 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 150 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 151 _FDT(offset); 152 g_free(nodename); 153 154 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 155 156 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 157 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 158 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 159 160 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 161 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 162 env->dcache_line_size))); 163 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 164 env->dcache_line_size))); 165 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 166 env->icache_line_size))); 167 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 168 env->icache_line_size))); 169 170 if (pcc->l1_dcache_size) { 171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 172 pcc->l1_dcache_size))); 173 } else { 174 warn_report("Unknown L1 dcache size for cpu"); 175 } 176 if (pcc->l1_icache_size) { 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 178 pcc->l1_icache_size))); 179 } else { 180 warn_report("Unknown L1 icache size for cpu"); 181 } 182 183 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 184 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 185 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 186 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 187 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 188 189 if (env->spr_cb[SPR_PURR].oea_read) { 190 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 191 } 192 193 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 194 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 195 segs, sizeof(segs)))); 196 } 197 198 /* Advertise VMX/VSX (vector extensions) if available 199 * 0 / no property == no vector extensions 200 * 1 == VMX / Altivec available 201 * 2 == VSX available */ 202 if (env->insns_flags & PPC_ALTIVEC) { 203 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 204 205 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 206 } 207 208 /* Advertise DFP (Decimal Floating Point) if available 209 * 0 / no property == no DFP 210 * 1 == DFP available */ 211 if (env->insns_flags2 & PPC2_DFP) { 212 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 213 } 214 215 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 216 sizeof(page_sizes_prop)); 217 if (page_sizes_prop_size) { 218 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 219 page_sizes_prop, page_sizes_prop_size))); 220 } 221 222 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 223 pa_features, sizeof(pa_features)))); 224 225 /* Build interrupt servers properties */ 226 for (i = 0; i < smt_threads; i++) { 227 servers_prop[i] = cpu_to_be32(pc->pir + i); 228 } 229 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 230 servers_prop, sizeof(servers_prop)))); 231 } 232 233 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 234 uint32_t nr_threads) 235 { 236 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 237 char *name; 238 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 239 uint32_t irange[2], i, rsize; 240 uint64_t *reg; 241 int offset; 242 243 irange[0] = cpu_to_be32(pir); 244 irange[1] = cpu_to_be32(nr_threads); 245 246 rsize = sizeof(uint64_t) * 2 * nr_threads; 247 reg = g_malloc(rsize); 248 for (i = 0; i < nr_threads; i++) { 249 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 250 reg[i * 2 + 1] = cpu_to_be64(0x1000); 251 } 252 253 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 254 offset = fdt_add_subnode(fdt, 0, name); 255 _FDT(offset); 256 g_free(name); 257 258 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 259 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 260 _FDT((fdt_setprop_string(fdt, offset, "device_type", 261 "PowerPC-External-Interrupt-Presentation"))); 262 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 263 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 264 irange, sizeof(irange)))); 265 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 266 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 267 g_free(reg); 268 } 269 270 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 271 { 272 const char *typename = pnv_chip_core_typename(chip); 273 size_t typesize = object_type_get_instance_size(typename); 274 int i; 275 276 pnv_dt_xscom(chip, fdt, 0); 277 278 for (i = 0; i < chip->nr_cores; i++) { 279 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 280 281 pnv_dt_core(chip, pnv_core, fdt); 282 283 /* Interrupt Control Presenters (ICP). One per core. */ 284 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 285 } 286 287 if (chip->ram_size) { 288 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 289 } 290 } 291 292 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 293 { 294 const char *typename = pnv_chip_core_typename(chip); 295 size_t typesize = object_type_get_instance_size(typename); 296 int i; 297 298 pnv_dt_xscom(chip, fdt, 0); 299 300 for (i = 0; i < chip->nr_cores; i++) { 301 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 302 303 pnv_dt_core(chip, pnv_core, fdt); 304 } 305 306 if (chip->ram_size) { 307 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 308 } 309 } 310 311 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 312 { 313 uint32_t io_base = d->ioport_id; 314 uint32_t io_regs[] = { 315 cpu_to_be32(1), 316 cpu_to_be32(io_base), 317 cpu_to_be32(2) 318 }; 319 char *name; 320 int node; 321 322 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 323 node = fdt_add_subnode(fdt, lpc_off, name); 324 _FDT(node); 325 g_free(name); 326 327 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 328 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 329 } 330 331 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 332 { 333 const char compatible[] = "ns16550\0pnpPNP,501"; 334 uint32_t io_base = d->ioport_id; 335 uint32_t io_regs[] = { 336 cpu_to_be32(1), 337 cpu_to_be32(io_base), 338 cpu_to_be32(8) 339 }; 340 char *name; 341 int node; 342 343 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 344 node = fdt_add_subnode(fdt, lpc_off, name); 345 _FDT(node); 346 g_free(name); 347 348 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 349 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 350 sizeof(compatible)))); 351 352 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 353 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 354 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 355 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 356 fdt_get_phandle(fdt, lpc_off)))); 357 358 /* This is needed by Linux */ 359 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 360 } 361 362 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 363 { 364 const char compatible[] = "bt\0ipmi-bt"; 365 uint32_t io_base; 366 uint32_t io_regs[] = { 367 cpu_to_be32(1), 368 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 369 cpu_to_be32(3) 370 }; 371 uint32_t irq; 372 char *name; 373 int node; 374 375 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 376 io_regs[1] = cpu_to_be32(io_base); 377 378 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 379 380 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 381 node = fdt_add_subnode(fdt, lpc_off, name); 382 _FDT(node); 383 g_free(name); 384 385 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 386 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 387 sizeof(compatible)))); 388 389 /* Mark it as reserved to avoid Linux trying to claim it */ 390 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 391 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 392 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 393 fdt_get_phandle(fdt, lpc_off)))); 394 } 395 396 typedef struct ForeachPopulateArgs { 397 void *fdt; 398 int offset; 399 } ForeachPopulateArgs; 400 401 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 402 { 403 ForeachPopulateArgs *args = opaque; 404 ISADevice *d = ISA_DEVICE(dev); 405 406 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 407 pnv_dt_rtc(d, args->fdt, args->offset); 408 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 409 pnv_dt_serial(d, args->fdt, args->offset); 410 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 411 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 412 } else { 413 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 414 d->ioport_id); 415 } 416 417 return 0; 418 } 419 420 static int pnv_chip_isa_offset(PnvChip *chip, void *fdt) 421 { 422 char *name; 423 int offset; 424 425 name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 426 (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE); 427 offset = fdt_path_offset(fdt, name); 428 g_free(name); 429 return offset; 430 } 431 432 /* The default LPC bus of a multichip system is on chip 0. It's 433 * recognized by the firmware (skiboot) using a "primary" property. 434 */ 435 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 436 { 437 int isa_offset = pnv_chip_isa_offset(pnv->chips[0], fdt); 438 ForeachPopulateArgs args = { 439 .fdt = fdt, 440 .offset = isa_offset, 441 }; 442 443 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 444 445 /* ISA devices are not necessarily parented to the ISA bus so we 446 * can not use object_child_foreach() */ 447 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 448 &args); 449 } 450 451 static void *pnv_dt_create(MachineState *machine) 452 { 453 const char plat_compat[] = "qemu,powernv\0ibm,powernv"; 454 PnvMachineState *pnv = PNV_MACHINE(machine); 455 void *fdt; 456 char *buf; 457 int off; 458 int i; 459 460 fdt = g_malloc0(FDT_MAX_SIZE); 461 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 462 463 /* Root node */ 464 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 465 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 466 _FDT((fdt_setprop_string(fdt, 0, "model", 467 "IBM PowerNV (emulated by qemu)"))); 468 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat, 469 sizeof(plat_compat)))); 470 471 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 472 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 473 if (qemu_uuid_set) { 474 _FDT((fdt_property_string(fdt, "system-id", buf))); 475 } 476 g_free(buf); 477 478 off = fdt_add_subnode(fdt, 0, "chosen"); 479 if (machine->kernel_cmdline) { 480 _FDT((fdt_setprop_string(fdt, off, "bootargs", 481 machine->kernel_cmdline))); 482 } 483 484 if (pnv->initrd_size) { 485 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 486 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 487 488 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 489 &start_prop, sizeof(start_prop)))); 490 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 491 &end_prop, sizeof(end_prop)))); 492 } 493 494 /* Populate device tree for each chip */ 495 for (i = 0; i < pnv->num_chips; i++) { 496 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 497 } 498 499 /* Populate ISA devices on chip 0 */ 500 pnv_dt_isa(pnv, fdt); 501 502 if (pnv->bmc) { 503 pnv_dt_bmc_sensors(pnv->bmc, fdt); 504 } 505 506 return fdt; 507 } 508 509 static void pnv_powerdown_notify(Notifier *n, void *opaque) 510 { 511 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 512 513 if (pnv->bmc) { 514 pnv_bmc_powerdown(pnv->bmc); 515 } 516 } 517 518 static void pnv_reset(void) 519 { 520 MachineState *machine = MACHINE(qdev_get_machine()); 521 PnvMachineState *pnv = PNV_MACHINE(machine); 522 void *fdt; 523 Object *obj; 524 525 qemu_devices_reset(); 526 527 /* OpenPOWER systems have a BMC, which can be defined on the 528 * command line with: 529 * 530 * -device ipmi-bmc-sim,id=bmc0 531 * 532 * This is the internal simulator but it could also be an external 533 * BMC. 534 */ 535 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); 536 if (obj) { 537 pnv->bmc = IPMI_BMC(obj); 538 } 539 540 fdt = pnv_dt_create(machine); 541 542 /* Pack resulting tree */ 543 _FDT((fdt_pack(fdt))); 544 545 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 546 } 547 548 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 549 { 550 Pnv8Chip *chip8 = PNV8_CHIP(chip); 551 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 552 } 553 554 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 555 { 556 Pnv8Chip *chip8 = PNV8_CHIP(chip); 557 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 558 } 559 560 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 561 { 562 return NULL; 563 } 564 565 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 566 { 567 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 568 } 569 570 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 571 { 572 Pnv8Chip *chip8 = PNV8_CHIP(chip); 573 574 ics_pic_print_info(&chip8->psi.ics, mon); 575 } 576 577 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 578 { 579 Pnv9Chip *chip9 = PNV9_CHIP(chip); 580 581 pnv_xive_pic_print_info(&chip9->xive, mon); 582 } 583 584 static void pnv_init(MachineState *machine) 585 { 586 PnvMachineState *pnv = PNV_MACHINE(machine); 587 MemoryRegion *ram; 588 char *fw_filename; 589 long fw_size; 590 int i; 591 char *chip_typename; 592 593 /* allocate RAM */ 594 if (machine->ram_size < (1 * GiB)) { 595 warn_report("skiboot may not work with < 1GB of RAM"); 596 } 597 598 ram = g_new(MemoryRegion, 1); 599 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 600 machine->ram_size); 601 memory_region_add_subregion(get_system_memory(), 0, ram); 602 603 /* load skiboot firmware */ 604 if (bios_name == NULL) { 605 bios_name = FW_FILE_NAME; 606 } 607 608 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 609 if (!fw_filename) { 610 error_report("Could not find OPAL firmware '%s'", bios_name); 611 exit(1); 612 } 613 614 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 615 if (fw_size < 0) { 616 error_report("Could not load OPAL firmware '%s'", fw_filename); 617 exit(1); 618 } 619 g_free(fw_filename); 620 621 /* load kernel */ 622 if (machine->kernel_filename) { 623 long kernel_size; 624 625 kernel_size = load_image_targphys(machine->kernel_filename, 626 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 627 if (kernel_size < 0) { 628 error_report("Could not load kernel '%s'", 629 machine->kernel_filename); 630 exit(1); 631 } 632 } 633 634 /* load initrd */ 635 if (machine->initrd_filename) { 636 pnv->initrd_base = INITRD_LOAD_ADDR; 637 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 638 pnv->initrd_base, INITRD_MAX_SIZE); 639 if (pnv->initrd_size < 0) { 640 error_report("Could not load initial ram disk '%s'", 641 machine->initrd_filename); 642 exit(1); 643 } 644 } 645 646 /* Create the processor chips */ 647 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 648 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 649 i, machine->cpu_type); 650 if (!object_class_by_name(chip_typename)) { 651 error_report("invalid CPU model '%.*s' for %s machine", 652 i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name); 653 exit(1); 654 } 655 656 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 657 for (i = 0; i < pnv->num_chips; i++) { 658 char chip_name[32]; 659 Object *chip = object_new(chip_typename); 660 661 pnv->chips[i] = PNV_CHIP(chip); 662 663 /* TODO: put all the memory in one node on chip 0 until we find a 664 * way to specify different ranges for each chip 665 */ 666 if (i == 0) { 667 object_property_set_int(chip, machine->ram_size, "ram-size", 668 &error_fatal); 669 } 670 671 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 672 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 673 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 674 &error_fatal); 675 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal); 676 object_property_set_bool(chip, true, "realized", &error_fatal); 677 } 678 g_free(chip_typename); 679 680 /* Instantiate ISA bus on chip 0 */ 681 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 682 683 /* Create serial port */ 684 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 685 686 /* Create an RTC ISA device too */ 687 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 688 689 /* OpenPOWER systems use a IPMI SEL Event message to notify the 690 * host to powerdown */ 691 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 692 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 693 } 694 695 /* 696 * 0:21 Reserved - Read as zeros 697 * 22:24 Chip ID 698 * 25:28 Core number 699 * 29:31 Thread ID 700 */ 701 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 702 { 703 return (chip->chip_id << 7) | (core_id << 3); 704 } 705 706 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 707 Error **errp) 708 { 709 Error *local_err = NULL; 710 Object *obj; 711 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 712 713 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 714 &local_err); 715 if (local_err) { 716 error_propagate(errp, local_err); 717 return; 718 } 719 720 pnv_cpu->intc = obj; 721 } 722 723 /* 724 * 0:48 Reserved - Read as zeroes 725 * 49:52 Node ID 726 * 53:55 Chip ID 727 * 56 Reserved - Read as zero 728 * 57:61 Core number 729 * 62:63 Thread ID 730 * 731 * We only care about the lower bits. uint32_t is fine for the moment. 732 */ 733 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 734 { 735 return (chip->chip_id << 8) | (core_id << 2); 736 } 737 738 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 739 Error **errp) 740 { 741 Pnv9Chip *chip9 = PNV9_CHIP(chip); 742 Error *local_err = NULL; 743 Object *obj; 744 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 745 746 /* 747 * The core creates its interrupt presenter but the XIVE interrupt 748 * controller object is initialized afterwards. Hopefully, it's 749 * only used at runtime. 750 */ 751 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), errp); 752 if (local_err) { 753 error_propagate(errp, local_err); 754 return; 755 } 756 757 pnv_cpu->intc = obj; 758 } 759 760 /* Allowed core identifiers on a POWER8 Processor Chip : 761 * 762 * <EX0 reserved> 763 * EX1 - Venice only 764 * EX2 - Venice only 765 * EX3 - Venice only 766 * EX4 767 * EX5 768 * EX6 769 * <EX7,8 reserved> <reserved> 770 * EX9 - Venice only 771 * EX10 - Venice only 772 * EX11 - Venice only 773 * EX12 774 * EX13 775 * EX14 776 * <EX15 reserved> 777 */ 778 #define POWER8E_CORE_MASK (0x7070ull) 779 #define POWER8_CORE_MASK (0x7e7eull) 780 781 /* 782 * POWER9 has 24 cores, ids starting at 0x0 783 */ 784 #define POWER9_CORE_MASK (0xffffffffffffffull) 785 786 static void pnv_chip_power8_instance_init(Object *obj) 787 { 788 Pnv8Chip *chip8 = PNV8_CHIP(obj); 789 790 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 791 TYPE_PNV_PSI, &error_abort, NULL); 792 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 793 OBJECT(qdev_get_machine()), &error_abort); 794 795 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 796 TYPE_PNV_LPC, &error_abort, NULL); 797 object_property_add_const_link(OBJECT(&chip8->lpc), "psi", 798 OBJECT(&chip8->psi), &error_abort); 799 800 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 801 TYPE_PNV_OCC, &error_abort, NULL); 802 object_property_add_const_link(OBJECT(&chip8->occ), "psi", 803 OBJECT(&chip8->psi), &error_abort); 804 } 805 806 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 807 { 808 PnvChip *chip = PNV_CHIP(chip8); 809 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 810 const char *typename = pnv_chip_core_typename(chip); 811 size_t typesize = object_type_get_instance_size(typename); 812 int i, j; 813 char *name; 814 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 815 816 name = g_strdup_printf("icp-%x", chip->chip_id); 817 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 818 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 819 g_free(name); 820 821 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 822 823 /* Map the ICP registers for each thread */ 824 for (i = 0; i < chip->nr_cores; i++) { 825 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 826 int core_hwid = CPU_CORE(pnv_core)->core_id; 827 828 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 829 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 830 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 831 832 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 833 &icp->mmio); 834 } 835 } 836 } 837 838 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 839 { 840 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 841 PnvChip *chip = PNV_CHIP(dev); 842 Pnv8Chip *chip8 = PNV8_CHIP(dev); 843 Error *local_err = NULL; 844 845 pcc->parent_realize(dev, &local_err); 846 if (local_err) { 847 error_propagate(errp, local_err); 848 return; 849 } 850 851 /* Processor Service Interface (PSI) Host Bridge */ 852 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 853 "bar", &error_fatal); 854 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 855 if (local_err) { 856 error_propagate(errp, local_err); 857 return; 858 } 859 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip8->psi.xscom_regs); 860 861 /* Create LPC controller */ 862 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 863 &error_fatal); 864 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 865 866 /* Interrupt Management Area. This is the memory region holding 867 * all the Interrupt Control Presenter (ICP) registers */ 868 pnv_chip_icp_realize(chip8, &local_err); 869 if (local_err) { 870 error_propagate(errp, local_err); 871 return; 872 } 873 874 /* Create the simplified OCC model */ 875 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 876 if (local_err) { 877 error_propagate(errp, local_err); 878 return; 879 } 880 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 881 } 882 883 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 884 { 885 DeviceClass *dc = DEVICE_CLASS(klass); 886 PnvChipClass *k = PNV_CHIP_CLASS(klass); 887 888 k->chip_type = PNV_CHIP_POWER8E; 889 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 890 k->cores_mask = POWER8E_CORE_MASK; 891 k->core_pir = pnv_chip_core_pir_p8; 892 k->intc_create = pnv_chip_power8_intc_create; 893 k->isa_create = pnv_chip_power8_isa_create; 894 k->dt_populate = pnv_chip_power8_dt_populate; 895 k->pic_print_info = pnv_chip_power8_pic_print_info; 896 k->xscom_base = 0x003fc0000000000ull; 897 dc->desc = "PowerNV Chip POWER8E"; 898 899 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 900 &k->parent_realize); 901 } 902 903 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 904 { 905 DeviceClass *dc = DEVICE_CLASS(klass); 906 PnvChipClass *k = PNV_CHIP_CLASS(klass); 907 908 k->chip_type = PNV_CHIP_POWER8; 909 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 910 k->cores_mask = POWER8_CORE_MASK; 911 k->core_pir = pnv_chip_core_pir_p8; 912 k->intc_create = pnv_chip_power8_intc_create; 913 k->isa_create = pnv_chip_power8_isa_create; 914 k->dt_populate = pnv_chip_power8_dt_populate; 915 k->pic_print_info = pnv_chip_power8_pic_print_info; 916 k->xscom_base = 0x003fc0000000000ull; 917 dc->desc = "PowerNV Chip POWER8"; 918 919 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 920 &k->parent_realize); 921 } 922 923 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 924 { 925 DeviceClass *dc = DEVICE_CLASS(klass); 926 PnvChipClass *k = PNV_CHIP_CLASS(klass); 927 928 k->chip_type = PNV_CHIP_POWER8NVL; 929 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 930 k->cores_mask = POWER8_CORE_MASK; 931 k->core_pir = pnv_chip_core_pir_p8; 932 k->intc_create = pnv_chip_power8_intc_create; 933 k->isa_create = pnv_chip_power8nvl_isa_create; 934 k->dt_populate = pnv_chip_power8_dt_populate; 935 k->pic_print_info = pnv_chip_power8_pic_print_info; 936 k->xscom_base = 0x003fc0000000000ull; 937 dc->desc = "PowerNV Chip POWER8NVL"; 938 939 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 940 &k->parent_realize); 941 } 942 943 static void pnv_chip_power9_instance_init(Object *obj) 944 { 945 Pnv9Chip *chip9 = PNV9_CHIP(obj); 946 947 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 948 TYPE_PNV_XIVE, &error_abort, NULL); 949 object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj, 950 &error_abort); 951 } 952 953 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 954 { 955 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 956 Pnv9Chip *chip9 = PNV9_CHIP(dev); 957 PnvChip *chip = PNV_CHIP(dev); 958 Error *local_err = NULL; 959 960 pcc->parent_realize(dev, &local_err); 961 if (local_err) { 962 error_propagate(errp, local_err); 963 return; 964 } 965 966 /* XIVE interrupt controller (POWER9) */ 967 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 968 "ic-bar", &error_fatal); 969 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 970 "vc-bar", &error_fatal); 971 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 972 "pc-bar", &error_fatal); 973 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 974 "tm-bar", &error_fatal); 975 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 976 &local_err); 977 if (local_err) { 978 error_propagate(errp, local_err); 979 return; 980 } 981 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 982 &chip9->xive.xscom_regs); 983 } 984 985 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 986 { 987 DeviceClass *dc = DEVICE_CLASS(klass); 988 PnvChipClass *k = PNV_CHIP_CLASS(klass); 989 990 k->chip_type = PNV_CHIP_POWER9; 991 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 992 k->cores_mask = POWER9_CORE_MASK; 993 k->core_pir = pnv_chip_core_pir_p9; 994 k->intc_create = pnv_chip_power9_intc_create; 995 k->isa_create = pnv_chip_power9_isa_create; 996 k->dt_populate = pnv_chip_power9_dt_populate; 997 k->pic_print_info = pnv_chip_power9_pic_print_info; 998 k->xscom_base = 0x00603fc00000000ull; 999 dc->desc = "PowerNV Chip POWER9"; 1000 1001 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1002 &k->parent_realize); 1003 } 1004 1005 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1006 { 1007 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1008 int cores_max; 1009 1010 /* 1011 * No custom mask for this chip, let's use the default one from * 1012 * the chip class 1013 */ 1014 if (!chip->cores_mask) { 1015 chip->cores_mask = pcc->cores_mask; 1016 } 1017 1018 /* filter alien core ids ! some are reserved */ 1019 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1020 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1021 chip->cores_mask); 1022 return; 1023 } 1024 chip->cores_mask &= pcc->cores_mask; 1025 1026 /* now that we have a sane layout, let check the number of cores */ 1027 cores_max = ctpop64(chip->cores_mask); 1028 if (chip->nr_cores > cores_max) { 1029 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1030 cores_max); 1031 return; 1032 } 1033 } 1034 1035 static void pnv_chip_instance_init(Object *obj) 1036 { 1037 PNV_CHIP(obj)->xscom_base = PNV_CHIP_GET_CLASS(obj)->xscom_base; 1038 } 1039 1040 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1041 { 1042 Error *error = NULL; 1043 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1044 const char *typename = pnv_chip_core_typename(chip); 1045 size_t typesize = object_type_get_instance_size(typename); 1046 int i, core_hwid; 1047 1048 if (!object_class_by_name(typename)) { 1049 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1050 return; 1051 } 1052 1053 /* Cores */ 1054 pnv_chip_core_sanitize(chip, &error); 1055 if (error) { 1056 error_propagate(errp, error); 1057 return; 1058 } 1059 1060 chip->cores = g_malloc0(typesize * chip->nr_cores); 1061 1062 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1063 && (i < chip->nr_cores); core_hwid++) { 1064 char core_name[32]; 1065 void *pnv_core = chip->cores + i * typesize; 1066 uint64_t xscom_core_base; 1067 1068 if (!(chip->cores_mask & (1ull << core_hwid))) { 1069 continue; 1070 } 1071 1072 object_initialize(pnv_core, typesize, typename); 1073 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1074 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1075 &error_fatal); 1076 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads", 1077 &error_fatal); 1078 object_property_set_int(OBJECT(pnv_core), core_hwid, 1079 CPU_CORE_PROP_CORE_ID, &error_fatal); 1080 object_property_set_int(OBJECT(pnv_core), 1081 pcc->core_pir(chip, core_hwid), 1082 "pir", &error_fatal); 1083 object_property_add_const_link(OBJECT(pnv_core), "chip", 1084 OBJECT(chip), &error_fatal); 1085 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1086 &error_fatal); 1087 object_unref(OBJECT(pnv_core)); 1088 1089 /* Each core has an XSCOM MMIO region */ 1090 if (!pnv_chip_is_power9(chip)) { 1091 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); 1092 } else { 1093 xscom_core_base = PNV_XSCOM_P9_EC_BASE(core_hwid); 1094 } 1095 1096 pnv_xscom_add_subregion(chip, xscom_core_base, 1097 &PNV_CORE(pnv_core)->xscom_regs); 1098 i++; 1099 } 1100 } 1101 1102 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1103 { 1104 PnvChip *chip = PNV_CHIP(dev); 1105 Error *error = NULL; 1106 1107 /* XSCOM bridge */ 1108 pnv_xscom_realize(chip, &error); 1109 if (error) { 1110 error_propagate(errp, error); 1111 return; 1112 } 1113 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1114 1115 /* Cores */ 1116 pnv_chip_core_realize(chip, &error); 1117 if (error) { 1118 error_propagate(errp, error); 1119 return; 1120 } 1121 } 1122 1123 static Property pnv_chip_properties[] = { 1124 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1125 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1126 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1127 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1128 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1129 DEFINE_PROP_END_OF_LIST(), 1130 }; 1131 1132 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1133 { 1134 DeviceClass *dc = DEVICE_CLASS(klass); 1135 1136 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1137 dc->realize = pnv_chip_realize; 1138 dc->props = pnv_chip_properties; 1139 dc->desc = "PowerNV Chip"; 1140 } 1141 1142 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1143 { 1144 PnvMachineState *pnv = PNV_MACHINE(xi); 1145 int i; 1146 1147 for (i = 0; i < pnv->num_chips; i++) { 1148 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1149 1150 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1151 return &chip8->psi.ics; 1152 } 1153 } 1154 return NULL; 1155 } 1156 1157 static void pnv_ics_resend(XICSFabric *xi) 1158 { 1159 PnvMachineState *pnv = PNV_MACHINE(xi); 1160 int i; 1161 1162 for (i = 0; i < pnv->num_chips; i++) { 1163 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1164 ics_resend(&chip8->psi.ics); 1165 } 1166 } 1167 1168 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1169 { 1170 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1171 1172 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1173 } 1174 1175 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1176 Monitor *mon) 1177 { 1178 PnvMachineState *pnv = PNV_MACHINE(obj); 1179 int i; 1180 CPUState *cs; 1181 1182 CPU_FOREACH(cs) { 1183 PowerPCCPU *cpu = POWERPC_CPU(cs); 1184 1185 if (pnv_chip_is_power9(pnv->chips[0])) { 1186 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1187 } else { 1188 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1189 } 1190 } 1191 1192 for (i = 0; i < pnv->num_chips; i++) { 1193 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1194 } 1195 } 1196 1197 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1198 void *opaque, Error **errp) 1199 { 1200 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1201 } 1202 1203 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1204 void *opaque, Error **errp) 1205 { 1206 PnvMachineState *pnv = PNV_MACHINE(obj); 1207 uint32_t num_chips; 1208 Error *local_err = NULL; 1209 1210 visit_type_uint32(v, name, &num_chips, &local_err); 1211 if (local_err) { 1212 error_propagate(errp, local_err); 1213 return; 1214 } 1215 1216 /* 1217 * TODO: should we decide on how many chips we can create based 1218 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1219 */ 1220 if (!is_power_of_2(num_chips) || num_chips > 4) { 1221 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1222 return; 1223 } 1224 1225 pnv->num_chips = num_chips; 1226 } 1227 1228 static void pnv_machine_instance_init(Object *obj) 1229 { 1230 PnvMachineState *pnv = PNV_MACHINE(obj); 1231 pnv->num_chips = 1; 1232 } 1233 1234 static void pnv_machine_class_props_init(ObjectClass *oc) 1235 { 1236 object_class_property_add(oc, "num-chips", "uint32", 1237 pnv_get_num_chips, pnv_set_num_chips, 1238 NULL, NULL, NULL); 1239 object_class_property_set_description(oc, "num-chips", 1240 "Specifies the number of processor chips", 1241 NULL); 1242 } 1243 1244 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1245 { 1246 MachineClass *mc = MACHINE_CLASS(oc); 1247 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1248 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1249 1250 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1251 mc->init = pnv_init; 1252 mc->reset = pnv_reset; 1253 mc->max_cpus = MAX_CPUS; 1254 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1255 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for 1256 * storage */ 1257 mc->no_parallel = 1; 1258 mc->default_boot_order = NULL; 1259 mc->default_ram_size = 1 * GiB; 1260 xic->icp_get = pnv_icp_get; 1261 xic->ics_get = pnv_ics_get; 1262 xic->ics_resend = pnv_ics_resend; 1263 ispc->print_info = pnv_pic_print_info; 1264 1265 pnv_machine_class_props_init(oc); 1266 } 1267 1268 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1269 { \ 1270 .name = type, \ 1271 .class_init = class_initfn, \ 1272 .parent = TYPE_PNV8_CHIP, \ 1273 } 1274 1275 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1276 { \ 1277 .name = type, \ 1278 .class_init = class_initfn, \ 1279 .parent = TYPE_PNV9_CHIP, \ 1280 } 1281 1282 static const TypeInfo types[] = { 1283 { 1284 .name = TYPE_PNV_MACHINE, 1285 .parent = TYPE_MACHINE, 1286 .instance_size = sizeof(PnvMachineState), 1287 .instance_init = pnv_machine_instance_init, 1288 .class_init = pnv_machine_class_init, 1289 .interfaces = (InterfaceInfo[]) { 1290 { TYPE_XICS_FABRIC }, 1291 { TYPE_INTERRUPT_STATS_PROVIDER }, 1292 { }, 1293 }, 1294 }, 1295 { 1296 .name = TYPE_PNV_CHIP, 1297 .parent = TYPE_SYS_BUS_DEVICE, 1298 .class_init = pnv_chip_class_init, 1299 .instance_init = pnv_chip_instance_init, 1300 .instance_size = sizeof(PnvChip), 1301 .class_size = sizeof(PnvChipClass), 1302 .abstract = true, 1303 }, 1304 1305 /* 1306 * P9 chip and variants 1307 */ 1308 { 1309 .name = TYPE_PNV9_CHIP, 1310 .parent = TYPE_PNV_CHIP, 1311 .instance_init = pnv_chip_power9_instance_init, 1312 .instance_size = sizeof(Pnv9Chip), 1313 }, 1314 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1315 1316 /* 1317 * P8 chip and variants 1318 */ 1319 { 1320 .name = TYPE_PNV8_CHIP, 1321 .parent = TYPE_PNV_CHIP, 1322 .instance_init = pnv_chip_power8_instance_init, 1323 .instance_size = sizeof(Pnv8Chip), 1324 }, 1325 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1326 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1327 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1328 pnv_chip_power8nvl_class_init), 1329 }; 1330 1331 DEFINE_TYPES(types) 1332