1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/cpus.h" 28 #include "sysemu/device_tree.h" 29 #include "target/ppc/cpu.h" 30 #include "qemu/log.h" 31 #include "hw/ppc/fdt.h" 32 #include "hw/ppc/ppc.h" 33 #include "hw/ppc/pnv.h" 34 #include "hw/ppc/pnv_core.h" 35 #include "hw/loader.h" 36 #include "exec/address-spaces.h" 37 #include "qapi/visitor.h" 38 #include "monitor/monitor.h" 39 #include "hw/intc/intc.h" 40 #include "hw/ipmi/ipmi.h" 41 #include "target/ppc/mmu-hash64.h" 42 43 #include "hw/ppc/xics.h" 44 #include "hw/qdev-properties.h" 45 #include "hw/ppc/pnv_xscom.h" 46 47 #include "hw/isa/isa.h" 48 #include "hw/boards.h" 49 #include "hw/char/serial.h" 50 #include "hw/timer/mc146818rtc.h" 51 52 #include <libfdt.h> 53 54 #define FDT_MAX_SIZE (1 * MiB) 55 56 #define FW_FILE_NAME "skiboot.lid" 57 #define FW_LOAD_ADDR 0x0 58 #define FW_MAX_SIZE (4 * MiB) 59 60 #define KERNEL_LOAD_ADDR 0x20000000 61 #define KERNEL_MAX_SIZE (256 * MiB) 62 #define INITRD_LOAD_ADDR 0x60000000 63 #define INITRD_MAX_SIZE (256 * MiB) 64 65 static const char *pnv_chip_core_typename(const PnvChip *o) 66 { 67 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 68 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 69 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 70 const char *core_type = object_class_get_name(object_class_by_name(s)); 71 g_free(s); 72 return core_type; 73 } 74 75 /* 76 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 77 * 4 * 4 sockets * 12 cores * 8 threads = 1536 78 * Let's make it 2^11 79 */ 80 #define MAX_CPUS 2048 81 82 /* 83 * Memory nodes are created by hostboot, one for each range of memory 84 * that has a different "affinity". In practice, it means one range 85 * per chip. 86 */ 87 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 88 { 89 char *mem_name; 90 uint64_t mem_reg_property[2]; 91 int off; 92 93 mem_reg_property[0] = cpu_to_be64(start); 94 mem_reg_property[1] = cpu_to_be64(size); 95 96 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 97 off = fdt_add_subnode(fdt, 0, mem_name); 98 g_free(mem_name); 99 100 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 101 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 102 sizeof(mem_reg_property)))); 103 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 104 } 105 106 static int get_cpus_node(void *fdt) 107 { 108 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 109 110 if (cpus_offset < 0) { 111 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 112 if (cpus_offset) { 113 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 114 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 115 } 116 } 117 _FDT(cpus_offset); 118 return cpus_offset; 119 } 120 121 /* 122 * The PowerNV cores (and threads) need to use real HW ids and not an 123 * incremental index like it has been done on other platforms. This HW 124 * id is stored in the CPU PIR, it is used to create cpu nodes in the 125 * device tree, used in XSCOM to address cores and in interrupt 126 * servers. 127 */ 128 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 129 { 130 PowerPCCPU *cpu = pc->threads[0]; 131 CPUState *cs = CPU(cpu); 132 DeviceClass *dc = DEVICE_GET_CLASS(cs); 133 int smt_threads = CPU_CORE(pc)->nr_threads; 134 CPUPPCState *env = &cpu->env; 135 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 136 uint32_t servers_prop[smt_threads]; 137 int i; 138 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 139 0xffffffff, 0xffffffff}; 140 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 141 uint32_t cpufreq = 1000000000; 142 uint32_t page_sizes_prop[64]; 143 size_t page_sizes_prop_size; 144 const uint8_t pa_features[] = { 24, 0, 145 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 146 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 147 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 148 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 149 int offset; 150 char *nodename; 151 int cpus_offset = get_cpus_node(fdt); 152 153 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 154 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 155 _FDT(offset); 156 g_free(nodename); 157 158 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 159 160 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 161 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 162 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 163 164 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 165 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 166 env->dcache_line_size))); 167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 168 env->dcache_line_size))); 169 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 170 env->icache_line_size))); 171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 172 env->icache_line_size))); 173 174 if (pcc->l1_dcache_size) { 175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 176 pcc->l1_dcache_size))); 177 } else { 178 warn_report("Unknown L1 dcache size for cpu"); 179 } 180 if (pcc->l1_icache_size) { 181 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 182 pcc->l1_icache_size))); 183 } else { 184 warn_report("Unknown L1 icache size for cpu"); 185 } 186 187 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 188 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 189 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 190 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 191 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 192 193 if (env->spr_cb[SPR_PURR].oea_read) { 194 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 195 } 196 197 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 198 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 199 segs, sizeof(segs)))); 200 } 201 202 /* Advertise VMX/VSX (vector extensions) if available 203 * 0 / no property == no vector extensions 204 * 1 == VMX / Altivec available 205 * 2 == VSX available */ 206 if (env->insns_flags & PPC_ALTIVEC) { 207 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 208 209 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 210 } 211 212 /* Advertise DFP (Decimal Floating Point) if available 213 * 0 / no property == no DFP 214 * 1 == DFP available */ 215 if (env->insns_flags2 & PPC2_DFP) { 216 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 217 } 218 219 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 220 sizeof(page_sizes_prop)); 221 if (page_sizes_prop_size) { 222 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 223 page_sizes_prop, page_sizes_prop_size))); 224 } 225 226 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 227 pa_features, sizeof(pa_features)))); 228 229 /* Build interrupt servers properties */ 230 for (i = 0; i < smt_threads; i++) { 231 servers_prop[i] = cpu_to_be32(pc->pir + i); 232 } 233 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 234 servers_prop, sizeof(servers_prop)))); 235 } 236 237 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 238 uint32_t nr_threads) 239 { 240 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 241 char *name; 242 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 243 uint32_t irange[2], i, rsize; 244 uint64_t *reg; 245 int offset; 246 247 irange[0] = cpu_to_be32(pir); 248 irange[1] = cpu_to_be32(nr_threads); 249 250 rsize = sizeof(uint64_t) * 2 * nr_threads; 251 reg = g_malloc(rsize); 252 for (i = 0; i < nr_threads; i++) { 253 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 254 reg[i * 2 + 1] = cpu_to_be64(0x1000); 255 } 256 257 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 258 offset = fdt_add_subnode(fdt, 0, name); 259 _FDT(offset); 260 g_free(name); 261 262 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 263 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 264 _FDT((fdt_setprop_string(fdt, offset, "device_type", 265 "PowerPC-External-Interrupt-Presentation"))); 266 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 267 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 268 irange, sizeof(irange)))); 269 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 270 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 271 g_free(reg); 272 } 273 274 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 275 { 276 const char *typename = pnv_chip_core_typename(chip); 277 size_t typesize = object_type_get_instance_size(typename); 278 int i; 279 280 pnv_dt_xscom(chip, fdt, 0); 281 282 for (i = 0; i < chip->nr_cores; i++) { 283 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 284 285 pnv_dt_core(chip, pnv_core, fdt); 286 287 /* Interrupt Control Presenters (ICP). One per core. */ 288 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 289 } 290 291 if (chip->ram_size) { 292 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 293 } 294 } 295 296 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 297 { 298 const char *typename = pnv_chip_core_typename(chip); 299 size_t typesize = object_type_get_instance_size(typename); 300 int i; 301 302 pnv_dt_xscom(chip, fdt, 0); 303 304 for (i = 0; i < chip->nr_cores; i++) { 305 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 306 307 pnv_dt_core(chip, pnv_core, fdt); 308 } 309 310 if (chip->ram_size) { 311 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 312 } 313 314 pnv_dt_lpc(chip, fdt, 0); 315 } 316 317 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 318 { 319 uint32_t io_base = d->ioport_id; 320 uint32_t io_regs[] = { 321 cpu_to_be32(1), 322 cpu_to_be32(io_base), 323 cpu_to_be32(2) 324 }; 325 char *name; 326 int node; 327 328 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 329 node = fdt_add_subnode(fdt, lpc_off, name); 330 _FDT(node); 331 g_free(name); 332 333 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 334 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 335 } 336 337 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 338 { 339 const char compatible[] = "ns16550\0pnpPNP,501"; 340 uint32_t io_base = d->ioport_id; 341 uint32_t io_regs[] = { 342 cpu_to_be32(1), 343 cpu_to_be32(io_base), 344 cpu_to_be32(8) 345 }; 346 char *name; 347 int node; 348 349 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 350 node = fdt_add_subnode(fdt, lpc_off, name); 351 _FDT(node); 352 g_free(name); 353 354 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 355 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 356 sizeof(compatible)))); 357 358 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 359 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 360 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 361 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 362 fdt_get_phandle(fdt, lpc_off)))); 363 364 /* This is needed by Linux */ 365 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 366 } 367 368 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 369 { 370 const char compatible[] = "bt\0ipmi-bt"; 371 uint32_t io_base; 372 uint32_t io_regs[] = { 373 cpu_to_be32(1), 374 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 375 cpu_to_be32(3) 376 }; 377 uint32_t irq; 378 char *name; 379 int node; 380 381 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 382 io_regs[1] = cpu_to_be32(io_base); 383 384 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 385 386 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 387 node = fdt_add_subnode(fdt, lpc_off, name); 388 _FDT(node); 389 g_free(name); 390 391 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 392 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 393 sizeof(compatible)))); 394 395 /* Mark it as reserved to avoid Linux trying to claim it */ 396 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 397 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 398 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 399 fdt_get_phandle(fdt, lpc_off)))); 400 } 401 402 typedef struct ForeachPopulateArgs { 403 void *fdt; 404 int offset; 405 } ForeachPopulateArgs; 406 407 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 408 { 409 ForeachPopulateArgs *args = opaque; 410 ISADevice *d = ISA_DEVICE(dev); 411 412 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 413 pnv_dt_rtc(d, args->fdt, args->offset); 414 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 415 pnv_dt_serial(d, args->fdt, args->offset); 416 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 417 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 418 } else { 419 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 420 d->ioport_id); 421 } 422 423 return 0; 424 } 425 426 /* The default LPC bus of a multichip system is on chip 0. It's 427 * recognized by the firmware (skiboot) using a "primary" property. 428 */ 429 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 430 { 431 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 432 ForeachPopulateArgs args = { 433 .fdt = fdt, 434 .offset = isa_offset, 435 }; 436 437 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 438 439 /* ISA devices are not necessarily parented to the ISA bus so we 440 * can not use object_child_foreach() */ 441 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 442 &args); 443 } 444 445 static void pnv_dt_power_mgt(void *fdt) 446 { 447 int off; 448 449 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 450 off = fdt_add_subnode(fdt, off, "power-mgt"); 451 452 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 453 } 454 455 static void *pnv_dt_create(MachineState *machine) 456 { 457 const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 458 const char plat_compat9[] = "qemu,powernv9\0ibm,powernv"; 459 PnvMachineState *pnv = PNV_MACHINE(machine); 460 void *fdt; 461 char *buf; 462 int off; 463 int i; 464 465 fdt = g_malloc0(FDT_MAX_SIZE); 466 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 467 468 /* Root node */ 469 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 470 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 471 _FDT((fdt_setprop_string(fdt, 0, "model", 472 "IBM PowerNV (emulated by qemu)"))); 473 if (pnv_is_power9(pnv)) { 474 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, 475 sizeof(plat_compat9)))); 476 } else { 477 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8, 478 sizeof(plat_compat8)))); 479 } 480 481 482 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 483 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 484 if (qemu_uuid_set) { 485 _FDT((fdt_property_string(fdt, "system-id", buf))); 486 } 487 g_free(buf); 488 489 off = fdt_add_subnode(fdt, 0, "chosen"); 490 if (machine->kernel_cmdline) { 491 _FDT((fdt_setprop_string(fdt, off, "bootargs", 492 machine->kernel_cmdline))); 493 } 494 495 if (pnv->initrd_size) { 496 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 497 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 498 499 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 500 &start_prop, sizeof(start_prop)))); 501 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 502 &end_prop, sizeof(end_prop)))); 503 } 504 505 /* Populate device tree for each chip */ 506 for (i = 0; i < pnv->num_chips; i++) { 507 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 508 } 509 510 /* Populate ISA devices on chip 0 */ 511 pnv_dt_isa(pnv, fdt); 512 513 if (pnv->bmc) { 514 pnv_dt_bmc_sensors(pnv->bmc, fdt); 515 } 516 517 /* Create an extra node for power management on Power9 */ 518 if (pnv_is_power9(pnv)) { 519 pnv_dt_power_mgt(fdt); 520 } 521 522 return fdt; 523 } 524 525 static void pnv_powerdown_notify(Notifier *n, void *opaque) 526 { 527 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 528 529 if (pnv->bmc) { 530 pnv_bmc_powerdown(pnv->bmc); 531 } 532 } 533 534 static void pnv_reset(MachineState *machine) 535 { 536 PnvMachineState *pnv = PNV_MACHINE(machine); 537 void *fdt; 538 Object *obj; 539 540 qemu_devices_reset(); 541 542 /* OpenPOWER systems have a BMC, which can be defined on the 543 * command line with: 544 * 545 * -device ipmi-bmc-sim,id=bmc0 546 * 547 * This is the internal simulator but it could also be an external 548 * BMC. 549 */ 550 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); 551 if (obj) { 552 pnv->bmc = IPMI_BMC(obj); 553 } 554 555 fdt = pnv_dt_create(machine); 556 557 /* Pack resulting tree */ 558 _FDT((fdt_pack(fdt))); 559 560 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 561 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 562 } 563 564 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 565 { 566 Pnv8Chip *chip8 = PNV8_CHIP(chip); 567 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 568 } 569 570 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 571 { 572 Pnv8Chip *chip8 = PNV8_CHIP(chip); 573 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 574 } 575 576 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 577 { 578 Pnv9Chip *chip9 = PNV9_CHIP(chip); 579 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 580 } 581 582 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 583 { 584 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 585 } 586 587 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 588 { 589 Pnv8Chip *chip8 = PNV8_CHIP(chip); 590 591 ics_pic_print_info(&chip8->psi.ics, mon); 592 } 593 594 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 595 { 596 Pnv9Chip *chip9 = PNV9_CHIP(chip); 597 598 pnv_xive_pic_print_info(&chip9->xive, mon); 599 pnv_psi_pic_print_info(&chip9->psi, mon); 600 } 601 602 static void pnv_init(MachineState *machine) 603 { 604 PnvMachineState *pnv = PNV_MACHINE(machine); 605 MemoryRegion *ram; 606 char *fw_filename; 607 long fw_size; 608 int i; 609 char *chip_typename; 610 611 /* allocate RAM */ 612 if (machine->ram_size < (1 * GiB)) { 613 warn_report("skiboot may not work with < 1GB of RAM"); 614 } 615 616 ram = g_new(MemoryRegion, 1); 617 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 618 machine->ram_size); 619 memory_region_add_subregion(get_system_memory(), 0, ram); 620 621 /* load skiboot firmware */ 622 if (bios_name == NULL) { 623 bios_name = FW_FILE_NAME; 624 } 625 626 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 627 if (!fw_filename) { 628 error_report("Could not find OPAL firmware '%s'", bios_name); 629 exit(1); 630 } 631 632 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 633 if (fw_size < 0) { 634 error_report("Could not load OPAL firmware '%s'", fw_filename); 635 exit(1); 636 } 637 g_free(fw_filename); 638 639 /* load kernel */ 640 if (machine->kernel_filename) { 641 long kernel_size; 642 643 kernel_size = load_image_targphys(machine->kernel_filename, 644 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 645 if (kernel_size < 0) { 646 error_report("Could not load kernel '%s'", 647 machine->kernel_filename); 648 exit(1); 649 } 650 } 651 652 /* load initrd */ 653 if (machine->initrd_filename) { 654 pnv->initrd_base = INITRD_LOAD_ADDR; 655 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 656 pnv->initrd_base, INITRD_MAX_SIZE); 657 if (pnv->initrd_size < 0) { 658 error_report("Could not load initial ram disk '%s'", 659 machine->initrd_filename); 660 exit(1); 661 } 662 } 663 664 /* Create the processor chips */ 665 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 666 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 667 i, machine->cpu_type); 668 if (!object_class_by_name(chip_typename)) { 669 error_report("invalid CPU model '%.*s' for %s machine", 670 i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name); 671 exit(1); 672 } 673 674 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 675 for (i = 0; i < pnv->num_chips; i++) { 676 char chip_name[32]; 677 Object *chip = object_new(chip_typename); 678 679 pnv->chips[i] = PNV_CHIP(chip); 680 681 /* TODO: put all the memory in one node on chip 0 until we find a 682 * way to specify different ranges for each chip 683 */ 684 if (i == 0) { 685 object_property_set_int(chip, machine->ram_size, "ram-size", 686 &error_fatal); 687 } 688 689 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 690 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 691 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 692 &error_fatal); 693 object_property_set_int(chip, machine->smp.cores, 694 "nr-cores", &error_fatal); 695 object_property_set_bool(chip, true, "realized", &error_fatal); 696 } 697 g_free(chip_typename); 698 699 /* Instantiate ISA bus on chip 0 */ 700 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 701 702 /* Create serial port */ 703 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 704 705 /* Create an RTC ISA device too */ 706 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 707 708 /* OpenPOWER systems use a IPMI SEL Event message to notify the 709 * host to powerdown */ 710 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 711 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 712 } 713 714 /* 715 * 0:21 Reserved - Read as zeros 716 * 22:24 Chip ID 717 * 25:28 Core number 718 * 29:31 Thread ID 719 */ 720 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 721 { 722 return (chip->chip_id << 7) | (core_id << 3); 723 } 724 725 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 726 Error **errp) 727 { 728 Error *local_err = NULL; 729 Object *obj; 730 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 731 732 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 733 &local_err); 734 if (local_err) { 735 error_propagate(errp, local_err); 736 return; 737 } 738 739 pnv_cpu->intc = obj; 740 } 741 742 /* 743 * 0:48 Reserved - Read as zeroes 744 * 49:52 Node ID 745 * 53:55 Chip ID 746 * 56 Reserved - Read as zero 747 * 57:61 Core number 748 * 62:63 Thread ID 749 * 750 * We only care about the lower bits. uint32_t is fine for the moment. 751 */ 752 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 753 { 754 return (chip->chip_id << 8) | (core_id << 2); 755 } 756 757 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 758 Error **errp) 759 { 760 Pnv9Chip *chip9 = PNV9_CHIP(chip); 761 Error *local_err = NULL; 762 Object *obj; 763 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 764 765 /* 766 * The core creates its interrupt presenter but the XIVE interrupt 767 * controller object is initialized afterwards. Hopefully, it's 768 * only used at runtime. 769 */ 770 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); 771 if (local_err) { 772 error_propagate(errp, local_err); 773 return; 774 } 775 776 pnv_cpu->intc = obj; 777 } 778 779 /* Allowed core identifiers on a POWER8 Processor Chip : 780 * 781 * <EX0 reserved> 782 * EX1 - Venice only 783 * EX2 - Venice only 784 * EX3 - Venice only 785 * EX4 786 * EX5 787 * EX6 788 * <EX7,8 reserved> <reserved> 789 * EX9 - Venice only 790 * EX10 - Venice only 791 * EX11 - Venice only 792 * EX12 793 * EX13 794 * EX14 795 * <EX15 reserved> 796 */ 797 #define POWER8E_CORE_MASK (0x7070ull) 798 #define POWER8_CORE_MASK (0x7e7eull) 799 800 /* 801 * POWER9 has 24 cores, ids starting at 0x0 802 */ 803 #define POWER9_CORE_MASK (0xffffffffffffffull) 804 805 static void pnv_chip_power8_instance_init(Object *obj) 806 { 807 Pnv8Chip *chip8 = PNV8_CHIP(obj); 808 809 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 810 TYPE_PNV8_PSI, &error_abort, NULL); 811 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 812 OBJECT(qdev_get_machine()), &error_abort); 813 814 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 815 TYPE_PNV8_LPC, &error_abort, NULL); 816 object_property_add_const_link(OBJECT(&chip8->lpc), "psi", 817 OBJECT(&chip8->psi), &error_abort); 818 819 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 820 TYPE_PNV8_OCC, &error_abort, NULL); 821 object_property_add_const_link(OBJECT(&chip8->occ), "psi", 822 OBJECT(&chip8->psi), &error_abort); 823 } 824 825 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 826 { 827 PnvChip *chip = PNV_CHIP(chip8); 828 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 829 const char *typename = pnv_chip_core_typename(chip); 830 size_t typesize = object_type_get_instance_size(typename); 831 int i, j; 832 char *name; 833 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 834 835 name = g_strdup_printf("icp-%x", chip->chip_id); 836 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 837 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 838 g_free(name); 839 840 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 841 842 /* Map the ICP registers for each thread */ 843 for (i = 0; i < chip->nr_cores; i++) { 844 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 845 int core_hwid = CPU_CORE(pnv_core)->core_id; 846 847 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 848 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 849 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 850 851 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 852 &icp->mmio); 853 } 854 } 855 } 856 857 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 858 { 859 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 860 PnvChip *chip = PNV_CHIP(dev); 861 Pnv8Chip *chip8 = PNV8_CHIP(dev); 862 Pnv8Psi *psi8 = &chip8->psi; 863 Error *local_err = NULL; 864 865 /* XSCOM bridge is first */ 866 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 867 if (local_err) { 868 error_propagate(errp, local_err); 869 return; 870 } 871 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 872 873 pcc->parent_realize(dev, &local_err); 874 if (local_err) { 875 error_propagate(errp, local_err); 876 return; 877 } 878 879 /* Processor Service Interface (PSI) Host Bridge */ 880 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 881 "bar", &error_fatal); 882 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 883 if (local_err) { 884 error_propagate(errp, local_err); 885 return; 886 } 887 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 888 &PNV_PSI(psi8)->xscom_regs); 889 890 /* Create LPC controller */ 891 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 892 &error_fatal); 893 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 894 895 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 896 (uint64_t) PNV_XSCOM_BASE(chip), 897 PNV_XSCOM_LPC_BASE); 898 899 /* Interrupt Management Area. This is the memory region holding 900 * all the Interrupt Control Presenter (ICP) registers */ 901 pnv_chip_icp_realize(chip8, &local_err); 902 if (local_err) { 903 error_propagate(errp, local_err); 904 return; 905 } 906 907 /* Create the simplified OCC model */ 908 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 909 if (local_err) { 910 error_propagate(errp, local_err); 911 return; 912 } 913 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 914 } 915 916 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 917 { 918 DeviceClass *dc = DEVICE_CLASS(klass); 919 PnvChipClass *k = PNV_CHIP_CLASS(klass); 920 921 k->chip_type = PNV_CHIP_POWER8E; 922 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 923 k->cores_mask = POWER8E_CORE_MASK; 924 k->core_pir = pnv_chip_core_pir_p8; 925 k->intc_create = pnv_chip_power8_intc_create; 926 k->isa_create = pnv_chip_power8_isa_create; 927 k->dt_populate = pnv_chip_power8_dt_populate; 928 k->pic_print_info = pnv_chip_power8_pic_print_info; 929 dc->desc = "PowerNV Chip POWER8E"; 930 931 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 932 &k->parent_realize); 933 } 934 935 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 936 { 937 DeviceClass *dc = DEVICE_CLASS(klass); 938 PnvChipClass *k = PNV_CHIP_CLASS(klass); 939 940 k->chip_type = PNV_CHIP_POWER8; 941 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 942 k->cores_mask = POWER8_CORE_MASK; 943 k->core_pir = pnv_chip_core_pir_p8; 944 k->intc_create = pnv_chip_power8_intc_create; 945 k->isa_create = pnv_chip_power8_isa_create; 946 k->dt_populate = pnv_chip_power8_dt_populate; 947 k->pic_print_info = pnv_chip_power8_pic_print_info; 948 dc->desc = "PowerNV Chip POWER8"; 949 950 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 951 &k->parent_realize); 952 } 953 954 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 955 { 956 DeviceClass *dc = DEVICE_CLASS(klass); 957 PnvChipClass *k = PNV_CHIP_CLASS(klass); 958 959 k->chip_type = PNV_CHIP_POWER8NVL; 960 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 961 k->cores_mask = POWER8_CORE_MASK; 962 k->core_pir = pnv_chip_core_pir_p8; 963 k->intc_create = pnv_chip_power8_intc_create; 964 k->isa_create = pnv_chip_power8nvl_isa_create; 965 k->dt_populate = pnv_chip_power8_dt_populate; 966 k->pic_print_info = pnv_chip_power8_pic_print_info; 967 dc->desc = "PowerNV Chip POWER8NVL"; 968 969 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 970 &k->parent_realize); 971 } 972 973 static void pnv_chip_power9_instance_init(Object *obj) 974 { 975 Pnv9Chip *chip9 = PNV9_CHIP(obj); 976 977 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 978 TYPE_PNV_XIVE, &error_abort, NULL); 979 object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj, 980 &error_abort); 981 982 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 983 TYPE_PNV9_PSI, &error_abort, NULL); 984 object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj, 985 &error_abort); 986 987 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 988 TYPE_PNV9_LPC, &error_abort, NULL); 989 object_property_add_const_link(OBJECT(&chip9->lpc), "psi", 990 OBJECT(&chip9->psi), &error_abort); 991 992 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 993 TYPE_PNV9_OCC, &error_abort, NULL); 994 object_property_add_const_link(OBJECT(&chip9->occ), "psi", 995 OBJECT(&chip9->psi), &error_abort); 996 } 997 998 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 999 { 1000 PnvChip *chip = PNV_CHIP(chip9); 1001 const char *typename = pnv_chip_core_typename(chip); 1002 size_t typesize = object_type_get_instance_size(typename); 1003 int i; 1004 1005 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1006 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1007 1008 for (i = 0; i < chip9->nr_quads; i++) { 1009 char eq_name[32]; 1010 PnvQuad *eq = &chip9->quads[i]; 1011 PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize); 1012 int core_id = CPU_CORE(pnv_core)->core_id; 1013 1014 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1015 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1016 TYPE_PNV_QUAD, &error_fatal, NULL); 1017 1018 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1019 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1020 1021 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1022 &eq->xscom_regs); 1023 } 1024 } 1025 1026 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1027 { 1028 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1029 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1030 PnvChip *chip = PNV_CHIP(dev); 1031 Pnv9Psi *psi9 = &chip9->psi; 1032 Error *local_err = NULL; 1033 1034 /* XSCOM bridge is first */ 1035 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1036 if (local_err) { 1037 error_propagate(errp, local_err); 1038 return; 1039 } 1040 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1041 1042 pcc->parent_realize(dev, &local_err); 1043 if (local_err) { 1044 error_propagate(errp, local_err); 1045 return; 1046 } 1047 1048 pnv_chip_quad_realize(chip9, &local_err); 1049 if (local_err) { 1050 error_propagate(errp, local_err); 1051 return; 1052 } 1053 1054 /* XIVE interrupt controller (POWER9) */ 1055 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1056 "ic-bar", &error_fatal); 1057 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1058 "vc-bar", &error_fatal); 1059 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1060 "pc-bar", &error_fatal); 1061 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1062 "tm-bar", &error_fatal); 1063 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1064 &local_err); 1065 if (local_err) { 1066 error_propagate(errp, local_err); 1067 return; 1068 } 1069 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1070 &chip9->xive.xscom_regs); 1071 1072 /* Processor Service Interface (PSI) Host Bridge */ 1073 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1074 "bar", &error_fatal); 1075 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1076 if (local_err) { 1077 error_propagate(errp, local_err); 1078 return; 1079 } 1080 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1081 &PNV_PSI(psi9)->xscom_regs); 1082 1083 /* LPC */ 1084 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1085 if (local_err) { 1086 error_propagate(errp, local_err); 1087 return; 1088 } 1089 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1090 &chip9->lpc.xscom_regs); 1091 1092 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1093 (uint64_t) PNV9_LPCM_BASE(chip)); 1094 1095 /* Create the simplified OCC model */ 1096 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1097 if (local_err) { 1098 error_propagate(errp, local_err); 1099 return; 1100 } 1101 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1102 } 1103 1104 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1105 { 1106 DeviceClass *dc = DEVICE_CLASS(klass); 1107 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1108 1109 k->chip_type = PNV_CHIP_POWER9; 1110 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1111 k->cores_mask = POWER9_CORE_MASK; 1112 k->core_pir = pnv_chip_core_pir_p9; 1113 k->intc_create = pnv_chip_power9_intc_create; 1114 k->isa_create = pnv_chip_power9_isa_create; 1115 k->dt_populate = pnv_chip_power9_dt_populate; 1116 k->pic_print_info = pnv_chip_power9_pic_print_info; 1117 dc->desc = "PowerNV Chip POWER9"; 1118 1119 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1120 &k->parent_realize); 1121 } 1122 1123 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1124 { 1125 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1126 int cores_max; 1127 1128 /* 1129 * No custom mask for this chip, let's use the default one from * 1130 * the chip class 1131 */ 1132 if (!chip->cores_mask) { 1133 chip->cores_mask = pcc->cores_mask; 1134 } 1135 1136 /* filter alien core ids ! some are reserved */ 1137 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1138 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1139 chip->cores_mask); 1140 return; 1141 } 1142 chip->cores_mask &= pcc->cores_mask; 1143 1144 /* now that we have a sane layout, let check the number of cores */ 1145 cores_max = ctpop64(chip->cores_mask); 1146 if (chip->nr_cores > cores_max) { 1147 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1148 cores_max); 1149 return; 1150 } 1151 } 1152 1153 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1154 { 1155 MachineState *ms = MACHINE(qdev_get_machine()); 1156 Error *error = NULL; 1157 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1158 const char *typename = pnv_chip_core_typename(chip); 1159 size_t typesize = object_type_get_instance_size(typename); 1160 int i, core_hwid; 1161 1162 if (!object_class_by_name(typename)) { 1163 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1164 return; 1165 } 1166 1167 /* Cores */ 1168 pnv_chip_core_sanitize(chip, &error); 1169 if (error) { 1170 error_propagate(errp, error); 1171 return; 1172 } 1173 1174 chip->cores = g_malloc0(typesize * chip->nr_cores); 1175 1176 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1177 && (i < chip->nr_cores); core_hwid++) { 1178 char core_name[32]; 1179 void *pnv_core = chip->cores + i * typesize; 1180 uint64_t xscom_core_base; 1181 1182 if (!(chip->cores_mask & (1ull << core_hwid))) { 1183 continue; 1184 } 1185 1186 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1187 object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize, 1188 typename, &error_fatal, NULL); 1189 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", 1190 &error_fatal); 1191 object_property_set_int(OBJECT(pnv_core), core_hwid, 1192 CPU_CORE_PROP_CORE_ID, &error_fatal); 1193 object_property_set_int(OBJECT(pnv_core), 1194 pcc->core_pir(chip, core_hwid), 1195 "pir", &error_fatal); 1196 object_property_add_const_link(OBJECT(pnv_core), "chip", 1197 OBJECT(chip), &error_fatal); 1198 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1199 &error_fatal); 1200 1201 /* Each core has an XSCOM MMIO region */ 1202 if (!pnv_chip_is_power9(chip)) { 1203 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); 1204 } else { 1205 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); 1206 } 1207 1208 pnv_xscom_add_subregion(chip, xscom_core_base, 1209 &PNV_CORE(pnv_core)->xscom_regs); 1210 i++; 1211 } 1212 } 1213 1214 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1215 { 1216 PnvChip *chip = PNV_CHIP(dev); 1217 Error *error = NULL; 1218 1219 /* Cores */ 1220 pnv_chip_core_realize(chip, &error); 1221 if (error) { 1222 error_propagate(errp, error); 1223 return; 1224 } 1225 } 1226 1227 static Property pnv_chip_properties[] = { 1228 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1229 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1230 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1231 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1232 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1233 DEFINE_PROP_END_OF_LIST(), 1234 }; 1235 1236 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1237 { 1238 DeviceClass *dc = DEVICE_CLASS(klass); 1239 1240 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1241 dc->realize = pnv_chip_realize; 1242 dc->props = pnv_chip_properties; 1243 dc->desc = "PowerNV Chip"; 1244 } 1245 1246 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1247 { 1248 PnvMachineState *pnv = PNV_MACHINE(xi); 1249 int i; 1250 1251 for (i = 0; i < pnv->num_chips; i++) { 1252 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1253 1254 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1255 return &chip8->psi.ics; 1256 } 1257 } 1258 return NULL; 1259 } 1260 1261 static void pnv_ics_resend(XICSFabric *xi) 1262 { 1263 PnvMachineState *pnv = PNV_MACHINE(xi); 1264 int i; 1265 1266 for (i = 0; i < pnv->num_chips; i++) { 1267 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1268 ics_resend(&chip8->psi.ics); 1269 } 1270 } 1271 1272 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1273 { 1274 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1275 1276 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1277 } 1278 1279 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1280 Monitor *mon) 1281 { 1282 PnvMachineState *pnv = PNV_MACHINE(obj); 1283 int i; 1284 CPUState *cs; 1285 1286 CPU_FOREACH(cs) { 1287 PowerPCCPU *cpu = POWERPC_CPU(cs); 1288 1289 if (pnv_chip_is_power9(pnv->chips[0])) { 1290 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1291 } else { 1292 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1293 } 1294 } 1295 1296 for (i = 0; i < pnv->num_chips; i++) { 1297 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1298 } 1299 } 1300 1301 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1302 void *opaque, Error **errp) 1303 { 1304 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1305 } 1306 1307 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1308 void *opaque, Error **errp) 1309 { 1310 PnvMachineState *pnv = PNV_MACHINE(obj); 1311 uint32_t num_chips; 1312 Error *local_err = NULL; 1313 1314 visit_type_uint32(v, name, &num_chips, &local_err); 1315 if (local_err) { 1316 error_propagate(errp, local_err); 1317 return; 1318 } 1319 1320 /* 1321 * TODO: should we decide on how many chips we can create based 1322 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1323 */ 1324 if (!is_power_of_2(num_chips) || num_chips > 4) { 1325 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1326 return; 1327 } 1328 1329 pnv->num_chips = num_chips; 1330 } 1331 1332 static void pnv_machine_instance_init(Object *obj) 1333 { 1334 PnvMachineState *pnv = PNV_MACHINE(obj); 1335 pnv->num_chips = 1; 1336 } 1337 1338 static void pnv_machine_class_props_init(ObjectClass *oc) 1339 { 1340 object_class_property_add(oc, "num-chips", "uint32", 1341 pnv_get_num_chips, pnv_set_num_chips, 1342 NULL, NULL, NULL); 1343 object_class_property_set_description(oc, "num-chips", 1344 "Specifies the number of processor chips", 1345 NULL); 1346 } 1347 1348 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1349 { 1350 MachineClass *mc = MACHINE_CLASS(oc); 1351 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1352 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1353 1354 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1355 mc->init = pnv_init; 1356 mc->reset = pnv_reset; 1357 mc->max_cpus = MAX_CPUS; 1358 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1359 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for 1360 * storage */ 1361 mc->no_parallel = 1; 1362 mc->default_boot_order = NULL; 1363 mc->default_ram_size = 1 * GiB; 1364 xic->icp_get = pnv_icp_get; 1365 xic->ics_get = pnv_ics_get; 1366 xic->ics_resend = pnv_ics_resend; 1367 ispc->print_info = pnv_pic_print_info; 1368 1369 pnv_machine_class_props_init(oc); 1370 } 1371 1372 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1373 { \ 1374 .name = type, \ 1375 .class_init = class_initfn, \ 1376 .parent = TYPE_PNV8_CHIP, \ 1377 } 1378 1379 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1380 { \ 1381 .name = type, \ 1382 .class_init = class_initfn, \ 1383 .parent = TYPE_PNV9_CHIP, \ 1384 } 1385 1386 static const TypeInfo types[] = { 1387 { 1388 .name = TYPE_PNV_MACHINE, 1389 .parent = TYPE_MACHINE, 1390 .instance_size = sizeof(PnvMachineState), 1391 .instance_init = pnv_machine_instance_init, 1392 .class_init = pnv_machine_class_init, 1393 .interfaces = (InterfaceInfo[]) { 1394 { TYPE_XICS_FABRIC }, 1395 { TYPE_INTERRUPT_STATS_PROVIDER }, 1396 { }, 1397 }, 1398 }, 1399 { 1400 .name = TYPE_PNV_CHIP, 1401 .parent = TYPE_SYS_BUS_DEVICE, 1402 .class_init = pnv_chip_class_init, 1403 .instance_size = sizeof(PnvChip), 1404 .class_size = sizeof(PnvChipClass), 1405 .abstract = true, 1406 }, 1407 1408 /* 1409 * P9 chip and variants 1410 */ 1411 { 1412 .name = TYPE_PNV9_CHIP, 1413 .parent = TYPE_PNV_CHIP, 1414 .instance_init = pnv_chip_power9_instance_init, 1415 .instance_size = sizeof(Pnv9Chip), 1416 }, 1417 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1418 1419 /* 1420 * P8 chip and variants 1421 */ 1422 { 1423 .name = TYPE_PNV8_CHIP, 1424 .parent = TYPE_PNV_CHIP, 1425 .instance_init = pnv_chip_power8_instance_init, 1426 .instance_size = sizeof(Pnv8Chip), 1427 }, 1428 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1429 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1430 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1431 pnv_chip_power8nvl_class_init), 1432 }; 1433 1434 DEFINE_TYPES(types) 1435