1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 47 #include "hw/ppc/xics.h" 48 #include "hw/qdev-properties.h" 49 #include "hw/ppc/pnv_xscom.h" 50 #include "hw/ppc/pnv_pnor.h" 51 52 #include "hw/isa/isa.h" 53 #include "hw/char/serial.h" 54 #include "hw/rtc/mc146818rtc.h" 55 56 #include <libfdt.h> 57 58 #define FDT_MAX_SIZE (1 * MiB) 59 60 #define FW_FILE_NAME "skiboot.lid" 61 #define FW_LOAD_ADDR 0x0 62 #define FW_MAX_SIZE (16 * MiB) 63 64 #define KERNEL_LOAD_ADDR 0x20000000 65 #define KERNEL_MAX_SIZE (128 * MiB) 66 #define INITRD_LOAD_ADDR 0x28000000 67 #define INITRD_MAX_SIZE (128 * MiB) 68 69 static const char *pnv_chip_core_typename(const PnvChip *o) 70 { 71 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 72 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 73 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 74 const char *core_type = object_class_get_name(object_class_by_name(s)); 75 g_free(s); 76 return core_type; 77 } 78 79 /* 80 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 81 * 4 * 4 sockets * 12 cores * 8 threads = 1536 82 * Let's make it 2^11 83 */ 84 #define MAX_CPUS 2048 85 86 /* 87 * Memory nodes are created by hostboot, one for each range of memory 88 * that has a different "affinity". In practice, it means one range 89 * per chip. 90 */ 91 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 92 { 93 char *mem_name; 94 uint64_t mem_reg_property[2]; 95 int off; 96 97 mem_reg_property[0] = cpu_to_be64(start); 98 mem_reg_property[1] = cpu_to_be64(size); 99 100 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 101 off = fdt_add_subnode(fdt, 0, mem_name); 102 g_free(mem_name); 103 104 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 105 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 106 sizeof(mem_reg_property)))); 107 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 108 } 109 110 static int get_cpus_node(void *fdt) 111 { 112 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 113 114 if (cpus_offset < 0) { 115 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 116 if (cpus_offset) { 117 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 119 } 120 } 121 _FDT(cpus_offset); 122 return cpus_offset; 123 } 124 125 /* 126 * The PowerNV cores (and threads) need to use real HW ids and not an 127 * incremental index like it has been done on other platforms. This HW 128 * id is stored in the CPU PIR, it is used to create cpu nodes in the 129 * device tree, used in XSCOM to address cores and in interrupt 130 * servers. 131 */ 132 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 133 { 134 PowerPCCPU *cpu = pc->threads[0]; 135 CPUState *cs = CPU(cpu); 136 DeviceClass *dc = DEVICE_GET_CLASS(cs); 137 int smt_threads = CPU_CORE(pc)->nr_threads; 138 CPUPPCState *env = &cpu->env; 139 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 140 uint32_t servers_prop[smt_threads]; 141 int i; 142 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 143 0xffffffff, 0xffffffff}; 144 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 145 uint32_t cpufreq = 1000000000; 146 uint32_t page_sizes_prop[64]; 147 size_t page_sizes_prop_size; 148 const uint8_t pa_features[] = { 24, 0, 149 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 150 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 151 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 152 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 153 int offset; 154 char *nodename; 155 int cpus_offset = get_cpus_node(fdt); 156 157 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 158 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 159 _FDT(offset); 160 g_free(nodename); 161 162 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 163 164 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 165 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 166 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 170 env->dcache_line_size))); 171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 172 env->dcache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 174 env->icache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 176 env->icache_line_size))); 177 178 if (pcc->l1_dcache_size) { 179 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 180 pcc->l1_dcache_size))); 181 } else { 182 warn_report("Unknown L1 dcache size for cpu"); 183 } 184 if (pcc->l1_icache_size) { 185 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 186 pcc->l1_icache_size))); 187 } else { 188 warn_report("Unknown L1 icache size for cpu"); 189 } 190 191 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 192 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 194 cpu->hash64_opts->slb_size))); 195 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 196 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 197 198 if (ppc_has_spr(cpu, SPR_PURR)) { 199 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 200 } 201 202 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 204 segs, sizeof(segs)))); 205 } 206 207 /* 208 * Advertise VMX/VSX (vector extensions) if available 209 * 0 / no property == no vector extensions 210 * 1 == VMX / Altivec available 211 * 2 == VSX available 212 */ 213 if (env->insns_flags & PPC_ALTIVEC) { 214 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 215 216 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 217 } 218 219 /* 220 * Advertise DFP (Decimal Floating Point) if available 221 * 0 / no property == no DFP 222 * 1 == DFP available 223 */ 224 if (env->insns_flags2 & PPC2_DFP) { 225 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 226 } 227 228 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 229 sizeof(page_sizes_prop)); 230 if (page_sizes_prop_size) { 231 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 232 page_sizes_prop, page_sizes_prop_size))); 233 } 234 235 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 236 pa_features, sizeof(pa_features)))); 237 238 /* Build interrupt servers properties */ 239 for (i = 0; i < smt_threads; i++) { 240 servers_prop[i] = cpu_to_be32(pc->pir + i); 241 } 242 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 243 servers_prop, sizeof(servers_prop)))); 244 } 245 246 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 247 uint32_t nr_threads) 248 { 249 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 250 char *name; 251 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 252 uint32_t irange[2], i, rsize; 253 uint64_t *reg; 254 int offset; 255 256 irange[0] = cpu_to_be32(pir); 257 irange[1] = cpu_to_be32(nr_threads); 258 259 rsize = sizeof(uint64_t) * 2 * nr_threads; 260 reg = g_malloc(rsize); 261 for (i = 0; i < nr_threads; i++) { 262 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 263 reg[i * 2 + 1] = cpu_to_be64(0x1000); 264 } 265 266 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 267 offset = fdt_add_subnode(fdt, 0, name); 268 _FDT(offset); 269 g_free(name); 270 271 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 272 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 273 _FDT((fdt_setprop_string(fdt, offset, "device_type", 274 "PowerPC-External-Interrupt-Presentation"))); 275 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 276 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 277 irange, sizeof(irange)))); 278 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 280 g_free(reg); 281 } 282 283 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 284 { 285 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 286 int i; 287 288 pnv_dt_xscom(chip, fdt, 0, 289 cpu_to_be64(PNV_XSCOM_BASE(chip)), 290 cpu_to_be64(PNV_XSCOM_SIZE), 291 compat, sizeof(compat)); 292 293 for (i = 0; i < chip->nr_cores; i++) { 294 PnvCore *pnv_core = chip->cores[i]; 295 296 pnv_dt_core(chip, pnv_core, fdt); 297 298 /* Interrupt Control Presenters (ICP). One per core. */ 299 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 300 } 301 302 if (chip->ram_size) { 303 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 304 } 305 } 306 307 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 308 { 309 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 310 int i; 311 312 pnv_dt_xscom(chip, fdt, 0, 313 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 314 cpu_to_be64(PNV9_XSCOM_SIZE), 315 compat, sizeof(compat)); 316 317 for (i = 0; i < chip->nr_cores; i++) { 318 PnvCore *pnv_core = chip->cores[i]; 319 320 pnv_dt_core(chip, pnv_core, fdt); 321 } 322 323 if (chip->ram_size) { 324 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 325 } 326 327 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 328 } 329 330 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 331 { 332 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 333 int i; 334 335 pnv_dt_xscom(chip, fdt, 0, 336 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 337 cpu_to_be64(PNV10_XSCOM_SIZE), 338 compat, sizeof(compat)); 339 340 for (i = 0; i < chip->nr_cores; i++) { 341 PnvCore *pnv_core = chip->cores[i]; 342 343 pnv_dt_core(chip, pnv_core, fdt); 344 } 345 346 if (chip->ram_size) { 347 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 348 } 349 350 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 351 } 352 353 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 354 { 355 uint32_t io_base = d->ioport_id; 356 uint32_t io_regs[] = { 357 cpu_to_be32(1), 358 cpu_to_be32(io_base), 359 cpu_to_be32(2) 360 }; 361 char *name; 362 int node; 363 364 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 365 node = fdt_add_subnode(fdt, lpc_off, name); 366 _FDT(node); 367 g_free(name); 368 369 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 370 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 371 } 372 373 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 374 { 375 const char compatible[] = "ns16550\0pnpPNP,501"; 376 uint32_t io_base = d->ioport_id; 377 uint32_t io_regs[] = { 378 cpu_to_be32(1), 379 cpu_to_be32(io_base), 380 cpu_to_be32(8) 381 }; 382 uint32_t irq; 383 char *name; 384 int node; 385 386 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 387 388 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 389 node = fdt_add_subnode(fdt, lpc_off, name); 390 _FDT(node); 391 g_free(name); 392 393 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 394 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 395 sizeof(compatible)))); 396 397 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 398 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 399 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 400 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 401 fdt_get_phandle(fdt, lpc_off)))); 402 403 /* This is needed by Linux */ 404 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 405 } 406 407 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 408 { 409 const char compatible[] = "bt\0ipmi-bt"; 410 uint32_t io_base; 411 uint32_t io_regs[] = { 412 cpu_to_be32(1), 413 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 414 cpu_to_be32(3) 415 }; 416 uint32_t irq; 417 char *name; 418 int node; 419 420 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 421 io_regs[1] = cpu_to_be32(io_base); 422 423 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 424 425 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 426 node = fdt_add_subnode(fdt, lpc_off, name); 427 _FDT(node); 428 g_free(name); 429 430 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 431 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 432 sizeof(compatible)))); 433 434 /* Mark it as reserved to avoid Linux trying to claim it */ 435 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 436 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 437 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 438 fdt_get_phandle(fdt, lpc_off)))); 439 } 440 441 typedef struct ForeachPopulateArgs { 442 void *fdt; 443 int offset; 444 } ForeachPopulateArgs; 445 446 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 447 { 448 ForeachPopulateArgs *args = opaque; 449 ISADevice *d = ISA_DEVICE(dev); 450 451 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 452 pnv_dt_rtc(d, args->fdt, args->offset); 453 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 454 pnv_dt_serial(d, args->fdt, args->offset); 455 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 456 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 457 } else { 458 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 459 d->ioport_id); 460 } 461 462 return 0; 463 } 464 465 /* 466 * The default LPC bus of a multichip system is on chip 0. It's 467 * recognized by the firmware (skiboot) using a "primary" property. 468 */ 469 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 470 { 471 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 472 ForeachPopulateArgs args = { 473 .fdt = fdt, 474 .offset = isa_offset, 475 }; 476 uint32_t phandle; 477 478 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 479 480 phandle = qemu_fdt_alloc_phandle(fdt); 481 assert(phandle > 0); 482 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 483 484 /* 485 * ISA devices are not necessarily parented to the ISA bus so we 486 * can not use object_child_foreach() 487 */ 488 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 489 &args); 490 } 491 492 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 493 { 494 int off; 495 496 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 497 off = fdt_add_subnode(fdt, off, "power-mgt"); 498 499 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 500 } 501 502 static void *pnv_dt_create(MachineState *machine) 503 { 504 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 505 PnvMachineState *pnv = PNV_MACHINE(machine); 506 void *fdt; 507 char *buf; 508 int off; 509 int i; 510 511 fdt = g_malloc0(FDT_MAX_SIZE); 512 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 513 514 /* /qemu node */ 515 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 516 517 /* Root node */ 518 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 519 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 520 _FDT((fdt_setprop_string(fdt, 0, "model", 521 "IBM PowerNV (emulated by qemu)"))); 522 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 523 524 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 525 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 526 if (qemu_uuid_set) { 527 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 528 } 529 g_free(buf); 530 531 off = fdt_add_subnode(fdt, 0, "chosen"); 532 if (machine->kernel_cmdline) { 533 _FDT((fdt_setprop_string(fdt, off, "bootargs", 534 machine->kernel_cmdline))); 535 } 536 537 if (pnv->initrd_size) { 538 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 539 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 540 541 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 542 &start_prop, sizeof(start_prop)))); 543 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 544 &end_prop, sizeof(end_prop)))); 545 } 546 547 /* Populate device tree for each chip */ 548 for (i = 0; i < pnv->num_chips; i++) { 549 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 550 } 551 552 /* Populate ISA devices on chip 0 */ 553 pnv_dt_isa(pnv, fdt); 554 555 if (pnv->bmc) { 556 pnv_dt_bmc_sensors(pnv->bmc, fdt); 557 } 558 559 /* Create an extra node for power management on machines that support it */ 560 if (pmc->dt_power_mgt) { 561 pmc->dt_power_mgt(pnv, fdt); 562 } 563 564 return fdt; 565 } 566 567 static void pnv_powerdown_notify(Notifier *n, void *opaque) 568 { 569 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 570 571 if (pnv->bmc) { 572 pnv_bmc_powerdown(pnv->bmc); 573 } 574 } 575 576 static void pnv_reset(MachineState *machine) 577 { 578 PnvMachineState *pnv = PNV_MACHINE(machine); 579 IPMIBmc *bmc; 580 void *fdt; 581 582 qemu_devices_reset(); 583 584 /* 585 * The machine should provide by default an internal BMC simulator. 586 * If not, try to use the BMC device that was provided on the command 587 * line. 588 */ 589 bmc = pnv_bmc_find(&error_fatal); 590 if (!pnv->bmc) { 591 if (!bmc) { 592 if (!qtest_enabled()) { 593 warn_report("machine has no BMC device. Use '-device " 594 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 595 "to define one"); 596 } 597 } else { 598 pnv_bmc_set_pnor(bmc, pnv->pnor); 599 pnv->bmc = bmc; 600 } 601 } 602 603 fdt = pnv_dt_create(machine); 604 605 /* Pack resulting tree */ 606 _FDT((fdt_pack(fdt))); 607 608 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 609 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 610 611 g_free(fdt); 612 } 613 614 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 615 { 616 Pnv8Chip *chip8 = PNV8_CHIP(chip); 617 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 618 619 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 620 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 621 } 622 623 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 624 { 625 Pnv8Chip *chip8 = PNV8_CHIP(chip); 626 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 627 628 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 629 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 630 } 631 632 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 633 { 634 Pnv9Chip *chip9 = PNV9_CHIP(chip); 635 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 636 637 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 638 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 639 } 640 641 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 642 { 643 Pnv10Chip *chip10 = PNV10_CHIP(chip); 644 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 645 646 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 647 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 648 } 649 650 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 651 { 652 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 653 } 654 655 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 656 { 657 Pnv8Chip *chip8 = PNV8_CHIP(chip); 658 int i; 659 660 ics_pic_print_info(&chip8->psi.ics, mon); 661 662 for (i = 0; i < chip8->num_phbs; i++) { 663 PnvPHB3 *phb3 = &chip8->phbs[i]; 664 665 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 666 ics_pic_print_info(&phb3->lsis, mon); 667 } 668 } 669 670 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 671 { 672 Monitor *mon = opaque; 673 PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4); 674 675 if (phb4) { 676 pnv_phb4_pic_print_info(phb4, mon); 677 } 678 return 0; 679 } 680 681 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 682 { 683 Pnv9Chip *chip9 = PNV9_CHIP(chip); 684 685 pnv_xive_pic_print_info(&chip9->xive, mon); 686 pnv_psi_pic_print_info(&chip9->psi, mon); 687 688 object_child_foreach_recursive(OBJECT(chip), 689 pnv_chip_power9_pic_print_info_child, mon); 690 } 691 692 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 693 uint32_t core_id) 694 { 695 return PNV_XSCOM_EX_BASE(core_id); 696 } 697 698 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 699 uint32_t core_id) 700 { 701 return PNV9_XSCOM_EC_BASE(core_id); 702 } 703 704 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 705 uint32_t core_id) 706 { 707 return PNV10_XSCOM_EC_BASE(core_id); 708 } 709 710 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 711 { 712 PowerPCCPUClass *ppc_default = 713 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 714 PowerPCCPUClass *ppc = 715 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 716 717 return ppc_default->pvr_match(ppc_default, ppc->pvr); 718 } 719 720 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 721 { 722 ISADevice *dev = isa_new("isa-ipmi-bt"); 723 724 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 725 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 726 isa_realize_and_unref(dev, bus, &error_fatal); 727 } 728 729 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 730 { 731 Pnv10Chip *chip10 = PNV10_CHIP(chip); 732 733 pnv_xive2_pic_print_info(&chip10->xive, mon); 734 pnv_psi_pic_print_info(&chip10->psi, mon); 735 736 object_child_foreach_recursive(OBJECT(chip), 737 pnv_chip_power9_pic_print_info_child, mon); 738 } 739 740 /* Always give the first 1GB to chip 0 else we won't boot */ 741 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 742 { 743 MachineState *machine = MACHINE(pnv); 744 uint64_t ram_per_chip; 745 746 assert(machine->ram_size >= 1 * GiB); 747 748 ram_per_chip = machine->ram_size / pnv->num_chips; 749 if (ram_per_chip >= 1 * GiB) { 750 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 751 } 752 753 assert(pnv->num_chips > 1); 754 755 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 756 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 757 } 758 759 static void pnv_init(MachineState *machine) 760 { 761 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 762 PnvMachineState *pnv = PNV_MACHINE(machine); 763 MachineClass *mc = MACHINE_GET_CLASS(machine); 764 char *fw_filename; 765 long fw_size; 766 uint64_t chip_ram_start = 0; 767 int i; 768 char *chip_typename; 769 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 770 DeviceState *dev; 771 772 if (kvm_enabled()) { 773 error_report("The powernv machine does not work with KVM acceleration"); 774 exit(EXIT_FAILURE); 775 } 776 777 /* allocate RAM */ 778 if (machine->ram_size < mc->default_ram_size) { 779 char *sz = size_to_str(mc->default_ram_size); 780 error_report("Invalid RAM size, should be bigger than %s", sz); 781 g_free(sz); 782 exit(EXIT_FAILURE); 783 } 784 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 785 786 /* 787 * Create our simple PNOR device 788 */ 789 dev = qdev_new(TYPE_PNV_PNOR); 790 if (pnor) { 791 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 792 } 793 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 794 pnv->pnor = PNV_PNOR(dev); 795 796 /* load skiboot firmware */ 797 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 798 if (!fw_filename) { 799 error_report("Could not find OPAL firmware '%s'", bios_name); 800 exit(1); 801 } 802 803 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 804 if (fw_size < 0) { 805 error_report("Could not load OPAL firmware '%s'", fw_filename); 806 exit(1); 807 } 808 g_free(fw_filename); 809 810 /* load kernel */ 811 if (machine->kernel_filename) { 812 long kernel_size; 813 814 kernel_size = load_image_targphys(machine->kernel_filename, 815 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 816 if (kernel_size < 0) { 817 error_report("Could not load kernel '%s'", 818 machine->kernel_filename); 819 exit(1); 820 } 821 } 822 823 /* load initrd */ 824 if (machine->initrd_filename) { 825 pnv->initrd_base = INITRD_LOAD_ADDR; 826 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 827 pnv->initrd_base, INITRD_MAX_SIZE); 828 if (pnv->initrd_size < 0) { 829 error_report("Could not load initial ram disk '%s'", 830 machine->initrd_filename); 831 exit(1); 832 } 833 } 834 835 /* MSIs are supported on this platform */ 836 msi_nonbroken = true; 837 838 /* 839 * Check compatibility of the specified CPU with the machine 840 * default. 841 */ 842 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 843 error_report("invalid CPU model '%s' for %s machine", 844 machine->cpu_type, mc->name); 845 exit(1); 846 } 847 848 /* Create the processor chips */ 849 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 850 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 851 i, machine->cpu_type); 852 if (!object_class_by_name(chip_typename)) { 853 error_report("invalid chip model '%.*s' for %s machine", 854 i, machine->cpu_type, mc->name); 855 exit(1); 856 } 857 858 pnv->num_chips = 859 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 860 /* 861 * TODO: should we decide on how many chips we can create based 862 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 863 */ 864 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 865 error_report("invalid number of chips: '%d'", pnv->num_chips); 866 error_printf( 867 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 868 exit(1); 869 } 870 871 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 872 for (i = 0; i < pnv->num_chips; i++) { 873 char chip_name[32]; 874 Object *chip = OBJECT(qdev_new(chip_typename)); 875 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 876 877 pnv->chips[i] = PNV_CHIP(chip); 878 879 /* Distribute RAM among the chips */ 880 object_property_set_int(chip, "ram-start", chip_ram_start, 881 &error_fatal); 882 object_property_set_int(chip, "ram-size", chip_ram_size, 883 &error_fatal); 884 chip_ram_start += chip_ram_size; 885 886 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 887 object_property_add_child(OBJECT(pnv), chip_name, chip); 888 object_property_set_int(chip, "chip-id", i, &error_fatal); 889 object_property_set_int(chip, "nr-cores", machine->smp.cores, 890 &error_fatal); 891 object_property_set_int(chip, "nr-threads", machine->smp.threads, 892 &error_fatal); 893 /* 894 * The POWER8 machine use the XICS interrupt interface. 895 * Propagate the XICS fabric to the chip and its controllers. 896 */ 897 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 898 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 899 } 900 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 901 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 902 &error_abort); 903 } 904 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 905 } 906 g_free(chip_typename); 907 908 /* Instantiate ISA bus on chip 0 */ 909 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 910 911 /* Create serial port */ 912 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 913 914 /* Create an RTC ISA device too */ 915 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 916 917 /* 918 * Create the machine BMC simulator and the IPMI BT device for 919 * communication with the BMC 920 */ 921 if (defaults_enabled()) { 922 pnv->bmc = pnv_bmc_create(pnv->pnor); 923 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 924 } 925 926 /* 927 * The PNOR is mapped on the LPC FW address space by the BMC. 928 * Since we can not reach the remote BMC machine with LPC memops, 929 * map it always for now. 930 */ 931 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 932 &pnv->pnor->mmio); 933 934 /* 935 * OpenPOWER systems use a IPMI SEL Event message to notify the 936 * host to powerdown 937 */ 938 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 939 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 940 } 941 942 /* 943 * 0:21 Reserved - Read as zeros 944 * 22:24 Chip ID 945 * 25:28 Core number 946 * 29:31 Thread ID 947 */ 948 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 949 { 950 return (chip->chip_id << 7) | (core_id << 3); 951 } 952 953 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 954 Error **errp) 955 { 956 Pnv8Chip *chip8 = PNV8_CHIP(chip); 957 Error *local_err = NULL; 958 Object *obj; 959 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 960 961 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 962 if (local_err) { 963 error_propagate(errp, local_err); 964 return; 965 } 966 967 pnv_cpu->intc = obj; 968 } 969 970 971 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 972 { 973 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 974 975 icp_reset(ICP(pnv_cpu->intc)); 976 } 977 978 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 979 { 980 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 981 982 icp_destroy(ICP(pnv_cpu->intc)); 983 pnv_cpu->intc = NULL; 984 } 985 986 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 987 Monitor *mon) 988 { 989 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 990 } 991 992 /* 993 * 0:48 Reserved - Read as zeroes 994 * 49:52 Node ID 995 * 53:55 Chip ID 996 * 56 Reserved - Read as zero 997 * 57:61 Core number 998 * 62:63 Thread ID 999 * 1000 * We only care about the lower bits. uint32_t is fine for the moment. 1001 */ 1002 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 1003 { 1004 return (chip->chip_id << 8) | (core_id << 2); 1005 } 1006 1007 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1008 { 1009 return (chip->chip_id << 8) | (core_id << 2); 1010 } 1011 1012 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1013 Error **errp) 1014 { 1015 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1016 Error *local_err = NULL; 1017 Object *obj; 1018 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1019 1020 /* 1021 * The core creates its interrupt presenter but the XIVE interrupt 1022 * controller object is initialized afterwards. Hopefully, it's 1023 * only used at runtime. 1024 */ 1025 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1026 &local_err); 1027 if (local_err) { 1028 error_propagate(errp, local_err); 1029 return; 1030 } 1031 1032 pnv_cpu->intc = obj; 1033 } 1034 1035 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1036 { 1037 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1038 1039 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1040 } 1041 1042 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1043 { 1044 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1045 1046 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1047 pnv_cpu->intc = NULL; 1048 } 1049 1050 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1051 Monitor *mon) 1052 { 1053 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1054 } 1055 1056 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1057 Error **errp) 1058 { 1059 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1060 Error *local_err = NULL; 1061 Object *obj; 1062 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1063 1064 /* 1065 * The core creates its interrupt presenter but the XIVE2 interrupt 1066 * controller object is initialized afterwards. Hopefully, it's 1067 * only used at runtime. 1068 */ 1069 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1070 &local_err); 1071 if (local_err) { 1072 error_propagate(errp, local_err); 1073 return; 1074 } 1075 1076 pnv_cpu->intc = obj; 1077 } 1078 1079 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1080 { 1081 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1082 1083 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1084 } 1085 1086 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1087 { 1088 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1089 1090 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1091 pnv_cpu->intc = NULL; 1092 } 1093 1094 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1095 Monitor *mon) 1096 { 1097 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1098 } 1099 1100 /* 1101 * Allowed core identifiers on a POWER8 Processor Chip : 1102 * 1103 * <EX0 reserved> 1104 * EX1 - Venice only 1105 * EX2 - Venice only 1106 * EX3 - Venice only 1107 * EX4 1108 * EX5 1109 * EX6 1110 * <EX7,8 reserved> <reserved> 1111 * EX9 - Venice only 1112 * EX10 - Venice only 1113 * EX11 - Venice only 1114 * EX12 1115 * EX13 1116 * EX14 1117 * <EX15 reserved> 1118 */ 1119 #define POWER8E_CORE_MASK (0x7070ull) 1120 #define POWER8_CORE_MASK (0x7e7eull) 1121 1122 /* 1123 * POWER9 has 24 cores, ids starting at 0x0 1124 */ 1125 #define POWER9_CORE_MASK (0xffffffffffffffull) 1126 1127 1128 #define POWER10_CORE_MASK (0xffffffffffffffull) 1129 1130 static void pnv_chip_power8_instance_init(Object *obj) 1131 { 1132 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1133 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1134 int i; 1135 1136 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1137 (Object **)&chip8->xics, 1138 object_property_allow_set_link, 1139 OBJ_PROP_LINK_STRONG); 1140 1141 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1142 1143 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1144 1145 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1146 1147 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1148 1149 chip8->num_phbs = pcc->num_phbs; 1150 1151 for (i = 0; i < chip8->num_phbs; i++) { 1152 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1153 } 1154 1155 } 1156 1157 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1158 { 1159 PnvChip *chip = PNV_CHIP(chip8); 1160 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1161 int i, j; 1162 char *name; 1163 1164 name = g_strdup_printf("icp-%x", chip->chip_id); 1165 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1166 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1167 g_free(name); 1168 1169 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1170 1171 /* Map the ICP registers for each thread */ 1172 for (i = 0; i < chip->nr_cores; i++) { 1173 PnvCore *pnv_core = chip->cores[i]; 1174 int core_hwid = CPU_CORE(pnv_core)->core_id; 1175 1176 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1177 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1178 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1179 1180 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1181 &icp->mmio); 1182 } 1183 } 1184 } 1185 1186 /* 1187 * Attach a root port device. 1188 * 1189 * 'index' will be used both as a PCIE slot value and to calculate 1190 * QOM id. 'chip_id' is going to be used as PCIE chassis for the 1191 * root port. 1192 */ 1193 void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, 1194 int index, int chip_id) 1195 { 1196 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name); 1197 g_autofree char *default_id = g_strdup_printf("%s[%d]", name, index); 1198 const char *dev_id = DEVICE(root)->id; 1199 1200 object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id, 1201 OBJECT(root)); 1202 1203 /* Set unique chassis/slot values for the root port */ 1204 qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id); 1205 qdev_prop_set_uint16(DEVICE(root), "slot", index); 1206 1207 pci_realize_and_unref(root, pci->bus, &error_fatal); 1208 } 1209 1210 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1211 { 1212 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1213 PnvChip *chip = PNV_CHIP(dev); 1214 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1215 Pnv8Psi *psi8 = &chip8->psi; 1216 Error *local_err = NULL; 1217 int i; 1218 1219 assert(chip8->xics); 1220 1221 /* XSCOM bridge is first */ 1222 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1223 if (local_err) { 1224 error_propagate(errp, local_err); 1225 return; 1226 } 1227 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1228 1229 pcc->parent_realize(dev, &local_err); 1230 if (local_err) { 1231 error_propagate(errp, local_err); 1232 return; 1233 } 1234 1235 /* Processor Service Interface (PSI) Host Bridge */ 1236 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1237 &error_fatal); 1238 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1239 OBJECT(chip8->xics), &error_abort); 1240 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1241 return; 1242 } 1243 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1244 &PNV_PSI(psi8)->xscom_regs); 1245 1246 /* Create LPC controller */ 1247 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1248 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1249 1250 chip->fw_mr = &chip8->lpc.isa_fw; 1251 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1252 (uint64_t) PNV_XSCOM_BASE(chip), 1253 PNV_XSCOM_LPC_BASE); 1254 1255 /* 1256 * Interrupt Management Area. This is the memory region holding 1257 * all the Interrupt Control Presenter (ICP) registers 1258 */ 1259 pnv_chip_icp_realize(chip8, &local_err); 1260 if (local_err) { 1261 error_propagate(errp, local_err); 1262 return; 1263 } 1264 1265 /* Create the simplified OCC model */ 1266 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1267 return; 1268 } 1269 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1270 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1271 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); 1272 1273 /* OCC SRAM model */ 1274 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1275 &chip8->occ.sram_regs); 1276 1277 /* HOMER */ 1278 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1279 &error_abort); 1280 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1281 return; 1282 } 1283 /* Homer Xscom region */ 1284 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1285 1286 /* Homer mmio region */ 1287 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1288 &chip8->homer.regs); 1289 1290 /* PHB3 controllers */ 1291 for (i = 0; i < chip8->num_phbs; i++) { 1292 PnvPHB3 *phb = &chip8->phbs[i]; 1293 1294 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1295 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1296 &error_fatal); 1297 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1298 &error_fatal); 1299 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1300 return; 1301 } 1302 } 1303 } 1304 1305 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1306 { 1307 addr &= (PNV_XSCOM_SIZE - 1); 1308 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1309 } 1310 1311 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1312 { 1313 DeviceClass *dc = DEVICE_CLASS(klass); 1314 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1315 1316 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1317 k->cores_mask = POWER8E_CORE_MASK; 1318 k->num_phbs = 3; 1319 k->core_pir = pnv_chip_core_pir_p8; 1320 k->intc_create = pnv_chip_power8_intc_create; 1321 k->intc_reset = pnv_chip_power8_intc_reset; 1322 k->intc_destroy = pnv_chip_power8_intc_destroy; 1323 k->intc_print_info = pnv_chip_power8_intc_print_info; 1324 k->isa_create = pnv_chip_power8_isa_create; 1325 k->dt_populate = pnv_chip_power8_dt_populate; 1326 k->pic_print_info = pnv_chip_power8_pic_print_info; 1327 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1328 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1329 dc->desc = "PowerNV Chip POWER8E"; 1330 1331 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1332 &k->parent_realize); 1333 } 1334 1335 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1336 { 1337 DeviceClass *dc = DEVICE_CLASS(klass); 1338 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1339 1340 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1341 k->cores_mask = POWER8_CORE_MASK; 1342 k->num_phbs = 3; 1343 k->core_pir = pnv_chip_core_pir_p8; 1344 k->intc_create = pnv_chip_power8_intc_create; 1345 k->intc_reset = pnv_chip_power8_intc_reset; 1346 k->intc_destroy = pnv_chip_power8_intc_destroy; 1347 k->intc_print_info = pnv_chip_power8_intc_print_info; 1348 k->isa_create = pnv_chip_power8_isa_create; 1349 k->dt_populate = pnv_chip_power8_dt_populate; 1350 k->pic_print_info = pnv_chip_power8_pic_print_info; 1351 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1352 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1353 dc->desc = "PowerNV Chip POWER8"; 1354 1355 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1356 &k->parent_realize); 1357 } 1358 1359 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1360 { 1361 DeviceClass *dc = DEVICE_CLASS(klass); 1362 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1363 1364 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1365 k->cores_mask = POWER8_CORE_MASK; 1366 k->num_phbs = 4; 1367 k->core_pir = pnv_chip_core_pir_p8; 1368 k->intc_create = pnv_chip_power8_intc_create; 1369 k->intc_reset = pnv_chip_power8_intc_reset; 1370 k->intc_destroy = pnv_chip_power8_intc_destroy; 1371 k->intc_print_info = pnv_chip_power8_intc_print_info; 1372 k->isa_create = pnv_chip_power8nvl_isa_create; 1373 k->dt_populate = pnv_chip_power8_dt_populate; 1374 k->pic_print_info = pnv_chip_power8_pic_print_info; 1375 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1376 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1377 dc->desc = "PowerNV Chip POWER8NVL"; 1378 1379 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1380 &k->parent_realize); 1381 } 1382 1383 static void pnv_chip_power9_instance_init(Object *obj) 1384 { 1385 PnvChip *chip = PNV_CHIP(obj); 1386 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1387 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1388 int i; 1389 1390 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1391 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1392 "xive-fabric"); 1393 1394 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1395 1396 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1397 1398 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1399 1400 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1401 1402 /* Number of PECs is the chip default */ 1403 chip->num_pecs = pcc->num_pecs; 1404 1405 for (i = 0; i < chip->num_pecs; i++) { 1406 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1407 TYPE_PNV_PHB4_PEC); 1408 } 1409 } 1410 1411 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1412 PnvCore *pnv_core) 1413 { 1414 char eq_name[32]; 1415 int core_id = CPU_CORE(pnv_core)->core_id; 1416 1417 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1418 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1419 sizeof(*eq), TYPE_PNV_QUAD, 1420 &error_fatal, NULL); 1421 1422 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1423 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1424 } 1425 1426 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1427 { 1428 PnvChip *chip = PNV_CHIP(chip9); 1429 int i; 1430 1431 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1432 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1433 1434 for (i = 0; i < chip9->nr_quads; i++) { 1435 PnvQuad *eq = &chip9->quads[i]; 1436 1437 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1438 1439 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1440 &eq->xscom_regs); 1441 } 1442 } 1443 1444 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1445 { 1446 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1447 int i; 1448 1449 for (i = 0; i < chip->num_pecs; i++) { 1450 PnvPhb4PecState *pec = &chip9->pecs[i]; 1451 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1452 uint32_t pec_nest_base; 1453 uint32_t pec_pci_base; 1454 1455 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1456 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1457 &error_fatal); 1458 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1459 &error_fatal); 1460 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1461 return; 1462 } 1463 1464 pec_nest_base = pecc->xscom_nest_base(pec); 1465 pec_pci_base = pecc->xscom_pci_base(pec); 1466 1467 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1468 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1469 } 1470 } 1471 1472 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1473 { 1474 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1475 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1476 PnvChip *chip = PNV_CHIP(dev); 1477 Pnv9Psi *psi9 = &chip9->psi; 1478 Error *local_err = NULL; 1479 1480 /* XSCOM bridge is first */ 1481 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1482 if (local_err) { 1483 error_propagate(errp, local_err); 1484 return; 1485 } 1486 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1487 1488 pcc->parent_realize(dev, &local_err); 1489 if (local_err) { 1490 error_propagate(errp, local_err); 1491 return; 1492 } 1493 1494 pnv_chip_quad_realize(chip9, &local_err); 1495 if (local_err) { 1496 error_propagate(errp, local_err); 1497 return; 1498 } 1499 1500 /* XIVE interrupt controller (POWER9) */ 1501 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1502 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1503 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1504 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1505 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1506 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1507 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1508 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1509 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1510 &error_abort); 1511 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1512 return; 1513 } 1514 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1515 &chip9->xive.xscom_regs); 1516 1517 /* Processor Service Interface (PSI) Host Bridge */ 1518 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1519 &error_fatal); 1520 /* This is the only device with 4k ESB pages */ 1521 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1522 &error_fatal); 1523 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1524 return; 1525 } 1526 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1527 &PNV_PSI(psi9)->xscom_regs); 1528 1529 /* LPC */ 1530 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1531 return; 1532 } 1533 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1534 &chip9->lpc.xscom_regs); 1535 1536 chip->fw_mr = &chip9->lpc.isa_fw; 1537 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1538 (uint64_t) PNV9_LPCM_BASE(chip)); 1539 1540 /* Create the simplified OCC model */ 1541 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1542 return; 1543 } 1544 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1545 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1546 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); 1547 1548 /* OCC SRAM model */ 1549 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1550 &chip9->occ.sram_regs); 1551 1552 /* HOMER */ 1553 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1554 &error_abort); 1555 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1556 return; 1557 } 1558 /* Homer Xscom region */ 1559 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1560 1561 /* Homer mmio region */ 1562 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1563 &chip9->homer.regs); 1564 1565 /* PEC PHBs */ 1566 pnv_chip_power9_pec_realize(chip, &local_err); 1567 if (local_err) { 1568 error_propagate(errp, local_err); 1569 return; 1570 } 1571 } 1572 1573 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1574 { 1575 addr &= (PNV9_XSCOM_SIZE - 1); 1576 return addr >> 3; 1577 } 1578 1579 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1580 { 1581 DeviceClass *dc = DEVICE_CLASS(klass); 1582 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1583 1584 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1585 k->cores_mask = POWER9_CORE_MASK; 1586 k->core_pir = pnv_chip_core_pir_p9; 1587 k->intc_create = pnv_chip_power9_intc_create; 1588 k->intc_reset = pnv_chip_power9_intc_reset; 1589 k->intc_destroy = pnv_chip_power9_intc_destroy; 1590 k->intc_print_info = pnv_chip_power9_intc_print_info; 1591 k->isa_create = pnv_chip_power9_isa_create; 1592 k->dt_populate = pnv_chip_power9_dt_populate; 1593 k->pic_print_info = pnv_chip_power9_pic_print_info; 1594 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1595 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1596 dc->desc = "PowerNV Chip POWER9"; 1597 k->num_pecs = PNV9_CHIP_MAX_PEC; 1598 1599 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1600 &k->parent_realize); 1601 } 1602 1603 static void pnv_chip_power10_instance_init(Object *obj) 1604 { 1605 PnvChip *chip = PNV_CHIP(obj); 1606 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1607 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1608 int i; 1609 1610 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1611 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1612 "xive-fabric"); 1613 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1614 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1615 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1616 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1617 1618 chip->num_pecs = pcc->num_pecs; 1619 1620 for (i = 0; i < chip->num_pecs; i++) { 1621 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1622 TYPE_PNV_PHB5_PEC); 1623 } 1624 } 1625 1626 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1627 { 1628 PnvChip *chip = PNV_CHIP(chip10); 1629 int i; 1630 1631 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1632 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1633 1634 for (i = 0; i < chip10->nr_quads; i++) { 1635 PnvQuad *eq = &chip10->quads[i]; 1636 1637 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1638 1639 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1640 &eq->xscom_regs); 1641 } 1642 } 1643 1644 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1645 { 1646 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1647 int i; 1648 1649 for (i = 0; i < chip->num_pecs; i++) { 1650 PnvPhb4PecState *pec = &chip10->pecs[i]; 1651 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1652 uint32_t pec_nest_base; 1653 uint32_t pec_pci_base; 1654 1655 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1656 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1657 &error_fatal); 1658 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1659 &error_fatal); 1660 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1661 return; 1662 } 1663 1664 pec_nest_base = pecc->xscom_nest_base(pec); 1665 pec_pci_base = pecc->xscom_pci_base(pec); 1666 1667 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1668 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1669 } 1670 } 1671 1672 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1673 { 1674 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1675 PnvChip *chip = PNV_CHIP(dev); 1676 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1677 Error *local_err = NULL; 1678 1679 /* XSCOM bridge is first */ 1680 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1681 if (local_err) { 1682 error_propagate(errp, local_err); 1683 return; 1684 } 1685 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1686 1687 pcc->parent_realize(dev, &local_err); 1688 if (local_err) { 1689 error_propagate(errp, local_err); 1690 return; 1691 } 1692 1693 pnv_chip_power10_quad_realize(chip10, &local_err); 1694 if (local_err) { 1695 error_propagate(errp, local_err); 1696 return; 1697 } 1698 1699 /* XIVE2 interrupt controller (POWER10) */ 1700 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1701 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1702 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1703 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1704 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1705 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1706 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1707 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1708 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1709 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1710 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1711 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1712 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1713 &error_abort); 1714 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1715 return; 1716 } 1717 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1718 &chip10->xive.xscom_regs); 1719 1720 /* Processor Service Interface (PSI) Host Bridge */ 1721 object_property_set_int(OBJECT(&chip10->psi), "bar", 1722 PNV10_PSIHB_BASE(chip), &error_fatal); 1723 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1724 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1725 &error_fatal); 1726 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1727 return; 1728 } 1729 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1730 &PNV_PSI(&chip10->psi)->xscom_regs); 1731 1732 /* LPC */ 1733 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1734 return; 1735 } 1736 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1737 &chip10->lpc.xscom_regs); 1738 1739 chip->fw_mr = &chip10->lpc.isa_fw; 1740 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1741 (uint64_t) PNV10_LPCM_BASE(chip)); 1742 1743 /* Create the simplified OCC model */ 1744 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1745 return; 1746 } 1747 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1748 &chip10->occ.xscom_regs); 1749 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1750 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1751 1752 /* OCC SRAM model */ 1753 memory_region_add_subregion(get_system_memory(), 1754 PNV10_OCC_SENSOR_BASE(chip), 1755 &chip10->occ.sram_regs); 1756 1757 /* HOMER */ 1758 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1759 &error_abort); 1760 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1761 return; 1762 } 1763 /* Homer Xscom region */ 1764 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1765 &chip10->homer.pba_regs); 1766 1767 /* Homer mmio region */ 1768 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1769 &chip10->homer.regs); 1770 1771 /* PHBs */ 1772 pnv_chip_power10_phb_realize(chip, &local_err); 1773 if (local_err) { 1774 error_propagate(errp, local_err); 1775 return; 1776 } 1777 } 1778 1779 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1780 { 1781 addr &= (PNV10_XSCOM_SIZE - 1); 1782 return addr >> 3; 1783 } 1784 1785 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1786 { 1787 DeviceClass *dc = DEVICE_CLASS(klass); 1788 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1789 1790 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1791 k->cores_mask = POWER10_CORE_MASK; 1792 k->core_pir = pnv_chip_core_pir_p10; 1793 k->intc_create = pnv_chip_power10_intc_create; 1794 k->intc_reset = pnv_chip_power10_intc_reset; 1795 k->intc_destroy = pnv_chip_power10_intc_destroy; 1796 k->intc_print_info = pnv_chip_power10_intc_print_info; 1797 k->isa_create = pnv_chip_power10_isa_create; 1798 k->dt_populate = pnv_chip_power10_dt_populate; 1799 k->pic_print_info = pnv_chip_power10_pic_print_info; 1800 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1801 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1802 dc->desc = "PowerNV Chip POWER10"; 1803 k->num_pecs = PNV10_CHIP_MAX_PEC; 1804 1805 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1806 &k->parent_realize); 1807 } 1808 1809 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1810 { 1811 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1812 int cores_max; 1813 1814 /* 1815 * No custom mask for this chip, let's use the default one from * 1816 * the chip class 1817 */ 1818 if (!chip->cores_mask) { 1819 chip->cores_mask = pcc->cores_mask; 1820 } 1821 1822 /* filter alien core ids ! some are reserved */ 1823 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1824 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1825 chip->cores_mask); 1826 return; 1827 } 1828 chip->cores_mask &= pcc->cores_mask; 1829 1830 /* now that we have a sane layout, let check the number of cores */ 1831 cores_max = ctpop64(chip->cores_mask); 1832 if (chip->nr_cores > cores_max) { 1833 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1834 cores_max); 1835 return; 1836 } 1837 } 1838 1839 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1840 { 1841 Error *error = NULL; 1842 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1843 const char *typename = pnv_chip_core_typename(chip); 1844 int i, core_hwid; 1845 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1846 1847 if (!object_class_by_name(typename)) { 1848 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1849 return; 1850 } 1851 1852 /* Cores */ 1853 pnv_chip_core_sanitize(chip, &error); 1854 if (error) { 1855 error_propagate(errp, error); 1856 return; 1857 } 1858 1859 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1860 1861 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1862 && (i < chip->nr_cores); core_hwid++) { 1863 char core_name[32]; 1864 PnvCore *pnv_core; 1865 uint64_t xscom_core_base; 1866 1867 if (!(chip->cores_mask & (1ull << core_hwid))) { 1868 continue; 1869 } 1870 1871 pnv_core = PNV_CORE(object_new(typename)); 1872 1873 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1874 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1875 chip->cores[i] = pnv_core; 1876 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1877 chip->nr_threads, &error_fatal); 1878 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1879 core_hwid, &error_fatal); 1880 object_property_set_int(OBJECT(pnv_core), "pir", 1881 pcc->core_pir(chip, core_hwid), &error_fatal); 1882 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1883 &error_fatal); 1884 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1885 &error_abort); 1886 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1887 1888 /* Each core has an XSCOM MMIO region */ 1889 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1890 1891 pnv_xscom_add_subregion(chip, xscom_core_base, 1892 &pnv_core->xscom_regs); 1893 i++; 1894 } 1895 } 1896 1897 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1898 { 1899 PnvChip *chip = PNV_CHIP(dev); 1900 Error *error = NULL; 1901 1902 /* Cores */ 1903 pnv_chip_core_realize(chip, &error); 1904 if (error) { 1905 error_propagate(errp, error); 1906 return; 1907 } 1908 } 1909 1910 static Property pnv_chip_properties[] = { 1911 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1912 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1913 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1914 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1915 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1916 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1917 DEFINE_PROP_END_OF_LIST(), 1918 }; 1919 1920 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1921 { 1922 DeviceClass *dc = DEVICE_CLASS(klass); 1923 1924 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1925 dc->realize = pnv_chip_realize; 1926 device_class_set_props(dc, pnv_chip_properties); 1927 dc->desc = "PowerNV Chip"; 1928 } 1929 1930 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1931 { 1932 int i, j; 1933 1934 for (i = 0; i < chip->nr_cores; i++) { 1935 PnvCore *pc = chip->cores[i]; 1936 CPUCore *cc = CPU_CORE(pc); 1937 1938 for (j = 0; j < cc->nr_threads; j++) { 1939 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1940 return pc->threads[j]; 1941 } 1942 } 1943 } 1944 return NULL; 1945 } 1946 1947 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1948 { 1949 PnvMachineState *pnv = PNV_MACHINE(xi); 1950 int i, j; 1951 1952 for (i = 0; i < pnv->num_chips; i++) { 1953 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1954 1955 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1956 return &chip8->psi.ics; 1957 } 1958 1959 for (j = 0; j < chip8->num_phbs; j++) { 1960 PnvPHB3 *phb3 = &chip8->phbs[j]; 1961 1962 if (ics_valid_irq(&phb3->lsis, irq)) { 1963 return &phb3->lsis; 1964 } 1965 1966 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 1967 return ICS(&phb3->msis); 1968 } 1969 } 1970 } 1971 return NULL; 1972 } 1973 1974 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 1975 { 1976 int i; 1977 1978 for (i = 0; i < pnv->num_chips; i++) { 1979 PnvChip *chip = pnv->chips[i]; 1980 if (chip->chip_id == chip_id) { 1981 return chip; 1982 } 1983 } 1984 return NULL; 1985 } 1986 1987 static void pnv_ics_resend(XICSFabric *xi) 1988 { 1989 PnvMachineState *pnv = PNV_MACHINE(xi); 1990 int i, j; 1991 1992 for (i = 0; i < pnv->num_chips; i++) { 1993 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1994 1995 ics_resend(&chip8->psi.ics); 1996 1997 for (j = 0; j < chip8->num_phbs; j++) { 1998 PnvPHB3 *phb3 = &chip8->phbs[j]; 1999 2000 ics_resend(&phb3->lsis); 2001 ics_resend(ICS(&phb3->msis)); 2002 } 2003 } 2004 } 2005 2006 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2007 { 2008 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2009 2010 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2011 } 2012 2013 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2014 Monitor *mon) 2015 { 2016 PnvMachineState *pnv = PNV_MACHINE(obj); 2017 int i; 2018 CPUState *cs; 2019 2020 CPU_FOREACH(cs) { 2021 PowerPCCPU *cpu = POWERPC_CPU(cs); 2022 2023 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2024 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2025 mon); 2026 } 2027 2028 for (i = 0; i < pnv->num_chips; i++) { 2029 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2030 } 2031 } 2032 2033 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2034 uint8_t nvt_blk, uint32_t nvt_idx, 2035 bool cam_ignore, uint8_t priority, 2036 uint32_t logic_serv, 2037 XiveTCTXMatch *match) 2038 { 2039 PnvMachineState *pnv = PNV_MACHINE(xfb); 2040 int total_count = 0; 2041 int i; 2042 2043 for (i = 0; i < pnv->num_chips; i++) { 2044 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2045 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2046 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2047 int count; 2048 2049 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2050 priority, logic_serv, match); 2051 2052 if (count < 0) { 2053 return count; 2054 } 2055 2056 total_count += count; 2057 } 2058 2059 return total_count; 2060 } 2061 2062 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2063 uint8_t nvt_blk, uint32_t nvt_idx, 2064 bool cam_ignore, uint8_t priority, 2065 uint32_t logic_serv, 2066 XiveTCTXMatch *match) 2067 { 2068 PnvMachineState *pnv = PNV_MACHINE(xfb); 2069 int total_count = 0; 2070 int i; 2071 2072 for (i = 0; i < pnv->num_chips; i++) { 2073 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2074 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2075 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2076 int count; 2077 2078 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2079 priority, logic_serv, match); 2080 2081 if (count < 0) { 2082 return count; 2083 } 2084 2085 total_count += count; 2086 } 2087 2088 return total_count; 2089 } 2090 2091 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2092 { 2093 MachineClass *mc = MACHINE_CLASS(oc); 2094 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2095 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2096 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2097 2098 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2099 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2100 2101 xic->icp_get = pnv_icp_get; 2102 xic->ics_get = pnv_ics_get; 2103 xic->ics_resend = pnv_ics_resend; 2104 2105 pmc->compat = compat; 2106 pmc->compat_size = sizeof(compat); 2107 } 2108 2109 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2110 { 2111 MachineClass *mc = MACHINE_CLASS(oc); 2112 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2113 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2114 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2115 2116 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2117 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 2118 xfc->match_nvt = pnv_match_nvt; 2119 2120 mc->alias = "powernv"; 2121 2122 pmc->compat = compat; 2123 pmc->compat_size = sizeof(compat); 2124 pmc->dt_power_mgt = pnv_dt_power_mgt; 2125 } 2126 2127 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2128 { 2129 MachineClass *mc = MACHINE_CLASS(oc); 2130 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2131 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2132 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2133 2134 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2135 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2136 2137 pmc->compat = compat; 2138 pmc->compat_size = sizeof(compat); 2139 pmc->dt_power_mgt = pnv_dt_power_mgt; 2140 2141 xfc->match_nvt = pnv10_xive_match_nvt; 2142 } 2143 2144 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2145 { 2146 PnvMachineState *pnv = PNV_MACHINE(obj); 2147 2148 return !!pnv->fw_load_addr; 2149 } 2150 2151 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2152 { 2153 PnvMachineState *pnv = PNV_MACHINE(obj); 2154 2155 if (value) { 2156 pnv->fw_load_addr = 0x8000000; 2157 } 2158 } 2159 2160 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2161 { 2162 PowerPCCPU *cpu = POWERPC_CPU(cs); 2163 CPUPPCState *env = &cpu->env; 2164 2165 cpu_synchronize_state(cs); 2166 ppc_cpu_do_system_reset(cs); 2167 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2168 /* 2169 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2170 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2171 * (PPC_BIT(43)). 2172 */ 2173 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2174 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2175 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2176 } 2177 } else { 2178 /* 2179 * For non-powersave system resets, SRR1[42:45] are defined to be 2180 * implementation-dependent. The POWER9 User Manual specifies that 2181 * an external (SCOM driven, which may come from a BMC nmi command or 2182 * another CPU requesting a NMI IPI) system reset exception should be 2183 * 0b0010 (PPC_BIT(44)). 2184 */ 2185 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2186 } 2187 } 2188 2189 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2190 { 2191 CPUState *cs; 2192 2193 CPU_FOREACH(cs) { 2194 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2195 } 2196 } 2197 2198 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2199 { 2200 MachineClass *mc = MACHINE_CLASS(oc); 2201 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2202 NMIClass *nc = NMI_CLASS(oc); 2203 2204 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2205 mc->init = pnv_init; 2206 mc->reset = pnv_reset; 2207 mc->max_cpus = MAX_CPUS; 2208 /* Pnv provides a AHCI device for storage */ 2209 mc->block_default_type = IF_IDE; 2210 mc->no_parallel = 1; 2211 mc->default_boot_order = NULL; 2212 /* 2213 * RAM defaults to less than 2048 for 32-bit hosts, and large 2214 * enough to fit the maximum initrd size at it's load address 2215 */ 2216 mc->default_ram_size = 1 * GiB; 2217 mc->default_ram_id = "pnv.ram"; 2218 ispc->print_info = pnv_pic_print_info; 2219 nc->nmi_monitor_handler = pnv_nmi; 2220 2221 object_class_property_add_bool(oc, "hb-mode", 2222 pnv_machine_get_hb, pnv_machine_set_hb); 2223 object_class_property_set_description(oc, "hb-mode", 2224 "Use a hostboot like boot loader"); 2225 } 2226 2227 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2228 { \ 2229 .name = type, \ 2230 .class_init = class_initfn, \ 2231 .parent = TYPE_PNV8_CHIP, \ 2232 } 2233 2234 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2235 { \ 2236 .name = type, \ 2237 .class_init = class_initfn, \ 2238 .parent = TYPE_PNV9_CHIP, \ 2239 } 2240 2241 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2242 { \ 2243 .name = type, \ 2244 .class_init = class_initfn, \ 2245 .parent = TYPE_PNV10_CHIP, \ 2246 } 2247 2248 static const TypeInfo types[] = { 2249 { 2250 .name = MACHINE_TYPE_NAME("powernv10"), 2251 .parent = TYPE_PNV_MACHINE, 2252 .class_init = pnv_machine_power10_class_init, 2253 .interfaces = (InterfaceInfo[]) { 2254 { TYPE_XIVE_FABRIC }, 2255 { }, 2256 }, 2257 }, 2258 { 2259 .name = MACHINE_TYPE_NAME("powernv9"), 2260 .parent = TYPE_PNV_MACHINE, 2261 .class_init = pnv_machine_power9_class_init, 2262 .interfaces = (InterfaceInfo[]) { 2263 { TYPE_XIVE_FABRIC }, 2264 { }, 2265 }, 2266 }, 2267 { 2268 .name = MACHINE_TYPE_NAME("powernv8"), 2269 .parent = TYPE_PNV_MACHINE, 2270 .class_init = pnv_machine_power8_class_init, 2271 .interfaces = (InterfaceInfo[]) { 2272 { TYPE_XICS_FABRIC }, 2273 { }, 2274 }, 2275 }, 2276 { 2277 .name = TYPE_PNV_MACHINE, 2278 .parent = TYPE_MACHINE, 2279 .abstract = true, 2280 .instance_size = sizeof(PnvMachineState), 2281 .class_init = pnv_machine_class_init, 2282 .class_size = sizeof(PnvMachineClass), 2283 .interfaces = (InterfaceInfo[]) { 2284 { TYPE_INTERRUPT_STATS_PROVIDER }, 2285 { TYPE_NMI }, 2286 { }, 2287 }, 2288 }, 2289 { 2290 .name = TYPE_PNV_CHIP, 2291 .parent = TYPE_SYS_BUS_DEVICE, 2292 .class_init = pnv_chip_class_init, 2293 .instance_size = sizeof(PnvChip), 2294 .class_size = sizeof(PnvChipClass), 2295 .abstract = true, 2296 }, 2297 2298 /* 2299 * P10 chip and variants 2300 */ 2301 { 2302 .name = TYPE_PNV10_CHIP, 2303 .parent = TYPE_PNV_CHIP, 2304 .instance_init = pnv_chip_power10_instance_init, 2305 .instance_size = sizeof(Pnv10Chip), 2306 }, 2307 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2308 2309 /* 2310 * P9 chip and variants 2311 */ 2312 { 2313 .name = TYPE_PNV9_CHIP, 2314 .parent = TYPE_PNV_CHIP, 2315 .instance_init = pnv_chip_power9_instance_init, 2316 .instance_size = sizeof(Pnv9Chip), 2317 }, 2318 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2319 2320 /* 2321 * P8 chip and variants 2322 */ 2323 { 2324 .name = TYPE_PNV8_CHIP, 2325 .parent = TYPE_PNV_CHIP, 2326 .instance_init = pnv_chip_power8_instance_init, 2327 .instance_size = sizeof(Pnv8Chip), 2328 }, 2329 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2330 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2331 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2332 pnv_chip_power8nvl_class_init), 2333 }; 2334 2335 DEFINE_TYPES(types) 2336