1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qemu/units.h" 24 #include "qemu/cutils.h" 25 #include "qapi/error.h" 26 #include "sysemu/qtest.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/reset.h" 30 #include "sysemu/runstate.h" 31 #include "sysemu/cpus.h" 32 #include "sysemu/device_tree.h" 33 #include "sysemu/hw_accel.h" 34 #include "target/ppc/cpu.h" 35 #include "hw/ppc/fdt.h" 36 #include "hw/ppc/ppc.h" 37 #include "hw/ppc/pnv.h" 38 #include "hw/ppc/pnv_core.h" 39 #include "hw/loader.h" 40 #include "hw/nmi.h" 41 #include "qapi/visitor.h" 42 #include "monitor/monitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 48 #include "hw/ppc/xics.h" 49 #include "hw/qdev-properties.h" 50 #include "hw/ppc/pnv_xscom.h" 51 #include "hw/ppc/pnv_pnor.h" 52 53 #include "hw/isa/isa.h" 54 #include "hw/char/serial.h" 55 #include "hw/rtc/mc146818rtc.h" 56 57 #include <libfdt.h> 58 59 #define FDT_MAX_SIZE (1 * MiB) 60 61 #define FW_FILE_NAME "skiboot.lid" 62 #define FW_LOAD_ADDR 0x0 63 #define FW_MAX_SIZE (16 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x20000000 66 #define KERNEL_MAX_SIZE (128 * MiB) 67 #define INITRD_LOAD_ADDR 0x28000000 68 #define INITRD_MAX_SIZE (128 * MiB) 69 70 static const char *pnv_chip_core_typename(const PnvChip *o) 71 { 72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 75 const char *core_type = object_class_get_name(object_class_by_name(s)); 76 g_free(s); 77 return core_type; 78 } 79 80 /* 81 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 82 * 4 * 4 sockets * 12 cores * 8 threads = 1536 83 * Let's make it 2^11 84 */ 85 #define MAX_CPUS 2048 86 87 /* 88 * Memory nodes are created by hostboot, one for each range of memory 89 * that has a different "affinity". In practice, it means one range 90 * per chip. 91 */ 92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 93 { 94 char *mem_name; 95 uint64_t mem_reg_property[2]; 96 int off; 97 98 mem_reg_property[0] = cpu_to_be64(start); 99 mem_reg_property[1] = cpu_to_be64(size); 100 101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 102 off = fdt_add_subnode(fdt, 0, mem_name); 103 g_free(mem_name); 104 105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 107 sizeof(mem_reg_property)))); 108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 109 } 110 111 static int get_cpus_node(void *fdt) 112 { 113 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 114 115 if (cpus_offset < 0) { 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 117 if (cpus_offset) { 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 120 } 121 } 122 _FDT(cpus_offset); 123 return cpus_offset; 124 } 125 126 /* 127 * The PowerNV cores (and threads) need to use real HW ids and not an 128 * incremental index like it has been done on other platforms. This HW 129 * id is stored in the CPU PIR, it is used to create cpu nodes in the 130 * device tree, used in XSCOM to address cores and in interrupt 131 * servers. 132 */ 133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 134 { 135 PowerPCCPU *cpu = pc->threads[0]; 136 CPUState *cs = CPU(cpu); 137 DeviceClass *dc = DEVICE_GET_CLASS(cs); 138 int smt_threads = CPU_CORE(pc)->nr_threads; 139 CPUPPCState *env = &cpu->env; 140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 141 uint32_t servers_prop[smt_threads]; 142 int i; 143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 144 0xffffffff, 0xffffffff}; 145 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 146 uint32_t cpufreq = 1000000000; 147 uint32_t page_sizes_prop[64]; 148 size_t page_sizes_prop_size; 149 const uint8_t pa_features[] = { 24, 0, 150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 154 int offset; 155 char *nodename; 156 int cpus_offset = get_cpus_node(fdt); 157 158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 159 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 160 _FDT(offset); 161 g_free(nodename); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 175 env->icache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 177 env->icache_line_size))); 178 179 if (pcc->l1_dcache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 181 pcc->l1_dcache_size))); 182 } else { 183 warn_report("Unknown L1 dcache size for cpu"); 184 } 185 if (pcc->l1_icache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 187 pcc->l1_icache_size))); 188 } else { 189 warn_report("Unknown L1 icache size for cpu"); 190 } 191 192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 195 cpu->hash64_opts->slb_size))); 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 198 199 if (ppc_has_spr(cpu, SPR_PURR)) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 201 } 202 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 205 segs, sizeof(segs)))); 206 } 207 208 /* 209 * Advertise VMX/VSX (vector extensions) if available 210 * 0 / no property == no vector extensions 211 * 1 == VMX / Altivec available 212 * 2 == VSX available 213 */ 214 if (env->insns_flags & PPC_ALTIVEC) { 215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 216 217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 218 } 219 220 /* 221 * Advertise DFP (Decimal Floating Point) if available 222 * 0 / no property == no DFP 223 * 1 == DFP available 224 */ 225 if (env->insns_flags2 & PPC2_DFP) { 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 227 } 228 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 230 sizeof(page_sizes_prop)); 231 if (page_sizes_prop_size) { 232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 233 page_sizes_prop, page_sizes_prop_size))); 234 } 235 236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 237 pa_features, sizeof(pa_features)))); 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pc->pir + i); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(servers_prop)))); 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 248 uint32_t nr_threads) 249 { 250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 251 char *name; 252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 253 uint32_t irange[2], i, rsize; 254 uint64_t *reg; 255 int offset; 256 257 irange[0] = cpu_to_be32(pir); 258 irange[1] = cpu_to_be32(nr_threads); 259 260 rsize = sizeof(uint64_t) * 2 * nr_threads; 261 reg = g_malloc(rsize); 262 for (i = 0; i < nr_threads; i++) { 263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 264 reg[i * 2 + 1] = cpu_to_be64(0x1000); 265 } 266 267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 268 offset = fdt_add_subnode(fdt, 0, name); 269 _FDT(offset); 270 g_free(name); 271 272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 274 _FDT((fdt_setprop_string(fdt, offset, "device_type", 275 "PowerPC-External-Interrupt-Presentation"))); 276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 278 irange, sizeof(irange)))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 281 g_free(reg); 282 } 283 284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 285 { 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 287 int i; 288 289 pnv_dt_xscom(chip, fdt, 0, 290 cpu_to_be64(PNV_XSCOM_BASE(chip)), 291 cpu_to_be64(PNV_XSCOM_SIZE), 292 compat, sizeof(compat)); 293 294 for (i = 0; i < chip->nr_cores; i++) { 295 PnvCore *pnv_core = chip->cores[i]; 296 297 pnv_dt_core(chip, pnv_core, fdt); 298 299 /* Interrupt Control Presenters (ICP). One per core. */ 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 301 } 302 303 if (chip->ram_size) { 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 305 } 306 } 307 308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 309 { 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 311 int i; 312 313 pnv_dt_xscom(chip, fdt, 0, 314 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 315 cpu_to_be64(PNV9_XSCOM_SIZE), 316 compat, sizeof(compat)); 317 318 for (i = 0; i < chip->nr_cores; i++) { 319 PnvCore *pnv_core = chip->cores[i]; 320 321 pnv_dt_core(chip, pnv_core, fdt); 322 } 323 324 if (chip->ram_size) { 325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 326 } 327 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 329 } 330 331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 332 { 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 334 int i; 335 336 pnv_dt_xscom(chip, fdt, 0, 337 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 338 cpu_to_be64(PNV10_XSCOM_SIZE), 339 compat, sizeof(compat)); 340 341 for (i = 0; i < chip->nr_cores; i++) { 342 PnvCore *pnv_core = chip->cores[i]; 343 344 pnv_dt_core(chip, pnv_core, fdt); 345 } 346 347 if (chip->ram_size) { 348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 349 } 350 351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 352 } 353 354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 355 { 356 uint32_t io_base = d->ioport_id; 357 uint32_t io_regs[] = { 358 cpu_to_be32(1), 359 cpu_to_be32(io_base), 360 cpu_to_be32(2) 361 }; 362 char *name; 363 int node; 364 365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 366 node = fdt_add_subnode(fdt, lpc_off, name); 367 _FDT(node); 368 g_free(name); 369 370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 372 } 373 374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 375 { 376 const char compatible[] = "ns16550\0pnpPNP,501"; 377 uint32_t io_base = d->ioport_id; 378 uint32_t io_regs[] = { 379 cpu_to_be32(1), 380 cpu_to_be32(io_base), 381 cpu_to_be32(8) 382 }; 383 char *name; 384 int node; 385 386 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 387 node = fdt_add_subnode(fdt, lpc_off, name); 388 _FDT(node); 389 g_free(name); 390 391 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 392 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 393 sizeof(compatible)))); 394 395 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 396 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 397 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 398 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 399 fdt_get_phandle(fdt, lpc_off)))); 400 401 /* This is needed by Linux */ 402 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 403 } 404 405 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 406 { 407 const char compatible[] = "bt\0ipmi-bt"; 408 uint32_t io_base; 409 uint32_t io_regs[] = { 410 cpu_to_be32(1), 411 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 412 cpu_to_be32(3) 413 }; 414 uint32_t irq; 415 char *name; 416 int node; 417 418 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 419 io_regs[1] = cpu_to_be32(io_base); 420 421 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 422 423 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 424 node = fdt_add_subnode(fdt, lpc_off, name); 425 _FDT(node); 426 g_free(name); 427 428 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 429 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 430 sizeof(compatible)))); 431 432 /* Mark it as reserved to avoid Linux trying to claim it */ 433 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 434 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 435 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 436 fdt_get_phandle(fdt, lpc_off)))); 437 } 438 439 typedef struct ForeachPopulateArgs { 440 void *fdt; 441 int offset; 442 } ForeachPopulateArgs; 443 444 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 445 { 446 ForeachPopulateArgs *args = opaque; 447 ISADevice *d = ISA_DEVICE(dev); 448 449 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 450 pnv_dt_rtc(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 452 pnv_dt_serial(d, args->fdt, args->offset); 453 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 454 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 455 } else { 456 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 457 d->ioport_id); 458 } 459 460 return 0; 461 } 462 463 /* 464 * The default LPC bus of a multichip system is on chip 0. It's 465 * recognized by the firmware (skiboot) using a "primary" property. 466 */ 467 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 468 { 469 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 470 ForeachPopulateArgs args = { 471 .fdt = fdt, 472 .offset = isa_offset, 473 }; 474 uint32_t phandle; 475 476 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 477 478 phandle = qemu_fdt_alloc_phandle(fdt); 479 assert(phandle > 0); 480 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 481 482 /* 483 * ISA devices are not necessarily parented to the ISA bus so we 484 * can not use object_child_foreach() 485 */ 486 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 487 &args); 488 } 489 490 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 491 { 492 int off; 493 494 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 495 off = fdt_add_subnode(fdt, off, "power-mgt"); 496 497 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 498 } 499 500 static void *pnv_dt_create(MachineState *machine) 501 { 502 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 503 PnvMachineState *pnv = PNV_MACHINE(machine); 504 void *fdt; 505 char *buf; 506 int off; 507 int i; 508 509 fdt = g_malloc0(FDT_MAX_SIZE); 510 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 511 512 /* /qemu node */ 513 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 514 515 /* Root node */ 516 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 517 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 518 _FDT((fdt_setprop_string(fdt, 0, "model", 519 "IBM PowerNV (emulated by qemu)"))); 520 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 521 522 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 523 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 524 if (qemu_uuid_set) { 525 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 526 } 527 g_free(buf); 528 529 off = fdt_add_subnode(fdt, 0, "chosen"); 530 if (machine->kernel_cmdline) { 531 _FDT((fdt_setprop_string(fdt, off, "bootargs", 532 machine->kernel_cmdline))); 533 } 534 535 if (pnv->initrd_size) { 536 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 537 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 538 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 540 &start_prop, sizeof(start_prop)))); 541 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 542 &end_prop, sizeof(end_prop)))); 543 } 544 545 /* Populate device tree for each chip */ 546 for (i = 0; i < pnv->num_chips; i++) { 547 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 548 } 549 550 /* Populate ISA devices on chip 0 */ 551 pnv_dt_isa(pnv, fdt); 552 553 if (pnv->bmc) { 554 pnv_dt_bmc_sensors(pnv->bmc, fdt); 555 } 556 557 /* Create an extra node for power management on machines that support it */ 558 if (pmc->dt_power_mgt) { 559 pmc->dt_power_mgt(pnv, fdt); 560 } 561 562 return fdt; 563 } 564 565 static void pnv_powerdown_notify(Notifier *n, void *opaque) 566 { 567 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 568 569 if (pnv->bmc) { 570 pnv_bmc_powerdown(pnv->bmc); 571 } 572 } 573 574 static void pnv_reset(MachineState *machine) 575 { 576 PnvMachineState *pnv = PNV_MACHINE(machine); 577 IPMIBmc *bmc; 578 void *fdt; 579 580 qemu_devices_reset(); 581 582 /* 583 * The machine should provide by default an internal BMC simulator. 584 * If not, try to use the BMC device that was provided on the command 585 * line. 586 */ 587 bmc = pnv_bmc_find(&error_fatal); 588 if (!pnv->bmc) { 589 if (!bmc) { 590 if (!qtest_enabled()) { 591 warn_report("machine has no BMC device. Use '-device " 592 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 593 "to define one"); 594 } 595 } else { 596 pnv_bmc_set_pnor(bmc, pnv->pnor); 597 pnv->bmc = bmc; 598 } 599 } 600 601 fdt = pnv_dt_create(machine); 602 603 /* Pack resulting tree */ 604 _FDT((fdt_pack(fdt))); 605 606 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 607 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 608 609 g_free(fdt); 610 } 611 612 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 613 { 614 Pnv8Chip *chip8 = PNV8_CHIP(chip); 615 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 616 } 617 618 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 619 { 620 Pnv8Chip *chip8 = PNV8_CHIP(chip); 621 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 622 } 623 624 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 625 { 626 Pnv9Chip *chip9 = PNV9_CHIP(chip); 627 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 628 } 629 630 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 631 { 632 Pnv10Chip *chip10 = PNV10_CHIP(chip); 633 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 634 } 635 636 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 637 { 638 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 639 } 640 641 static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaque) 642 { 643 Monitor *mon = opaque; 644 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); 645 646 if (phb3) { 647 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 648 ics_pic_print_info(&phb3->lsis, mon); 649 } 650 return 0; 651 } 652 653 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 654 { 655 Pnv8Chip *chip8 = PNV8_CHIP(chip); 656 657 ics_pic_print_info(&chip8->psi.ics, mon); 658 object_child_foreach(OBJECT(chip), 659 pnv_chip_power8_pic_print_info_child, mon); 660 } 661 662 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 663 { 664 Pnv9Chip *chip9 = PNV9_CHIP(chip); 665 int i, j; 666 667 pnv_xive_pic_print_info(&chip9->xive, mon); 668 pnv_psi_pic_print_info(&chip9->psi, mon); 669 670 for (i = 0; i < chip->num_pecs; i++) { 671 PnvPhb4PecState *pec = &chip9->pecs[i]; 672 for (j = 0; j < pec->num_stacks; j++) { 673 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 674 } 675 } 676 } 677 678 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 679 uint32_t core_id) 680 { 681 return PNV_XSCOM_EX_BASE(core_id); 682 } 683 684 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 685 uint32_t core_id) 686 { 687 return PNV9_XSCOM_EC_BASE(core_id); 688 } 689 690 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 691 uint32_t core_id) 692 { 693 return PNV10_XSCOM_EC_BASE(core_id); 694 } 695 696 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 697 { 698 PowerPCCPUClass *ppc_default = 699 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 700 PowerPCCPUClass *ppc = 701 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 702 703 return ppc_default->pvr_match(ppc_default, ppc->pvr); 704 } 705 706 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 707 { 708 ISADevice *dev = isa_new("isa-ipmi-bt"); 709 710 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 711 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 712 isa_realize_and_unref(dev, bus, &error_fatal); 713 } 714 715 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 716 { 717 Pnv10Chip *chip10 = PNV10_CHIP(chip); 718 719 pnv_psi_pic_print_info(&chip10->psi, mon); 720 } 721 722 /* Always give the first 1GB to chip 0 else we won't boot */ 723 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 724 { 725 MachineState *machine = MACHINE(pnv); 726 uint64_t ram_per_chip; 727 728 assert(machine->ram_size >= 1 * GiB); 729 730 ram_per_chip = machine->ram_size / pnv->num_chips; 731 if (ram_per_chip >= 1 * GiB) { 732 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 733 } 734 735 assert(pnv->num_chips > 1); 736 737 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 738 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 739 } 740 741 static void pnv_init(MachineState *machine) 742 { 743 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 744 PnvMachineState *pnv = PNV_MACHINE(machine); 745 MachineClass *mc = MACHINE_GET_CLASS(machine); 746 char *fw_filename; 747 long fw_size; 748 uint64_t chip_ram_start = 0; 749 int i; 750 char *chip_typename; 751 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 752 DeviceState *dev; 753 754 if (kvm_enabled()) { 755 error_report("The powernv machine does not work with KVM acceleration"); 756 exit(EXIT_FAILURE); 757 } 758 759 /* allocate RAM */ 760 if (machine->ram_size < mc->default_ram_size) { 761 char *sz = size_to_str(mc->default_ram_size); 762 error_report("Invalid RAM size, should be bigger than %s", sz); 763 g_free(sz); 764 exit(EXIT_FAILURE); 765 } 766 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 767 768 /* 769 * Create our simple PNOR device 770 */ 771 dev = qdev_new(TYPE_PNV_PNOR); 772 if (pnor) { 773 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 774 } 775 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 776 pnv->pnor = PNV_PNOR(dev); 777 778 /* load skiboot firmware */ 779 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 780 if (!fw_filename) { 781 error_report("Could not find OPAL firmware '%s'", bios_name); 782 exit(1); 783 } 784 785 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 786 if (fw_size < 0) { 787 error_report("Could not load OPAL firmware '%s'", fw_filename); 788 exit(1); 789 } 790 g_free(fw_filename); 791 792 /* load kernel */ 793 if (machine->kernel_filename) { 794 long kernel_size; 795 796 kernel_size = load_image_targphys(machine->kernel_filename, 797 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 798 if (kernel_size < 0) { 799 error_report("Could not load kernel '%s'", 800 machine->kernel_filename); 801 exit(1); 802 } 803 } 804 805 /* load initrd */ 806 if (machine->initrd_filename) { 807 pnv->initrd_base = INITRD_LOAD_ADDR; 808 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 809 pnv->initrd_base, INITRD_MAX_SIZE); 810 if (pnv->initrd_size < 0) { 811 error_report("Could not load initial ram disk '%s'", 812 machine->initrd_filename); 813 exit(1); 814 } 815 } 816 817 /* MSIs are supported on this platform */ 818 msi_nonbroken = true; 819 820 /* 821 * Check compatibility of the specified CPU with the machine 822 * default. 823 */ 824 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 825 error_report("invalid CPU model '%s' for %s machine", 826 machine->cpu_type, mc->name); 827 exit(1); 828 } 829 830 /* Create the processor chips */ 831 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 832 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 833 i, machine->cpu_type); 834 if (!object_class_by_name(chip_typename)) { 835 error_report("invalid chip model '%.*s' for %s machine", 836 i, machine->cpu_type, mc->name); 837 exit(1); 838 } 839 840 pnv->num_chips = 841 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 842 /* 843 * TODO: should we decide on how many chips we can create based 844 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 845 */ 846 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 847 error_report("invalid number of chips: '%d'", pnv->num_chips); 848 error_printf( 849 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 850 exit(1); 851 } 852 853 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 854 for (i = 0; i < pnv->num_chips; i++) { 855 char chip_name[32]; 856 Object *chip = OBJECT(qdev_new(chip_typename)); 857 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 858 859 pnv->chips[i] = PNV_CHIP(chip); 860 861 /* Distribute RAM among the chips */ 862 object_property_set_int(chip, "ram-start", chip_ram_start, 863 &error_fatal); 864 object_property_set_int(chip, "ram-size", chip_ram_size, 865 &error_fatal); 866 chip_ram_start += chip_ram_size; 867 868 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 869 object_property_add_child(OBJECT(pnv), chip_name, chip); 870 object_property_set_int(chip, "chip-id", i, &error_fatal); 871 object_property_set_int(chip, "nr-cores", machine->smp.cores, 872 &error_fatal); 873 object_property_set_int(chip, "nr-threads", machine->smp.threads, 874 &error_fatal); 875 /* 876 * The POWER8 machine use the XICS interrupt interface. 877 * Propagate the XICS fabric to the chip and its controllers. 878 */ 879 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 880 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 881 } 882 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 883 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 884 &error_abort); 885 } 886 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 887 } 888 g_free(chip_typename); 889 890 /* Instantiate ISA bus on chip 0 */ 891 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 892 893 /* Create serial port */ 894 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 895 896 /* Create an RTC ISA device too */ 897 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 898 899 /* 900 * Create the machine BMC simulator and the IPMI BT device for 901 * communication with the BMC 902 */ 903 if (defaults_enabled()) { 904 pnv->bmc = pnv_bmc_create(pnv->pnor); 905 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 906 } 907 908 /* 909 * The PNOR is mapped on the LPC FW address space by the BMC. 910 * Since we can not reach the remote BMC machine with LPC memops, 911 * map it always for now. 912 */ 913 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 914 &pnv->pnor->mmio); 915 916 /* 917 * OpenPOWER systems use a IPMI SEL Event message to notify the 918 * host to powerdown 919 */ 920 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 921 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 922 } 923 924 /* 925 * 0:21 Reserved - Read as zeros 926 * 22:24 Chip ID 927 * 25:28 Core number 928 * 29:31 Thread ID 929 */ 930 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 931 { 932 return (chip->chip_id << 7) | (core_id << 3); 933 } 934 935 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 936 Error **errp) 937 { 938 Pnv8Chip *chip8 = PNV8_CHIP(chip); 939 Error *local_err = NULL; 940 Object *obj; 941 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 942 943 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 944 if (local_err) { 945 error_propagate(errp, local_err); 946 return; 947 } 948 949 pnv_cpu->intc = obj; 950 } 951 952 953 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 954 { 955 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 956 957 icp_reset(ICP(pnv_cpu->intc)); 958 } 959 960 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 961 { 962 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 963 964 icp_destroy(ICP(pnv_cpu->intc)); 965 pnv_cpu->intc = NULL; 966 } 967 968 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 969 Monitor *mon) 970 { 971 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 972 } 973 974 /* 975 * 0:48 Reserved - Read as zeroes 976 * 49:52 Node ID 977 * 53:55 Chip ID 978 * 56 Reserved - Read as zero 979 * 57:61 Core number 980 * 62:63 Thread ID 981 * 982 * We only care about the lower bits. uint32_t is fine for the moment. 983 */ 984 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 985 { 986 return (chip->chip_id << 8) | (core_id << 2); 987 } 988 989 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 990 { 991 return (chip->chip_id << 8) | (core_id << 2); 992 } 993 994 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 995 Error **errp) 996 { 997 Pnv9Chip *chip9 = PNV9_CHIP(chip); 998 Error *local_err = NULL; 999 Object *obj; 1000 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1001 1002 /* 1003 * The core creates its interrupt presenter but the XIVE interrupt 1004 * controller object is initialized afterwards. Hopefully, it's 1005 * only used at runtime. 1006 */ 1007 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1008 &local_err); 1009 if (local_err) { 1010 error_propagate(errp, local_err); 1011 return; 1012 } 1013 1014 pnv_cpu->intc = obj; 1015 } 1016 1017 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1018 { 1019 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1020 1021 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1022 } 1023 1024 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1025 { 1026 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1027 1028 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1029 pnv_cpu->intc = NULL; 1030 } 1031 1032 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1033 Monitor *mon) 1034 { 1035 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1036 } 1037 1038 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1039 Error **errp) 1040 { 1041 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1042 1043 /* Will be defined when the interrupt controller is */ 1044 pnv_cpu->intc = NULL; 1045 } 1046 1047 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1048 { 1049 ; 1050 } 1051 1052 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1053 { 1054 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1055 1056 pnv_cpu->intc = NULL; 1057 } 1058 1059 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1060 Monitor *mon) 1061 { 1062 } 1063 1064 /* 1065 * Allowed core identifiers on a POWER8 Processor Chip : 1066 * 1067 * <EX0 reserved> 1068 * EX1 - Venice only 1069 * EX2 - Venice only 1070 * EX3 - Venice only 1071 * EX4 1072 * EX5 1073 * EX6 1074 * <EX7,8 reserved> <reserved> 1075 * EX9 - Venice only 1076 * EX10 - Venice only 1077 * EX11 - Venice only 1078 * EX12 1079 * EX13 1080 * EX14 1081 * <EX15 reserved> 1082 */ 1083 #define POWER8E_CORE_MASK (0x7070ull) 1084 #define POWER8_CORE_MASK (0x7e7eull) 1085 1086 /* 1087 * POWER9 has 24 cores, ids starting at 0x0 1088 */ 1089 #define POWER9_CORE_MASK (0xffffffffffffffull) 1090 1091 1092 #define POWER10_CORE_MASK (0xffffffffffffffull) 1093 1094 static void pnv_chip_power8_instance_init(Object *obj) 1095 { 1096 PnvChip *chip = PNV_CHIP(obj); 1097 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1098 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1099 int i; 1100 1101 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1102 (Object **)&chip8->xics, 1103 object_property_allow_set_link, 1104 OBJ_PROP_LINK_STRONG); 1105 1106 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1107 1108 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1109 1110 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1111 1112 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1113 1114 for (i = 0; i < pcc->num_phbs; i++) { 1115 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1116 } 1117 1118 /* 1119 * Number of PHBs is the chip default 1120 */ 1121 chip->num_phbs = pcc->num_phbs; 1122 } 1123 1124 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1125 { 1126 PnvChip *chip = PNV_CHIP(chip8); 1127 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1128 int i, j; 1129 char *name; 1130 1131 name = g_strdup_printf("icp-%x", chip->chip_id); 1132 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1133 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1134 g_free(name); 1135 1136 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1137 1138 /* Map the ICP registers for each thread */ 1139 for (i = 0; i < chip->nr_cores; i++) { 1140 PnvCore *pnv_core = chip->cores[i]; 1141 int core_hwid = CPU_CORE(pnv_core)->core_id; 1142 1143 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1144 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1145 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1146 1147 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1148 &icp->mmio); 1149 } 1150 } 1151 } 1152 1153 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1154 { 1155 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1156 PnvChip *chip = PNV_CHIP(dev); 1157 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1158 Pnv8Psi *psi8 = &chip8->psi; 1159 Error *local_err = NULL; 1160 int i; 1161 1162 assert(chip8->xics); 1163 1164 /* XSCOM bridge is first */ 1165 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1166 if (local_err) { 1167 error_propagate(errp, local_err); 1168 return; 1169 } 1170 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1171 1172 pcc->parent_realize(dev, &local_err); 1173 if (local_err) { 1174 error_propagate(errp, local_err); 1175 return; 1176 } 1177 1178 /* Processor Service Interface (PSI) Host Bridge */ 1179 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1180 &error_fatal); 1181 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1182 OBJECT(chip8->xics), &error_abort); 1183 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1184 return; 1185 } 1186 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1187 &PNV_PSI(psi8)->xscom_regs); 1188 1189 /* Create LPC controller */ 1190 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi), 1191 &error_abort); 1192 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1193 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1194 1195 chip->fw_mr = &chip8->lpc.isa_fw; 1196 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1197 (uint64_t) PNV_XSCOM_BASE(chip), 1198 PNV_XSCOM_LPC_BASE); 1199 1200 /* 1201 * Interrupt Management Area. This is the memory region holding 1202 * all the Interrupt Control Presenter (ICP) registers 1203 */ 1204 pnv_chip_icp_realize(chip8, &local_err); 1205 if (local_err) { 1206 error_propagate(errp, local_err); 1207 return; 1208 } 1209 1210 /* Create the simplified OCC model */ 1211 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi), 1212 &error_abort); 1213 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1214 return; 1215 } 1216 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1217 1218 /* OCC SRAM model */ 1219 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1220 &chip8->occ.sram_regs); 1221 1222 /* HOMER */ 1223 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1224 &error_abort); 1225 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1226 return; 1227 } 1228 /* Homer Xscom region */ 1229 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1230 1231 /* Homer mmio region */ 1232 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1233 &chip8->homer.regs); 1234 1235 /* PHB3 controllers */ 1236 for (i = 0; i < chip->num_phbs; i++) { 1237 PnvPHB3 *phb = &chip8->phbs[i]; 1238 1239 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1240 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1241 &error_fatal); 1242 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1243 &error_fatal); 1244 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1245 return; 1246 } 1247 } 1248 } 1249 1250 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1251 { 1252 addr &= (PNV_XSCOM_SIZE - 1); 1253 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1254 } 1255 1256 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1257 { 1258 DeviceClass *dc = DEVICE_CLASS(klass); 1259 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1260 1261 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1262 k->cores_mask = POWER8E_CORE_MASK; 1263 k->num_phbs = 3; 1264 k->core_pir = pnv_chip_core_pir_p8; 1265 k->intc_create = pnv_chip_power8_intc_create; 1266 k->intc_reset = pnv_chip_power8_intc_reset; 1267 k->intc_destroy = pnv_chip_power8_intc_destroy; 1268 k->intc_print_info = pnv_chip_power8_intc_print_info; 1269 k->isa_create = pnv_chip_power8_isa_create; 1270 k->dt_populate = pnv_chip_power8_dt_populate; 1271 k->pic_print_info = pnv_chip_power8_pic_print_info; 1272 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1273 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1274 dc->desc = "PowerNV Chip POWER8E"; 1275 1276 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1277 &k->parent_realize); 1278 } 1279 1280 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1281 { 1282 DeviceClass *dc = DEVICE_CLASS(klass); 1283 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1284 1285 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1286 k->cores_mask = POWER8_CORE_MASK; 1287 k->num_phbs = 3; 1288 k->core_pir = pnv_chip_core_pir_p8; 1289 k->intc_create = pnv_chip_power8_intc_create; 1290 k->intc_reset = pnv_chip_power8_intc_reset; 1291 k->intc_destroy = pnv_chip_power8_intc_destroy; 1292 k->intc_print_info = pnv_chip_power8_intc_print_info; 1293 k->isa_create = pnv_chip_power8_isa_create; 1294 k->dt_populate = pnv_chip_power8_dt_populate; 1295 k->pic_print_info = pnv_chip_power8_pic_print_info; 1296 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1297 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1298 dc->desc = "PowerNV Chip POWER8"; 1299 1300 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1301 &k->parent_realize); 1302 } 1303 1304 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1305 { 1306 DeviceClass *dc = DEVICE_CLASS(klass); 1307 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1308 1309 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1310 k->cores_mask = POWER8_CORE_MASK; 1311 k->num_phbs = 3; 1312 k->core_pir = pnv_chip_core_pir_p8; 1313 k->intc_create = pnv_chip_power8_intc_create; 1314 k->intc_reset = pnv_chip_power8_intc_reset; 1315 k->intc_destroy = pnv_chip_power8_intc_destroy; 1316 k->intc_print_info = pnv_chip_power8_intc_print_info; 1317 k->isa_create = pnv_chip_power8nvl_isa_create; 1318 k->dt_populate = pnv_chip_power8_dt_populate; 1319 k->pic_print_info = pnv_chip_power8_pic_print_info; 1320 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1321 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1322 dc->desc = "PowerNV Chip POWER8NVL"; 1323 1324 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1325 &k->parent_realize); 1326 } 1327 1328 static void pnv_chip_power9_instance_init(Object *obj) 1329 { 1330 PnvChip *chip = PNV_CHIP(obj); 1331 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1332 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1333 int i; 1334 1335 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1336 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1337 "xive-fabric"); 1338 1339 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1340 1341 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1342 1343 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1344 1345 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1346 1347 /* Number of PECs is the chip default */ 1348 chip->num_pecs = pcc->num_pecs; 1349 1350 for (i = 0; i < chip->num_pecs; i++) { 1351 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1352 TYPE_PNV_PHB4_PEC); 1353 } 1354 } 1355 1356 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1357 { 1358 PnvChip *chip = PNV_CHIP(chip9); 1359 int i; 1360 1361 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1362 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1363 1364 for (i = 0; i < chip9->nr_quads; i++) { 1365 char eq_name[32]; 1366 PnvQuad *eq = &chip9->quads[i]; 1367 PnvCore *pnv_core = chip->cores[i * 4]; 1368 int core_id = CPU_CORE(pnv_core)->core_id; 1369 1370 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1371 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1372 sizeof(*eq), TYPE_PNV_QUAD, 1373 &error_fatal, NULL); 1374 1375 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1376 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1377 1378 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1379 &eq->xscom_regs); 1380 } 1381 } 1382 1383 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1384 { 1385 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1386 int i, j; 1387 int phb_id = 0; 1388 1389 for (i = 0; i < chip->num_pecs; i++) { 1390 PnvPhb4PecState *pec = &chip9->pecs[i]; 1391 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1392 uint32_t pec_nest_base; 1393 uint32_t pec_pci_base; 1394 1395 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1396 /* 1397 * PEC0 -> 1 stack 1398 * PEC1 -> 2 stacks 1399 * PEC2 -> 3 stacks 1400 */ 1401 object_property_set_int(OBJECT(pec), "num-stacks", i + 1, 1402 &error_fatal); 1403 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1404 &error_fatal); 1405 object_property_set_link(OBJECT(pec), "system-memory", 1406 OBJECT(get_system_memory()), &error_abort); 1407 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1408 return; 1409 } 1410 1411 pec_nest_base = pecc->xscom_nest_base(pec); 1412 pec_pci_base = pecc->xscom_pci_base(pec); 1413 1414 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1415 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1416 1417 for (j = 0; j < pec->num_stacks; j++, phb_id++) { 1418 PnvPhb4PecStack *stack = &pec->stacks[j]; 1419 Object *obj = OBJECT(&stack->phb); 1420 1421 object_property_set_int(obj, "index", phb_id, &error_fatal); 1422 object_property_set_int(obj, "chip-id", chip->chip_id, 1423 &error_fatal); 1424 object_property_set_int(obj, "version", PNV_PHB4_VERSION, 1425 &error_fatal); 1426 object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID, 1427 &error_fatal); 1428 object_property_set_link(obj, "stack", OBJECT(stack), 1429 &error_abort); 1430 if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) { 1431 return; 1432 } 1433 1434 /* Populate the XSCOM address space. */ 1435 pnv_xscom_add_subregion(chip, 1436 pec_nest_base + 0x40 * (stack->stack_no + 1), 1437 &stack->nest_regs_mr); 1438 pnv_xscom_add_subregion(chip, 1439 pec_pci_base + 0x40 * (stack->stack_no + 1), 1440 &stack->pci_regs_mr); 1441 pnv_xscom_add_subregion(chip, 1442 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1443 0x40 * stack->stack_no, 1444 &stack->phb_regs_mr); 1445 } 1446 } 1447 } 1448 1449 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1450 { 1451 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1452 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1453 PnvChip *chip = PNV_CHIP(dev); 1454 Pnv9Psi *psi9 = &chip9->psi; 1455 Error *local_err = NULL; 1456 1457 /* XSCOM bridge is first */ 1458 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1459 if (local_err) { 1460 error_propagate(errp, local_err); 1461 return; 1462 } 1463 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1464 1465 pcc->parent_realize(dev, &local_err); 1466 if (local_err) { 1467 error_propagate(errp, local_err); 1468 return; 1469 } 1470 1471 pnv_chip_quad_realize(chip9, &local_err); 1472 if (local_err) { 1473 error_propagate(errp, local_err); 1474 return; 1475 } 1476 1477 /* XIVE interrupt controller (POWER9) */ 1478 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1479 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1480 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1481 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1482 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1483 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1484 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1485 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1486 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1487 &error_abort); 1488 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1489 return; 1490 } 1491 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1492 &chip9->xive.xscom_regs); 1493 1494 /* Processor Service Interface (PSI) Host Bridge */ 1495 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1496 &error_fatal); 1497 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1498 return; 1499 } 1500 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1501 &PNV_PSI(psi9)->xscom_regs); 1502 1503 /* LPC */ 1504 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi), 1505 &error_abort); 1506 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1507 return; 1508 } 1509 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1510 &chip9->lpc.xscom_regs); 1511 1512 chip->fw_mr = &chip9->lpc.isa_fw; 1513 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1514 (uint64_t) PNV9_LPCM_BASE(chip)); 1515 1516 /* Create the simplified OCC model */ 1517 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi), 1518 &error_abort); 1519 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1520 return; 1521 } 1522 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1523 1524 /* OCC SRAM model */ 1525 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1526 &chip9->occ.sram_regs); 1527 1528 /* HOMER */ 1529 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1530 &error_abort); 1531 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1532 return; 1533 } 1534 /* Homer Xscom region */ 1535 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1536 1537 /* Homer mmio region */ 1538 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1539 &chip9->homer.regs); 1540 1541 /* PHBs */ 1542 pnv_chip_power9_phb_realize(chip, &local_err); 1543 if (local_err) { 1544 error_propagate(errp, local_err); 1545 return; 1546 } 1547 } 1548 1549 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1550 { 1551 addr &= (PNV9_XSCOM_SIZE - 1); 1552 return addr >> 3; 1553 } 1554 1555 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1556 { 1557 DeviceClass *dc = DEVICE_CLASS(klass); 1558 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1559 1560 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1561 k->cores_mask = POWER9_CORE_MASK; 1562 k->core_pir = pnv_chip_core_pir_p9; 1563 k->intc_create = pnv_chip_power9_intc_create; 1564 k->intc_reset = pnv_chip_power9_intc_reset; 1565 k->intc_destroy = pnv_chip_power9_intc_destroy; 1566 k->intc_print_info = pnv_chip_power9_intc_print_info; 1567 k->isa_create = pnv_chip_power9_isa_create; 1568 k->dt_populate = pnv_chip_power9_dt_populate; 1569 k->pic_print_info = pnv_chip_power9_pic_print_info; 1570 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1571 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1572 dc->desc = "PowerNV Chip POWER9"; 1573 k->num_pecs = PNV9_CHIP_MAX_PEC; 1574 1575 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1576 &k->parent_realize); 1577 } 1578 1579 static void pnv_chip_power10_instance_init(Object *obj) 1580 { 1581 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1582 1583 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1584 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1585 } 1586 1587 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1588 { 1589 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1590 PnvChip *chip = PNV_CHIP(dev); 1591 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1592 Error *local_err = NULL; 1593 1594 /* XSCOM bridge is first */ 1595 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1596 if (local_err) { 1597 error_propagate(errp, local_err); 1598 return; 1599 } 1600 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1601 1602 pcc->parent_realize(dev, &local_err); 1603 if (local_err) { 1604 error_propagate(errp, local_err); 1605 return; 1606 } 1607 1608 /* Processor Service Interface (PSI) Host Bridge */ 1609 object_property_set_int(OBJECT(&chip10->psi), "bar", 1610 PNV10_PSIHB_BASE(chip), &error_fatal); 1611 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1612 return; 1613 } 1614 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1615 &PNV_PSI(&chip10->psi)->xscom_regs); 1616 1617 /* LPC */ 1618 object_property_set_link(OBJECT(&chip10->lpc), "psi", 1619 OBJECT(&chip10->psi), &error_abort); 1620 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1621 return; 1622 } 1623 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1624 &chip10->lpc.xscom_regs); 1625 1626 chip->fw_mr = &chip10->lpc.isa_fw; 1627 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1628 (uint64_t) PNV10_LPCM_BASE(chip)); 1629 } 1630 1631 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1632 { 1633 addr &= (PNV10_XSCOM_SIZE - 1); 1634 return addr >> 3; 1635 } 1636 1637 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1638 { 1639 DeviceClass *dc = DEVICE_CLASS(klass); 1640 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1641 1642 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1643 k->cores_mask = POWER10_CORE_MASK; 1644 k->core_pir = pnv_chip_core_pir_p10; 1645 k->intc_create = pnv_chip_power10_intc_create; 1646 k->intc_reset = pnv_chip_power10_intc_reset; 1647 k->intc_destroy = pnv_chip_power10_intc_destroy; 1648 k->intc_print_info = pnv_chip_power10_intc_print_info; 1649 k->isa_create = pnv_chip_power10_isa_create; 1650 k->dt_populate = pnv_chip_power10_dt_populate; 1651 k->pic_print_info = pnv_chip_power10_pic_print_info; 1652 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1653 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1654 dc->desc = "PowerNV Chip POWER10"; 1655 1656 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1657 &k->parent_realize); 1658 } 1659 1660 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1661 { 1662 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1663 int cores_max; 1664 1665 /* 1666 * No custom mask for this chip, let's use the default one from * 1667 * the chip class 1668 */ 1669 if (!chip->cores_mask) { 1670 chip->cores_mask = pcc->cores_mask; 1671 } 1672 1673 /* filter alien core ids ! some are reserved */ 1674 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1675 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1676 chip->cores_mask); 1677 return; 1678 } 1679 chip->cores_mask &= pcc->cores_mask; 1680 1681 /* now that we have a sane layout, let check the number of cores */ 1682 cores_max = ctpop64(chip->cores_mask); 1683 if (chip->nr_cores > cores_max) { 1684 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1685 cores_max); 1686 return; 1687 } 1688 } 1689 1690 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1691 { 1692 Error *error = NULL; 1693 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1694 const char *typename = pnv_chip_core_typename(chip); 1695 int i, core_hwid; 1696 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1697 1698 if (!object_class_by_name(typename)) { 1699 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1700 return; 1701 } 1702 1703 /* Cores */ 1704 pnv_chip_core_sanitize(chip, &error); 1705 if (error) { 1706 error_propagate(errp, error); 1707 return; 1708 } 1709 1710 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1711 1712 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1713 && (i < chip->nr_cores); core_hwid++) { 1714 char core_name[32]; 1715 PnvCore *pnv_core; 1716 uint64_t xscom_core_base; 1717 1718 if (!(chip->cores_mask & (1ull << core_hwid))) { 1719 continue; 1720 } 1721 1722 pnv_core = PNV_CORE(object_new(typename)); 1723 1724 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1725 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1726 chip->cores[i] = pnv_core; 1727 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1728 chip->nr_threads, &error_fatal); 1729 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1730 core_hwid, &error_fatal); 1731 object_property_set_int(OBJECT(pnv_core), "pir", 1732 pcc->core_pir(chip, core_hwid), &error_fatal); 1733 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1734 &error_fatal); 1735 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1736 &error_abort); 1737 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1738 1739 /* Each core has an XSCOM MMIO region */ 1740 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1741 1742 pnv_xscom_add_subregion(chip, xscom_core_base, 1743 &pnv_core->xscom_regs); 1744 i++; 1745 } 1746 } 1747 1748 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1749 { 1750 PnvChip *chip = PNV_CHIP(dev); 1751 Error *error = NULL; 1752 1753 /* Cores */ 1754 pnv_chip_core_realize(chip, &error); 1755 if (error) { 1756 error_propagate(errp, error); 1757 return; 1758 } 1759 } 1760 1761 static Property pnv_chip_properties[] = { 1762 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1763 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1764 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1765 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1766 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1767 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1768 DEFINE_PROP_END_OF_LIST(), 1769 }; 1770 1771 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1772 { 1773 DeviceClass *dc = DEVICE_CLASS(klass); 1774 1775 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1776 dc->realize = pnv_chip_realize; 1777 device_class_set_props(dc, pnv_chip_properties); 1778 dc->desc = "PowerNV Chip"; 1779 } 1780 1781 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1782 { 1783 int i, j; 1784 1785 for (i = 0; i < chip->nr_cores; i++) { 1786 PnvCore *pc = chip->cores[i]; 1787 CPUCore *cc = CPU_CORE(pc); 1788 1789 for (j = 0; j < cc->nr_threads; j++) { 1790 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1791 return pc->threads[j]; 1792 } 1793 } 1794 } 1795 return NULL; 1796 } 1797 1798 typedef struct ForeachPhb3Args { 1799 int irq; 1800 ICSState *ics; 1801 } ForeachPhb3Args; 1802 1803 static int pnv_ics_get_child(Object *child, void *opaque) 1804 { 1805 ForeachPhb3Args *args = opaque; 1806 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); 1807 1808 if (phb3) { 1809 if (ics_valid_irq(&phb3->lsis, args->irq)) { 1810 args->ics = &phb3->lsis; 1811 } 1812 if (ics_valid_irq(ICS(&phb3->msis), args->irq)) { 1813 args->ics = ICS(&phb3->msis); 1814 } 1815 } 1816 return args->ics ? 1 : 0; 1817 } 1818 1819 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1820 { 1821 PnvMachineState *pnv = PNV_MACHINE(xi); 1822 ForeachPhb3Args args = { irq, NULL }; 1823 int i; 1824 1825 for (i = 0; i < pnv->num_chips; i++) { 1826 PnvChip *chip = pnv->chips[i]; 1827 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1828 1829 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1830 return &chip8->psi.ics; 1831 } 1832 1833 object_child_foreach(OBJECT(chip), pnv_ics_get_child, &args); 1834 if (args.ics) { 1835 return args.ics; 1836 } 1837 } 1838 return NULL; 1839 } 1840 1841 static int pnv_ics_resend_child(Object *child, void *opaque) 1842 { 1843 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); 1844 1845 if (phb3) { 1846 ics_resend(&phb3->lsis); 1847 ics_resend(ICS(&phb3->msis)); 1848 } 1849 return 0; 1850 } 1851 1852 static void pnv_ics_resend(XICSFabric *xi) 1853 { 1854 PnvMachineState *pnv = PNV_MACHINE(xi); 1855 int i; 1856 1857 for (i = 0; i < pnv->num_chips; i++) { 1858 PnvChip *chip = pnv->chips[i]; 1859 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1860 1861 ics_resend(&chip8->psi.ics); 1862 object_child_foreach(OBJECT(chip), pnv_ics_resend_child, NULL); 1863 } 1864 } 1865 1866 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1867 { 1868 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1869 1870 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1871 } 1872 1873 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1874 Monitor *mon) 1875 { 1876 PnvMachineState *pnv = PNV_MACHINE(obj); 1877 int i; 1878 CPUState *cs; 1879 1880 CPU_FOREACH(cs) { 1881 PowerPCCPU *cpu = POWERPC_CPU(cs); 1882 1883 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1884 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1885 mon); 1886 } 1887 1888 for (i = 0; i < pnv->num_chips; i++) { 1889 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1890 } 1891 } 1892 1893 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1894 uint8_t nvt_blk, uint32_t nvt_idx, 1895 bool cam_ignore, uint8_t priority, 1896 uint32_t logic_serv, 1897 XiveTCTXMatch *match) 1898 { 1899 PnvMachineState *pnv = PNV_MACHINE(xfb); 1900 int total_count = 0; 1901 int i; 1902 1903 for (i = 0; i < pnv->num_chips; i++) { 1904 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1905 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1906 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1907 int count; 1908 1909 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1910 priority, logic_serv, match); 1911 1912 if (count < 0) { 1913 return count; 1914 } 1915 1916 total_count += count; 1917 } 1918 1919 return total_count; 1920 } 1921 1922 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1923 { 1924 MachineClass *mc = MACHINE_CLASS(oc); 1925 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1926 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1927 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1928 1929 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1930 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1931 1932 xic->icp_get = pnv_icp_get; 1933 xic->ics_get = pnv_ics_get; 1934 xic->ics_resend = pnv_ics_resend; 1935 1936 pmc->compat = compat; 1937 pmc->compat_size = sizeof(compat); 1938 } 1939 1940 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1941 { 1942 MachineClass *mc = MACHINE_CLASS(oc); 1943 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1944 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1945 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1946 1947 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1948 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1949 xfc->match_nvt = pnv_match_nvt; 1950 1951 mc->alias = "powernv"; 1952 1953 pmc->compat = compat; 1954 pmc->compat_size = sizeof(compat); 1955 pmc->dt_power_mgt = pnv_dt_power_mgt; 1956 } 1957 1958 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1959 { 1960 MachineClass *mc = MACHINE_CLASS(oc); 1961 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1962 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1963 1964 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1965 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 1966 1967 pmc->compat = compat; 1968 pmc->compat_size = sizeof(compat); 1969 pmc->dt_power_mgt = pnv_dt_power_mgt; 1970 } 1971 1972 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1973 { 1974 PnvMachineState *pnv = PNV_MACHINE(obj); 1975 1976 return !!pnv->fw_load_addr; 1977 } 1978 1979 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1980 { 1981 PnvMachineState *pnv = PNV_MACHINE(obj); 1982 1983 if (value) { 1984 pnv->fw_load_addr = 0x8000000; 1985 } 1986 } 1987 1988 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 1989 { 1990 PowerPCCPU *cpu = POWERPC_CPU(cs); 1991 CPUPPCState *env = &cpu->env; 1992 1993 cpu_synchronize_state(cs); 1994 ppc_cpu_do_system_reset(cs); 1995 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 1996 /* 1997 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 1998 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 1999 * (PPC_BIT(43)). 2000 */ 2001 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2002 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2003 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2004 } 2005 } else { 2006 /* 2007 * For non-powersave system resets, SRR1[42:45] are defined to be 2008 * implementation-dependent. The POWER9 User Manual specifies that 2009 * an external (SCOM driven, which may come from a BMC nmi command or 2010 * another CPU requesting a NMI IPI) system reset exception should be 2011 * 0b0010 (PPC_BIT(44)). 2012 */ 2013 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2014 } 2015 } 2016 2017 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2018 { 2019 CPUState *cs; 2020 2021 CPU_FOREACH(cs) { 2022 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2023 } 2024 } 2025 2026 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2027 { 2028 MachineClass *mc = MACHINE_CLASS(oc); 2029 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2030 NMIClass *nc = NMI_CLASS(oc); 2031 2032 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2033 mc->init = pnv_init; 2034 mc->reset = pnv_reset; 2035 mc->max_cpus = MAX_CPUS; 2036 /* Pnv provides a AHCI device for storage */ 2037 mc->block_default_type = IF_IDE; 2038 mc->no_parallel = 1; 2039 mc->default_boot_order = NULL; 2040 /* 2041 * RAM defaults to less than 2048 for 32-bit hosts, and large 2042 * enough to fit the maximum initrd size at it's load address 2043 */ 2044 mc->default_ram_size = 1 * GiB; 2045 mc->default_ram_id = "pnv.ram"; 2046 ispc->print_info = pnv_pic_print_info; 2047 nc->nmi_monitor_handler = pnv_nmi; 2048 2049 object_class_property_add_bool(oc, "hb-mode", 2050 pnv_machine_get_hb, pnv_machine_set_hb); 2051 object_class_property_set_description(oc, "hb-mode", 2052 "Use a hostboot like boot loader"); 2053 } 2054 2055 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2056 { \ 2057 .name = type, \ 2058 .class_init = class_initfn, \ 2059 .parent = TYPE_PNV8_CHIP, \ 2060 } 2061 2062 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2063 { \ 2064 .name = type, \ 2065 .class_init = class_initfn, \ 2066 .parent = TYPE_PNV9_CHIP, \ 2067 } 2068 2069 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2070 { \ 2071 .name = type, \ 2072 .class_init = class_initfn, \ 2073 .parent = TYPE_PNV10_CHIP, \ 2074 } 2075 2076 static const TypeInfo types[] = { 2077 { 2078 .name = MACHINE_TYPE_NAME("powernv10"), 2079 .parent = TYPE_PNV_MACHINE, 2080 .class_init = pnv_machine_power10_class_init, 2081 }, 2082 { 2083 .name = MACHINE_TYPE_NAME("powernv9"), 2084 .parent = TYPE_PNV_MACHINE, 2085 .class_init = pnv_machine_power9_class_init, 2086 .interfaces = (InterfaceInfo[]) { 2087 { TYPE_XIVE_FABRIC }, 2088 { }, 2089 }, 2090 }, 2091 { 2092 .name = MACHINE_TYPE_NAME("powernv8"), 2093 .parent = TYPE_PNV_MACHINE, 2094 .class_init = pnv_machine_power8_class_init, 2095 .interfaces = (InterfaceInfo[]) { 2096 { TYPE_XICS_FABRIC }, 2097 { }, 2098 }, 2099 }, 2100 { 2101 .name = TYPE_PNV_MACHINE, 2102 .parent = TYPE_MACHINE, 2103 .abstract = true, 2104 .instance_size = sizeof(PnvMachineState), 2105 .class_init = pnv_machine_class_init, 2106 .class_size = sizeof(PnvMachineClass), 2107 .interfaces = (InterfaceInfo[]) { 2108 { TYPE_INTERRUPT_STATS_PROVIDER }, 2109 { TYPE_NMI }, 2110 { }, 2111 }, 2112 }, 2113 { 2114 .name = TYPE_PNV_CHIP, 2115 .parent = TYPE_SYS_BUS_DEVICE, 2116 .class_init = pnv_chip_class_init, 2117 .instance_size = sizeof(PnvChip), 2118 .class_size = sizeof(PnvChipClass), 2119 .abstract = true, 2120 }, 2121 2122 /* 2123 * P10 chip and variants 2124 */ 2125 { 2126 .name = TYPE_PNV10_CHIP, 2127 .parent = TYPE_PNV_CHIP, 2128 .instance_init = pnv_chip_power10_instance_init, 2129 .instance_size = sizeof(Pnv10Chip), 2130 }, 2131 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2132 2133 /* 2134 * P9 chip and variants 2135 */ 2136 { 2137 .name = TYPE_PNV9_CHIP, 2138 .parent = TYPE_PNV_CHIP, 2139 .instance_init = pnv_chip_power9_instance_init, 2140 .instance_size = sizeof(Pnv9Chip), 2141 }, 2142 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2143 2144 /* 2145 * P8 chip and variants 2146 */ 2147 { 2148 .name = TYPE_PNV8_CHIP, 2149 .parent = TYPE_PNV_CHIP, 2150 .instance_init = pnv_chip_power8_instance_init, 2151 .instance_size = sizeof(Pnv8Chip), 2152 }, 2153 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2154 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2155 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2156 pnv_chip_power8nvl_class_init), 2157 }; 2158 2159 DEFINE_TYPES(types) 2160