1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 44 #include "hw/ppc/xics.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/ppc/pnv_xscom.h" 47 #include "hw/ppc/pnv_pnor.h" 48 49 #include "hw/isa/isa.h" 50 #include "hw/boards.h" 51 #include "hw/char/serial.h" 52 #include "hw/rtc/mc146818rtc.h" 53 54 #include <libfdt.h> 55 56 #define FDT_MAX_SIZE (1 * MiB) 57 58 #define FW_FILE_NAME "skiboot.lid" 59 #define FW_LOAD_ADDR 0x0 60 #define FW_MAX_SIZE (4 * MiB) 61 62 #define KERNEL_LOAD_ADDR 0x20000000 63 #define KERNEL_MAX_SIZE (256 * MiB) 64 #define INITRD_LOAD_ADDR 0x60000000 65 #define INITRD_MAX_SIZE (256 * MiB) 66 67 static const char *pnv_chip_core_typename(const PnvChip *o) 68 { 69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 72 const char *core_type = object_class_get_name(object_class_by_name(s)); 73 g_free(s); 74 return core_type; 75 } 76 77 /* 78 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 79 * 4 * 4 sockets * 12 cores * 8 threads = 1536 80 * Let's make it 2^11 81 */ 82 #define MAX_CPUS 2048 83 84 /* 85 * Memory nodes are created by hostboot, one for each range of memory 86 * that has a different "affinity". In practice, it means one range 87 * per chip. 88 */ 89 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 90 { 91 char *mem_name; 92 uint64_t mem_reg_property[2]; 93 int off; 94 95 mem_reg_property[0] = cpu_to_be64(start); 96 mem_reg_property[1] = cpu_to_be64(size); 97 98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 99 off = fdt_add_subnode(fdt, 0, mem_name); 100 g_free(mem_name); 101 102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 104 sizeof(mem_reg_property)))); 105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 106 } 107 108 static int get_cpus_node(void *fdt) 109 { 110 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 111 112 if (cpus_offset < 0) { 113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 114 if (cpus_offset) { 115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 117 } 118 } 119 _FDT(cpus_offset); 120 return cpus_offset; 121 } 122 123 /* 124 * The PowerNV cores (and threads) need to use real HW ids and not an 125 * incremental index like it has been done on other platforms. This HW 126 * id is stored in the CPU PIR, it is used to create cpu nodes in the 127 * device tree, used in XSCOM to address cores and in interrupt 128 * servers. 129 */ 130 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 131 { 132 PowerPCCPU *cpu = pc->threads[0]; 133 CPUState *cs = CPU(cpu); 134 DeviceClass *dc = DEVICE_GET_CLASS(cs); 135 int smt_threads = CPU_CORE(pc)->nr_threads; 136 CPUPPCState *env = &cpu->env; 137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 138 uint32_t servers_prop[smt_threads]; 139 int i; 140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 141 0xffffffff, 0xffffffff}; 142 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 143 uint32_t cpufreq = 1000000000; 144 uint32_t page_sizes_prop[64]; 145 size_t page_sizes_prop_size; 146 const uint8_t pa_features[] = { 24, 0, 147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 151 int offset; 152 char *nodename; 153 int cpus_offset = get_cpus_node(fdt); 154 155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 156 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 157 _FDT(offset); 158 g_free(nodename); 159 160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 161 162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 168 env->dcache_line_size))); 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 170 env->dcache_line_size))); 171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 172 env->icache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 174 env->icache_line_size))); 175 176 if (pcc->l1_dcache_size) { 177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 178 pcc->l1_dcache_size))); 179 } else { 180 warn_report("Unknown L1 dcache size for cpu"); 181 } 182 if (pcc->l1_icache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 184 pcc->l1_icache_size))); 185 } else { 186 warn_report("Unknown L1 icache size for cpu"); 187 } 188 189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 192 cpu->hash64_opts->slb_size))); 193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 195 196 if (env->spr_cb[SPR_PURR].oea_read) { 197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 198 } 199 200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 202 segs, sizeof(segs)))); 203 } 204 205 /* 206 * Advertise VMX/VSX (vector extensions) if available 207 * 0 / no property == no vector extensions 208 * 1 == VMX / Altivec available 209 * 2 == VSX available 210 */ 211 if (env->insns_flags & PPC_ALTIVEC) { 212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 213 214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 215 } 216 217 /* 218 * Advertise DFP (Decimal Floating Point) if available 219 * 0 / no property == no DFP 220 * 1 == DFP available 221 */ 222 if (env->insns_flags2 & PPC2_DFP) { 223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 224 } 225 226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 227 sizeof(page_sizes_prop)); 228 if (page_sizes_prop_size) { 229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 230 page_sizes_prop, page_sizes_prop_size))); 231 } 232 233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 234 pa_features, sizeof(pa_features)))); 235 236 /* Build interrupt servers properties */ 237 for (i = 0; i < smt_threads; i++) { 238 servers_prop[i] = cpu_to_be32(pc->pir + i); 239 } 240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 241 servers_prop, sizeof(servers_prop)))); 242 } 243 244 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 245 uint32_t nr_threads) 246 { 247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 248 char *name; 249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 250 uint32_t irange[2], i, rsize; 251 uint64_t *reg; 252 int offset; 253 254 irange[0] = cpu_to_be32(pir); 255 irange[1] = cpu_to_be32(nr_threads); 256 257 rsize = sizeof(uint64_t) * 2 * nr_threads; 258 reg = g_malloc(rsize); 259 for (i = 0; i < nr_threads; i++) { 260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 261 reg[i * 2 + 1] = cpu_to_be64(0x1000); 262 } 263 264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 265 offset = fdt_add_subnode(fdt, 0, name); 266 _FDT(offset); 267 g_free(name); 268 269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 271 _FDT((fdt_setprop_string(fdt, offset, "device_type", 272 "PowerPC-External-Interrupt-Presentation"))); 273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 275 irange, sizeof(irange)))); 276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 278 g_free(reg); 279 } 280 281 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 282 { 283 int i; 284 285 pnv_dt_xscom(chip, fdt, 0, 286 cpu_to_be64(PNV_XSCOM_BASE(chip)), 287 cpu_to_be64(PNV_XSCOM_SIZE)); 288 289 for (i = 0; i < chip->nr_cores; i++) { 290 PnvCore *pnv_core = chip->cores[i]; 291 292 pnv_dt_core(chip, pnv_core, fdt); 293 294 /* Interrupt Control Presenters (ICP). One per core. */ 295 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 296 } 297 298 if (chip->ram_size) { 299 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 300 } 301 } 302 303 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 304 { 305 int i; 306 307 pnv_dt_xscom(chip, fdt, 0, 308 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 309 cpu_to_be64(PNV9_XSCOM_SIZE)); 310 311 for (i = 0; i < chip->nr_cores; i++) { 312 PnvCore *pnv_core = chip->cores[i]; 313 314 pnv_dt_core(chip, pnv_core, fdt); 315 } 316 317 if (chip->ram_size) { 318 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 319 } 320 321 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 322 } 323 324 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 325 { 326 int i; 327 328 pnv_dt_xscom(chip, fdt, 0, 329 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 330 cpu_to_be64(PNV10_XSCOM_SIZE)); 331 332 for (i = 0; i < chip->nr_cores; i++) { 333 PnvCore *pnv_core = chip->cores[i]; 334 335 pnv_dt_core(chip, pnv_core, fdt); 336 } 337 338 if (chip->ram_size) { 339 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 340 } 341 342 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 343 } 344 345 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 346 { 347 uint32_t io_base = d->ioport_id; 348 uint32_t io_regs[] = { 349 cpu_to_be32(1), 350 cpu_to_be32(io_base), 351 cpu_to_be32(2) 352 }; 353 char *name; 354 int node; 355 356 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 357 node = fdt_add_subnode(fdt, lpc_off, name); 358 _FDT(node); 359 g_free(name); 360 361 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 362 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 363 } 364 365 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 366 { 367 const char compatible[] = "ns16550\0pnpPNP,501"; 368 uint32_t io_base = d->ioport_id; 369 uint32_t io_regs[] = { 370 cpu_to_be32(1), 371 cpu_to_be32(io_base), 372 cpu_to_be32(8) 373 }; 374 char *name; 375 int node; 376 377 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 378 node = fdt_add_subnode(fdt, lpc_off, name); 379 _FDT(node); 380 g_free(name); 381 382 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 383 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 384 sizeof(compatible)))); 385 386 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 387 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 388 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 389 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 390 fdt_get_phandle(fdt, lpc_off)))); 391 392 /* This is needed by Linux */ 393 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 394 } 395 396 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 397 { 398 const char compatible[] = "bt\0ipmi-bt"; 399 uint32_t io_base; 400 uint32_t io_regs[] = { 401 cpu_to_be32(1), 402 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 403 cpu_to_be32(3) 404 }; 405 uint32_t irq; 406 char *name; 407 int node; 408 409 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 410 io_regs[1] = cpu_to_be32(io_base); 411 412 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 413 414 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 415 node = fdt_add_subnode(fdt, lpc_off, name); 416 _FDT(node); 417 g_free(name); 418 419 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 420 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 421 sizeof(compatible)))); 422 423 /* Mark it as reserved to avoid Linux trying to claim it */ 424 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 425 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 426 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 427 fdt_get_phandle(fdt, lpc_off)))); 428 } 429 430 typedef struct ForeachPopulateArgs { 431 void *fdt; 432 int offset; 433 } ForeachPopulateArgs; 434 435 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 436 { 437 ForeachPopulateArgs *args = opaque; 438 ISADevice *d = ISA_DEVICE(dev); 439 440 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 441 pnv_dt_rtc(d, args->fdt, args->offset); 442 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 443 pnv_dt_serial(d, args->fdt, args->offset); 444 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 445 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 446 } else { 447 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 448 d->ioport_id); 449 } 450 451 return 0; 452 } 453 454 /* 455 * The default LPC bus of a multichip system is on chip 0. It's 456 * recognized by the firmware (skiboot) using a "primary" property. 457 */ 458 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 459 { 460 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 461 ForeachPopulateArgs args = { 462 .fdt = fdt, 463 .offset = isa_offset, 464 }; 465 uint32_t phandle; 466 467 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 468 469 phandle = qemu_fdt_alloc_phandle(fdt); 470 assert(phandle > 0); 471 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 472 473 /* 474 * ISA devices are not necessarily parented to the ISA bus so we 475 * can not use object_child_foreach() 476 */ 477 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 478 &args); 479 } 480 481 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 482 { 483 int off; 484 485 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 486 off = fdt_add_subnode(fdt, off, "power-mgt"); 487 488 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 489 } 490 491 static void *pnv_dt_create(MachineState *machine) 492 { 493 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 494 PnvMachineState *pnv = PNV_MACHINE(machine); 495 void *fdt; 496 char *buf; 497 int off; 498 int i; 499 500 fdt = g_malloc0(FDT_MAX_SIZE); 501 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 502 503 /* /qemu node */ 504 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 505 506 /* Root node */ 507 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 508 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 509 _FDT((fdt_setprop_string(fdt, 0, "model", 510 "IBM PowerNV (emulated by qemu)"))); 511 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 512 513 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 514 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 515 if (qemu_uuid_set) { 516 _FDT((fdt_property_string(fdt, "system-id", buf))); 517 } 518 g_free(buf); 519 520 off = fdt_add_subnode(fdt, 0, "chosen"); 521 if (machine->kernel_cmdline) { 522 _FDT((fdt_setprop_string(fdt, off, "bootargs", 523 machine->kernel_cmdline))); 524 } 525 526 if (pnv->initrd_size) { 527 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 528 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 529 530 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 531 &start_prop, sizeof(start_prop)))); 532 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 533 &end_prop, sizeof(end_prop)))); 534 } 535 536 /* Populate device tree for each chip */ 537 for (i = 0; i < pnv->num_chips; i++) { 538 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 539 } 540 541 /* Populate ISA devices on chip 0 */ 542 pnv_dt_isa(pnv, fdt); 543 544 if (pnv->bmc) { 545 pnv_dt_bmc_sensors(pnv->bmc, fdt); 546 } 547 548 /* Create an extra node for power management on machines that support it */ 549 if (pmc->dt_power_mgt) { 550 pmc->dt_power_mgt(pnv, fdt); 551 } 552 553 return fdt; 554 } 555 556 static void pnv_powerdown_notify(Notifier *n, void *opaque) 557 { 558 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 559 560 if (pnv->bmc) { 561 pnv_bmc_powerdown(pnv->bmc); 562 } 563 } 564 565 static void pnv_reset(MachineState *machine) 566 { 567 void *fdt; 568 569 qemu_devices_reset(); 570 571 fdt = pnv_dt_create(machine); 572 573 /* Pack resulting tree */ 574 _FDT((fdt_pack(fdt))); 575 576 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 577 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 578 } 579 580 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 581 { 582 Pnv8Chip *chip8 = PNV8_CHIP(chip); 583 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 584 } 585 586 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 587 { 588 Pnv8Chip *chip8 = PNV8_CHIP(chip); 589 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 590 } 591 592 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 593 { 594 Pnv9Chip *chip9 = PNV9_CHIP(chip); 595 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 596 } 597 598 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 599 { 600 Pnv10Chip *chip10 = PNV10_CHIP(chip); 601 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 602 } 603 604 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 605 { 606 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 607 } 608 609 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 610 { 611 Pnv8Chip *chip8 = PNV8_CHIP(chip); 612 613 ics_pic_print_info(&chip8->psi.ics, mon); 614 } 615 616 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 617 { 618 Pnv9Chip *chip9 = PNV9_CHIP(chip); 619 620 pnv_xive_pic_print_info(&chip9->xive, mon); 621 pnv_psi_pic_print_info(&chip9->psi, mon); 622 } 623 624 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 625 uint32_t core_id) 626 { 627 return PNV_XSCOM_EX_BASE(core_id); 628 } 629 630 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 631 uint32_t core_id) 632 { 633 return PNV9_XSCOM_EC_BASE(core_id); 634 } 635 636 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 637 uint32_t core_id) 638 { 639 return PNV10_XSCOM_EC_BASE(core_id); 640 } 641 642 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 643 { 644 PowerPCCPUClass *ppc_default = 645 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 646 PowerPCCPUClass *ppc = 647 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 648 649 return ppc_default->pvr_match(ppc_default, ppc->pvr); 650 } 651 652 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 653 { 654 Object *obj; 655 656 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 657 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 658 object_property_set_int(obj, irq, "irq", &error_fatal); 659 object_property_set_bool(obj, true, "realized", &error_fatal); 660 } 661 662 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 663 { 664 Pnv10Chip *chip10 = PNV10_CHIP(chip); 665 666 pnv_psi_pic_print_info(&chip10->psi, mon); 667 } 668 669 static void pnv_init(MachineState *machine) 670 { 671 PnvMachineState *pnv = PNV_MACHINE(machine); 672 MachineClass *mc = MACHINE_GET_CLASS(machine); 673 MemoryRegion *ram; 674 char *fw_filename; 675 long fw_size; 676 int i; 677 char *chip_typename; 678 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 679 DeviceState *dev; 680 681 /* allocate RAM */ 682 if (machine->ram_size < (1 * GiB)) { 683 warn_report("skiboot may not work with < 1GB of RAM"); 684 } 685 686 ram = g_new(MemoryRegion, 1); 687 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 688 machine->ram_size); 689 memory_region_add_subregion(get_system_memory(), 0, ram); 690 691 /* 692 * Create our simple PNOR device 693 */ 694 dev = qdev_create(NULL, TYPE_PNV_PNOR); 695 if (pnor) { 696 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 697 &error_abort); 698 } 699 qdev_init_nofail(dev); 700 pnv->pnor = PNV_PNOR(dev); 701 702 /* load skiboot firmware */ 703 if (bios_name == NULL) { 704 bios_name = FW_FILE_NAME; 705 } 706 707 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 708 if (!fw_filename) { 709 error_report("Could not find OPAL firmware '%s'", bios_name); 710 exit(1); 711 } 712 713 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 714 if (fw_size < 0) { 715 error_report("Could not load OPAL firmware '%s'", fw_filename); 716 exit(1); 717 } 718 g_free(fw_filename); 719 720 /* load kernel */ 721 if (machine->kernel_filename) { 722 long kernel_size; 723 724 kernel_size = load_image_targphys(machine->kernel_filename, 725 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 726 if (kernel_size < 0) { 727 error_report("Could not load kernel '%s'", 728 machine->kernel_filename); 729 exit(1); 730 } 731 } 732 733 /* load initrd */ 734 if (machine->initrd_filename) { 735 pnv->initrd_base = INITRD_LOAD_ADDR; 736 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 737 pnv->initrd_base, INITRD_MAX_SIZE); 738 if (pnv->initrd_size < 0) { 739 error_report("Could not load initial ram disk '%s'", 740 machine->initrd_filename); 741 exit(1); 742 } 743 } 744 745 /* 746 * Check compatibility of the specified CPU with the machine 747 * default. 748 */ 749 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 750 error_report("invalid CPU model '%s' for %s machine", 751 machine->cpu_type, mc->name); 752 exit(1); 753 } 754 755 /* Create the processor chips */ 756 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 757 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 758 i, machine->cpu_type); 759 if (!object_class_by_name(chip_typename)) { 760 error_report("invalid chip model '%.*s' for %s machine", 761 i, machine->cpu_type, mc->name); 762 exit(1); 763 } 764 765 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 766 for (i = 0; i < pnv->num_chips; i++) { 767 char chip_name[32]; 768 Object *chip = object_new(chip_typename); 769 770 pnv->chips[i] = PNV_CHIP(chip); 771 772 /* 773 * TODO: put all the memory in one node on chip 0 until we find a 774 * way to specify different ranges for each chip 775 */ 776 if (i == 0) { 777 object_property_set_int(chip, machine->ram_size, "ram-size", 778 &error_fatal); 779 } 780 781 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 782 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 783 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 784 &error_fatal); 785 object_property_set_int(chip, machine->smp.cores, 786 "nr-cores", &error_fatal); 787 object_property_set_bool(chip, true, "realized", &error_fatal); 788 } 789 g_free(chip_typename); 790 791 /* Create the machine BMC simulator */ 792 pnv->bmc = pnv_bmc_create(); 793 794 /* Instantiate ISA bus on chip 0 */ 795 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 796 797 /* Create serial port */ 798 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 799 800 /* Create an RTC ISA device too */ 801 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 802 803 /* Create the IPMI BT device for communication with the BMC */ 804 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 805 806 /* 807 * OpenPOWER systems use a IPMI SEL Event message to notify the 808 * host to powerdown 809 */ 810 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 811 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 812 } 813 814 /* 815 * 0:21 Reserved - Read as zeros 816 * 22:24 Chip ID 817 * 25:28 Core number 818 * 29:31 Thread ID 819 */ 820 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 821 { 822 return (chip->chip_id << 7) | (core_id << 3); 823 } 824 825 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 826 Error **errp) 827 { 828 Error *local_err = NULL; 829 Object *obj; 830 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 831 832 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 833 &local_err); 834 if (local_err) { 835 error_propagate(errp, local_err); 836 return; 837 } 838 839 pnv_cpu->intc = obj; 840 } 841 842 843 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 844 { 845 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 846 847 icp_reset(ICP(pnv_cpu->intc)); 848 } 849 850 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 851 { 852 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 853 854 icp_destroy(ICP(pnv_cpu->intc)); 855 pnv_cpu->intc = NULL; 856 } 857 858 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 859 Monitor *mon) 860 { 861 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 862 } 863 864 /* 865 * 0:48 Reserved - Read as zeroes 866 * 49:52 Node ID 867 * 53:55 Chip ID 868 * 56 Reserved - Read as zero 869 * 57:61 Core number 870 * 62:63 Thread ID 871 * 872 * We only care about the lower bits. uint32_t is fine for the moment. 873 */ 874 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 875 { 876 return (chip->chip_id << 8) | (core_id << 2); 877 } 878 879 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 880 { 881 return (chip->chip_id << 8) | (core_id << 2); 882 } 883 884 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 885 Error **errp) 886 { 887 Pnv9Chip *chip9 = PNV9_CHIP(chip); 888 Error *local_err = NULL; 889 Object *obj; 890 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 891 892 /* 893 * The core creates its interrupt presenter but the XIVE interrupt 894 * controller object is initialized afterwards. Hopefully, it's 895 * only used at runtime. 896 */ 897 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); 898 if (local_err) { 899 error_propagate(errp, local_err); 900 return; 901 } 902 903 pnv_cpu->intc = obj; 904 } 905 906 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 907 { 908 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 909 910 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 911 } 912 913 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 914 { 915 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 916 917 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 918 pnv_cpu->intc = NULL; 919 } 920 921 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 922 Monitor *mon) 923 { 924 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 925 } 926 927 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 928 Error **errp) 929 { 930 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 931 932 /* Will be defined when the interrupt controller is */ 933 pnv_cpu->intc = NULL; 934 } 935 936 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 937 { 938 ; 939 } 940 941 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 942 { 943 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 944 945 pnv_cpu->intc = NULL; 946 } 947 948 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 949 Monitor *mon) 950 { 951 } 952 953 /* 954 * Allowed core identifiers on a POWER8 Processor Chip : 955 * 956 * <EX0 reserved> 957 * EX1 - Venice only 958 * EX2 - Venice only 959 * EX3 - Venice only 960 * EX4 961 * EX5 962 * EX6 963 * <EX7,8 reserved> <reserved> 964 * EX9 - Venice only 965 * EX10 - Venice only 966 * EX11 - Venice only 967 * EX12 968 * EX13 969 * EX14 970 * <EX15 reserved> 971 */ 972 #define POWER8E_CORE_MASK (0x7070ull) 973 #define POWER8_CORE_MASK (0x7e7eull) 974 975 /* 976 * POWER9 has 24 cores, ids starting at 0x0 977 */ 978 #define POWER9_CORE_MASK (0xffffffffffffffull) 979 980 981 #define POWER10_CORE_MASK (0xffffffffffffffull) 982 983 static void pnv_chip_power8_instance_init(Object *obj) 984 { 985 Pnv8Chip *chip8 = PNV8_CHIP(obj); 986 987 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 988 TYPE_PNV8_PSI, &error_abort, NULL); 989 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 990 OBJECT(qdev_get_machine()), &error_abort); 991 992 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 993 TYPE_PNV8_LPC, &error_abort, NULL); 994 995 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 996 TYPE_PNV8_OCC, &error_abort, NULL); 997 998 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 999 TYPE_PNV8_HOMER, &error_abort, NULL); 1000 } 1001 1002 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1003 { 1004 PnvChip *chip = PNV_CHIP(chip8); 1005 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1006 int i, j; 1007 char *name; 1008 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 1009 1010 name = g_strdup_printf("icp-%x", chip->chip_id); 1011 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1012 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1013 g_free(name); 1014 1015 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1016 1017 /* Map the ICP registers for each thread */ 1018 for (i = 0; i < chip->nr_cores; i++) { 1019 PnvCore *pnv_core = chip->cores[i]; 1020 int core_hwid = CPU_CORE(pnv_core)->core_id; 1021 1022 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1023 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1024 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 1025 1026 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1027 &icp->mmio); 1028 } 1029 } 1030 } 1031 1032 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1033 { 1034 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1035 PnvChip *chip = PNV_CHIP(dev); 1036 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1037 Pnv8Psi *psi8 = &chip8->psi; 1038 Error *local_err = NULL; 1039 1040 /* XSCOM bridge is first */ 1041 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1042 if (local_err) { 1043 error_propagate(errp, local_err); 1044 return; 1045 } 1046 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1047 1048 pcc->parent_realize(dev, &local_err); 1049 if (local_err) { 1050 error_propagate(errp, local_err); 1051 return; 1052 } 1053 1054 /* Processor Service Interface (PSI) Host Bridge */ 1055 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1056 "bar", &error_fatal); 1057 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 1058 if (local_err) { 1059 error_propagate(errp, local_err); 1060 return; 1061 } 1062 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1063 &PNV_PSI(psi8)->xscom_regs); 1064 1065 /* Create LPC controller */ 1066 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1067 &error_abort); 1068 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 1069 &error_fatal); 1070 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1071 1072 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1073 (uint64_t) PNV_XSCOM_BASE(chip), 1074 PNV_XSCOM_LPC_BASE); 1075 1076 /* 1077 * Interrupt Management Area. This is the memory region holding 1078 * all the Interrupt Control Presenter (ICP) registers 1079 */ 1080 pnv_chip_icp_realize(chip8, &local_err); 1081 if (local_err) { 1082 error_propagate(errp, local_err); 1083 return; 1084 } 1085 1086 /* Create the simplified OCC model */ 1087 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1088 &error_abort); 1089 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1090 if (local_err) { 1091 error_propagate(errp, local_err); 1092 return; 1093 } 1094 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1095 1096 /* OCC SRAM model */ 1097 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1098 &chip8->occ.sram_regs); 1099 1100 /* HOMER */ 1101 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1102 &error_abort); 1103 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1104 &local_err); 1105 if (local_err) { 1106 error_propagate(errp, local_err); 1107 return; 1108 } 1109 /* Homer Xscom region */ 1110 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1111 1112 /* Homer mmio region */ 1113 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1114 &chip8->homer.regs); 1115 } 1116 1117 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1118 { 1119 DeviceClass *dc = DEVICE_CLASS(klass); 1120 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1121 1122 k->chip_type = PNV_CHIP_POWER8E; 1123 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1124 k->cores_mask = POWER8E_CORE_MASK; 1125 k->core_pir = pnv_chip_core_pir_p8; 1126 k->intc_create = pnv_chip_power8_intc_create; 1127 k->intc_reset = pnv_chip_power8_intc_reset; 1128 k->intc_destroy = pnv_chip_power8_intc_destroy; 1129 k->intc_print_info = pnv_chip_power8_intc_print_info; 1130 k->isa_create = pnv_chip_power8_isa_create; 1131 k->dt_populate = pnv_chip_power8_dt_populate; 1132 k->pic_print_info = pnv_chip_power8_pic_print_info; 1133 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1134 dc->desc = "PowerNV Chip POWER8E"; 1135 1136 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1137 &k->parent_realize); 1138 } 1139 1140 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1141 { 1142 DeviceClass *dc = DEVICE_CLASS(klass); 1143 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1144 1145 k->chip_type = PNV_CHIP_POWER8; 1146 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1147 k->cores_mask = POWER8_CORE_MASK; 1148 k->core_pir = pnv_chip_core_pir_p8; 1149 k->intc_create = pnv_chip_power8_intc_create; 1150 k->intc_reset = pnv_chip_power8_intc_reset; 1151 k->intc_destroy = pnv_chip_power8_intc_destroy; 1152 k->intc_print_info = pnv_chip_power8_intc_print_info; 1153 k->isa_create = pnv_chip_power8_isa_create; 1154 k->dt_populate = pnv_chip_power8_dt_populate; 1155 k->pic_print_info = pnv_chip_power8_pic_print_info; 1156 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1157 dc->desc = "PowerNV Chip POWER8"; 1158 1159 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1160 &k->parent_realize); 1161 } 1162 1163 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1164 { 1165 DeviceClass *dc = DEVICE_CLASS(klass); 1166 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1167 1168 k->chip_type = PNV_CHIP_POWER8NVL; 1169 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1170 k->cores_mask = POWER8_CORE_MASK; 1171 k->core_pir = pnv_chip_core_pir_p8; 1172 k->intc_create = pnv_chip_power8_intc_create; 1173 k->intc_reset = pnv_chip_power8_intc_reset; 1174 k->intc_destroy = pnv_chip_power8_intc_destroy; 1175 k->intc_print_info = pnv_chip_power8_intc_print_info; 1176 k->isa_create = pnv_chip_power8nvl_isa_create; 1177 k->dt_populate = pnv_chip_power8_dt_populate; 1178 k->pic_print_info = pnv_chip_power8_pic_print_info; 1179 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1180 dc->desc = "PowerNV Chip POWER8NVL"; 1181 1182 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1183 &k->parent_realize); 1184 } 1185 1186 static void pnv_chip_power9_instance_init(Object *obj) 1187 { 1188 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1189 1190 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1191 TYPE_PNV_XIVE, &error_abort, NULL); 1192 1193 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1194 TYPE_PNV9_PSI, &error_abort, NULL); 1195 1196 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1197 TYPE_PNV9_LPC, &error_abort, NULL); 1198 1199 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1200 TYPE_PNV9_OCC, &error_abort, NULL); 1201 1202 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1203 TYPE_PNV9_HOMER, &error_abort, NULL); 1204 } 1205 1206 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1207 { 1208 PnvChip *chip = PNV_CHIP(chip9); 1209 int i; 1210 1211 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1212 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1213 1214 for (i = 0; i < chip9->nr_quads; i++) { 1215 char eq_name[32]; 1216 PnvQuad *eq = &chip9->quads[i]; 1217 PnvCore *pnv_core = chip->cores[i * 4]; 1218 int core_id = CPU_CORE(pnv_core)->core_id; 1219 1220 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1221 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1222 TYPE_PNV_QUAD, &error_fatal, NULL); 1223 1224 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1225 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1226 1227 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1228 &eq->xscom_regs); 1229 } 1230 } 1231 1232 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1233 { 1234 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1235 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1236 PnvChip *chip = PNV_CHIP(dev); 1237 Pnv9Psi *psi9 = &chip9->psi; 1238 Error *local_err = NULL; 1239 1240 /* XSCOM bridge is first */ 1241 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1242 if (local_err) { 1243 error_propagate(errp, local_err); 1244 return; 1245 } 1246 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1247 1248 pcc->parent_realize(dev, &local_err); 1249 if (local_err) { 1250 error_propagate(errp, local_err); 1251 return; 1252 } 1253 1254 pnv_chip_quad_realize(chip9, &local_err); 1255 if (local_err) { 1256 error_propagate(errp, local_err); 1257 return; 1258 } 1259 1260 /* XIVE interrupt controller (POWER9) */ 1261 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1262 "ic-bar", &error_fatal); 1263 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1264 "vc-bar", &error_fatal); 1265 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1266 "pc-bar", &error_fatal); 1267 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1268 "tm-bar", &error_fatal); 1269 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1270 &error_abort); 1271 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1272 &local_err); 1273 if (local_err) { 1274 error_propagate(errp, local_err); 1275 return; 1276 } 1277 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1278 &chip9->xive.xscom_regs); 1279 1280 /* Processor Service Interface (PSI) Host Bridge */ 1281 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1282 "bar", &error_fatal); 1283 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1284 if (local_err) { 1285 error_propagate(errp, local_err); 1286 return; 1287 } 1288 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1289 &PNV_PSI(psi9)->xscom_regs); 1290 1291 /* LPC */ 1292 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1293 &error_abort); 1294 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1295 if (local_err) { 1296 error_propagate(errp, local_err); 1297 return; 1298 } 1299 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1300 &chip9->lpc.xscom_regs); 1301 1302 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1303 (uint64_t) PNV9_LPCM_BASE(chip)); 1304 1305 /* Create the simplified OCC model */ 1306 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1307 &error_abort); 1308 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1309 if (local_err) { 1310 error_propagate(errp, local_err); 1311 return; 1312 } 1313 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1314 1315 /* OCC SRAM model */ 1316 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1317 &chip9->occ.sram_regs); 1318 1319 /* HOMER */ 1320 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1321 &error_abort); 1322 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1323 &local_err); 1324 if (local_err) { 1325 error_propagate(errp, local_err); 1326 return; 1327 } 1328 /* Homer Xscom region */ 1329 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1330 1331 /* Homer mmio region */ 1332 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1333 &chip9->homer.regs); 1334 } 1335 1336 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1337 { 1338 DeviceClass *dc = DEVICE_CLASS(klass); 1339 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1340 1341 k->chip_type = PNV_CHIP_POWER9; 1342 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1343 k->cores_mask = POWER9_CORE_MASK; 1344 k->core_pir = pnv_chip_core_pir_p9; 1345 k->intc_create = pnv_chip_power9_intc_create; 1346 k->intc_reset = pnv_chip_power9_intc_reset; 1347 k->intc_destroy = pnv_chip_power9_intc_destroy; 1348 k->intc_print_info = pnv_chip_power9_intc_print_info; 1349 k->isa_create = pnv_chip_power9_isa_create; 1350 k->dt_populate = pnv_chip_power9_dt_populate; 1351 k->pic_print_info = pnv_chip_power9_pic_print_info; 1352 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1353 dc->desc = "PowerNV Chip POWER9"; 1354 1355 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1356 &k->parent_realize); 1357 } 1358 1359 static void pnv_chip_power10_instance_init(Object *obj) 1360 { 1361 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1362 1363 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), 1364 TYPE_PNV10_PSI, &error_abort, NULL); 1365 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), 1366 TYPE_PNV10_LPC, &error_abort, NULL); 1367 } 1368 1369 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1370 { 1371 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1372 PnvChip *chip = PNV_CHIP(dev); 1373 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1374 Error *local_err = NULL; 1375 1376 /* XSCOM bridge is first */ 1377 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1378 if (local_err) { 1379 error_propagate(errp, local_err); 1380 return; 1381 } 1382 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1383 1384 pcc->parent_realize(dev, &local_err); 1385 if (local_err) { 1386 error_propagate(errp, local_err); 1387 return; 1388 } 1389 1390 /* Processor Service Interface (PSI) Host Bridge */ 1391 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1392 "bar", &error_fatal); 1393 object_property_set_bool(OBJECT(&chip10->psi), true, "realized", 1394 &local_err); 1395 if (local_err) { 1396 error_propagate(errp, local_err); 1397 return; 1398 } 1399 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1400 &PNV_PSI(&chip10->psi)->xscom_regs); 1401 1402 /* LPC */ 1403 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1404 &error_abort); 1405 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", 1406 &local_err); 1407 if (local_err) { 1408 error_propagate(errp, local_err); 1409 return; 1410 } 1411 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1412 &chip10->lpc.xscom_regs); 1413 1414 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1415 (uint64_t) PNV10_LPCM_BASE(chip)); 1416 } 1417 1418 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1419 { 1420 DeviceClass *dc = DEVICE_CLASS(klass); 1421 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1422 1423 k->chip_type = PNV_CHIP_POWER10; 1424 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1425 k->cores_mask = POWER10_CORE_MASK; 1426 k->core_pir = pnv_chip_core_pir_p10; 1427 k->intc_create = pnv_chip_power10_intc_create; 1428 k->intc_reset = pnv_chip_power10_intc_reset; 1429 k->intc_destroy = pnv_chip_power10_intc_destroy; 1430 k->intc_print_info = pnv_chip_power10_intc_print_info; 1431 k->isa_create = pnv_chip_power10_isa_create; 1432 k->dt_populate = pnv_chip_power10_dt_populate; 1433 k->pic_print_info = pnv_chip_power10_pic_print_info; 1434 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1435 dc->desc = "PowerNV Chip POWER10"; 1436 1437 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1438 &k->parent_realize); 1439 } 1440 1441 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1442 { 1443 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1444 int cores_max; 1445 1446 /* 1447 * No custom mask for this chip, let's use the default one from * 1448 * the chip class 1449 */ 1450 if (!chip->cores_mask) { 1451 chip->cores_mask = pcc->cores_mask; 1452 } 1453 1454 /* filter alien core ids ! some are reserved */ 1455 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1456 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1457 chip->cores_mask); 1458 return; 1459 } 1460 chip->cores_mask &= pcc->cores_mask; 1461 1462 /* now that we have a sane layout, let check the number of cores */ 1463 cores_max = ctpop64(chip->cores_mask); 1464 if (chip->nr_cores > cores_max) { 1465 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1466 cores_max); 1467 return; 1468 } 1469 } 1470 1471 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1472 { 1473 MachineState *ms = MACHINE(qdev_get_machine()); 1474 Error *error = NULL; 1475 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1476 const char *typename = pnv_chip_core_typename(chip); 1477 int i, core_hwid; 1478 1479 if (!object_class_by_name(typename)) { 1480 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1481 return; 1482 } 1483 1484 /* Cores */ 1485 pnv_chip_core_sanitize(chip, &error); 1486 if (error) { 1487 error_propagate(errp, error); 1488 return; 1489 } 1490 1491 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1492 1493 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1494 && (i < chip->nr_cores); core_hwid++) { 1495 char core_name[32]; 1496 PnvCore *pnv_core; 1497 uint64_t xscom_core_base; 1498 1499 if (!(chip->cores_mask & (1ull << core_hwid))) { 1500 continue; 1501 } 1502 1503 pnv_core = PNV_CORE(object_new(typename)); 1504 1505 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1506 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1507 &error_abort); 1508 chip->cores[i] = pnv_core; 1509 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", 1510 &error_fatal); 1511 object_property_set_int(OBJECT(pnv_core), core_hwid, 1512 CPU_CORE_PROP_CORE_ID, &error_fatal); 1513 object_property_set_int(OBJECT(pnv_core), 1514 pcc->core_pir(chip, core_hwid), 1515 "pir", &error_fatal); 1516 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1517 &error_abort); 1518 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1519 &error_fatal); 1520 1521 /* Each core has an XSCOM MMIO region */ 1522 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1523 1524 pnv_xscom_add_subregion(chip, xscom_core_base, 1525 &pnv_core->xscom_regs); 1526 i++; 1527 } 1528 } 1529 1530 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1531 { 1532 PnvChip *chip = PNV_CHIP(dev); 1533 Error *error = NULL; 1534 1535 /* Cores */ 1536 pnv_chip_core_realize(chip, &error); 1537 if (error) { 1538 error_propagate(errp, error); 1539 return; 1540 } 1541 } 1542 1543 static Property pnv_chip_properties[] = { 1544 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1545 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1546 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1547 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1548 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1549 DEFINE_PROP_END_OF_LIST(), 1550 }; 1551 1552 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1553 { 1554 DeviceClass *dc = DEVICE_CLASS(klass); 1555 1556 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1557 dc->realize = pnv_chip_realize; 1558 dc->props = pnv_chip_properties; 1559 dc->desc = "PowerNV Chip"; 1560 } 1561 1562 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1563 { 1564 int i, j; 1565 1566 for (i = 0; i < chip->nr_cores; i++) { 1567 PnvCore *pc = chip->cores[i]; 1568 CPUCore *cc = CPU_CORE(pc); 1569 1570 for (j = 0; j < cc->nr_threads; j++) { 1571 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1572 return pc->threads[j]; 1573 } 1574 } 1575 } 1576 return NULL; 1577 } 1578 1579 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1580 { 1581 PnvMachineState *pnv = PNV_MACHINE(xi); 1582 int i; 1583 1584 for (i = 0; i < pnv->num_chips; i++) { 1585 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1586 1587 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1588 return &chip8->psi.ics; 1589 } 1590 } 1591 return NULL; 1592 } 1593 1594 static void pnv_ics_resend(XICSFabric *xi) 1595 { 1596 PnvMachineState *pnv = PNV_MACHINE(xi); 1597 int i; 1598 1599 for (i = 0; i < pnv->num_chips; i++) { 1600 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1601 ics_resend(&chip8->psi.ics); 1602 } 1603 } 1604 1605 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1606 { 1607 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1608 1609 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1610 } 1611 1612 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1613 Monitor *mon) 1614 { 1615 PnvMachineState *pnv = PNV_MACHINE(obj); 1616 int i; 1617 CPUState *cs; 1618 1619 CPU_FOREACH(cs) { 1620 PowerPCCPU *cpu = POWERPC_CPU(cs); 1621 1622 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1623 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1624 mon); 1625 } 1626 1627 for (i = 0; i < pnv->num_chips; i++) { 1628 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1629 } 1630 } 1631 1632 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1633 uint8_t nvt_blk, uint32_t nvt_idx, 1634 bool cam_ignore, uint8_t priority, 1635 uint32_t logic_serv, 1636 XiveTCTXMatch *match) 1637 { 1638 PnvMachineState *pnv = PNV_MACHINE(xfb); 1639 int total_count = 0; 1640 int i; 1641 1642 for (i = 0; i < pnv->num_chips; i++) { 1643 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1644 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1645 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1646 int count; 1647 1648 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1649 priority, logic_serv, match); 1650 1651 if (count < 0) { 1652 return count; 1653 } 1654 1655 total_count += count; 1656 } 1657 1658 return total_count; 1659 } 1660 1661 PnvChip *pnv_get_chip(uint32_t chip_id) 1662 { 1663 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1664 int i; 1665 1666 for (i = 0; i < pnv->num_chips; i++) { 1667 PnvChip *chip = pnv->chips[i]; 1668 if (chip->chip_id == chip_id) { 1669 return chip; 1670 } 1671 } 1672 return NULL; 1673 } 1674 1675 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1676 void *opaque, Error **errp) 1677 { 1678 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1679 } 1680 1681 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1682 void *opaque, Error **errp) 1683 { 1684 PnvMachineState *pnv = PNV_MACHINE(obj); 1685 uint32_t num_chips; 1686 Error *local_err = NULL; 1687 1688 visit_type_uint32(v, name, &num_chips, &local_err); 1689 if (local_err) { 1690 error_propagate(errp, local_err); 1691 return; 1692 } 1693 1694 /* 1695 * TODO: should we decide on how many chips we can create based 1696 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1697 */ 1698 if (!is_power_of_2(num_chips) || num_chips > 4) { 1699 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1700 return; 1701 } 1702 1703 pnv->num_chips = num_chips; 1704 } 1705 1706 static void pnv_machine_instance_init(Object *obj) 1707 { 1708 PnvMachineState *pnv = PNV_MACHINE(obj); 1709 pnv->num_chips = 1; 1710 } 1711 1712 static void pnv_machine_class_props_init(ObjectClass *oc) 1713 { 1714 object_class_property_add(oc, "num-chips", "uint32", 1715 pnv_get_num_chips, pnv_set_num_chips, 1716 NULL, NULL, NULL); 1717 object_class_property_set_description(oc, "num-chips", 1718 "Specifies the number of processor chips", 1719 NULL); 1720 } 1721 1722 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1723 { 1724 MachineClass *mc = MACHINE_CLASS(oc); 1725 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1726 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1727 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1728 1729 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1730 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1731 1732 xic->icp_get = pnv_icp_get; 1733 xic->ics_get = pnv_ics_get; 1734 xic->ics_resend = pnv_ics_resend; 1735 1736 pmc->compat = compat; 1737 pmc->compat_size = sizeof(compat); 1738 } 1739 1740 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1741 { 1742 MachineClass *mc = MACHINE_CLASS(oc); 1743 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1744 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1745 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1746 1747 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1748 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1749 xfc->match_nvt = pnv_match_nvt; 1750 1751 mc->alias = "powernv"; 1752 1753 pmc->compat = compat; 1754 pmc->compat_size = sizeof(compat); 1755 pmc->dt_power_mgt = pnv_dt_power_mgt; 1756 } 1757 1758 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1759 { 1760 MachineClass *mc = MACHINE_CLASS(oc); 1761 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1762 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1763 1764 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1765 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1766 1767 pmc->compat = compat; 1768 pmc->compat_size = sizeof(compat); 1769 pmc->dt_power_mgt = pnv_dt_power_mgt; 1770 } 1771 1772 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1773 { 1774 MachineClass *mc = MACHINE_CLASS(oc); 1775 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1776 1777 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1778 mc->init = pnv_init; 1779 mc->reset = pnv_reset; 1780 mc->max_cpus = MAX_CPUS; 1781 /* Pnv provides a AHCI device for storage */ 1782 mc->block_default_type = IF_IDE; 1783 mc->no_parallel = 1; 1784 mc->default_boot_order = NULL; 1785 /* 1786 * RAM defaults to less than 2048 for 32-bit hosts, and large 1787 * enough to fit the maximum initrd size at it's load address 1788 */ 1789 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1790 ispc->print_info = pnv_pic_print_info; 1791 1792 pnv_machine_class_props_init(oc); 1793 } 1794 1795 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1796 { \ 1797 .name = type, \ 1798 .class_init = class_initfn, \ 1799 .parent = TYPE_PNV8_CHIP, \ 1800 } 1801 1802 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1803 { \ 1804 .name = type, \ 1805 .class_init = class_initfn, \ 1806 .parent = TYPE_PNV9_CHIP, \ 1807 } 1808 1809 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 1810 { \ 1811 .name = type, \ 1812 .class_init = class_initfn, \ 1813 .parent = TYPE_PNV10_CHIP, \ 1814 } 1815 1816 static const TypeInfo types[] = { 1817 { 1818 .name = MACHINE_TYPE_NAME("powernv10"), 1819 .parent = TYPE_PNV_MACHINE, 1820 .class_init = pnv_machine_power10_class_init, 1821 }, 1822 { 1823 .name = MACHINE_TYPE_NAME("powernv9"), 1824 .parent = TYPE_PNV_MACHINE, 1825 .class_init = pnv_machine_power9_class_init, 1826 .interfaces = (InterfaceInfo[]) { 1827 { TYPE_XIVE_FABRIC }, 1828 { }, 1829 }, 1830 }, 1831 { 1832 .name = MACHINE_TYPE_NAME("powernv8"), 1833 .parent = TYPE_PNV_MACHINE, 1834 .class_init = pnv_machine_power8_class_init, 1835 .interfaces = (InterfaceInfo[]) { 1836 { TYPE_XICS_FABRIC }, 1837 { }, 1838 }, 1839 }, 1840 { 1841 .name = TYPE_PNV_MACHINE, 1842 .parent = TYPE_MACHINE, 1843 .abstract = true, 1844 .instance_size = sizeof(PnvMachineState), 1845 .instance_init = pnv_machine_instance_init, 1846 .class_init = pnv_machine_class_init, 1847 .class_size = sizeof(PnvMachineClass), 1848 .interfaces = (InterfaceInfo[]) { 1849 { TYPE_INTERRUPT_STATS_PROVIDER }, 1850 { }, 1851 }, 1852 }, 1853 { 1854 .name = TYPE_PNV_CHIP, 1855 .parent = TYPE_SYS_BUS_DEVICE, 1856 .class_init = pnv_chip_class_init, 1857 .instance_size = sizeof(PnvChip), 1858 .class_size = sizeof(PnvChipClass), 1859 .abstract = true, 1860 }, 1861 1862 /* 1863 * P10 chip and variants 1864 */ 1865 { 1866 .name = TYPE_PNV10_CHIP, 1867 .parent = TYPE_PNV_CHIP, 1868 .instance_init = pnv_chip_power10_instance_init, 1869 .instance_size = sizeof(Pnv10Chip), 1870 }, 1871 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 1872 1873 /* 1874 * P9 chip and variants 1875 */ 1876 { 1877 .name = TYPE_PNV9_CHIP, 1878 .parent = TYPE_PNV_CHIP, 1879 .instance_init = pnv_chip_power9_instance_init, 1880 .instance_size = sizeof(Pnv9Chip), 1881 }, 1882 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1883 1884 /* 1885 * P8 chip and variants 1886 */ 1887 { 1888 .name = TYPE_PNV8_CHIP, 1889 .parent = TYPE_PNV_CHIP, 1890 .instance_init = pnv_chip_power8_instance_init, 1891 .instance_size = sizeof(Pnv8Chip), 1892 }, 1893 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1894 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1895 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1896 pnv_chip_power8nvl_class_init), 1897 }; 1898 1899 DEFINE_TYPES(types) 1900