1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qemu/units.h" 24 #include "qemu/cutils.h" 25 #include "qapi/error.h" 26 #include "sysemu/qtest.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/reset.h" 30 #include "sysemu/runstate.h" 31 #include "sysemu/cpus.h" 32 #include "sysemu/device_tree.h" 33 #include "sysemu/hw_accel.h" 34 #include "target/ppc/cpu.h" 35 #include "hw/ppc/fdt.h" 36 #include "hw/ppc/ppc.h" 37 #include "hw/ppc/pnv.h" 38 #include "hw/ppc/pnv_core.h" 39 #include "hw/loader.h" 40 #include "hw/nmi.h" 41 #include "qapi/visitor.h" 42 #include "monitor/monitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 48 #include "hw/ppc/xics.h" 49 #include "hw/qdev-properties.h" 50 #include "hw/ppc/pnv_xscom.h" 51 #include "hw/ppc/pnv_pnor.h" 52 53 #include "hw/isa/isa.h" 54 #include "hw/char/serial.h" 55 #include "hw/rtc/mc146818rtc.h" 56 57 #include <libfdt.h> 58 59 #define FDT_MAX_SIZE (1 * MiB) 60 61 #define FW_FILE_NAME "skiboot.lid" 62 #define FW_LOAD_ADDR 0x0 63 #define FW_MAX_SIZE (16 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x20000000 66 #define KERNEL_MAX_SIZE (128 * MiB) 67 #define INITRD_LOAD_ADDR 0x28000000 68 #define INITRD_MAX_SIZE (128 * MiB) 69 70 static const char *pnv_chip_core_typename(const PnvChip *o) 71 { 72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 75 const char *core_type = object_class_get_name(object_class_by_name(s)); 76 g_free(s); 77 return core_type; 78 } 79 80 /* 81 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 82 * 4 * 4 sockets * 12 cores * 8 threads = 1536 83 * Let's make it 2^11 84 */ 85 #define MAX_CPUS 2048 86 87 /* 88 * Memory nodes are created by hostboot, one for each range of memory 89 * that has a different "affinity". In practice, it means one range 90 * per chip. 91 */ 92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 93 { 94 char *mem_name; 95 uint64_t mem_reg_property[2]; 96 int off; 97 98 mem_reg_property[0] = cpu_to_be64(start); 99 mem_reg_property[1] = cpu_to_be64(size); 100 101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 102 off = fdt_add_subnode(fdt, 0, mem_name); 103 g_free(mem_name); 104 105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 107 sizeof(mem_reg_property)))); 108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 109 } 110 111 static int get_cpus_node(void *fdt) 112 { 113 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 114 115 if (cpus_offset < 0) { 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 117 if (cpus_offset) { 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 120 } 121 } 122 _FDT(cpus_offset); 123 return cpus_offset; 124 } 125 126 /* 127 * The PowerNV cores (and threads) need to use real HW ids and not an 128 * incremental index like it has been done on other platforms. This HW 129 * id is stored in the CPU PIR, it is used to create cpu nodes in the 130 * device tree, used in XSCOM to address cores and in interrupt 131 * servers. 132 */ 133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 134 { 135 PowerPCCPU *cpu = pc->threads[0]; 136 CPUState *cs = CPU(cpu); 137 DeviceClass *dc = DEVICE_GET_CLASS(cs); 138 int smt_threads = CPU_CORE(pc)->nr_threads; 139 CPUPPCState *env = &cpu->env; 140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 141 uint32_t servers_prop[smt_threads]; 142 int i; 143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 144 0xffffffff, 0xffffffff}; 145 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 146 uint32_t cpufreq = 1000000000; 147 uint32_t page_sizes_prop[64]; 148 size_t page_sizes_prop_size; 149 const uint8_t pa_features[] = { 24, 0, 150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 154 int offset; 155 char *nodename; 156 int cpus_offset = get_cpus_node(fdt); 157 158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 159 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 160 _FDT(offset); 161 g_free(nodename); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 175 env->icache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 177 env->icache_line_size))); 178 179 if (pcc->l1_dcache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 181 pcc->l1_dcache_size))); 182 } else { 183 warn_report("Unknown L1 dcache size for cpu"); 184 } 185 if (pcc->l1_icache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 187 pcc->l1_icache_size))); 188 } else { 189 warn_report("Unknown L1 icache size for cpu"); 190 } 191 192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 195 cpu->hash64_opts->slb_size))); 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 198 199 if (ppc_has_spr(cpu, SPR_PURR)) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 201 } 202 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 205 segs, sizeof(segs)))); 206 } 207 208 /* 209 * Advertise VMX/VSX (vector extensions) if available 210 * 0 / no property == no vector extensions 211 * 1 == VMX / Altivec available 212 * 2 == VSX available 213 */ 214 if (env->insns_flags & PPC_ALTIVEC) { 215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 216 217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 218 } 219 220 /* 221 * Advertise DFP (Decimal Floating Point) if available 222 * 0 / no property == no DFP 223 * 1 == DFP available 224 */ 225 if (env->insns_flags2 & PPC2_DFP) { 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 227 } 228 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 230 sizeof(page_sizes_prop)); 231 if (page_sizes_prop_size) { 232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 233 page_sizes_prop, page_sizes_prop_size))); 234 } 235 236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 237 pa_features, sizeof(pa_features)))); 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pc->pir + i); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(servers_prop)))); 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 248 uint32_t nr_threads) 249 { 250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 251 char *name; 252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 253 uint32_t irange[2], i, rsize; 254 uint64_t *reg; 255 int offset; 256 257 irange[0] = cpu_to_be32(pir); 258 irange[1] = cpu_to_be32(nr_threads); 259 260 rsize = sizeof(uint64_t) * 2 * nr_threads; 261 reg = g_malloc(rsize); 262 for (i = 0; i < nr_threads; i++) { 263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 264 reg[i * 2 + 1] = cpu_to_be64(0x1000); 265 } 266 267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 268 offset = fdt_add_subnode(fdt, 0, name); 269 _FDT(offset); 270 g_free(name); 271 272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 274 _FDT((fdt_setprop_string(fdt, offset, "device_type", 275 "PowerPC-External-Interrupt-Presentation"))); 276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 278 irange, sizeof(irange)))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 281 g_free(reg); 282 } 283 284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 285 { 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 287 int i; 288 289 pnv_dt_xscom(chip, fdt, 0, 290 cpu_to_be64(PNV_XSCOM_BASE(chip)), 291 cpu_to_be64(PNV_XSCOM_SIZE), 292 compat, sizeof(compat)); 293 294 for (i = 0; i < chip->nr_cores; i++) { 295 PnvCore *pnv_core = chip->cores[i]; 296 297 pnv_dt_core(chip, pnv_core, fdt); 298 299 /* Interrupt Control Presenters (ICP). One per core. */ 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 301 } 302 303 if (chip->ram_size) { 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 305 } 306 } 307 308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 309 { 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 311 int i; 312 313 pnv_dt_xscom(chip, fdt, 0, 314 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 315 cpu_to_be64(PNV9_XSCOM_SIZE), 316 compat, sizeof(compat)); 317 318 for (i = 0; i < chip->nr_cores; i++) { 319 PnvCore *pnv_core = chip->cores[i]; 320 321 pnv_dt_core(chip, pnv_core, fdt); 322 } 323 324 if (chip->ram_size) { 325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 326 } 327 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 329 } 330 331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 332 { 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 334 int i; 335 336 pnv_dt_xscom(chip, fdt, 0, 337 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 338 cpu_to_be64(PNV10_XSCOM_SIZE), 339 compat, sizeof(compat)); 340 341 for (i = 0; i < chip->nr_cores; i++) { 342 PnvCore *pnv_core = chip->cores[i]; 343 344 pnv_dt_core(chip, pnv_core, fdt); 345 } 346 347 if (chip->ram_size) { 348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 349 } 350 351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 352 } 353 354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 355 { 356 uint32_t io_base = d->ioport_id; 357 uint32_t io_regs[] = { 358 cpu_to_be32(1), 359 cpu_to_be32(io_base), 360 cpu_to_be32(2) 361 }; 362 char *name; 363 int node; 364 365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 366 node = fdt_add_subnode(fdt, lpc_off, name); 367 _FDT(node); 368 g_free(name); 369 370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 372 } 373 374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 375 { 376 const char compatible[] = "ns16550\0pnpPNP,501"; 377 uint32_t io_base = d->ioport_id; 378 uint32_t io_regs[] = { 379 cpu_to_be32(1), 380 cpu_to_be32(io_base), 381 cpu_to_be32(8) 382 }; 383 char *name; 384 int node; 385 386 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 387 node = fdt_add_subnode(fdt, lpc_off, name); 388 _FDT(node); 389 g_free(name); 390 391 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 392 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 393 sizeof(compatible)))); 394 395 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 396 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 397 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 398 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 399 fdt_get_phandle(fdt, lpc_off)))); 400 401 /* This is needed by Linux */ 402 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 403 } 404 405 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 406 { 407 const char compatible[] = "bt\0ipmi-bt"; 408 uint32_t io_base; 409 uint32_t io_regs[] = { 410 cpu_to_be32(1), 411 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 412 cpu_to_be32(3) 413 }; 414 uint32_t irq; 415 char *name; 416 int node; 417 418 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 419 io_regs[1] = cpu_to_be32(io_base); 420 421 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 422 423 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 424 node = fdt_add_subnode(fdt, lpc_off, name); 425 _FDT(node); 426 g_free(name); 427 428 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 429 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 430 sizeof(compatible)))); 431 432 /* Mark it as reserved to avoid Linux trying to claim it */ 433 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 434 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 435 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 436 fdt_get_phandle(fdt, lpc_off)))); 437 } 438 439 typedef struct ForeachPopulateArgs { 440 void *fdt; 441 int offset; 442 } ForeachPopulateArgs; 443 444 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 445 { 446 ForeachPopulateArgs *args = opaque; 447 ISADevice *d = ISA_DEVICE(dev); 448 449 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 450 pnv_dt_rtc(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 452 pnv_dt_serial(d, args->fdt, args->offset); 453 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 454 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 455 } else { 456 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 457 d->ioport_id); 458 } 459 460 return 0; 461 } 462 463 /* 464 * The default LPC bus of a multichip system is on chip 0. It's 465 * recognized by the firmware (skiboot) using a "primary" property. 466 */ 467 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 468 { 469 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 470 ForeachPopulateArgs args = { 471 .fdt = fdt, 472 .offset = isa_offset, 473 }; 474 uint32_t phandle; 475 476 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 477 478 phandle = qemu_fdt_alloc_phandle(fdt); 479 assert(phandle > 0); 480 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 481 482 /* 483 * ISA devices are not necessarily parented to the ISA bus so we 484 * can not use object_child_foreach() 485 */ 486 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 487 &args); 488 } 489 490 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 491 { 492 int off; 493 494 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 495 off = fdt_add_subnode(fdt, off, "power-mgt"); 496 497 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 498 } 499 500 static void *pnv_dt_create(MachineState *machine) 501 { 502 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 503 PnvMachineState *pnv = PNV_MACHINE(machine); 504 void *fdt; 505 char *buf; 506 int off; 507 int i; 508 509 fdt = g_malloc0(FDT_MAX_SIZE); 510 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 511 512 /* /qemu node */ 513 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 514 515 /* Root node */ 516 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 517 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 518 _FDT((fdt_setprop_string(fdt, 0, "model", 519 "IBM PowerNV (emulated by qemu)"))); 520 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 521 522 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 523 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 524 if (qemu_uuid_set) { 525 _FDT((fdt_property_string(fdt, "system-id", buf))); 526 } 527 g_free(buf); 528 529 off = fdt_add_subnode(fdt, 0, "chosen"); 530 if (machine->kernel_cmdline) { 531 _FDT((fdt_setprop_string(fdt, off, "bootargs", 532 machine->kernel_cmdline))); 533 } 534 535 if (pnv->initrd_size) { 536 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 537 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 538 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 540 &start_prop, sizeof(start_prop)))); 541 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 542 &end_prop, sizeof(end_prop)))); 543 } 544 545 /* Populate device tree for each chip */ 546 for (i = 0; i < pnv->num_chips; i++) { 547 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 548 } 549 550 /* Populate ISA devices on chip 0 */ 551 pnv_dt_isa(pnv, fdt); 552 553 if (pnv->bmc) { 554 pnv_dt_bmc_sensors(pnv->bmc, fdt); 555 } 556 557 /* Create an extra node for power management on machines that support it */ 558 if (pmc->dt_power_mgt) { 559 pmc->dt_power_mgt(pnv, fdt); 560 } 561 562 return fdt; 563 } 564 565 static void pnv_powerdown_notify(Notifier *n, void *opaque) 566 { 567 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 568 569 if (pnv->bmc) { 570 pnv_bmc_powerdown(pnv->bmc); 571 } 572 } 573 574 static void pnv_reset(MachineState *machine) 575 { 576 PnvMachineState *pnv = PNV_MACHINE(machine); 577 IPMIBmc *bmc; 578 void *fdt; 579 580 qemu_devices_reset(); 581 582 /* 583 * The machine should provide by default an internal BMC simulator. 584 * If not, try to use the BMC device that was provided on the command 585 * line. 586 */ 587 bmc = pnv_bmc_find(&error_fatal); 588 if (!pnv->bmc) { 589 if (!bmc) { 590 if (!qtest_enabled()) { 591 warn_report("machine has no BMC device. Use '-device " 592 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 593 "to define one"); 594 } 595 } else { 596 pnv_bmc_set_pnor(bmc, pnv->pnor); 597 pnv->bmc = bmc; 598 } 599 } 600 601 fdt = pnv_dt_create(machine); 602 603 /* Pack resulting tree */ 604 _FDT((fdt_pack(fdt))); 605 606 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 607 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 608 609 g_free(fdt); 610 } 611 612 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 613 { 614 Pnv8Chip *chip8 = PNV8_CHIP(chip); 615 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 616 } 617 618 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 619 { 620 Pnv8Chip *chip8 = PNV8_CHIP(chip); 621 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 622 } 623 624 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 625 { 626 Pnv9Chip *chip9 = PNV9_CHIP(chip); 627 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 628 } 629 630 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 631 { 632 Pnv10Chip *chip10 = PNV10_CHIP(chip); 633 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 634 } 635 636 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 637 { 638 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 639 } 640 641 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 642 { 643 Pnv8Chip *chip8 = PNV8_CHIP(chip); 644 int i; 645 646 ics_pic_print_info(&chip8->psi.ics, mon); 647 for (i = 0; i < chip->num_phbs; i++) { 648 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 649 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 650 } 651 } 652 653 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 654 { 655 Pnv9Chip *chip9 = PNV9_CHIP(chip); 656 int i, j; 657 658 pnv_xive_pic_print_info(&chip9->xive, mon); 659 pnv_psi_pic_print_info(&chip9->psi, mon); 660 661 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 662 PnvPhb4PecState *pec = &chip9->pecs[i]; 663 for (j = 0; j < pec->num_stacks; j++) { 664 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 665 } 666 } 667 } 668 669 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 670 uint32_t core_id) 671 { 672 return PNV_XSCOM_EX_BASE(core_id); 673 } 674 675 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 676 uint32_t core_id) 677 { 678 return PNV9_XSCOM_EC_BASE(core_id); 679 } 680 681 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 682 uint32_t core_id) 683 { 684 return PNV10_XSCOM_EC_BASE(core_id); 685 } 686 687 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 688 { 689 PowerPCCPUClass *ppc_default = 690 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 691 PowerPCCPUClass *ppc = 692 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 693 694 return ppc_default->pvr_match(ppc_default, ppc->pvr); 695 } 696 697 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 698 { 699 ISADevice *dev = isa_new("isa-ipmi-bt"); 700 701 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 702 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 703 isa_realize_and_unref(dev, bus, &error_fatal); 704 } 705 706 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 707 { 708 Pnv10Chip *chip10 = PNV10_CHIP(chip); 709 710 pnv_psi_pic_print_info(&chip10->psi, mon); 711 } 712 713 /* Always give the first 1GB to chip 0 else we won't boot */ 714 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 715 { 716 MachineState *machine = MACHINE(pnv); 717 uint64_t ram_per_chip; 718 719 assert(machine->ram_size >= 1 * GiB); 720 721 ram_per_chip = machine->ram_size / pnv->num_chips; 722 if (ram_per_chip >= 1 * GiB) { 723 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 724 } 725 726 assert(pnv->num_chips > 1); 727 728 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 729 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 730 } 731 732 static void pnv_init(MachineState *machine) 733 { 734 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 735 PnvMachineState *pnv = PNV_MACHINE(machine); 736 MachineClass *mc = MACHINE_GET_CLASS(machine); 737 char *fw_filename; 738 long fw_size; 739 uint64_t chip_ram_start = 0; 740 int i; 741 char *chip_typename; 742 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 743 DeviceState *dev; 744 745 if (kvm_enabled()) { 746 error_report("The powernv machine does not work with KVM acceleration"); 747 exit(EXIT_FAILURE); 748 } 749 750 /* allocate RAM */ 751 if (machine->ram_size < mc->default_ram_size) { 752 char *sz = size_to_str(mc->default_ram_size); 753 error_report("Invalid RAM size, should be bigger than %s", sz); 754 g_free(sz); 755 exit(EXIT_FAILURE); 756 } 757 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 758 759 /* 760 * Create our simple PNOR device 761 */ 762 dev = qdev_new(TYPE_PNV_PNOR); 763 if (pnor) { 764 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 765 } 766 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 767 pnv->pnor = PNV_PNOR(dev); 768 769 /* load skiboot firmware */ 770 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 771 if (!fw_filename) { 772 error_report("Could not find OPAL firmware '%s'", bios_name); 773 exit(1); 774 } 775 776 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 777 if (fw_size < 0) { 778 error_report("Could not load OPAL firmware '%s'", fw_filename); 779 exit(1); 780 } 781 g_free(fw_filename); 782 783 /* load kernel */ 784 if (machine->kernel_filename) { 785 long kernel_size; 786 787 kernel_size = load_image_targphys(machine->kernel_filename, 788 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 789 if (kernel_size < 0) { 790 error_report("Could not load kernel '%s'", 791 machine->kernel_filename); 792 exit(1); 793 } 794 } 795 796 /* load initrd */ 797 if (machine->initrd_filename) { 798 pnv->initrd_base = INITRD_LOAD_ADDR; 799 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 800 pnv->initrd_base, INITRD_MAX_SIZE); 801 if (pnv->initrd_size < 0) { 802 error_report("Could not load initial ram disk '%s'", 803 machine->initrd_filename); 804 exit(1); 805 } 806 } 807 808 /* MSIs are supported on this platform */ 809 msi_nonbroken = true; 810 811 /* 812 * Check compatibility of the specified CPU with the machine 813 * default. 814 */ 815 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 816 error_report("invalid CPU model '%s' for %s machine", 817 machine->cpu_type, mc->name); 818 exit(1); 819 } 820 821 /* Create the processor chips */ 822 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 823 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 824 i, machine->cpu_type); 825 if (!object_class_by_name(chip_typename)) { 826 error_report("invalid chip model '%.*s' for %s machine", 827 i, machine->cpu_type, mc->name); 828 exit(1); 829 } 830 831 pnv->num_chips = 832 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 833 /* 834 * TODO: should we decide on how many chips we can create based 835 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 836 */ 837 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 838 error_report("invalid number of chips: '%d'", pnv->num_chips); 839 error_printf( 840 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 841 exit(1); 842 } 843 844 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 845 for (i = 0; i < pnv->num_chips; i++) { 846 char chip_name[32]; 847 Object *chip = OBJECT(qdev_new(chip_typename)); 848 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 849 850 pnv->chips[i] = PNV_CHIP(chip); 851 852 /* Distribute RAM among the chips */ 853 object_property_set_int(chip, "ram-start", chip_ram_start, 854 &error_fatal); 855 object_property_set_int(chip, "ram-size", chip_ram_size, 856 &error_fatal); 857 chip_ram_start += chip_ram_size; 858 859 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 860 object_property_add_child(OBJECT(pnv), chip_name, chip); 861 object_property_set_int(chip, "chip-id", i, &error_fatal); 862 object_property_set_int(chip, "nr-cores", machine->smp.cores, 863 &error_fatal); 864 object_property_set_int(chip, "nr-threads", machine->smp.threads, 865 &error_fatal); 866 /* 867 * The POWER8 machine use the XICS interrupt interface. 868 * Propagate the XICS fabric to the chip and its controllers. 869 */ 870 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 871 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 872 } 873 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 874 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 875 &error_abort); 876 } 877 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 878 } 879 g_free(chip_typename); 880 881 /* Instantiate ISA bus on chip 0 */ 882 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 883 884 /* Create serial port */ 885 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 886 887 /* Create an RTC ISA device too */ 888 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 889 890 /* 891 * Create the machine BMC simulator and the IPMI BT device for 892 * communication with the BMC 893 */ 894 if (defaults_enabled()) { 895 pnv->bmc = pnv_bmc_create(pnv->pnor); 896 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 897 } 898 899 /* 900 * The PNOR is mapped on the LPC FW address space by the BMC. 901 * Since we can not reach the remote BMC machine with LPC memops, 902 * map it always for now. 903 */ 904 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 905 &pnv->pnor->mmio); 906 907 /* 908 * OpenPOWER systems use a IPMI SEL Event message to notify the 909 * host to powerdown 910 */ 911 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 912 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 913 } 914 915 /* 916 * 0:21 Reserved - Read as zeros 917 * 22:24 Chip ID 918 * 25:28 Core number 919 * 29:31 Thread ID 920 */ 921 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 922 { 923 return (chip->chip_id << 7) | (core_id << 3); 924 } 925 926 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 927 Error **errp) 928 { 929 Pnv8Chip *chip8 = PNV8_CHIP(chip); 930 Error *local_err = NULL; 931 Object *obj; 932 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 933 934 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 935 if (local_err) { 936 error_propagate(errp, local_err); 937 return; 938 } 939 940 pnv_cpu->intc = obj; 941 } 942 943 944 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 945 { 946 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 947 948 icp_reset(ICP(pnv_cpu->intc)); 949 } 950 951 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 952 { 953 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 954 955 icp_destroy(ICP(pnv_cpu->intc)); 956 pnv_cpu->intc = NULL; 957 } 958 959 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 960 Monitor *mon) 961 { 962 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 963 } 964 965 /* 966 * 0:48 Reserved - Read as zeroes 967 * 49:52 Node ID 968 * 53:55 Chip ID 969 * 56 Reserved - Read as zero 970 * 57:61 Core number 971 * 62:63 Thread ID 972 * 973 * We only care about the lower bits. uint32_t is fine for the moment. 974 */ 975 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 976 { 977 return (chip->chip_id << 8) | (core_id << 2); 978 } 979 980 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 981 { 982 return (chip->chip_id << 8) | (core_id << 2); 983 } 984 985 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 986 Error **errp) 987 { 988 Pnv9Chip *chip9 = PNV9_CHIP(chip); 989 Error *local_err = NULL; 990 Object *obj; 991 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 992 993 /* 994 * The core creates its interrupt presenter but the XIVE interrupt 995 * controller object is initialized afterwards. Hopefully, it's 996 * only used at runtime. 997 */ 998 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 999 &local_err); 1000 if (local_err) { 1001 error_propagate(errp, local_err); 1002 return; 1003 } 1004 1005 pnv_cpu->intc = obj; 1006 } 1007 1008 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1009 { 1010 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1011 1012 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1013 } 1014 1015 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1016 { 1017 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1018 1019 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1020 pnv_cpu->intc = NULL; 1021 } 1022 1023 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1024 Monitor *mon) 1025 { 1026 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1027 } 1028 1029 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1030 Error **errp) 1031 { 1032 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1033 1034 /* Will be defined when the interrupt controller is */ 1035 pnv_cpu->intc = NULL; 1036 } 1037 1038 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1039 { 1040 ; 1041 } 1042 1043 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1044 { 1045 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1046 1047 pnv_cpu->intc = NULL; 1048 } 1049 1050 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1051 Monitor *mon) 1052 { 1053 } 1054 1055 /* 1056 * Allowed core identifiers on a POWER8 Processor Chip : 1057 * 1058 * <EX0 reserved> 1059 * EX1 - Venice only 1060 * EX2 - Venice only 1061 * EX3 - Venice only 1062 * EX4 1063 * EX5 1064 * EX6 1065 * <EX7,8 reserved> <reserved> 1066 * EX9 - Venice only 1067 * EX10 - Venice only 1068 * EX11 - Venice only 1069 * EX12 1070 * EX13 1071 * EX14 1072 * <EX15 reserved> 1073 */ 1074 #define POWER8E_CORE_MASK (0x7070ull) 1075 #define POWER8_CORE_MASK (0x7e7eull) 1076 1077 /* 1078 * POWER9 has 24 cores, ids starting at 0x0 1079 */ 1080 #define POWER9_CORE_MASK (0xffffffffffffffull) 1081 1082 1083 #define POWER10_CORE_MASK (0xffffffffffffffull) 1084 1085 static void pnv_chip_power8_instance_init(Object *obj) 1086 { 1087 PnvChip *chip = PNV_CHIP(obj); 1088 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1089 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1090 int i; 1091 1092 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1093 (Object **)&chip8->xics, 1094 object_property_allow_set_link, 1095 OBJ_PROP_LINK_STRONG); 1096 1097 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1098 1099 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1100 1101 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1102 1103 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1104 1105 for (i = 0; i < pcc->num_phbs; i++) { 1106 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1107 } 1108 1109 /* 1110 * Number of PHBs is the chip default 1111 */ 1112 chip->num_phbs = pcc->num_phbs; 1113 } 1114 1115 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1116 { 1117 PnvChip *chip = PNV_CHIP(chip8); 1118 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1119 int i, j; 1120 char *name; 1121 1122 name = g_strdup_printf("icp-%x", chip->chip_id); 1123 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1124 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1125 g_free(name); 1126 1127 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1128 1129 /* Map the ICP registers for each thread */ 1130 for (i = 0; i < chip->nr_cores; i++) { 1131 PnvCore *pnv_core = chip->cores[i]; 1132 int core_hwid = CPU_CORE(pnv_core)->core_id; 1133 1134 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1135 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1136 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1137 1138 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1139 &icp->mmio); 1140 } 1141 } 1142 } 1143 1144 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1145 { 1146 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1147 PnvChip *chip = PNV_CHIP(dev); 1148 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1149 Pnv8Psi *psi8 = &chip8->psi; 1150 Error *local_err = NULL; 1151 int i; 1152 1153 assert(chip8->xics); 1154 1155 /* XSCOM bridge is first */ 1156 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1157 if (local_err) { 1158 error_propagate(errp, local_err); 1159 return; 1160 } 1161 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1162 1163 pcc->parent_realize(dev, &local_err); 1164 if (local_err) { 1165 error_propagate(errp, local_err); 1166 return; 1167 } 1168 1169 /* Processor Service Interface (PSI) Host Bridge */ 1170 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1171 &error_fatal); 1172 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1173 OBJECT(chip8->xics), &error_abort); 1174 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1175 return; 1176 } 1177 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1178 &PNV_PSI(psi8)->xscom_regs); 1179 1180 /* Create LPC controller */ 1181 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi), 1182 &error_abort); 1183 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1184 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1185 1186 chip->fw_mr = &chip8->lpc.isa_fw; 1187 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1188 (uint64_t) PNV_XSCOM_BASE(chip), 1189 PNV_XSCOM_LPC_BASE); 1190 1191 /* 1192 * Interrupt Management Area. This is the memory region holding 1193 * all the Interrupt Control Presenter (ICP) registers 1194 */ 1195 pnv_chip_icp_realize(chip8, &local_err); 1196 if (local_err) { 1197 error_propagate(errp, local_err); 1198 return; 1199 } 1200 1201 /* Create the simplified OCC model */ 1202 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi), 1203 &error_abort); 1204 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1205 return; 1206 } 1207 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1208 1209 /* OCC SRAM model */ 1210 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1211 &chip8->occ.sram_regs); 1212 1213 /* HOMER */ 1214 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1215 &error_abort); 1216 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1217 return; 1218 } 1219 /* Homer Xscom region */ 1220 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1221 1222 /* Homer mmio region */ 1223 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1224 &chip8->homer.regs); 1225 1226 /* PHB3 controllers */ 1227 for (i = 0; i < chip->num_phbs; i++) { 1228 PnvPHB3 *phb = &chip8->phbs[i]; 1229 PnvPBCQState *pbcq = &phb->pbcq; 1230 1231 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1232 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1233 &error_fatal); 1234 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1235 return; 1236 } 1237 1238 /* Populate the XSCOM address space. */ 1239 pnv_xscom_add_subregion(chip, 1240 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1241 &pbcq->xscom_nest_regs); 1242 pnv_xscom_add_subregion(chip, 1243 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1244 &pbcq->xscom_pci_regs); 1245 pnv_xscom_add_subregion(chip, 1246 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1247 &pbcq->xscom_spci_regs); 1248 } 1249 } 1250 1251 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1252 { 1253 addr &= (PNV_XSCOM_SIZE - 1); 1254 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1255 } 1256 1257 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1258 { 1259 DeviceClass *dc = DEVICE_CLASS(klass); 1260 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1261 1262 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1263 k->cores_mask = POWER8E_CORE_MASK; 1264 k->num_phbs = 3; 1265 k->core_pir = pnv_chip_core_pir_p8; 1266 k->intc_create = pnv_chip_power8_intc_create; 1267 k->intc_reset = pnv_chip_power8_intc_reset; 1268 k->intc_destroy = pnv_chip_power8_intc_destroy; 1269 k->intc_print_info = pnv_chip_power8_intc_print_info; 1270 k->isa_create = pnv_chip_power8_isa_create; 1271 k->dt_populate = pnv_chip_power8_dt_populate; 1272 k->pic_print_info = pnv_chip_power8_pic_print_info; 1273 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1274 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1275 dc->desc = "PowerNV Chip POWER8E"; 1276 1277 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1278 &k->parent_realize); 1279 } 1280 1281 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1282 { 1283 DeviceClass *dc = DEVICE_CLASS(klass); 1284 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1285 1286 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1287 k->cores_mask = POWER8_CORE_MASK; 1288 k->num_phbs = 3; 1289 k->core_pir = pnv_chip_core_pir_p8; 1290 k->intc_create = pnv_chip_power8_intc_create; 1291 k->intc_reset = pnv_chip_power8_intc_reset; 1292 k->intc_destroy = pnv_chip_power8_intc_destroy; 1293 k->intc_print_info = pnv_chip_power8_intc_print_info; 1294 k->isa_create = pnv_chip_power8_isa_create; 1295 k->dt_populate = pnv_chip_power8_dt_populate; 1296 k->pic_print_info = pnv_chip_power8_pic_print_info; 1297 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1298 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1299 dc->desc = "PowerNV Chip POWER8"; 1300 1301 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1302 &k->parent_realize); 1303 } 1304 1305 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1306 { 1307 DeviceClass *dc = DEVICE_CLASS(klass); 1308 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1309 1310 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1311 k->cores_mask = POWER8_CORE_MASK; 1312 k->num_phbs = 3; 1313 k->core_pir = pnv_chip_core_pir_p8; 1314 k->intc_create = pnv_chip_power8_intc_create; 1315 k->intc_reset = pnv_chip_power8_intc_reset; 1316 k->intc_destroy = pnv_chip_power8_intc_destroy; 1317 k->intc_print_info = pnv_chip_power8_intc_print_info; 1318 k->isa_create = pnv_chip_power8nvl_isa_create; 1319 k->dt_populate = pnv_chip_power8_dt_populate; 1320 k->pic_print_info = pnv_chip_power8_pic_print_info; 1321 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1322 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1323 dc->desc = "PowerNV Chip POWER8NVL"; 1324 1325 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1326 &k->parent_realize); 1327 } 1328 1329 static void pnv_chip_power9_instance_init(Object *obj) 1330 { 1331 PnvChip *chip = PNV_CHIP(obj); 1332 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1333 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1334 int i; 1335 1336 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1337 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1338 "xive-fabric"); 1339 1340 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1341 1342 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1343 1344 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1345 1346 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1347 1348 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1349 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1350 TYPE_PNV_PHB4_PEC); 1351 } 1352 1353 /* 1354 * Number of PHBs is the chip default 1355 */ 1356 chip->num_phbs = pcc->num_phbs; 1357 } 1358 1359 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1360 { 1361 PnvChip *chip = PNV_CHIP(chip9); 1362 int i; 1363 1364 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1365 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1366 1367 for (i = 0; i < chip9->nr_quads; i++) { 1368 char eq_name[32]; 1369 PnvQuad *eq = &chip9->quads[i]; 1370 PnvCore *pnv_core = chip->cores[i * 4]; 1371 int core_id = CPU_CORE(pnv_core)->core_id; 1372 1373 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1374 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1375 sizeof(*eq), TYPE_PNV_QUAD, 1376 &error_fatal, NULL); 1377 1378 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1379 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1380 1381 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1382 &eq->xscom_regs); 1383 } 1384 } 1385 1386 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1387 { 1388 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1389 int i, j; 1390 int phb_id = 0; 1391 1392 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1393 PnvPhb4PecState *pec = &chip9->pecs[i]; 1394 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1395 uint32_t pec_nest_base; 1396 uint32_t pec_pci_base; 1397 1398 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1399 /* 1400 * PEC0 -> 1 stack 1401 * PEC1 -> 2 stacks 1402 * PEC2 -> 3 stacks 1403 */ 1404 object_property_set_int(OBJECT(pec), "num-stacks", i + 1, 1405 &error_fatal); 1406 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1407 &error_fatal); 1408 object_property_set_link(OBJECT(pec), "system-memory", 1409 OBJECT(get_system_memory()), &error_abort); 1410 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1411 return; 1412 } 1413 1414 pec_nest_base = pecc->xscom_nest_base(pec); 1415 pec_pci_base = pecc->xscom_pci_base(pec); 1416 1417 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1418 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1419 1420 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1421 j++, phb_id++) { 1422 PnvPhb4PecStack *stack = &pec->stacks[j]; 1423 Object *obj = OBJECT(&stack->phb); 1424 1425 object_property_set_int(obj, "index", phb_id, &error_fatal); 1426 object_property_set_int(obj, "chip-id", chip->chip_id, 1427 &error_fatal); 1428 object_property_set_int(obj, "version", PNV_PHB4_VERSION, 1429 &error_fatal); 1430 object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID, 1431 &error_fatal); 1432 object_property_set_link(obj, "stack", OBJECT(stack), 1433 &error_abort); 1434 if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) { 1435 return; 1436 } 1437 1438 /* Populate the XSCOM address space. */ 1439 pnv_xscom_add_subregion(chip, 1440 pec_nest_base + 0x40 * (stack->stack_no + 1), 1441 &stack->nest_regs_mr); 1442 pnv_xscom_add_subregion(chip, 1443 pec_pci_base + 0x40 * (stack->stack_no + 1), 1444 &stack->pci_regs_mr); 1445 pnv_xscom_add_subregion(chip, 1446 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1447 0x40 * stack->stack_no, 1448 &stack->phb_regs_mr); 1449 } 1450 } 1451 } 1452 1453 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1454 { 1455 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1456 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1457 PnvChip *chip = PNV_CHIP(dev); 1458 Pnv9Psi *psi9 = &chip9->psi; 1459 Error *local_err = NULL; 1460 1461 /* XSCOM bridge is first */ 1462 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1463 if (local_err) { 1464 error_propagate(errp, local_err); 1465 return; 1466 } 1467 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1468 1469 pcc->parent_realize(dev, &local_err); 1470 if (local_err) { 1471 error_propagate(errp, local_err); 1472 return; 1473 } 1474 1475 pnv_chip_quad_realize(chip9, &local_err); 1476 if (local_err) { 1477 error_propagate(errp, local_err); 1478 return; 1479 } 1480 1481 /* XIVE interrupt controller (POWER9) */ 1482 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1483 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1484 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1485 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1486 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1487 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1488 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1489 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1490 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1491 &error_abort); 1492 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1493 return; 1494 } 1495 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1496 &chip9->xive.xscom_regs); 1497 1498 /* Processor Service Interface (PSI) Host Bridge */ 1499 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1500 &error_fatal); 1501 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1502 return; 1503 } 1504 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1505 &PNV_PSI(psi9)->xscom_regs); 1506 1507 /* LPC */ 1508 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi), 1509 &error_abort); 1510 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1511 return; 1512 } 1513 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1514 &chip9->lpc.xscom_regs); 1515 1516 chip->fw_mr = &chip9->lpc.isa_fw; 1517 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1518 (uint64_t) PNV9_LPCM_BASE(chip)); 1519 1520 /* Create the simplified OCC model */ 1521 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi), 1522 &error_abort); 1523 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1524 return; 1525 } 1526 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1527 1528 /* OCC SRAM model */ 1529 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1530 &chip9->occ.sram_regs); 1531 1532 /* HOMER */ 1533 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1534 &error_abort); 1535 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1536 return; 1537 } 1538 /* Homer Xscom region */ 1539 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1540 1541 /* Homer mmio region */ 1542 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1543 &chip9->homer.regs); 1544 1545 /* PHBs */ 1546 pnv_chip_power9_phb_realize(chip, &local_err); 1547 if (local_err) { 1548 error_propagate(errp, local_err); 1549 return; 1550 } 1551 } 1552 1553 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1554 { 1555 addr &= (PNV9_XSCOM_SIZE - 1); 1556 return addr >> 3; 1557 } 1558 1559 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1560 { 1561 DeviceClass *dc = DEVICE_CLASS(klass); 1562 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1563 1564 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1565 k->cores_mask = POWER9_CORE_MASK; 1566 k->core_pir = pnv_chip_core_pir_p9; 1567 k->intc_create = pnv_chip_power9_intc_create; 1568 k->intc_reset = pnv_chip_power9_intc_reset; 1569 k->intc_destroy = pnv_chip_power9_intc_destroy; 1570 k->intc_print_info = pnv_chip_power9_intc_print_info; 1571 k->isa_create = pnv_chip_power9_isa_create; 1572 k->dt_populate = pnv_chip_power9_dt_populate; 1573 k->pic_print_info = pnv_chip_power9_pic_print_info; 1574 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1575 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1576 dc->desc = "PowerNV Chip POWER9"; 1577 k->num_phbs = 6; 1578 1579 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1580 &k->parent_realize); 1581 } 1582 1583 static void pnv_chip_power10_instance_init(Object *obj) 1584 { 1585 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1586 1587 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1588 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1589 } 1590 1591 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1592 { 1593 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1594 PnvChip *chip = PNV_CHIP(dev); 1595 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1596 Error *local_err = NULL; 1597 1598 /* XSCOM bridge is first */ 1599 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1600 if (local_err) { 1601 error_propagate(errp, local_err); 1602 return; 1603 } 1604 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1605 1606 pcc->parent_realize(dev, &local_err); 1607 if (local_err) { 1608 error_propagate(errp, local_err); 1609 return; 1610 } 1611 1612 /* Processor Service Interface (PSI) Host Bridge */ 1613 object_property_set_int(OBJECT(&chip10->psi), "bar", 1614 PNV10_PSIHB_BASE(chip), &error_fatal); 1615 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1616 return; 1617 } 1618 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1619 &PNV_PSI(&chip10->psi)->xscom_regs); 1620 1621 /* LPC */ 1622 object_property_set_link(OBJECT(&chip10->lpc), "psi", 1623 OBJECT(&chip10->psi), &error_abort); 1624 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1625 return; 1626 } 1627 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1628 &chip10->lpc.xscom_regs); 1629 1630 chip->fw_mr = &chip10->lpc.isa_fw; 1631 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1632 (uint64_t) PNV10_LPCM_BASE(chip)); 1633 } 1634 1635 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1636 { 1637 addr &= (PNV10_XSCOM_SIZE - 1); 1638 return addr >> 3; 1639 } 1640 1641 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1642 { 1643 DeviceClass *dc = DEVICE_CLASS(klass); 1644 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1645 1646 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1647 k->cores_mask = POWER10_CORE_MASK; 1648 k->core_pir = pnv_chip_core_pir_p10; 1649 k->intc_create = pnv_chip_power10_intc_create; 1650 k->intc_reset = pnv_chip_power10_intc_reset; 1651 k->intc_destroy = pnv_chip_power10_intc_destroy; 1652 k->intc_print_info = pnv_chip_power10_intc_print_info; 1653 k->isa_create = pnv_chip_power10_isa_create; 1654 k->dt_populate = pnv_chip_power10_dt_populate; 1655 k->pic_print_info = pnv_chip_power10_pic_print_info; 1656 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1657 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1658 dc->desc = "PowerNV Chip POWER10"; 1659 1660 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1661 &k->parent_realize); 1662 } 1663 1664 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1665 { 1666 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1667 int cores_max; 1668 1669 /* 1670 * No custom mask for this chip, let's use the default one from * 1671 * the chip class 1672 */ 1673 if (!chip->cores_mask) { 1674 chip->cores_mask = pcc->cores_mask; 1675 } 1676 1677 /* filter alien core ids ! some are reserved */ 1678 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1679 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1680 chip->cores_mask); 1681 return; 1682 } 1683 chip->cores_mask &= pcc->cores_mask; 1684 1685 /* now that we have a sane layout, let check the number of cores */ 1686 cores_max = ctpop64(chip->cores_mask); 1687 if (chip->nr_cores > cores_max) { 1688 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1689 cores_max); 1690 return; 1691 } 1692 } 1693 1694 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1695 { 1696 Error *error = NULL; 1697 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1698 const char *typename = pnv_chip_core_typename(chip); 1699 int i, core_hwid; 1700 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1701 1702 if (!object_class_by_name(typename)) { 1703 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1704 return; 1705 } 1706 1707 /* Cores */ 1708 pnv_chip_core_sanitize(chip, &error); 1709 if (error) { 1710 error_propagate(errp, error); 1711 return; 1712 } 1713 1714 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1715 1716 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1717 && (i < chip->nr_cores); core_hwid++) { 1718 char core_name[32]; 1719 PnvCore *pnv_core; 1720 uint64_t xscom_core_base; 1721 1722 if (!(chip->cores_mask & (1ull << core_hwid))) { 1723 continue; 1724 } 1725 1726 pnv_core = PNV_CORE(object_new(typename)); 1727 1728 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1729 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1730 chip->cores[i] = pnv_core; 1731 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1732 chip->nr_threads, &error_fatal); 1733 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1734 core_hwid, &error_fatal); 1735 object_property_set_int(OBJECT(pnv_core), "pir", 1736 pcc->core_pir(chip, core_hwid), &error_fatal); 1737 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1738 &error_fatal); 1739 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1740 &error_abort); 1741 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1742 1743 /* Each core has an XSCOM MMIO region */ 1744 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1745 1746 pnv_xscom_add_subregion(chip, xscom_core_base, 1747 &pnv_core->xscom_regs); 1748 i++; 1749 } 1750 } 1751 1752 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1753 { 1754 PnvChip *chip = PNV_CHIP(dev); 1755 Error *error = NULL; 1756 1757 /* Cores */ 1758 pnv_chip_core_realize(chip, &error); 1759 if (error) { 1760 error_propagate(errp, error); 1761 return; 1762 } 1763 } 1764 1765 static Property pnv_chip_properties[] = { 1766 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1767 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1768 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1769 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1770 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1771 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1772 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1773 DEFINE_PROP_END_OF_LIST(), 1774 }; 1775 1776 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1777 { 1778 DeviceClass *dc = DEVICE_CLASS(klass); 1779 1780 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1781 dc->realize = pnv_chip_realize; 1782 device_class_set_props(dc, pnv_chip_properties); 1783 dc->desc = "PowerNV Chip"; 1784 } 1785 1786 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1787 { 1788 int i, j; 1789 1790 for (i = 0; i < chip->nr_cores; i++) { 1791 PnvCore *pc = chip->cores[i]; 1792 CPUCore *cc = CPU_CORE(pc); 1793 1794 for (j = 0; j < cc->nr_threads; j++) { 1795 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1796 return pc->threads[j]; 1797 } 1798 } 1799 } 1800 return NULL; 1801 } 1802 1803 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1804 { 1805 PnvMachineState *pnv = PNV_MACHINE(xi); 1806 int i, j; 1807 1808 for (i = 0; i < pnv->num_chips; i++) { 1809 PnvChip *chip = pnv->chips[i]; 1810 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1811 1812 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1813 return &chip8->psi.ics; 1814 } 1815 for (j = 0; j < chip->num_phbs; j++) { 1816 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1817 return &chip8->phbs[j].lsis; 1818 } 1819 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1820 return ICS(&chip8->phbs[j].msis); 1821 } 1822 } 1823 } 1824 return NULL; 1825 } 1826 1827 static void pnv_ics_resend(XICSFabric *xi) 1828 { 1829 PnvMachineState *pnv = PNV_MACHINE(xi); 1830 int i, j; 1831 1832 for (i = 0; i < pnv->num_chips; i++) { 1833 PnvChip *chip = pnv->chips[i]; 1834 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1835 1836 ics_resend(&chip8->psi.ics); 1837 for (j = 0; j < chip->num_phbs; j++) { 1838 ics_resend(&chip8->phbs[j].lsis); 1839 ics_resend(ICS(&chip8->phbs[j].msis)); 1840 } 1841 } 1842 } 1843 1844 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1845 { 1846 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1847 1848 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1849 } 1850 1851 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1852 Monitor *mon) 1853 { 1854 PnvMachineState *pnv = PNV_MACHINE(obj); 1855 int i; 1856 CPUState *cs; 1857 1858 CPU_FOREACH(cs) { 1859 PowerPCCPU *cpu = POWERPC_CPU(cs); 1860 1861 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1862 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1863 mon); 1864 } 1865 1866 for (i = 0; i < pnv->num_chips; i++) { 1867 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1868 } 1869 } 1870 1871 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1872 uint8_t nvt_blk, uint32_t nvt_idx, 1873 bool cam_ignore, uint8_t priority, 1874 uint32_t logic_serv, 1875 XiveTCTXMatch *match) 1876 { 1877 PnvMachineState *pnv = PNV_MACHINE(xfb); 1878 int total_count = 0; 1879 int i; 1880 1881 for (i = 0; i < pnv->num_chips; i++) { 1882 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1883 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1884 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1885 int count; 1886 1887 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1888 priority, logic_serv, match); 1889 1890 if (count < 0) { 1891 return count; 1892 } 1893 1894 total_count += count; 1895 } 1896 1897 return total_count; 1898 } 1899 1900 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1901 { 1902 MachineClass *mc = MACHINE_CLASS(oc); 1903 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1904 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1905 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1906 1907 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1908 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1909 1910 xic->icp_get = pnv_icp_get; 1911 xic->ics_get = pnv_ics_get; 1912 xic->ics_resend = pnv_ics_resend; 1913 1914 pmc->compat = compat; 1915 pmc->compat_size = sizeof(compat); 1916 } 1917 1918 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1919 { 1920 MachineClass *mc = MACHINE_CLASS(oc); 1921 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1922 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1923 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1924 1925 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1926 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1927 xfc->match_nvt = pnv_match_nvt; 1928 1929 mc->alias = "powernv"; 1930 1931 pmc->compat = compat; 1932 pmc->compat_size = sizeof(compat); 1933 pmc->dt_power_mgt = pnv_dt_power_mgt; 1934 } 1935 1936 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1937 { 1938 MachineClass *mc = MACHINE_CLASS(oc); 1939 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1940 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1941 1942 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1943 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 1944 1945 pmc->compat = compat; 1946 pmc->compat_size = sizeof(compat); 1947 pmc->dt_power_mgt = pnv_dt_power_mgt; 1948 } 1949 1950 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1951 { 1952 PnvMachineState *pnv = PNV_MACHINE(obj); 1953 1954 return !!pnv->fw_load_addr; 1955 } 1956 1957 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1958 { 1959 PnvMachineState *pnv = PNV_MACHINE(obj); 1960 1961 if (value) { 1962 pnv->fw_load_addr = 0x8000000; 1963 } 1964 } 1965 1966 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 1967 { 1968 PowerPCCPU *cpu = POWERPC_CPU(cs); 1969 CPUPPCState *env = &cpu->env; 1970 1971 cpu_synchronize_state(cs); 1972 ppc_cpu_do_system_reset(cs); 1973 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 1974 /* 1975 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 1976 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 1977 * (PPC_BIT(43)). 1978 */ 1979 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 1980 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 1981 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 1982 } 1983 } else { 1984 /* 1985 * For non-powersave system resets, SRR1[42:45] are defined to be 1986 * implementation-dependent. The POWER9 User Manual specifies that 1987 * an external (SCOM driven, which may come from a BMC nmi command or 1988 * another CPU requesting a NMI IPI) system reset exception should be 1989 * 0b0010 (PPC_BIT(44)). 1990 */ 1991 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 1992 } 1993 } 1994 1995 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 1996 { 1997 CPUState *cs; 1998 1999 CPU_FOREACH(cs) { 2000 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2001 } 2002 } 2003 2004 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2005 { 2006 MachineClass *mc = MACHINE_CLASS(oc); 2007 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2008 NMIClass *nc = NMI_CLASS(oc); 2009 2010 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2011 mc->init = pnv_init; 2012 mc->reset = pnv_reset; 2013 mc->max_cpus = MAX_CPUS; 2014 /* Pnv provides a AHCI device for storage */ 2015 mc->block_default_type = IF_IDE; 2016 mc->no_parallel = 1; 2017 mc->default_boot_order = NULL; 2018 /* 2019 * RAM defaults to less than 2048 for 32-bit hosts, and large 2020 * enough to fit the maximum initrd size at it's load address 2021 */ 2022 mc->default_ram_size = 1 * GiB; 2023 mc->default_ram_id = "pnv.ram"; 2024 ispc->print_info = pnv_pic_print_info; 2025 nc->nmi_monitor_handler = pnv_nmi; 2026 2027 object_class_property_add_bool(oc, "hb-mode", 2028 pnv_machine_get_hb, pnv_machine_set_hb); 2029 object_class_property_set_description(oc, "hb-mode", 2030 "Use a hostboot like boot loader"); 2031 } 2032 2033 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2034 { \ 2035 .name = type, \ 2036 .class_init = class_initfn, \ 2037 .parent = TYPE_PNV8_CHIP, \ 2038 } 2039 2040 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2041 { \ 2042 .name = type, \ 2043 .class_init = class_initfn, \ 2044 .parent = TYPE_PNV9_CHIP, \ 2045 } 2046 2047 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2048 { \ 2049 .name = type, \ 2050 .class_init = class_initfn, \ 2051 .parent = TYPE_PNV10_CHIP, \ 2052 } 2053 2054 static const TypeInfo types[] = { 2055 { 2056 .name = MACHINE_TYPE_NAME("powernv10"), 2057 .parent = TYPE_PNV_MACHINE, 2058 .class_init = pnv_machine_power10_class_init, 2059 }, 2060 { 2061 .name = MACHINE_TYPE_NAME("powernv9"), 2062 .parent = TYPE_PNV_MACHINE, 2063 .class_init = pnv_machine_power9_class_init, 2064 .interfaces = (InterfaceInfo[]) { 2065 { TYPE_XIVE_FABRIC }, 2066 { }, 2067 }, 2068 }, 2069 { 2070 .name = MACHINE_TYPE_NAME("powernv8"), 2071 .parent = TYPE_PNV_MACHINE, 2072 .class_init = pnv_machine_power8_class_init, 2073 .interfaces = (InterfaceInfo[]) { 2074 { TYPE_XICS_FABRIC }, 2075 { }, 2076 }, 2077 }, 2078 { 2079 .name = TYPE_PNV_MACHINE, 2080 .parent = TYPE_MACHINE, 2081 .abstract = true, 2082 .instance_size = sizeof(PnvMachineState), 2083 .class_init = pnv_machine_class_init, 2084 .class_size = sizeof(PnvMachineClass), 2085 .interfaces = (InterfaceInfo[]) { 2086 { TYPE_INTERRUPT_STATS_PROVIDER }, 2087 { TYPE_NMI }, 2088 { }, 2089 }, 2090 }, 2091 { 2092 .name = TYPE_PNV_CHIP, 2093 .parent = TYPE_SYS_BUS_DEVICE, 2094 .class_init = pnv_chip_class_init, 2095 .instance_size = sizeof(PnvChip), 2096 .class_size = sizeof(PnvChipClass), 2097 .abstract = true, 2098 }, 2099 2100 /* 2101 * P10 chip and variants 2102 */ 2103 { 2104 .name = TYPE_PNV10_CHIP, 2105 .parent = TYPE_PNV_CHIP, 2106 .instance_init = pnv_chip_power10_instance_init, 2107 .instance_size = sizeof(Pnv10Chip), 2108 }, 2109 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2110 2111 /* 2112 * P9 chip and variants 2113 */ 2114 { 2115 .name = TYPE_PNV9_CHIP, 2116 .parent = TYPE_PNV_CHIP, 2117 .instance_init = pnv_chip_power9_instance_init, 2118 .instance_size = sizeof(Pnv9Chip), 2119 }, 2120 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2121 2122 /* 2123 * P8 chip and variants 2124 */ 2125 { 2126 .name = TYPE_PNV8_CHIP, 2127 .parent = TYPE_PNV_CHIP, 2128 .instance_init = pnv_chip_power8_instance_init, 2129 .instance_size = sizeof(Pnv8Chip), 2130 }, 2131 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2132 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2133 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2134 pnv_chip_power8nvl_class_init), 2135 }; 2136 2137 DEFINE_TYPES(types) 2138