1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 #include "hw/pci/msi.h" 44 45 #include "hw/ppc/xics.h" 46 #include "hw/qdev-properties.h" 47 #include "hw/ppc/pnv_xscom.h" 48 #include "hw/ppc/pnv_pnor.h" 49 50 #include "hw/isa/isa.h" 51 #include "hw/boards.h" 52 #include "hw/char/serial.h" 53 #include "hw/rtc/mc146818rtc.h" 54 55 #include <libfdt.h> 56 57 #define FDT_MAX_SIZE (1 * MiB) 58 59 #define FW_FILE_NAME "skiboot.lid" 60 #define FW_LOAD_ADDR 0x0 61 #define FW_MAX_SIZE (4 * MiB) 62 63 #define KERNEL_LOAD_ADDR 0x20000000 64 #define KERNEL_MAX_SIZE (256 * MiB) 65 #define INITRD_LOAD_ADDR 0x60000000 66 #define INITRD_MAX_SIZE (256 * MiB) 67 68 static const char *pnv_chip_core_typename(const PnvChip *o) 69 { 70 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 71 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 72 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 73 const char *core_type = object_class_get_name(object_class_by_name(s)); 74 g_free(s); 75 return core_type; 76 } 77 78 /* 79 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 80 * 4 * 4 sockets * 12 cores * 8 threads = 1536 81 * Let's make it 2^11 82 */ 83 #define MAX_CPUS 2048 84 85 /* 86 * Memory nodes are created by hostboot, one for each range of memory 87 * that has a different "affinity". In practice, it means one range 88 * per chip. 89 */ 90 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 91 { 92 char *mem_name; 93 uint64_t mem_reg_property[2]; 94 int off; 95 96 mem_reg_property[0] = cpu_to_be64(start); 97 mem_reg_property[1] = cpu_to_be64(size); 98 99 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 100 off = fdt_add_subnode(fdt, 0, mem_name); 101 g_free(mem_name); 102 103 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 104 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 105 sizeof(mem_reg_property)))); 106 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 107 } 108 109 static int get_cpus_node(void *fdt) 110 { 111 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 112 113 if (cpus_offset < 0) { 114 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 115 if (cpus_offset) { 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 117 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 118 } 119 } 120 _FDT(cpus_offset); 121 return cpus_offset; 122 } 123 124 /* 125 * The PowerNV cores (and threads) need to use real HW ids and not an 126 * incremental index like it has been done on other platforms. This HW 127 * id is stored in the CPU PIR, it is used to create cpu nodes in the 128 * device tree, used in XSCOM to address cores and in interrupt 129 * servers. 130 */ 131 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 132 { 133 PowerPCCPU *cpu = pc->threads[0]; 134 CPUState *cs = CPU(cpu); 135 DeviceClass *dc = DEVICE_GET_CLASS(cs); 136 int smt_threads = CPU_CORE(pc)->nr_threads; 137 CPUPPCState *env = &cpu->env; 138 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 139 uint32_t servers_prop[smt_threads]; 140 int i; 141 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 142 0xffffffff, 0xffffffff}; 143 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 144 uint32_t cpufreq = 1000000000; 145 uint32_t page_sizes_prop[64]; 146 size_t page_sizes_prop_size; 147 const uint8_t pa_features[] = { 24, 0, 148 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 149 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 150 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 151 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 152 int offset; 153 char *nodename; 154 int cpus_offset = get_cpus_node(fdt); 155 156 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 157 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 158 _FDT(offset); 159 g_free(nodename); 160 161 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 165 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 166 167 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 168 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 169 env->dcache_line_size))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 173 env->icache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 175 env->icache_line_size))); 176 177 if (pcc->l1_dcache_size) { 178 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 179 pcc->l1_dcache_size))); 180 } else { 181 warn_report("Unknown L1 dcache size for cpu"); 182 } 183 if (pcc->l1_icache_size) { 184 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 185 pcc->l1_icache_size))); 186 } else { 187 warn_report("Unknown L1 icache size for cpu"); 188 } 189 190 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 192 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 193 cpu->hash64_opts->slb_size))); 194 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 195 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 196 197 if (env->spr_cb[SPR_PURR].oea_read) { 198 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 199 } 200 201 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 202 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 203 segs, sizeof(segs)))); 204 } 205 206 /* 207 * Advertise VMX/VSX (vector extensions) if available 208 * 0 / no property == no vector extensions 209 * 1 == VMX / Altivec available 210 * 2 == VSX available 211 */ 212 if (env->insns_flags & PPC_ALTIVEC) { 213 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 214 215 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 216 } 217 218 /* 219 * Advertise DFP (Decimal Floating Point) if available 220 * 0 / no property == no DFP 221 * 1 == DFP available 222 */ 223 if (env->insns_flags2 & PPC2_DFP) { 224 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 225 } 226 227 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 228 sizeof(page_sizes_prop)); 229 if (page_sizes_prop_size) { 230 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 231 page_sizes_prop, page_sizes_prop_size))); 232 } 233 234 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 235 pa_features, sizeof(pa_features)))); 236 237 /* Build interrupt servers properties */ 238 for (i = 0; i < smt_threads; i++) { 239 servers_prop[i] = cpu_to_be32(pc->pir + i); 240 } 241 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 242 servers_prop, sizeof(servers_prop)))); 243 } 244 245 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 246 uint32_t nr_threads) 247 { 248 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 249 char *name; 250 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 251 uint32_t irange[2], i, rsize; 252 uint64_t *reg; 253 int offset; 254 255 irange[0] = cpu_to_be32(pir); 256 irange[1] = cpu_to_be32(nr_threads); 257 258 rsize = sizeof(uint64_t) * 2 * nr_threads; 259 reg = g_malloc(rsize); 260 for (i = 0; i < nr_threads; i++) { 261 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 262 reg[i * 2 + 1] = cpu_to_be64(0x1000); 263 } 264 265 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 266 offset = fdt_add_subnode(fdt, 0, name); 267 _FDT(offset); 268 g_free(name); 269 270 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 271 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 272 _FDT((fdt_setprop_string(fdt, offset, "device_type", 273 "PowerPC-External-Interrupt-Presentation"))); 274 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 275 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 276 irange, sizeof(irange)))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 278 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 279 g_free(reg); 280 } 281 282 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 283 { 284 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 285 int i; 286 287 pnv_dt_xscom(chip, fdt, 0, 288 cpu_to_be64(PNV_XSCOM_BASE(chip)), 289 cpu_to_be64(PNV_XSCOM_SIZE), 290 compat, sizeof(compat)); 291 292 for (i = 0; i < chip->nr_cores; i++) { 293 PnvCore *pnv_core = chip->cores[i]; 294 295 pnv_dt_core(chip, pnv_core, fdt); 296 297 /* Interrupt Control Presenters (ICP). One per core. */ 298 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 299 } 300 301 if (chip->ram_size) { 302 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 303 } 304 } 305 306 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 307 { 308 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 309 int i; 310 311 pnv_dt_xscom(chip, fdt, 0, 312 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 313 cpu_to_be64(PNV9_XSCOM_SIZE), 314 compat, sizeof(compat)); 315 316 for (i = 0; i < chip->nr_cores; i++) { 317 PnvCore *pnv_core = chip->cores[i]; 318 319 pnv_dt_core(chip, pnv_core, fdt); 320 } 321 322 if (chip->ram_size) { 323 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 324 } 325 326 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 327 } 328 329 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 330 { 331 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 332 int i; 333 334 pnv_dt_xscom(chip, fdt, 0, 335 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 336 cpu_to_be64(PNV10_XSCOM_SIZE), 337 compat, sizeof(compat)); 338 339 for (i = 0; i < chip->nr_cores; i++) { 340 PnvCore *pnv_core = chip->cores[i]; 341 342 pnv_dt_core(chip, pnv_core, fdt); 343 } 344 345 if (chip->ram_size) { 346 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 347 } 348 349 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 350 } 351 352 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 353 { 354 uint32_t io_base = d->ioport_id; 355 uint32_t io_regs[] = { 356 cpu_to_be32(1), 357 cpu_to_be32(io_base), 358 cpu_to_be32(2) 359 }; 360 char *name; 361 int node; 362 363 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 364 node = fdt_add_subnode(fdt, lpc_off, name); 365 _FDT(node); 366 g_free(name); 367 368 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 369 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 370 } 371 372 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 373 { 374 const char compatible[] = "ns16550\0pnpPNP,501"; 375 uint32_t io_base = d->ioport_id; 376 uint32_t io_regs[] = { 377 cpu_to_be32(1), 378 cpu_to_be32(io_base), 379 cpu_to_be32(8) 380 }; 381 char *name; 382 int node; 383 384 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 385 node = fdt_add_subnode(fdt, lpc_off, name); 386 _FDT(node); 387 g_free(name); 388 389 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 390 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 391 sizeof(compatible)))); 392 393 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 394 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 395 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 396 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 397 fdt_get_phandle(fdt, lpc_off)))); 398 399 /* This is needed by Linux */ 400 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 401 } 402 403 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 404 { 405 const char compatible[] = "bt\0ipmi-bt"; 406 uint32_t io_base; 407 uint32_t io_regs[] = { 408 cpu_to_be32(1), 409 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 410 cpu_to_be32(3) 411 }; 412 uint32_t irq; 413 char *name; 414 int node; 415 416 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 417 io_regs[1] = cpu_to_be32(io_base); 418 419 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 420 421 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 422 node = fdt_add_subnode(fdt, lpc_off, name); 423 _FDT(node); 424 g_free(name); 425 426 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 427 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 428 sizeof(compatible)))); 429 430 /* Mark it as reserved to avoid Linux trying to claim it */ 431 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 432 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 433 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 434 fdt_get_phandle(fdt, lpc_off)))); 435 } 436 437 typedef struct ForeachPopulateArgs { 438 void *fdt; 439 int offset; 440 } ForeachPopulateArgs; 441 442 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 443 { 444 ForeachPopulateArgs *args = opaque; 445 ISADevice *d = ISA_DEVICE(dev); 446 447 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 448 pnv_dt_rtc(d, args->fdt, args->offset); 449 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 450 pnv_dt_serial(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 452 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 453 } else { 454 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 455 d->ioport_id); 456 } 457 458 return 0; 459 } 460 461 /* 462 * The default LPC bus of a multichip system is on chip 0. It's 463 * recognized by the firmware (skiboot) using a "primary" property. 464 */ 465 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 466 { 467 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 468 ForeachPopulateArgs args = { 469 .fdt = fdt, 470 .offset = isa_offset, 471 }; 472 uint32_t phandle; 473 474 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 475 476 phandle = qemu_fdt_alloc_phandle(fdt); 477 assert(phandle > 0); 478 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 479 480 /* 481 * ISA devices are not necessarily parented to the ISA bus so we 482 * can not use object_child_foreach() 483 */ 484 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 485 &args); 486 } 487 488 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 489 { 490 int off; 491 492 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 493 off = fdt_add_subnode(fdt, off, "power-mgt"); 494 495 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 496 } 497 498 static void *pnv_dt_create(MachineState *machine) 499 { 500 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 501 PnvMachineState *pnv = PNV_MACHINE(machine); 502 void *fdt; 503 char *buf; 504 int off; 505 int i; 506 507 fdt = g_malloc0(FDT_MAX_SIZE); 508 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 509 510 /* /qemu node */ 511 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 512 513 /* Root node */ 514 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 515 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 516 _FDT((fdt_setprop_string(fdt, 0, "model", 517 "IBM PowerNV (emulated by qemu)"))); 518 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 519 520 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 521 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 522 if (qemu_uuid_set) { 523 _FDT((fdt_property_string(fdt, "system-id", buf))); 524 } 525 g_free(buf); 526 527 off = fdt_add_subnode(fdt, 0, "chosen"); 528 if (machine->kernel_cmdline) { 529 _FDT((fdt_setprop_string(fdt, off, "bootargs", 530 machine->kernel_cmdline))); 531 } 532 533 if (pnv->initrd_size) { 534 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 535 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 536 537 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 538 &start_prop, sizeof(start_prop)))); 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 540 &end_prop, sizeof(end_prop)))); 541 } 542 543 /* Populate device tree for each chip */ 544 for (i = 0; i < pnv->num_chips; i++) { 545 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 546 } 547 548 /* Populate ISA devices on chip 0 */ 549 pnv_dt_isa(pnv, fdt); 550 551 if (pnv->bmc) { 552 pnv_dt_bmc_sensors(pnv->bmc, fdt); 553 } 554 555 /* Create an extra node for power management on machines that support it */ 556 if (pmc->dt_power_mgt) { 557 pmc->dt_power_mgt(pnv, fdt); 558 } 559 560 return fdt; 561 } 562 563 static void pnv_powerdown_notify(Notifier *n, void *opaque) 564 { 565 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 566 567 if (pnv->bmc) { 568 pnv_bmc_powerdown(pnv->bmc); 569 } 570 } 571 572 static void pnv_reset(MachineState *machine) 573 { 574 PnvMachineState *pnv = PNV_MACHINE(machine); 575 IPMIBmc *bmc; 576 void *fdt; 577 578 qemu_devices_reset(); 579 580 /* 581 * The machine should provide by default an internal BMC simulator. 582 * If not, try to use the BMC device that was provided on the command 583 * line. 584 */ 585 bmc = pnv_bmc_find(&error_fatal); 586 if (!pnv->bmc) { 587 if (!bmc) { 588 warn_report("machine has no BMC device. Use '-device " 589 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 590 "to define one"); 591 } else { 592 pnv_bmc_set_pnor(bmc, pnv->pnor); 593 pnv->bmc = bmc; 594 } 595 } 596 597 fdt = pnv_dt_create(machine); 598 599 /* Pack resulting tree */ 600 _FDT((fdt_pack(fdt))); 601 602 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 603 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 604 605 g_free(fdt); 606 } 607 608 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 609 { 610 Pnv8Chip *chip8 = PNV8_CHIP(chip); 611 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 612 } 613 614 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 615 { 616 Pnv8Chip *chip8 = PNV8_CHIP(chip); 617 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 618 } 619 620 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 621 { 622 Pnv9Chip *chip9 = PNV9_CHIP(chip); 623 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 624 } 625 626 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 627 { 628 Pnv10Chip *chip10 = PNV10_CHIP(chip); 629 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 630 } 631 632 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 633 { 634 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 635 } 636 637 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 638 { 639 Pnv8Chip *chip8 = PNV8_CHIP(chip); 640 int i; 641 642 ics_pic_print_info(&chip8->psi.ics, mon); 643 for (i = 0; i < chip->num_phbs; i++) { 644 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 645 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 646 } 647 } 648 649 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 650 { 651 Pnv9Chip *chip9 = PNV9_CHIP(chip); 652 int i, j; 653 654 pnv_xive_pic_print_info(&chip9->xive, mon); 655 pnv_psi_pic_print_info(&chip9->psi, mon); 656 657 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 658 PnvPhb4PecState *pec = &chip9->pecs[i]; 659 for (j = 0; j < pec->num_stacks; j++) { 660 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 661 } 662 } 663 } 664 665 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 666 uint32_t core_id) 667 { 668 return PNV_XSCOM_EX_BASE(core_id); 669 } 670 671 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 672 uint32_t core_id) 673 { 674 return PNV9_XSCOM_EC_BASE(core_id); 675 } 676 677 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 678 uint32_t core_id) 679 { 680 return PNV10_XSCOM_EC_BASE(core_id); 681 } 682 683 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 684 { 685 PowerPCCPUClass *ppc_default = 686 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 687 PowerPCCPUClass *ppc = 688 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 689 690 return ppc_default->pvr_match(ppc_default, ppc->pvr); 691 } 692 693 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 694 { 695 Object *obj; 696 697 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 698 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 699 object_property_set_int(obj, irq, "irq", &error_fatal); 700 object_property_set_bool(obj, true, "realized", &error_fatal); 701 } 702 703 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 704 { 705 Pnv10Chip *chip10 = PNV10_CHIP(chip); 706 707 pnv_psi_pic_print_info(&chip10->psi, mon); 708 } 709 710 static void pnv_init(MachineState *machine) 711 { 712 PnvMachineState *pnv = PNV_MACHINE(machine); 713 MachineClass *mc = MACHINE_GET_CLASS(machine); 714 char *fw_filename; 715 long fw_size; 716 int i; 717 char *chip_typename; 718 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 719 DeviceState *dev; 720 721 /* allocate RAM */ 722 if (machine->ram_size < (1 * GiB)) { 723 warn_report("skiboot may not work with < 1GB of RAM"); 724 } 725 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 726 727 /* 728 * Create our simple PNOR device 729 */ 730 dev = qdev_create(NULL, TYPE_PNV_PNOR); 731 if (pnor) { 732 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 733 &error_abort); 734 } 735 qdev_init_nofail(dev); 736 pnv->pnor = PNV_PNOR(dev); 737 738 /* load skiboot firmware */ 739 if (bios_name == NULL) { 740 bios_name = FW_FILE_NAME; 741 } 742 743 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 744 if (!fw_filename) { 745 error_report("Could not find OPAL firmware '%s'", bios_name); 746 exit(1); 747 } 748 749 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 750 if (fw_size < 0) { 751 error_report("Could not load OPAL firmware '%s'", fw_filename); 752 exit(1); 753 } 754 g_free(fw_filename); 755 756 /* load kernel */ 757 if (machine->kernel_filename) { 758 long kernel_size; 759 760 kernel_size = load_image_targphys(machine->kernel_filename, 761 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 762 if (kernel_size < 0) { 763 error_report("Could not load kernel '%s'", 764 machine->kernel_filename); 765 exit(1); 766 } 767 } 768 769 /* load initrd */ 770 if (machine->initrd_filename) { 771 pnv->initrd_base = INITRD_LOAD_ADDR; 772 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 773 pnv->initrd_base, INITRD_MAX_SIZE); 774 if (pnv->initrd_size < 0) { 775 error_report("Could not load initial ram disk '%s'", 776 machine->initrd_filename); 777 exit(1); 778 } 779 } 780 781 /* MSIs are supported on this platform */ 782 msi_nonbroken = true; 783 784 /* 785 * Check compatibility of the specified CPU with the machine 786 * default. 787 */ 788 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 789 error_report("invalid CPU model '%s' for %s machine", 790 machine->cpu_type, mc->name); 791 exit(1); 792 } 793 794 /* Create the processor chips */ 795 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 796 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 797 i, machine->cpu_type); 798 if (!object_class_by_name(chip_typename)) { 799 error_report("invalid chip model '%.*s' for %s machine", 800 i, machine->cpu_type, mc->name); 801 exit(1); 802 } 803 804 pnv->num_chips = 805 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 806 /* 807 * TODO: should we decide on how many chips we can create based 808 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 809 */ 810 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 811 error_report("invalid number of chips: '%d'", pnv->num_chips); 812 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 813 exit(1); 814 } 815 816 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 817 for (i = 0; i < pnv->num_chips; i++) { 818 char chip_name[32]; 819 Object *chip = object_new(chip_typename); 820 821 pnv->chips[i] = PNV_CHIP(chip); 822 823 /* 824 * TODO: put all the memory in one node on chip 0 until we find a 825 * way to specify different ranges for each chip 826 */ 827 if (i == 0) { 828 object_property_set_int(chip, machine->ram_size, "ram-size", 829 &error_fatal); 830 } 831 832 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 833 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 834 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 835 &error_fatal); 836 object_property_set_int(chip, machine->smp.cores, 837 "nr-cores", &error_fatal); 838 object_property_set_int(chip, machine->smp.threads, 839 "nr-threads", &error_fatal); 840 /* 841 * The POWER8 machine use the XICS interrupt interface. 842 * Propagate the XICS fabric to the chip and its controllers. 843 */ 844 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 845 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); 846 } 847 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 848 object_property_set_link(chip, OBJECT(pnv), "xive-fabric", 849 &error_abort); 850 } 851 object_property_set_bool(chip, true, "realized", &error_fatal); 852 } 853 g_free(chip_typename); 854 855 /* Instantiate ISA bus on chip 0 */ 856 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 857 858 /* Create serial port */ 859 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 860 861 /* Create an RTC ISA device too */ 862 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 863 864 /* 865 * Create the machine BMC simulator and the IPMI BT device for 866 * communication with the BMC 867 */ 868 if (defaults_enabled()) { 869 pnv->bmc = pnv_bmc_create(pnv->pnor); 870 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 871 } 872 873 /* 874 * OpenPOWER systems use a IPMI SEL Event message to notify the 875 * host to powerdown 876 */ 877 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 878 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 879 } 880 881 /* 882 * 0:21 Reserved - Read as zeros 883 * 22:24 Chip ID 884 * 25:28 Core number 885 * 29:31 Thread ID 886 */ 887 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 888 { 889 return (chip->chip_id << 7) | (core_id << 3); 890 } 891 892 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 893 Error **errp) 894 { 895 Pnv8Chip *chip8 = PNV8_CHIP(chip); 896 Error *local_err = NULL; 897 Object *obj; 898 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 899 900 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 901 if (local_err) { 902 error_propagate(errp, local_err); 903 return; 904 } 905 906 pnv_cpu->intc = obj; 907 } 908 909 910 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 911 { 912 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 913 914 icp_reset(ICP(pnv_cpu->intc)); 915 } 916 917 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 918 { 919 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 920 921 icp_destroy(ICP(pnv_cpu->intc)); 922 pnv_cpu->intc = NULL; 923 } 924 925 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 926 Monitor *mon) 927 { 928 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 929 } 930 931 /* 932 * 0:48 Reserved - Read as zeroes 933 * 49:52 Node ID 934 * 53:55 Chip ID 935 * 56 Reserved - Read as zero 936 * 57:61 Core number 937 * 62:63 Thread ID 938 * 939 * We only care about the lower bits. uint32_t is fine for the moment. 940 */ 941 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 942 { 943 return (chip->chip_id << 8) | (core_id << 2); 944 } 945 946 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 947 { 948 return (chip->chip_id << 8) | (core_id << 2); 949 } 950 951 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 952 Error **errp) 953 { 954 Pnv9Chip *chip9 = PNV9_CHIP(chip); 955 Error *local_err = NULL; 956 Object *obj; 957 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 958 959 /* 960 * The core creates its interrupt presenter but the XIVE interrupt 961 * controller object is initialized afterwards. Hopefully, it's 962 * only used at runtime. 963 */ 964 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 965 &local_err); 966 if (local_err) { 967 error_propagate(errp, local_err); 968 return; 969 } 970 971 pnv_cpu->intc = obj; 972 } 973 974 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 975 { 976 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 977 978 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 979 } 980 981 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 982 { 983 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 984 985 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 986 pnv_cpu->intc = NULL; 987 } 988 989 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 990 Monitor *mon) 991 { 992 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 993 } 994 995 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 996 Error **errp) 997 { 998 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 999 1000 /* Will be defined when the interrupt controller is */ 1001 pnv_cpu->intc = NULL; 1002 } 1003 1004 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1005 { 1006 ; 1007 } 1008 1009 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1010 { 1011 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1012 1013 pnv_cpu->intc = NULL; 1014 } 1015 1016 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1017 Monitor *mon) 1018 { 1019 } 1020 1021 /* 1022 * Allowed core identifiers on a POWER8 Processor Chip : 1023 * 1024 * <EX0 reserved> 1025 * EX1 - Venice only 1026 * EX2 - Venice only 1027 * EX3 - Venice only 1028 * EX4 1029 * EX5 1030 * EX6 1031 * <EX7,8 reserved> <reserved> 1032 * EX9 - Venice only 1033 * EX10 - Venice only 1034 * EX11 - Venice only 1035 * EX12 1036 * EX13 1037 * EX14 1038 * <EX15 reserved> 1039 */ 1040 #define POWER8E_CORE_MASK (0x7070ull) 1041 #define POWER8_CORE_MASK (0x7e7eull) 1042 1043 /* 1044 * POWER9 has 24 cores, ids starting at 0x0 1045 */ 1046 #define POWER9_CORE_MASK (0xffffffffffffffull) 1047 1048 1049 #define POWER10_CORE_MASK (0xffffffffffffffull) 1050 1051 static void pnv_chip_power8_instance_init(Object *obj) 1052 { 1053 PnvChip *chip = PNV_CHIP(obj); 1054 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1055 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1056 int i; 1057 1058 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1059 (Object **)&chip8->xics, 1060 object_property_allow_set_link, 1061 OBJ_PROP_LINK_STRONG, 1062 &error_abort); 1063 1064 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 1065 TYPE_PNV8_PSI, &error_abort, NULL); 1066 1067 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 1068 TYPE_PNV8_LPC, &error_abort, NULL); 1069 1070 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 1071 TYPE_PNV8_OCC, &error_abort, NULL); 1072 1073 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 1074 TYPE_PNV8_HOMER, &error_abort, NULL); 1075 1076 for (i = 0; i < pcc->num_phbs; i++) { 1077 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], 1078 sizeof(chip8->phbs[i]), TYPE_PNV_PHB3, 1079 &error_abort, NULL); 1080 } 1081 1082 /* 1083 * Number of PHBs is the chip default 1084 */ 1085 chip->num_phbs = pcc->num_phbs; 1086 } 1087 1088 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1089 { 1090 PnvChip *chip = PNV_CHIP(chip8); 1091 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1092 int i, j; 1093 char *name; 1094 1095 name = g_strdup_printf("icp-%x", chip->chip_id); 1096 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1097 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1098 g_free(name); 1099 1100 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1101 1102 /* Map the ICP registers for each thread */ 1103 for (i = 0; i < chip->nr_cores; i++) { 1104 PnvCore *pnv_core = chip->cores[i]; 1105 int core_hwid = CPU_CORE(pnv_core)->core_id; 1106 1107 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1108 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1109 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1110 1111 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1112 &icp->mmio); 1113 } 1114 } 1115 } 1116 1117 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1118 { 1119 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1120 PnvChip *chip = PNV_CHIP(dev); 1121 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1122 Pnv8Psi *psi8 = &chip8->psi; 1123 Error *local_err = NULL; 1124 int i; 1125 1126 assert(chip8->xics); 1127 1128 /* XSCOM bridge is first */ 1129 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1130 if (local_err) { 1131 error_propagate(errp, local_err); 1132 return; 1133 } 1134 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1135 1136 pcc->parent_realize(dev, &local_err); 1137 if (local_err) { 1138 error_propagate(errp, local_err); 1139 return; 1140 } 1141 1142 /* Processor Service Interface (PSI) Host Bridge */ 1143 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1144 "bar", &error_fatal); 1145 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), 1146 ICS_PROP_XICS, &error_abort); 1147 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 1148 if (local_err) { 1149 error_propagate(errp, local_err); 1150 return; 1151 } 1152 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1153 &PNV_PSI(psi8)->xscom_regs); 1154 1155 /* Create LPC controller */ 1156 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1157 &error_abort); 1158 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 1159 &error_fatal); 1160 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1161 1162 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1163 (uint64_t) PNV_XSCOM_BASE(chip), 1164 PNV_XSCOM_LPC_BASE); 1165 1166 /* 1167 * Interrupt Management Area. This is the memory region holding 1168 * all the Interrupt Control Presenter (ICP) registers 1169 */ 1170 pnv_chip_icp_realize(chip8, &local_err); 1171 if (local_err) { 1172 error_propagate(errp, local_err); 1173 return; 1174 } 1175 1176 /* Create the simplified OCC model */ 1177 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1178 &error_abort); 1179 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1180 if (local_err) { 1181 error_propagate(errp, local_err); 1182 return; 1183 } 1184 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1185 1186 /* OCC SRAM model */ 1187 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1188 &chip8->occ.sram_regs); 1189 1190 /* HOMER */ 1191 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1192 &error_abort); 1193 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1194 &local_err); 1195 if (local_err) { 1196 error_propagate(errp, local_err); 1197 return; 1198 } 1199 /* Homer Xscom region */ 1200 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1201 1202 /* Homer mmio region */ 1203 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1204 &chip8->homer.regs); 1205 1206 /* PHB3 controllers */ 1207 for (i = 0; i < chip->num_phbs; i++) { 1208 PnvPHB3 *phb = &chip8->phbs[i]; 1209 PnvPBCQState *pbcq = &phb->pbcq; 1210 1211 object_property_set_int(OBJECT(phb), i, "index", &error_fatal); 1212 object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id", 1213 &error_fatal); 1214 object_property_set_bool(OBJECT(phb), true, "realized", &local_err); 1215 if (local_err) { 1216 error_propagate(errp, local_err); 1217 return; 1218 } 1219 qdev_set_parent_bus(DEVICE(phb), sysbus_get_default()); 1220 1221 /* Populate the XSCOM address space. */ 1222 pnv_xscom_add_subregion(chip, 1223 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1224 &pbcq->xscom_nest_regs); 1225 pnv_xscom_add_subregion(chip, 1226 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1227 &pbcq->xscom_pci_regs); 1228 pnv_xscom_add_subregion(chip, 1229 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1230 &pbcq->xscom_spci_regs); 1231 } 1232 } 1233 1234 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1235 { 1236 addr &= (PNV_XSCOM_SIZE - 1); 1237 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1238 } 1239 1240 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1241 { 1242 DeviceClass *dc = DEVICE_CLASS(klass); 1243 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1244 1245 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1246 k->cores_mask = POWER8E_CORE_MASK; 1247 k->num_phbs = 3; 1248 k->core_pir = pnv_chip_core_pir_p8; 1249 k->intc_create = pnv_chip_power8_intc_create; 1250 k->intc_reset = pnv_chip_power8_intc_reset; 1251 k->intc_destroy = pnv_chip_power8_intc_destroy; 1252 k->intc_print_info = pnv_chip_power8_intc_print_info; 1253 k->isa_create = pnv_chip_power8_isa_create; 1254 k->dt_populate = pnv_chip_power8_dt_populate; 1255 k->pic_print_info = pnv_chip_power8_pic_print_info; 1256 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1257 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1258 dc->desc = "PowerNV Chip POWER8E"; 1259 1260 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1261 &k->parent_realize); 1262 } 1263 1264 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1265 { 1266 DeviceClass *dc = DEVICE_CLASS(klass); 1267 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1268 1269 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1270 k->cores_mask = POWER8_CORE_MASK; 1271 k->num_phbs = 3; 1272 k->core_pir = pnv_chip_core_pir_p8; 1273 k->intc_create = pnv_chip_power8_intc_create; 1274 k->intc_reset = pnv_chip_power8_intc_reset; 1275 k->intc_destroy = pnv_chip_power8_intc_destroy; 1276 k->intc_print_info = pnv_chip_power8_intc_print_info; 1277 k->isa_create = pnv_chip_power8_isa_create; 1278 k->dt_populate = pnv_chip_power8_dt_populate; 1279 k->pic_print_info = pnv_chip_power8_pic_print_info; 1280 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1281 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1282 dc->desc = "PowerNV Chip POWER8"; 1283 1284 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1285 &k->parent_realize); 1286 } 1287 1288 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1289 { 1290 DeviceClass *dc = DEVICE_CLASS(klass); 1291 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1292 1293 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1294 k->cores_mask = POWER8_CORE_MASK; 1295 k->num_phbs = 3; 1296 k->core_pir = pnv_chip_core_pir_p8; 1297 k->intc_create = pnv_chip_power8_intc_create; 1298 k->intc_reset = pnv_chip_power8_intc_reset; 1299 k->intc_destroy = pnv_chip_power8_intc_destroy; 1300 k->intc_print_info = pnv_chip_power8_intc_print_info; 1301 k->isa_create = pnv_chip_power8nvl_isa_create; 1302 k->dt_populate = pnv_chip_power8_dt_populate; 1303 k->pic_print_info = pnv_chip_power8_pic_print_info; 1304 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1305 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1306 dc->desc = "PowerNV Chip POWER8NVL"; 1307 1308 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1309 &k->parent_realize); 1310 } 1311 1312 static void pnv_chip_power9_instance_init(Object *obj) 1313 { 1314 PnvChip *chip = PNV_CHIP(obj); 1315 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1316 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1317 int i; 1318 1319 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1320 TYPE_PNV_XIVE, &error_abort, NULL); 1321 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1322 "xive-fabric", &error_abort); 1323 1324 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1325 TYPE_PNV9_PSI, &error_abort, NULL); 1326 1327 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1328 TYPE_PNV9_LPC, &error_abort, NULL); 1329 1330 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1331 TYPE_PNV9_OCC, &error_abort, NULL); 1332 1333 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1334 TYPE_PNV9_HOMER, &error_abort, NULL); 1335 1336 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1337 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1338 sizeof(chip9->pecs[i]), TYPE_PNV_PHB4_PEC, 1339 &error_abort, NULL); 1340 } 1341 1342 /* 1343 * Number of PHBs is the chip default 1344 */ 1345 chip->num_phbs = pcc->num_phbs; 1346 } 1347 1348 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1349 { 1350 PnvChip *chip = PNV_CHIP(chip9); 1351 int i; 1352 1353 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1354 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1355 1356 for (i = 0; i < chip9->nr_quads; i++) { 1357 char eq_name[32]; 1358 PnvQuad *eq = &chip9->quads[i]; 1359 PnvCore *pnv_core = chip->cores[i * 4]; 1360 int core_id = CPU_CORE(pnv_core)->core_id; 1361 1362 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1363 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1364 TYPE_PNV_QUAD, &error_fatal, NULL); 1365 1366 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1367 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1368 1369 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1370 &eq->xscom_regs); 1371 } 1372 } 1373 1374 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1375 { 1376 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1377 Error *local_err = NULL; 1378 int i, j; 1379 int phb_id = 0; 1380 1381 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1382 PnvPhb4PecState *pec = &chip9->pecs[i]; 1383 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1384 uint32_t pec_nest_base; 1385 uint32_t pec_pci_base; 1386 1387 object_property_set_int(OBJECT(pec), i, "index", &error_fatal); 1388 /* 1389 * PEC0 -> 1 stack 1390 * PEC1 -> 2 stacks 1391 * PEC2 -> 3 stacks 1392 */ 1393 object_property_set_int(OBJECT(pec), i + 1, "num-stacks", 1394 &error_fatal); 1395 object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id", 1396 &error_fatal); 1397 object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()), 1398 "system-memory", &error_abort); 1399 object_property_set_bool(OBJECT(pec), true, "realized", &local_err); 1400 if (local_err) { 1401 error_propagate(errp, local_err); 1402 return; 1403 } 1404 1405 pec_nest_base = pecc->xscom_nest_base(pec); 1406 pec_pci_base = pecc->xscom_pci_base(pec); 1407 1408 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1409 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1410 1411 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1412 j++, phb_id++) { 1413 PnvPhb4PecStack *stack = &pec->stacks[j]; 1414 Object *obj = OBJECT(&stack->phb); 1415 1416 object_property_set_int(obj, phb_id, "index", &error_fatal); 1417 object_property_set_int(obj, chip->chip_id, "chip-id", 1418 &error_fatal); 1419 object_property_set_int(obj, PNV_PHB4_VERSION, "version", 1420 &error_fatal); 1421 object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id", 1422 &error_fatal); 1423 object_property_set_link(obj, OBJECT(stack), "stack", &error_abort); 1424 object_property_set_bool(obj, true, "realized", &local_err); 1425 if (local_err) { 1426 error_propagate(errp, local_err); 1427 return; 1428 } 1429 qdev_set_parent_bus(DEVICE(obj), sysbus_get_default()); 1430 1431 /* Populate the XSCOM address space. */ 1432 pnv_xscom_add_subregion(chip, 1433 pec_nest_base + 0x40 * (stack->stack_no + 1), 1434 &stack->nest_regs_mr); 1435 pnv_xscom_add_subregion(chip, 1436 pec_pci_base + 0x40 * (stack->stack_no + 1), 1437 &stack->pci_regs_mr); 1438 pnv_xscom_add_subregion(chip, 1439 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1440 0x40 * stack->stack_no, 1441 &stack->phb_regs_mr); 1442 } 1443 } 1444 } 1445 1446 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1447 { 1448 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1449 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1450 PnvChip *chip = PNV_CHIP(dev); 1451 Pnv9Psi *psi9 = &chip9->psi; 1452 Error *local_err = NULL; 1453 1454 /* XSCOM bridge is first */ 1455 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1456 if (local_err) { 1457 error_propagate(errp, local_err); 1458 return; 1459 } 1460 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1461 1462 pcc->parent_realize(dev, &local_err); 1463 if (local_err) { 1464 error_propagate(errp, local_err); 1465 return; 1466 } 1467 1468 pnv_chip_quad_realize(chip9, &local_err); 1469 if (local_err) { 1470 error_propagate(errp, local_err); 1471 return; 1472 } 1473 1474 /* XIVE interrupt controller (POWER9) */ 1475 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1476 "ic-bar", &error_fatal); 1477 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1478 "vc-bar", &error_fatal); 1479 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1480 "pc-bar", &error_fatal); 1481 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1482 "tm-bar", &error_fatal); 1483 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1484 &error_abort); 1485 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1486 &local_err); 1487 if (local_err) { 1488 error_propagate(errp, local_err); 1489 return; 1490 } 1491 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1492 &chip9->xive.xscom_regs); 1493 1494 /* Processor Service Interface (PSI) Host Bridge */ 1495 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1496 "bar", &error_fatal); 1497 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1498 if (local_err) { 1499 error_propagate(errp, local_err); 1500 return; 1501 } 1502 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1503 &PNV_PSI(psi9)->xscom_regs); 1504 1505 /* LPC */ 1506 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1507 &error_abort); 1508 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1509 if (local_err) { 1510 error_propagate(errp, local_err); 1511 return; 1512 } 1513 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1514 &chip9->lpc.xscom_regs); 1515 1516 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1517 (uint64_t) PNV9_LPCM_BASE(chip)); 1518 1519 /* Create the simplified OCC model */ 1520 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1521 &error_abort); 1522 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1523 if (local_err) { 1524 error_propagate(errp, local_err); 1525 return; 1526 } 1527 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1528 1529 /* OCC SRAM model */ 1530 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1531 &chip9->occ.sram_regs); 1532 1533 /* HOMER */ 1534 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1535 &error_abort); 1536 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1537 &local_err); 1538 if (local_err) { 1539 error_propagate(errp, local_err); 1540 return; 1541 } 1542 /* Homer Xscom region */ 1543 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1544 1545 /* Homer mmio region */ 1546 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1547 &chip9->homer.regs); 1548 1549 /* PHBs */ 1550 pnv_chip_power9_phb_realize(chip, &local_err); 1551 if (local_err) { 1552 error_propagate(errp, local_err); 1553 return; 1554 } 1555 } 1556 1557 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1558 { 1559 addr &= (PNV9_XSCOM_SIZE - 1); 1560 return addr >> 3; 1561 } 1562 1563 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1564 { 1565 DeviceClass *dc = DEVICE_CLASS(klass); 1566 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1567 1568 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1569 k->cores_mask = POWER9_CORE_MASK; 1570 k->core_pir = pnv_chip_core_pir_p9; 1571 k->intc_create = pnv_chip_power9_intc_create; 1572 k->intc_reset = pnv_chip_power9_intc_reset; 1573 k->intc_destroy = pnv_chip_power9_intc_destroy; 1574 k->intc_print_info = pnv_chip_power9_intc_print_info; 1575 k->isa_create = pnv_chip_power9_isa_create; 1576 k->dt_populate = pnv_chip_power9_dt_populate; 1577 k->pic_print_info = pnv_chip_power9_pic_print_info; 1578 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1579 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1580 dc->desc = "PowerNV Chip POWER9"; 1581 k->num_phbs = 6; 1582 1583 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1584 &k->parent_realize); 1585 } 1586 1587 static void pnv_chip_power10_instance_init(Object *obj) 1588 { 1589 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1590 1591 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), 1592 TYPE_PNV10_PSI, &error_abort, NULL); 1593 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), 1594 TYPE_PNV10_LPC, &error_abort, NULL); 1595 } 1596 1597 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1598 { 1599 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1600 PnvChip *chip = PNV_CHIP(dev); 1601 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1602 Error *local_err = NULL; 1603 1604 /* XSCOM bridge is first */ 1605 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1606 if (local_err) { 1607 error_propagate(errp, local_err); 1608 return; 1609 } 1610 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1611 1612 pcc->parent_realize(dev, &local_err); 1613 if (local_err) { 1614 error_propagate(errp, local_err); 1615 return; 1616 } 1617 1618 /* Processor Service Interface (PSI) Host Bridge */ 1619 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1620 "bar", &error_fatal); 1621 object_property_set_bool(OBJECT(&chip10->psi), true, "realized", 1622 &local_err); 1623 if (local_err) { 1624 error_propagate(errp, local_err); 1625 return; 1626 } 1627 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1628 &PNV_PSI(&chip10->psi)->xscom_regs); 1629 1630 /* LPC */ 1631 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1632 &error_abort); 1633 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", 1634 &local_err); 1635 if (local_err) { 1636 error_propagate(errp, local_err); 1637 return; 1638 } 1639 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1640 &chip10->lpc.xscom_regs); 1641 1642 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1643 (uint64_t) PNV10_LPCM_BASE(chip)); 1644 } 1645 1646 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1647 { 1648 addr &= (PNV10_XSCOM_SIZE - 1); 1649 return addr >> 3; 1650 } 1651 1652 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1653 { 1654 DeviceClass *dc = DEVICE_CLASS(klass); 1655 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1656 1657 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1658 k->cores_mask = POWER10_CORE_MASK; 1659 k->core_pir = pnv_chip_core_pir_p10; 1660 k->intc_create = pnv_chip_power10_intc_create; 1661 k->intc_reset = pnv_chip_power10_intc_reset; 1662 k->intc_destroy = pnv_chip_power10_intc_destroy; 1663 k->intc_print_info = pnv_chip_power10_intc_print_info; 1664 k->isa_create = pnv_chip_power10_isa_create; 1665 k->dt_populate = pnv_chip_power10_dt_populate; 1666 k->pic_print_info = pnv_chip_power10_pic_print_info; 1667 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1668 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1669 dc->desc = "PowerNV Chip POWER10"; 1670 1671 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1672 &k->parent_realize); 1673 } 1674 1675 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1676 { 1677 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1678 int cores_max; 1679 1680 /* 1681 * No custom mask for this chip, let's use the default one from * 1682 * the chip class 1683 */ 1684 if (!chip->cores_mask) { 1685 chip->cores_mask = pcc->cores_mask; 1686 } 1687 1688 /* filter alien core ids ! some are reserved */ 1689 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1690 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1691 chip->cores_mask); 1692 return; 1693 } 1694 chip->cores_mask &= pcc->cores_mask; 1695 1696 /* now that we have a sane layout, let check the number of cores */ 1697 cores_max = ctpop64(chip->cores_mask); 1698 if (chip->nr_cores > cores_max) { 1699 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1700 cores_max); 1701 return; 1702 } 1703 } 1704 1705 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1706 { 1707 Error *error = NULL; 1708 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1709 const char *typename = pnv_chip_core_typename(chip); 1710 int i, core_hwid; 1711 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1712 1713 if (!object_class_by_name(typename)) { 1714 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1715 return; 1716 } 1717 1718 /* Cores */ 1719 pnv_chip_core_sanitize(chip, &error); 1720 if (error) { 1721 error_propagate(errp, error); 1722 return; 1723 } 1724 1725 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1726 1727 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1728 && (i < chip->nr_cores); core_hwid++) { 1729 char core_name[32]; 1730 PnvCore *pnv_core; 1731 uint64_t xscom_core_base; 1732 1733 if (!(chip->cores_mask & (1ull << core_hwid))) { 1734 continue; 1735 } 1736 1737 pnv_core = PNV_CORE(object_new(typename)); 1738 1739 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1740 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1741 &error_abort); 1742 chip->cores[i] = pnv_core; 1743 object_property_set_int(OBJECT(pnv_core), chip->nr_threads, 1744 "nr-threads", &error_fatal); 1745 object_property_set_int(OBJECT(pnv_core), core_hwid, 1746 CPU_CORE_PROP_CORE_ID, &error_fatal); 1747 object_property_set_int(OBJECT(pnv_core), 1748 pcc->core_pir(chip, core_hwid), 1749 "pir", &error_fatal); 1750 object_property_set_int(OBJECT(pnv_core), pnv->fw_load_addr, 1751 "hrmor", &error_fatal); 1752 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1753 &error_abort); 1754 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1755 &error_fatal); 1756 1757 /* Each core has an XSCOM MMIO region */ 1758 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1759 1760 pnv_xscom_add_subregion(chip, xscom_core_base, 1761 &pnv_core->xscom_regs); 1762 i++; 1763 } 1764 } 1765 1766 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1767 { 1768 PnvChip *chip = PNV_CHIP(dev); 1769 Error *error = NULL; 1770 1771 /* Cores */ 1772 pnv_chip_core_realize(chip, &error); 1773 if (error) { 1774 error_propagate(errp, error); 1775 return; 1776 } 1777 } 1778 1779 static Property pnv_chip_properties[] = { 1780 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1781 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1782 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1783 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1784 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1785 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1786 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1787 DEFINE_PROP_END_OF_LIST(), 1788 }; 1789 1790 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1791 { 1792 DeviceClass *dc = DEVICE_CLASS(klass); 1793 1794 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1795 dc->realize = pnv_chip_realize; 1796 device_class_set_props(dc, pnv_chip_properties); 1797 dc->desc = "PowerNV Chip"; 1798 } 1799 1800 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1801 { 1802 int i, j; 1803 1804 for (i = 0; i < chip->nr_cores; i++) { 1805 PnvCore *pc = chip->cores[i]; 1806 CPUCore *cc = CPU_CORE(pc); 1807 1808 for (j = 0; j < cc->nr_threads; j++) { 1809 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1810 return pc->threads[j]; 1811 } 1812 } 1813 } 1814 return NULL; 1815 } 1816 1817 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1818 { 1819 PnvMachineState *pnv = PNV_MACHINE(xi); 1820 int i, j; 1821 1822 for (i = 0; i < pnv->num_chips; i++) { 1823 PnvChip *chip = pnv->chips[i]; 1824 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1825 1826 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1827 return &chip8->psi.ics; 1828 } 1829 for (j = 0; j < chip->num_phbs; j++) { 1830 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1831 return &chip8->phbs[j].lsis; 1832 } 1833 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1834 return ICS(&chip8->phbs[j].msis); 1835 } 1836 } 1837 } 1838 return NULL; 1839 } 1840 1841 static void pnv_ics_resend(XICSFabric *xi) 1842 { 1843 PnvMachineState *pnv = PNV_MACHINE(xi); 1844 int i, j; 1845 1846 for (i = 0; i < pnv->num_chips; i++) { 1847 PnvChip *chip = pnv->chips[i]; 1848 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1849 1850 ics_resend(&chip8->psi.ics); 1851 for (j = 0; j < chip->num_phbs; j++) { 1852 ics_resend(&chip8->phbs[j].lsis); 1853 ics_resend(ICS(&chip8->phbs[j].msis)); 1854 } 1855 } 1856 } 1857 1858 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1859 { 1860 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1861 1862 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1863 } 1864 1865 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1866 Monitor *mon) 1867 { 1868 PnvMachineState *pnv = PNV_MACHINE(obj); 1869 int i; 1870 CPUState *cs; 1871 1872 CPU_FOREACH(cs) { 1873 PowerPCCPU *cpu = POWERPC_CPU(cs); 1874 1875 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1876 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1877 mon); 1878 } 1879 1880 for (i = 0; i < pnv->num_chips; i++) { 1881 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1882 } 1883 } 1884 1885 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1886 uint8_t nvt_blk, uint32_t nvt_idx, 1887 bool cam_ignore, uint8_t priority, 1888 uint32_t logic_serv, 1889 XiveTCTXMatch *match) 1890 { 1891 PnvMachineState *pnv = PNV_MACHINE(xfb); 1892 int total_count = 0; 1893 int i; 1894 1895 for (i = 0; i < pnv->num_chips; i++) { 1896 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1897 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1898 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1899 int count; 1900 1901 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1902 priority, logic_serv, match); 1903 1904 if (count < 0) { 1905 return count; 1906 } 1907 1908 total_count += count; 1909 } 1910 1911 return total_count; 1912 } 1913 1914 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1915 { 1916 MachineClass *mc = MACHINE_CLASS(oc); 1917 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1918 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1919 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1920 1921 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1922 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1923 1924 xic->icp_get = pnv_icp_get; 1925 xic->ics_get = pnv_ics_get; 1926 xic->ics_resend = pnv_ics_resend; 1927 1928 pmc->compat = compat; 1929 pmc->compat_size = sizeof(compat); 1930 } 1931 1932 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1933 { 1934 MachineClass *mc = MACHINE_CLASS(oc); 1935 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1936 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1937 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1938 1939 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1940 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1941 xfc->match_nvt = pnv_match_nvt; 1942 1943 mc->alias = "powernv"; 1944 1945 pmc->compat = compat; 1946 pmc->compat_size = sizeof(compat); 1947 pmc->dt_power_mgt = pnv_dt_power_mgt; 1948 } 1949 1950 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1951 { 1952 MachineClass *mc = MACHINE_CLASS(oc); 1953 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1954 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1955 1956 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1957 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1958 1959 pmc->compat = compat; 1960 pmc->compat_size = sizeof(compat); 1961 pmc->dt_power_mgt = pnv_dt_power_mgt; 1962 } 1963 1964 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1965 { 1966 PnvMachineState *pnv = PNV_MACHINE(obj); 1967 1968 return !!pnv->fw_load_addr; 1969 } 1970 1971 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1972 { 1973 PnvMachineState *pnv = PNV_MACHINE(obj); 1974 1975 if (value) { 1976 pnv->fw_load_addr = 0x8000000; 1977 } 1978 } 1979 1980 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1981 { 1982 MachineClass *mc = MACHINE_CLASS(oc); 1983 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1984 1985 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1986 mc->init = pnv_init; 1987 mc->reset = pnv_reset; 1988 mc->max_cpus = MAX_CPUS; 1989 /* Pnv provides a AHCI device for storage */ 1990 mc->block_default_type = IF_IDE; 1991 mc->no_parallel = 1; 1992 mc->default_boot_order = NULL; 1993 /* 1994 * RAM defaults to less than 2048 for 32-bit hosts, and large 1995 * enough to fit the maximum initrd size at it's load address 1996 */ 1997 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1998 mc->default_ram_id = "pnv.ram"; 1999 ispc->print_info = pnv_pic_print_info; 2000 2001 object_class_property_add_bool(oc, "hb-mode", 2002 pnv_machine_get_hb, pnv_machine_set_hb, 2003 &error_abort); 2004 object_class_property_set_description(oc, "hb-mode", 2005 "Use a hostboot like boot loader", 2006 NULL); 2007 } 2008 2009 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2010 { \ 2011 .name = type, \ 2012 .class_init = class_initfn, \ 2013 .parent = TYPE_PNV8_CHIP, \ 2014 } 2015 2016 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2017 { \ 2018 .name = type, \ 2019 .class_init = class_initfn, \ 2020 .parent = TYPE_PNV9_CHIP, \ 2021 } 2022 2023 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2024 { \ 2025 .name = type, \ 2026 .class_init = class_initfn, \ 2027 .parent = TYPE_PNV10_CHIP, \ 2028 } 2029 2030 static const TypeInfo types[] = { 2031 { 2032 .name = MACHINE_TYPE_NAME("powernv10"), 2033 .parent = TYPE_PNV_MACHINE, 2034 .class_init = pnv_machine_power10_class_init, 2035 }, 2036 { 2037 .name = MACHINE_TYPE_NAME("powernv9"), 2038 .parent = TYPE_PNV_MACHINE, 2039 .class_init = pnv_machine_power9_class_init, 2040 .interfaces = (InterfaceInfo[]) { 2041 { TYPE_XIVE_FABRIC }, 2042 { }, 2043 }, 2044 }, 2045 { 2046 .name = MACHINE_TYPE_NAME("powernv8"), 2047 .parent = TYPE_PNV_MACHINE, 2048 .class_init = pnv_machine_power8_class_init, 2049 .interfaces = (InterfaceInfo[]) { 2050 { TYPE_XICS_FABRIC }, 2051 { }, 2052 }, 2053 }, 2054 { 2055 .name = TYPE_PNV_MACHINE, 2056 .parent = TYPE_MACHINE, 2057 .abstract = true, 2058 .instance_size = sizeof(PnvMachineState), 2059 .class_init = pnv_machine_class_init, 2060 .class_size = sizeof(PnvMachineClass), 2061 .interfaces = (InterfaceInfo[]) { 2062 { TYPE_INTERRUPT_STATS_PROVIDER }, 2063 { }, 2064 }, 2065 }, 2066 { 2067 .name = TYPE_PNV_CHIP, 2068 .parent = TYPE_SYS_BUS_DEVICE, 2069 .class_init = pnv_chip_class_init, 2070 .instance_size = sizeof(PnvChip), 2071 .class_size = sizeof(PnvChipClass), 2072 .abstract = true, 2073 }, 2074 2075 /* 2076 * P10 chip and variants 2077 */ 2078 { 2079 .name = TYPE_PNV10_CHIP, 2080 .parent = TYPE_PNV_CHIP, 2081 .instance_init = pnv_chip_power10_instance_init, 2082 .instance_size = sizeof(Pnv10Chip), 2083 }, 2084 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2085 2086 /* 2087 * P9 chip and variants 2088 */ 2089 { 2090 .name = TYPE_PNV9_CHIP, 2091 .parent = TYPE_PNV_CHIP, 2092 .instance_init = pnv_chip_power9_instance_init, 2093 .instance_size = sizeof(Pnv9Chip), 2094 }, 2095 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2096 2097 /* 2098 * P8 chip and variants 2099 */ 2100 { 2101 .name = TYPE_PNV8_CHIP, 2102 .parent = TYPE_PNV_CHIP, 2103 .instance_init = pnv_chip_power8_instance_init, 2104 .instance_size = sizeof(Pnv8Chip), 2105 }, 2106 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2107 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2108 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2109 pnv_chip_power8nvl_class_init), 2110 }; 2111 2112 DEFINE_TYPES(types) 2113