1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/qtest.h" 25 #include "sysemu/sysemu.h" 26 #include "sysemu/numa.h" 27 #include "sysemu/reset.h" 28 #include "sysemu/runstate.h" 29 #include "sysemu/cpus.h" 30 #include "sysemu/device_tree.h" 31 #include "sysemu/hw_accel.h" 32 #include "target/ppc/cpu.h" 33 #include "qemu/log.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "exec/address-spaces.h" 41 #include "qapi/visitor.h" 42 #include "monitor/monitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 48 #include "hw/ppc/xics.h" 49 #include "hw/qdev-properties.h" 50 #include "hw/ppc/pnv_xscom.h" 51 #include "hw/ppc/pnv_pnor.h" 52 53 #include "hw/isa/isa.h" 54 #include "hw/boards.h" 55 #include "hw/char/serial.h" 56 #include "hw/rtc/mc146818rtc.h" 57 58 #include <libfdt.h> 59 60 #define FDT_MAX_SIZE (1 * MiB) 61 62 #define FW_FILE_NAME "skiboot.lid" 63 #define FW_LOAD_ADDR 0x0 64 #define FW_MAX_SIZE (16 * MiB) 65 66 #define KERNEL_LOAD_ADDR 0x20000000 67 #define KERNEL_MAX_SIZE (256 * MiB) 68 #define INITRD_LOAD_ADDR 0x60000000 69 #define INITRD_MAX_SIZE (256 * MiB) 70 71 static const char *pnv_chip_core_typename(const PnvChip *o) 72 { 73 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 74 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 75 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 76 const char *core_type = object_class_get_name(object_class_by_name(s)); 77 g_free(s); 78 return core_type; 79 } 80 81 /* 82 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 83 * 4 * 4 sockets * 12 cores * 8 threads = 1536 84 * Let's make it 2^11 85 */ 86 #define MAX_CPUS 2048 87 88 /* 89 * Memory nodes are created by hostboot, one for each range of memory 90 * that has a different "affinity". In practice, it means one range 91 * per chip. 92 */ 93 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 94 { 95 char *mem_name; 96 uint64_t mem_reg_property[2]; 97 int off; 98 99 mem_reg_property[0] = cpu_to_be64(start); 100 mem_reg_property[1] = cpu_to_be64(size); 101 102 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 103 off = fdt_add_subnode(fdt, 0, mem_name); 104 g_free(mem_name); 105 106 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 107 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 108 sizeof(mem_reg_property)))); 109 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 110 } 111 112 static int get_cpus_node(void *fdt) 113 { 114 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 115 116 if (cpus_offset < 0) { 117 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 118 if (cpus_offset) { 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 121 } 122 } 123 _FDT(cpus_offset); 124 return cpus_offset; 125 } 126 127 /* 128 * The PowerNV cores (and threads) need to use real HW ids and not an 129 * incremental index like it has been done on other platforms. This HW 130 * id is stored in the CPU PIR, it is used to create cpu nodes in the 131 * device tree, used in XSCOM to address cores and in interrupt 132 * servers. 133 */ 134 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 135 { 136 PowerPCCPU *cpu = pc->threads[0]; 137 CPUState *cs = CPU(cpu); 138 DeviceClass *dc = DEVICE_GET_CLASS(cs); 139 int smt_threads = CPU_CORE(pc)->nr_threads; 140 CPUPPCState *env = &cpu->env; 141 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 142 uint32_t servers_prop[smt_threads]; 143 int i; 144 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 145 0xffffffff, 0xffffffff}; 146 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 147 uint32_t cpufreq = 1000000000; 148 uint32_t page_sizes_prop[64]; 149 size_t page_sizes_prop_size; 150 const uint8_t pa_features[] = { 24, 0, 151 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 152 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 153 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 154 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 155 int offset; 156 char *nodename; 157 int cpus_offset = get_cpus_node(fdt); 158 159 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 160 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 161 _FDT(offset); 162 g_free(nodename); 163 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 167 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 168 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 169 170 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 172 env->dcache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 176 env->icache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 178 env->icache_line_size))); 179 180 if (pcc->l1_dcache_size) { 181 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 182 pcc->l1_dcache_size))); 183 } else { 184 warn_report("Unknown L1 dcache size for cpu"); 185 } 186 if (pcc->l1_icache_size) { 187 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 188 pcc->l1_icache_size))); 189 } else { 190 warn_report("Unknown L1 icache size for cpu"); 191 } 192 193 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 195 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 196 cpu->hash64_opts->slb_size))); 197 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 198 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 199 200 if (env->spr_cb[SPR_PURR].oea_read) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 202 } 203 204 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 205 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 206 segs, sizeof(segs)))); 207 } 208 209 /* 210 * Advertise VMX/VSX (vector extensions) if available 211 * 0 / no property == no vector extensions 212 * 1 == VMX / Altivec available 213 * 2 == VSX available 214 */ 215 if (env->insns_flags & PPC_ALTIVEC) { 216 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 217 218 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 219 } 220 221 /* 222 * Advertise DFP (Decimal Floating Point) if available 223 * 0 / no property == no DFP 224 * 1 == DFP available 225 */ 226 if (env->insns_flags2 & PPC2_DFP) { 227 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 228 } 229 230 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 231 sizeof(page_sizes_prop)); 232 if (page_sizes_prop_size) { 233 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 234 page_sizes_prop, page_sizes_prop_size))); 235 } 236 237 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 238 pa_features, sizeof(pa_features)))); 239 240 /* Build interrupt servers properties */ 241 for (i = 0; i < smt_threads; i++) { 242 servers_prop[i] = cpu_to_be32(pc->pir + i); 243 } 244 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 245 servers_prop, sizeof(servers_prop)))); 246 } 247 248 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 249 uint32_t nr_threads) 250 { 251 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 252 char *name; 253 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 254 uint32_t irange[2], i, rsize; 255 uint64_t *reg; 256 int offset; 257 258 irange[0] = cpu_to_be32(pir); 259 irange[1] = cpu_to_be32(nr_threads); 260 261 rsize = sizeof(uint64_t) * 2 * nr_threads; 262 reg = g_malloc(rsize); 263 for (i = 0; i < nr_threads; i++) { 264 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 265 reg[i * 2 + 1] = cpu_to_be64(0x1000); 266 } 267 268 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 269 offset = fdt_add_subnode(fdt, 0, name); 270 _FDT(offset); 271 g_free(name); 272 273 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 274 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 275 _FDT((fdt_setprop_string(fdt, offset, "device_type", 276 "PowerPC-External-Interrupt-Presentation"))); 277 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 278 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 279 irange, sizeof(irange)))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 281 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 282 g_free(reg); 283 } 284 285 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 286 { 287 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 288 int i; 289 290 pnv_dt_xscom(chip, fdt, 0, 291 cpu_to_be64(PNV_XSCOM_BASE(chip)), 292 cpu_to_be64(PNV_XSCOM_SIZE), 293 compat, sizeof(compat)); 294 295 for (i = 0; i < chip->nr_cores; i++) { 296 PnvCore *pnv_core = chip->cores[i]; 297 298 pnv_dt_core(chip, pnv_core, fdt); 299 300 /* Interrupt Control Presenters (ICP). One per core. */ 301 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 302 } 303 304 if (chip->ram_size) { 305 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 306 } 307 } 308 309 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 310 { 311 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 312 int i; 313 314 pnv_dt_xscom(chip, fdt, 0, 315 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 316 cpu_to_be64(PNV9_XSCOM_SIZE), 317 compat, sizeof(compat)); 318 319 for (i = 0; i < chip->nr_cores; i++) { 320 PnvCore *pnv_core = chip->cores[i]; 321 322 pnv_dt_core(chip, pnv_core, fdt); 323 } 324 325 if (chip->ram_size) { 326 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 327 } 328 329 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 330 } 331 332 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 333 { 334 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 335 int i; 336 337 pnv_dt_xscom(chip, fdt, 0, 338 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 339 cpu_to_be64(PNV10_XSCOM_SIZE), 340 compat, sizeof(compat)); 341 342 for (i = 0; i < chip->nr_cores; i++) { 343 PnvCore *pnv_core = chip->cores[i]; 344 345 pnv_dt_core(chip, pnv_core, fdt); 346 } 347 348 if (chip->ram_size) { 349 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 350 } 351 352 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 353 } 354 355 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 356 { 357 uint32_t io_base = d->ioport_id; 358 uint32_t io_regs[] = { 359 cpu_to_be32(1), 360 cpu_to_be32(io_base), 361 cpu_to_be32(2) 362 }; 363 char *name; 364 int node; 365 366 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 367 node = fdt_add_subnode(fdt, lpc_off, name); 368 _FDT(node); 369 g_free(name); 370 371 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 372 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 373 } 374 375 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 376 { 377 const char compatible[] = "ns16550\0pnpPNP,501"; 378 uint32_t io_base = d->ioport_id; 379 uint32_t io_regs[] = { 380 cpu_to_be32(1), 381 cpu_to_be32(io_base), 382 cpu_to_be32(8) 383 }; 384 char *name; 385 int node; 386 387 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 388 node = fdt_add_subnode(fdt, lpc_off, name); 389 _FDT(node); 390 g_free(name); 391 392 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 393 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 394 sizeof(compatible)))); 395 396 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 397 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 398 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 399 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 400 fdt_get_phandle(fdt, lpc_off)))); 401 402 /* This is needed by Linux */ 403 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 404 } 405 406 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 407 { 408 const char compatible[] = "bt\0ipmi-bt"; 409 uint32_t io_base; 410 uint32_t io_regs[] = { 411 cpu_to_be32(1), 412 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 413 cpu_to_be32(3) 414 }; 415 uint32_t irq; 416 char *name; 417 int node; 418 419 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 420 io_regs[1] = cpu_to_be32(io_base); 421 422 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 423 424 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 425 node = fdt_add_subnode(fdt, lpc_off, name); 426 _FDT(node); 427 g_free(name); 428 429 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 430 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 431 sizeof(compatible)))); 432 433 /* Mark it as reserved to avoid Linux trying to claim it */ 434 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 435 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 436 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 437 fdt_get_phandle(fdt, lpc_off)))); 438 } 439 440 typedef struct ForeachPopulateArgs { 441 void *fdt; 442 int offset; 443 } ForeachPopulateArgs; 444 445 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 446 { 447 ForeachPopulateArgs *args = opaque; 448 ISADevice *d = ISA_DEVICE(dev); 449 450 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 451 pnv_dt_rtc(d, args->fdt, args->offset); 452 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 453 pnv_dt_serial(d, args->fdt, args->offset); 454 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 455 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 456 } else { 457 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 458 d->ioport_id); 459 } 460 461 return 0; 462 } 463 464 /* 465 * The default LPC bus of a multichip system is on chip 0. It's 466 * recognized by the firmware (skiboot) using a "primary" property. 467 */ 468 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 469 { 470 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 471 ForeachPopulateArgs args = { 472 .fdt = fdt, 473 .offset = isa_offset, 474 }; 475 uint32_t phandle; 476 477 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 478 479 phandle = qemu_fdt_alloc_phandle(fdt); 480 assert(phandle > 0); 481 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 482 483 /* 484 * ISA devices are not necessarily parented to the ISA bus so we 485 * can not use object_child_foreach() 486 */ 487 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 488 &args); 489 } 490 491 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 492 { 493 int off; 494 495 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 496 off = fdt_add_subnode(fdt, off, "power-mgt"); 497 498 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 499 } 500 501 static void *pnv_dt_create(MachineState *machine) 502 { 503 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 504 PnvMachineState *pnv = PNV_MACHINE(machine); 505 void *fdt; 506 char *buf; 507 int off; 508 int i; 509 510 fdt = g_malloc0(FDT_MAX_SIZE); 511 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 512 513 /* /qemu node */ 514 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 515 516 /* Root node */ 517 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 518 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 519 _FDT((fdt_setprop_string(fdt, 0, "model", 520 "IBM PowerNV (emulated by qemu)"))); 521 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 522 523 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 524 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 525 if (qemu_uuid_set) { 526 _FDT((fdt_property_string(fdt, "system-id", buf))); 527 } 528 g_free(buf); 529 530 off = fdt_add_subnode(fdt, 0, "chosen"); 531 if (machine->kernel_cmdline) { 532 _FDT((fdt_setprop_string(fdt, off, "bootargs", 533 machine->kernel_cmdline))); 534 } 535 536 if (pnv->initrd_size) { 537 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 538 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 539 540 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 541 &start_prop, sizeof(start_prop)))); 542 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 543 &end_prop, sizeof(end_prop)))); 544 } 545 546 /* Populate device tree for each chip */ 547 for (i = 0; i < pnv->num_chips; i++) { 548 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 549 } 550 551 /* Populate ISA devices on chip 0 */ 552 pnv_dt_isa(pnv, fdt); 553 554 if (pnv->bmc) { 555 pnv_dt_bmc_sensors(pnv->bmc, fdt); 556 } 557 558 /* Create an extra node for power management on machines that support it */ 559 if (pmc->dt_power_mgt) { 560 pmc->dt_power_mgt(pnv, fdt); 561 } 562 563 return fdt; 564 } 565 566 static void pnv_powerdown_notify(Notifier *n, void *opaque) 567 { 568 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 569 570 if (pnv->bmc) { 571 pnv_bmc_powerdown(pnv->bmc); 572 } 573 } 574 575 static void pnv_reset(MachineState *machine) 576 { 577 PnvMachineState *pnv = PNV_MACHINE(machine); 578 IPMIBmc *bmc; 579 void *fdt; 580 581 qemu_devices_reset(); 582 583 /* 584 * The machine should provide by default an internal BMC simulator. 585 * If not, try to use the BMC device that was provided on the command 586 * line. 587 */ 588 bmc = pnv_bmc_find(&error_fatal); 589 if (!pnv->bmc) { 590 if (!bmc) { 591 if (!qtest_enabled()) { 592 warn_report("machine has no BMC device. Use '-device " 593 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 594 "to define one"); 595 } 596 } else { 597 pnv_bmc_set_pnor(bmc, pnv->pnor); 598 pnv->bmc = bmc; 599 } 600 } 601 602 fdt = pnv_dt_create(machine); 603 604 /* Pack resulting tree */ 605 _FDT((fdt_pack(fdt))); 606 607 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 608 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 609 610 g_free(fdt); 611 } 612 613 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 614 { 615 Pnv8Chip *chip8 = PNV8_CHIP(chip); 616 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 617 } 618 619 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 620 { 621 Pnv8Chip *chip8 = PNV8_CHIP(chip); 622 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 623 } 624 625 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 626 { 627 Pnv9Chip *chip9 = PNV9_CHIP(chip); 628 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 629 } 630 631 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 632 { 633 Pnv10Chip *chip10 = PNV10_CHIP(chip); 634 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 635 } 636 637 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 638 { 639 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 640 } 641 642 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 643 { 644 Pnv8Chip *chip8 = PNV8_CHIP(chip); 645 int i; 646 647 ics_pic_print_info(&chip8->psi.ics, mon); 648 for (i = 0; i < chip->num_phbs; i++) { 649 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 650 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 651 } 652 } 653 654 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 655 { 656 Pnv9Chip *chip9 = PNV9_CHIP(chip); 657 int i, j; 658 659 pnv_xive_pic_print_info(&chip9->xive, mon); 660 pnv_psi_pic_print_info(&chip9->psi, mon); 661 662 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 663 PnvPhb4PecState *pec = &chip9->pecs[i]; 664 for (j = 0; j < pec->num_stacks; j++) { 665 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 666 } 667 } 668 } 669 670 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 671 uint32_t core_id) 672 { 673 return PNV_XSCOM_EX_BASE(core_id); 674 } 675 676 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 677 uint32_t core_id) 678 { 679 return PNV9_XSCOM_EC_BASE(core_id); 680 } 681 682 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 683 uint32_t core_id) 684 { 685 return PNV10_XSCOM_EC_BASE(core_id); 686 } 687 688 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 689 { 690 PowerPCCPUClass *ppc_default = 691 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 692 PowerPCCPUClass *ppc = 693 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 694 695 return ppc_default->pvr_match(ppc_default, ppc->pvr); 696 } 697 698 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 699 { 700 ISADevice *dev = isa_new("isa-ipmi-bt"); 701 702 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 703 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 704 isa_realize_and_unref(dev, bus, &error_fatal); 705 } 706 707 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 708 { 709 Pnv10Chip *chip10 = PNV10_CHIP(chip); 710 711 pnv_psi_pic_print_info(&chip10->psi, mon); 712 } 713 714 static void pnv_init(MachineState *machine) 715 { 716 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 717 PnvMachineState *pnv = PNV_MACHINE(machine); 718 MachineClass *mc = MACHINE_GET_CLASS(machine); 719 char *fw_filename; 720 long fw_size; 721 int i; 722 char *chip_typename; 723 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 724 DeviceState *dev; 725 726 /* allocate RAM */ 727 if (machine->ram_size < (1 * GiB)) { 728 warn_report("skiboot may not work with < 1GB of RAM"); 729 } 730 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 731 732 /* 733 * Create our simple PNOR device 734 */ 735 dev = qdev_new(TYPE_PNV_PNOR); 736 if (pnor) { 737 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 738 } 739 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 740 pnv->pnor = PNV_PNOR(dev); 741 742 /* load skiboot firmware */ 743 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 744 if (!fw_filename) { 745 error_report("Could not find OPAL firmware '%s'", bios_name); 746 exit(1); 747 } 748 749 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 750 if (fw_size < 0) { 751 error_report("Could not load OPAL firmware '%s'", fw_filename); 752 exit(1); 753 } 754 g_free(fw_filename); 755 756 /* load kernel */ 757 if (machine->kernel_filename) { 758 long kernel_size; 759 760 kernel_size = load_image_targphys(machine->kernel_filename, 761 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 762 if (kernel_size < 0) { 763 error_report("Could not load kernel '%s'", 764 machine->kernel_filename); 765 exit(1); 766 } 767 } 768 769 /* load initrd */ 770 if (machine->initrd_filename) { 771 pnv->initrd_base = INITRD_LOAD_ADDR; 772 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 773 pnv->initrd_base, INITRD_MAX_SIZE); 774 if (pnv->initrd_size < 0) { 775 error_report("Could not load initial ram disk '%s'", 776 machine->initrd_filename); 777 exit(1); 778 } 779 } 780 781 /* MSIs are supported on this platform */ 782 msi_nonbroken = true; 783 784 /* 785 * Check compatibility of the specified CPU with the machine 786 * default. 787 */ 788 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 789 error_report("invalid CPU model '%s' for %s machine", 790 machine->cpu_type, mc->name); 791 exit(1); 792 } 793 794 /* Create the processor chips */ 795 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 796 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 797 i, machine->cpu_type); 798 if (!object_class_by_name(chip_typename)) { 799 error_report("invalid chip model '%.*s' for %s machine", 800 i, machine->cpu_type, mc->name); 801 exit(1); 802 } 803 804 pnv->num_chips = 805 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 806 /* 807 * TODO: should we decide on how many chips we can create based 808 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 809 */ 810 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 811 error_report("invalid number of chips: '%d'", pnv->num_chips); 812 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 813 exit(1); 814 } 815 816 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 817 for (i = 0; i < pnv->num_chips; i++) { 818 char chip_name[32]; 819 Object *chip = OBJECT(qdev_new(chip_typename)); 820 821 pnv->chips[i] = PNV_CHIP(chip); 822 823 /* 824 * TODO: put all the memory in one node on chip 0 until we find a 825 * way to specify different ranges for each chip 826 */ 827 if (i == 0) { 828 object_property_set_int(chip, "ram-size", machine->ram_size, 829 &error_fatal); 830 } 831 832 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 833 object_property_add_child(OBJECT(pnv), chip_name, chip); 834 object_property_set_int(chip, "chip-id", PNV_CHIP_HWID(i), 835 &error_fatal); 836 object_property_set_int(chip, "nr-cores", machine->smp.cores, 837 &error_fatal); 838 object_property_set_int(chip, "nr-threads", machine->smp.threads, 839 &error_fatal); 840 /* 841 * The POWER8 machine use the XICS interrupt interface. 842 * Propagate the XICS fabric to the chip and its controllers. 843 */ 844 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 845 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 846 } 847 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 848 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 849 &error_abort); 850 } 851 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 852 } 853 g_free(chip_typename); 854 855 /* Instantiate ISA bus on chip 0 */ 856 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 857 858 /* Create serial port */ 859 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 860 861 /* Create an RTC ISA device too */ 862 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 863 864 /* 865 * Create the machine BMC simulator and the IPMI BT device for 866 * communication with the BMC 867 */ 868 if (defaults_enabled()) { 869 pnv->bmc = pnv_bmc_create(pnv->pnor); 870 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 871 } 872 873 /* 874 * OpenPOWER systems use a IPMI SEL Event message to notify the 875 * host to powerdown 876 */ 877 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 878 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 879 } 880 881 /* 882 * 0:21 Reserved - Read as zeros 883 * 22:24 Chip ID 884 * 25:28 Core number 885 * 29:31 Thread ID 886 */ 887 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 888 { 889 return (chip->chip_id << 7) | (core_id << 3); 890 } 891 892 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 893 Error **errp) 894 { 895 Pnv8Chip *chip8 = PNV8_CHIP(chip); 896 Error *local_err = NULL; 897 Object *obj; 898 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 899 900 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 901 if (local_err) { 902 error_propagate(errp, local_err); 903 return; 904 } 905 906 pnv_cpu->intc = obj; 907 } 908 909 910 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 911 { 912 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 913 914 icp_reset(ICP(pnv_cpu->intc)); 915 } 916 917 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 918 { 919 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 920 921 icp_destroy(ICP(pnv_cpu->intc)); 922 pnv_cpu->intc = NULL; 923 } 924 925 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 926 Monitor *mon) 927 { 928 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 929 } 930 931 /* 932 * 0:48 Reserved - Read as zeroes 933 * 49:52 Node ID 934 * 53:55 Chip ID 935 * 56 Reserved - Read as zero 936 * 57:61 Core number 937 * 62:63 Thread ID 938 * 939 * We only care about the lower bits. uint32_t is fine for the moment. 940 */ 941 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 942 { 943 return (chip->chip_id << 8) | (core_id << 2); 944 } 945 946 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 947 { 948 return (chip->chip_id << 8) | (core_id << 2); 949 } 950 951 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 952 Error **errp) 953 { 954 Pnv9Chip *chip9 = PNV9_CHIP(chip); 955 Error *local_err = NULL; 956 Object *obj; 957 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 958 959 /* 960 * The core creates its interrupt presenter but the XIVE interrupt 961 * controller object is initialized afterwards. Hopefully, it's 962 * only used at runtime. 963 */ 964 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 965 &local_err); 966 if (local_err) { 967 error_propagate(errp, local_err); 968 return; 969 } 970 971 pnv_cpu->intc = obj; 972 } 973 974 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 975 { 976 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 977 978 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 979 } 980 981 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 982 { 983 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 984 985 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 986 pnv_cpu->intc = NULL; 987 } 988 989 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 990 Monitor *mon) 991 { 992 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 993 } 994 995 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 996 Error **errp) 997 { 998 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 999 1000 /* Will be defined when the interrupt controller is */ 1001 pnv_cpu->intc = NULL; 1002 } 1003 1004 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1005 { 1006 ; 1007 } 1008 1009 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1010 { 1011 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1012 1013 pnv_cpu->intc = NULL; 1014 } 1015 1016 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1017 Monitor *mon) 1018 { 1019 } 1020 1021 /* 1022 * Allowed core identifiers on a POWER8 Processor Chip : 1023 * 1024 * <EX0 reserved> 1025 * EX1 - Venice only 1026 * EX2 - Venice only 1027 * EX3 - Venice only 1028 * EX4 1029 * EX5 1030 * EX6 1031 * <EX7,8 reserved> <reserved> 1032 * EX9 - Venice only 1033 * EX10 - Venice only 1034 * EX11 - Venice only 1035 * EX12 1036 * EX13 1037 * EX14 1038 * <EX15 reserved> 1039 */ 1040 #define POWER8E_CORE_MASK (0x7070ull) 1041 #define POWER8_CORE_MASK (0x7e7eull) 1042 1043 /* 1044 * POWER9 has 24 cores, ids starting at 0x0 1045 */ 1046 #define POWER9_CORE_MASK (0xffffffffffffffull) 1047 1048 1049 #define POWER10_CORE_MASK (0xffffffffffffffull) 1050 1051 static void pnv_chip_power8_instance_init(Object *obj) 1052 { 1053 PnvChip *chip = PNV_CHIP(obj); 1054 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1055 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1056 int i; 1057 1058 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1059 (Object **)&chip8->xics, 1060 object_property_allow_set_link, 1061 OBJ_PROP_LINK_STRONG); 1062 1063 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1064 1065 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1066 1067 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1068 1069 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1070 1071 for (i = 0; i < pcc->num_phbs; i++) { 1072 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1073 } 1074 1075 /* 1076 * Number of PHBs is the chip default 1077 */ 1078 chip->num_phbs = pcc->num_phbs; 1079 } 1080 1081 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1082 { 1083 PnvChip *chip = PNV_CHIP(chip8); 1084 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1085 int i, j; 1086 char *name; 1087 1088 name = g_strdup_printf("icp-%x", chip->chip_id); 1089 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1090 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1091 g_free(name); 1092 1093 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1094 1095 /* Map the ICP registers for each thread */ 1096 for (i = 0; i < chip->nr_cores; i++) { 1097 PnvCore *pnv_core = chip->cores[i]; 1098 int core_hwid = CPU_CORE(pnv_core)->core_id; 1099 1100 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1101 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1102 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1103 1104 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1105 &icp->mmio); 1106 } 1107 } 1108 } 1109 1110 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1111 { 1112 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1113 PnvChip *chip = PNV_CHIP(dev); 1114 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1115 Pnv8Psi *psi8 = &chip8->psi; 1116 Error *local_err = NULL; 1117 int i; 1118 1119 assert(chip8->xics); 1120 1121 /* XSCOM bridge is first */ 1122 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1123 if (local_err) { 1124 error_propagate(errp, local_err); 1125 return; 1126 } 1127 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1128 1129 pcc->parent_realize(dev, &local_err); 1130 if (local_err) { 1131 error_propagate(errp, local_err); 1132 return; 1133 } 1134 1135 /* Processor Service Interface (PSI) Host Bridge */ 1136 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1137 &error_fatal); 1138 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1139 OBJECT(chip8->xics), &error_abort); 1140 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1141 return; 1142 } 1143 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1144 &PNV_PSI(psi8)->xscom_regs); 1145 1146 /* Create LPC controller */ 1147 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi), 1148 &error_abort); 1149 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1150 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1151 1152 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1153 (uint64_t) PNV_XSCOM_BASE(chip), 1154 PNV_XSCOM_LPC_BASE); 1155 1156 /* 1157 * Interrupt Management Area. This is the memory region holding 1158 * all the Interrupt Control Presenter (ICP) registers 1159 */ 1160 pnv_chip_icp_realize(chip8, &local_err); 1161 if (local_err) { 1162 error_propagate(errp, local_err); 1163 return; 1164 } 1165 1166 /* Create the simplified OCC model */ 1167 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi), 1168 &error_abort); 1169 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1170 return; 1171 } 1172 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1173 1174 /* OCC SRAM model */ 1175 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1176 &chip8->occ.sram_regs); 1177 1178 /* HOMER */ 1179 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1180 &error_abort); 1181 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1182 return; 1183 } 1184 /* Homer Xscom region */ 1185 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1186 1187 /* Homer mmio region */ 1188 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1189 &chip8->homer.regs); 1190 1191 /* PHB3 controllers */ 1192 for (i = 0; i < chip->num_phbs; i++) { 1193 PnvPHB3 *phb = &chip8->phbs[i]; 1194 PnvPBCQState *pbcq = &phb->pbcq; 1195 1196 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1197 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1198 &error_fatal); 1199 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1200 return; 1201 } 1202 1203 /* Populate the XSCOM address space. */ 1204 pnv_xscom_add_subregion(chip, 1205 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1206 &pbcq->xscom_nest_regs); 1207 pnv_xscom_add_subregion(chip, 1208 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1209 &pbcq->xscom_pci_regs); 1210 pnv_xscom_add_subregion(chip, 1211 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1212 &pbcq->xscom_spci_regs); 1213 } 1214 } 1215 1216 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1217 { 1218 addr &= (PNV_XSCOM_SIZE - 1); 1219 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1220 } 1221 1222 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1223 { 1224 DeviceClass *dc = DEVICE_CLASS(klass); 1225 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1226 1227 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1228 k->cores_mask = POWER8E_CORE_MASK; 1229 k->num_phbs = 3; 1230 k->core_pir = pnv_chip_core_pir_p8; 1231 k->intc_create = pnv_chip_power8_intc_create; 1232 k->intc_reset = pnv_chip_power8_intc_reset; 1233 k->intc_destroy = pnv_chip_power8_intc_destroy; 1234 k->intc_print_info = pnv_chip_power8_intc_print_info; 1235 k->isa_create = pnv_chip_power8_isa_create; 1236 k->dt_populate = pnv_chip_power8_dt_populate; 1237 k->pic_print_info = pnv_chip_power8_pic_print_info; 1238 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1239 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1240 dc->desc = "PowerNV Chip POWER8E"; 1241 1242 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1243 &k->parent_realize); 1244 } 1245 1246 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1247 { 1248 DeviceClass *dc = DEVICE_CLASS(klass); 1249 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1250 1251 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1252 k->cores_mask = POWER8_CORE_MASK; 1253 k->num_phbs = 3; 1254 k->core_pir = pnv_chip_core_pir_p8; 1255 k->intc_create = pnv_chip_power8_intc_create; 1256 k->intc_reset = pnv_chip_power8_intc_reset; 1257 k->intc_destroy = pnv_chip_power8_intc_destroy; 1258 k->intc_print_info = pnv_chip_power8_intc_print_info; 1259 k->isa_create = pnv_chip_power8_isa_create; 1260 k->dt_populate = pnv_chip_power8_dt_populate; 1261 k->pic_print_info = pnv_chip_power8_pic_print_info; 1262 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1263 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1264 dc->desc = "PowerNV Chip POWER8"; 1265 1266 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1267 &k->parent_realize); 1268 } 1269 1270 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1271 { 1272 DeviceClass *dc = DEVICE_CLASS(klass); 1273 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1274 1275 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1276 k->cores_mask = POWER8_CORE_MASK; 1277 k->num_phbs = 3; 1278 k->core_pir = pnv_chip_core_pir_p8; 1279 k->intc_create = pnv_chip_power8_intc_create; 1280 k->intc_reset = pnv_chip_power8_intc_reset; 1281 k->intc_destroy = pnv_chip_power8_intc_destroy; 1282 k->intc_print_info = pnv_chip_power8_intc_print_info; 1283 k->isa_create = pnv_chip_power8nvl_isa_create; 1284 k->dt_populate = pnv_chip_power8_dt_populate; 1285 k->pic_print_info = pnv_chip_power8_pic_print_info; 1286 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1287 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1288 dc->desc = "PowerNV Chip POWER8NVL"; 1289 1290 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1291 &k->parent_realize); 1292 } 1293 1294 static void pnv_chip_power9_instance_init(Object *obj) 1295 { 1296 PnvChip *chip = PNV_CHIP(obj); 1297 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1298 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1299 int i; 1300 1301 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1302 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1303 "xive-fabric"); 1304 1305 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1306 1307 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1308 1309 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1310 1311 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1312 1313 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1314 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1315 TYPE_PNV_PHB4_PEC); 1316 } 1317 1318 /* 1319 * Number of PHBs is the chip default 1320 */ 1321 chip->num_phbs = pcc->num_phbs; 1322 } 1323 1324 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1325 { 1326 PnvChip *chip = PNV_CHIP(chip9); 1327 int i; 1328 1329 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1330 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1331 1332 for (i = 0; i < chip9->nr_quads; i++) { 1333 char eq_name[32]; 1334 PnvQuad *eq = &chip9->quads[i]; 1335 PnvCore *pnv_core = chip->cores[i * 4]; 1336 int core_id = CPU_CORE(pnv_core)->core_id; 1337 1338 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1339 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1340 sizeof(*eq), TYPE_PNV_QUAD, 1341 &error_fatal, NULL); 1342 1343 object_property_set_int(OBJECT(eq), "id", core_id, &error_fatal); 1344 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1345 1346 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1347 &eq->xscom_regs); 1348 } 1349 } 1350 1351 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1352 { 1353 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1354 int i, j; 1355 int phb_id = 0; 1356 1357 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1358 PnvPhb4PecState *pec = &chip9->pecs[i]; 1359 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1360 uint32_t pec_nest_base; 1361 uint32_t pec_pci_base; 1362 1363 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1364 /* 1365 * PEC0 -> 1 stack 1366 * PEC1 -> 2 stacks 1367 * PEC2 -> 3 stacks 1368 */ 1369 object_property_set_int(OBJECT(pec), "num-stacks", i + 1, 1370 &error_fatal); 1371 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1372 &error_fatal); 1373 object_property_set_link(OBJECT(pec), "system-memory", 1374 OBJECT(get_system_memory()), &error_abort); 1375 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1376 return; 1377 } 1378 1379 pec_nest_base = pecc->xscom_nest_base(pec); 1380 pec_pci_base = pecc->xscom_pci_base(pec); 1381 1382 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1383 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1384 1385 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1386 j++, phb_id++) { 1387 PnvPhb4PecStack *stack = &pec->stacks[j]; 1388 Object *obj = OBJECT(&stack->phb); 1389 1390 object_property_set_int(obj, "index", phb_id, &error_fatal); 1391 object_property_set_int(obj, "chip-id", chip->chip_id, 1392 &error_fatal); 1393 object_property_set_int(obj, "version", PNV_PHB4_VERSION, 1394 &error_fatal); 1395 object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID, 1396 &error_fatal); 1397 object_property_set_link(obj, "stack", OBJECT(stack), 1398 &error_abort); 1399 if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) { 1400 return; 1401 } 1402 1403 /* Populate the XSCOM address space. */ 1404 pnv_xscom_add_subregion(chip, 1405 pec_nest_base + 0x40 * (stack->stack_no + 1), 1406 &stack->nest_regs_mr); 1407 pnv_xscom_add_subregion(chip, 1408 pec_pci_base + 0x40 * (stack->stack_no + 1), 1409 &stack->pci_regs_mr); 1410 pnv_xscom_add_subregion(chip, 1411 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1412 0x40 * stack->stack_no, 1413 &stack->phb_regs_mr); 1414 } 1415 } 1416 } 1417 1418 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1419 { 1420 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1421 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1422 PnvChip *chip = PNV_CHIP(dev); 1423 Pnv9Psi *psi9 = &chip9->psi; 1424 Error *local_err = NULL; 1425 1426 /* XSCOM bridge is first */ 1427 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1428 if (local_err) { 1429 error_propagate(errp, local_err); 1430 return; 1431 } 1432 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1433 1434 pcc->parent_realize(dev, &local_err); 1435 if (local_err) { 1436 error_propagate(errp, local_err); 1437 return; 1438 } 1439 1440 pnv_chip_quad_realize(chip9, &local_err); 1441 if (local_err) { 1442 error_propagate(errp, local_err); 1443 return; 1444 } 1445 1446 /* XIVE interrupt controller (POWER9) */ 1447 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1448 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1449 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1450 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1451 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1452 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1453 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1454 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1455 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1456 &error_abort); 1457 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1458 return; 1459 } 1460 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1461 &chip9->xive.xscom_regs); 1462 1463 /* Processor Service Interface (PSI) Host Bridge */ 1464 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1465 &error_fatal); 1466 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1467 return; 1468 } 1469 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1470 &PNV_PSI(psi9)->xscom_regs); 1471 1472 /* LPC */ 1473 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi), 1474 &error_abort); 1475 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1476 return; 1477 } 1478 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1479 &chip9->lpc.xscom_regs); 1480 1481 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1482 (uint64_t) PNV9_LPCM_BASE(chip)); 1483 1484 /* Create the simplified OCC model */ 1485 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi), 1486 &error_abort); 1487 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1488 return; 1489 } 1490 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1491 1492 /* OCC SRAM model */ 1493 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1494 &chip9->occ.sram_regs); 1495 1496 /* HOMER */ 1497 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1498 &error_abort); 1499 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1500 return; 1501 } 1502 /* Homer Xscom region */ 1503 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1504 1505 /* Homer mmio region */ 1506 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1507 &chip9->homer.regs); 1508 1509 /* PHBs */ 1510 pnv_chip_power9_phb_realize(chip, &local_err); 1511 if (local_err) { 1512 error_propagate(errp, local_err); 1513 return; 1514 } 1515 } 1516 1517 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1518 { 1519 addr &= (PNV9_XSCOM_SIZE - 1); 1520 return addr >> 3; 1521 } 1522 1523 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1524 { 1525 DeviceClass *dc = DEVICE_CLASS(klass); 1526 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1527 1528 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1529 k->cores_mask = POWER9_CORE_MASK; 1530 k->core_pir = pnv_chip_core_pir_p9; 1531 k->intc_create = pnv_chip_power9_intc_create; 1532 k->intc_reset = pnv_chip_power9_intc_reset; 1533 k->intc_destroy = pnv_chip_power9_intc_destroy; 1534 k->intc_print_info = pnv_chip_power9_intc_print_info; 1535 k->isa_create = pnv_chip_power9_isa_create; 1536 k->dt_populate = pnv_chip_power9_dt_populate; 1537 k->pic_print_info = pnv_chip_power9_pic_print_info; 1538 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1539 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1540 dc->desc = "PowerNV Chip POWER9"; 1541 k->num_phbs = 6; 1542 1543 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1544 &k->parent_realize); 1545 } 1546 1547 static void pnv_chip_power10_instance_init(Object *obj) 1548 { 1549 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1550 1551 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1552 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1553 } 1554 1555 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1556 { 1557 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1558 PnvChip *chip = PNV_CHIP(dev); 1559 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1560 Error *local_err = NULL; 1561 1562 /* XSCOM bridge is first */ 1563 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1564 if (local_err) { 1565 error_propagate(errp, local_err); 1566 return; 1567 } 1568 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1569 1570 pcc->parent_realize(dev, &local_err); 1571 if (local_err) { 1572 error_propagate(errp, local_err); 1573 return; 1574 } 1575 1576 /* Processor Service Interface (PSI) Host Bridge */ 1577 object_property_set_int(OBJECT(&chip10->psi), "bar", 1578 PNV10_PSIHB_BASE(chip), &error_fatal); 1579 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1580 return; 1581 } 1582 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1583 &PNV_PSI(&chip10->psi)->xscom_regs); 1584 1585 /* LPC */ 1586 object_property_set_link(OBJECT(&chip10->lpc), "psi", 1587 OBJECT(&chip10->psi), &error_abort); 1588 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1589 return; 1590 } 1591 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1592 &chip10->lpc.xscom_regs); 1593 1594 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1595 (uint64_t) PNV10_LPCM_BASE(chip)); 1596 } 1597 1598 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1599 { 1600 addr &= (PNV10_XSCOM_SIZE - 1); 1601 return addr >> 3; 1602 } 1603 1604 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1605 { 1606 DeviceClass *dc = DEVICE_CLASS(klass); 1607 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1608 1609 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1610 k->cores_mask = POWER10_CORE_MASK; 1611 k->core_pir = pnv_chip_core_pir_p10; 1612 k->intc_create = pnv_chip_power10_intc_create; 1613 k->intc_reset = pnv_chip_power10_intc_reset; 1614 k->intc_destroy = pnv_chip_power10_intc_destroy; 1615 k->intc_print_info = pnv_chip_power10_intc_print_info; 1616 k->isa_create = pnv_chip_power10_isa_create; 1617 k->dt_populate = pnv_chip_power10_dt_populate; 1618 k->pic_print_info = pnv_chip_power10_pic_print_info; 1619 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1620 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1621 dc->desc = "PowerNV Chip POWER10"; 1622 1623 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1624 &k->parent_realize); 1625 } 1626 1627 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1628 { 1629 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1630 int cores_max; 1631 1632 /* 1633 * No custom mask for this chip, let's use the default one from * 1634 * the chip class 1635 */ 1636 if (!chip->cores_mask) { 1637 chip->cores_mask = pcc->cores_mask; 1638 } 1639 1640 /* filter alien core ids ! some are reserved */ 1641 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1642 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1643 chip->cores_mask); 1644 return; 1645 } 1646 chip->cores_mask &= pcc->cores_mask; 1647 1648 /* now that we have a sane layout, let check the number of cores */ 1649 cores_max = ctpop64(chip->cores_mask); 1650 if (chip->nr_cores > cores_max) { 1651 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1652 cores_max); 1653 return; 1654 } 1655 } 1656 1657 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1658 { 1659 Error *error = NULL; 1660 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1661 const char *typename = pnv_chip_core_typename(chip); 1662 int i, core_hwid; 1663 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1664 1665 if (!object_class_by_name(typename)) { 1666 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1667 return; 1668 } 1669 1670 /* Cores */ 1671 pnv_chip_core_sanitize(chip, &error); 1672 if (error) { 1673 error_propagate(errp, error); 1674 return; 1675 } 1676 1677 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1678 1679 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1680 && (i < chip->nr_cores); core_hwid++) { 1681 char core_name[32]; 1682 PnvCore *pnv_core; 1683 uint64_t xscom_core_base; 1684 1685 if (!(chip->cores_mask & (1ull << core_hwid))) { 1686 continue; 1687 } 1688 1689 pnv_core = PNV_CORE(object_new(typename)); 1690 1691 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1692 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1693 chip->cores[i] = pnv_core; 1694 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1695 chip->nr_threads, &error_fatal); 1696 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1697 core_hwid, &error_fatal); 1698 object_property_set_int(OBJECT(pnv_core), "pir", 1699 pcc->core_pir(chip, core_hwid), &error_fatal); 1700 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1701 &error_fatal); 1702 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1703 &error_abort); 1704 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1705 1706 /* Each core has an XSCOM MMIO region */ 1707 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1708 1709 pnv_xscom_add_subregion(chip, xscom_core_base, 1710 &pnv_core->xscom_regs); 1711 i++; 1712 } 1713 } 1714 1715 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1716 { 1717 PnvChip *chip = PNV_CHIP(dev); 1718 Error *error = NULL; 1719 1720 /* Cores */ 1721 pnv_chip_core_realize(chip, &error); 1722 if (error) { 1723 error_propagate(errp, error); 1724 return; 1725 } 1726 } 1727 1728 static Property pnv_chip_properties[] = { 1729 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1730 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1731 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1732 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1733 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1734 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1735 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1736 DEFINE_PROP_END_OF_LIST(), 1737 }; 1738 1739 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1740 { 1741 DeviceClass *dc = DEVICE_CLASS(klass); 1742 1743 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1744 dc->realize = pnv_chip_realize; 1745 device_class_set_props(dc, pnv_chip_properties); 1746 dc->desc = "PowerNV Chip"; 1747 } 1748 1749 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1750 { 1751 int i, j; 1752 1753 for (i = 0; i < chip->nr_cores; i++) { 1754 PnvCore *pc = chip->cores[i]; 1755 CPUCore *cc = CPU_CORE(pc); 1756 1757 for (j = 0; j < cc->nr_threads; j++) { 1758 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1759 return pc->threads[j]; 1760 } 1761 } 1762 } 1763 return NULL; 1764 } 1765 1766 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1767 { 1768 PnvMachineState *pnv = PNV_MACHINE(xi); 1769 int i, j; 1770 1771 for (i = 0; i < pnv->num_chips; i++) { 1772 PnvChip *chip = pnv->chips[i]; 1773 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1774 1775 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1776 return &chip8->psi.ics; 1777 } 1778 for (j = 0; j < chip->num_phbs; j++) { 1779 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1780 return &chip8->phbs[j].lsis; 1781 } 1782 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1783 return ICS(&chip8->phbs[j].msis); 1784 } 1785 } 1786 } 1787 return NULL; 1788 } 1789 1790 static void pnv_ics_resend(XICSFabric *xi) 1791 { 1792 PnvMachineState *pnv = PNV_MACHINE(xi); 1793 int i, j; 1794 1795 for (i = 0; i < pnv->num_chips; i++) { 1796 PnvChip *chip = pnv->chips[i]; 1797 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1798 1799 ics_resend(&chip8->psi.ics); 1800 for (j = 0; j < chip->num_phbs; j++) { 1801 ics_resend(&chip8->phbs[j].lsis); 1802 ics_resend(ICS(&chip8->phbs[j].msis)); 1803 } 1804 } 1805 } 1806 1807 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1808 { 1809 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1810 1811 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1812 } 1813 1814 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1815 Monitor *mon) 1816 { 1817 PnvMachineState *pnv = PNV_MACHINE(obj); 1818 int i; 1819 CPUState *cs; 1820 1821 CPU_FOREACH(cs) { 1822 PowerPCCPU *cpu = POWERPC_CPU(cs); 1823 1824 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1825 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1826 mon); 1827 } 1828 1829 for (i = 0; i < pnv->num_chips; i++) { 1830 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1831 } 1832 } 1833 1834 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1835 uint8_t nvt_blk, uint32_t nvt_idx, 1836 bool cam_ignore, uint8_t priority, 1837 uint32_t logic_serv, 1838 XiveTCTXMatch *match) 1839 { 1840 PnvMachineState *pnv = PNV_MACHINE(xfb); 1841 int total_count = 0; 1842 int i; 1843 1844 for (i = 0; i < pnv->num_chips; i++) { 1845 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1846 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1847 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1848 int count; 1849 1850 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1851 priority, logic_serv, match); 1852 1853 if (count < 0) { 1854 return count; 1855 } 1856 1857 total_count += count; 1858 } 1859 1860 return total_count; 1861 } 1862 1863 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1864 { 1865 MachineClass *mc = MACHINE_CLASS(oc); 1866 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1867 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1868 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1869 1870 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1871 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1872 1873 xic->icp_get = pnv_icp_get; 1874 xic->ics_get = pnv_ics_get; 1875 xic->ics_resend = pnv_ics_resend; 1876 1877 pmc->compat = compat; 1878 pmc->compat_size = sizeof(compat); 1879 } 1880 1881 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1882 { 1883 MachineClass *mc = MACHINE_CLASS(oc); 1884 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1885 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1886 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1887 1888 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1889 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1890 xfc->match_nvt = pnv_match_nvt; 1891 1892 mc->alias = "powernv"; 1893 1894 pmc->compat = compat; 1895 pmc->compat_size = sizeof(compat); 1896 pmc->dt_power_mgt = pnv_dt_power_mgt; 1897 } 1898 1899 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1900 { 1901 MachineClass *mc = MACHINE_CLASS(oc); 1902 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1903 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1904 1905 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1906 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1907 1908 pmc->compat = compat; 1909 pmc->compat_size = sizeof(compat); 1910 pmc->dt_power_mgt = pnv_dt_power_mgt; 1911 } 1912 1913 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1914 { 1915 PnvMachineState *pnv = PNV_MACHINE(obj); 1916 1917 return !!pnv->fw_load_addr; 1918 } 1919 1920 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1921 { 1922 PnvMachineState *pnv = PNV_MACHINE(obj); 1923 1924 if (value) { 1925 pnv->fw_load_addr = 0x8000000; 1926 } 1927 } 1928 1929 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 1930 { 1931 PowerPCCPU *cpu = POWERPC_CPU(cs); 1932 CPUPPCState *env = &cpu->env; 1933 1934 cpu_synchronize_state(cs); 1935 ppc_cpu_do_system_reset(cs); 1936 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 1937 /* 1938 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 1939 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 1940 * (PPC_BIT(43)). 1941 */ 1942 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 1943 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 1944 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 1945 } 1946 } else { 1947 /* 1948 * For non-powersave system resets, SRR1[42:45] are defined to be 1949 * implementation-dependent. The POWER9 User Manual specifies that 1950 * an external (SCOM driven, which may come from a BMC nmi command or 1951 * another CPU requesting a NMI IPI) system reset exception should be 1952 * 0b0010 (PPC_BIT(44)). 1953 */ 1954 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 1955 } 1956 } 1957 1958 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 1959 { 1960 CPUState *cs; 1961 1962 CPU_FOREACH(cs) { 1963 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 1964 } 1965 } 1966 1967 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1968 { 1969 MachineClass *mc = MACHINE_CLASS(oc); 1970 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1971 NMIClass *nc = NMI_CLASS(oc); 1972 1973 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1974 mc->init = pnv_init; 1975 mc->reset = pnv_reset; 1976 mc->max_cpus = MAX_CPUS; 1977 /* Pnv provides a AHCI device for storage */ 1978 mc->block_default_type = IF_IDE; 1979 mc->no_parallel = 1; 1980 mc->default_boot_order = NULL; 1981 /* 1982 * RAM defaults to less than 2048 for 32-bit hosts, and large 1983 * enough to fit the maximum initrd size at it's load address 1984 */ 1985 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1986 mc->default_ram_id = "pnv.ram"; 1987 ispc->print_info = pnv_pic_print_info; 1988 nc->nmi_monitor_handler = pnv_nmi; 1989 1990 object_class_property_add_bool(oc, "hb-mode", 1991 pnv_machine_get_hb, pnv_machine_set_hb); 1992 object_class_property_set_description(oc, "hb-mode", 1993 "Use a hostboot like boot loader"); 1994 } 1995 1996 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1997 { \ 1998 .name = type, \ 1999 .class_init = class_initfn, \ 2000 .parent = TYPE_PNV8_CHIP, \ 2001 } 2002 2003 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2004 { \ 2005 .name = type, \ 2006 .class_init = class_initfn, \ 2007 .parent = TYPE_PNV9_CHIP, \ 2008 } 2009 2010 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2011 { \ 2012 .name = type, \ 2013 .class_init = class_initfn, \ 2014 .parent = TYPE_PNV10_CHIP, \ 2015 } 2016 2017 static const TypeInfo types[] = { 2018 { 2019 .name = MACHINE_TYPE_NAME("powernv10"), 2020 .parent = TYPE_PNV_MACHINE, 2021 .class_init = pnv_machine_power10_class_init, 2022 }, 2023 { 2024 .name = MACHINE_TYPE_NAME("powernv9"), 2025 .parent = TYPE_PNV_MACHINE, 2026 .class_init = pnv_machine_power9_class_init, 2027 .interfaces = (InterfaceInfo[]) { 2028 { TYPE_XIVE_FABRIC }, 2029 { }, 2030 }, 2031 }, 2032 { 2033 .name = MACHINE_TYPE_NAME("powernv8"), 2034 .parent = TYPE_PNV_MACHINE, 2035 .class_init = pnv_machine_power8_class_init, 2036 .interfaces = (InterfaceInfo[]) { 2037 { TYPE_XICS_FABRIC }, 2038 { }, 2039 }, 2040 }, 2041 { 2042 .name = TYPE_PNV_MACHINE, 2043 .parent = TYPE_MACHINE, 2044 .abstract = true, 2045 .instance_size = sizeof(PnvMachineState), 2046 .class_init = pnv_machine_class_init, 2047 .class_size = sizeof(PnvMachineClass), 2048 .interfaces = (InterfaceInfo[]) { 2049 { TYPE_INTERRUPT_STATS_PROVIDER }, 2050 { TYPE_NMI }, 2051 { }, 2052 }, 2053 }, 2054 { 2055 .name = TYPE_PNV_CHIP, 2056 .parent = TYPE_SYS_BUS_DEVICE, 2057 .class_init = pnv_chip_class_init, 2058 .instance_size = sizeof(PnvChip), 2059 .class_size = sizeof(PnvChipClass), 2060 .abstract = true, 2061 }, 2062 2063 /* 2064 * P10 chip and variants 2065 */ 2066 { 2067 .name = TYPE_PNV10_CHIP, 2068 .parent = TYPE_PNV_CHIP, 2069 .instance_init = pnv_chip_power10_instance_init, 2070 .instance_size = sizeof(Pnv10Chip), 2071 }, 2072 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2073 2074 /* 2075 * P9 chip and variants 2076 */ 2077 { 2078 .name = TYPE_PNV9_CHIP, 2079 .parent = TYPE_PNV_CHIP, 2080 .instance_init = pnv_chip_power9_instance_init, 2081 .instance_size = sizeof(Pnv9Chip), 2082 }, 2083 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2084 2085 /* 2086 * P8 chip and variants 2087 */ 2088 { 2089 .name = TYPE_PNV8_CHIP, 2090 .parent = TYPE_PNV_CHIP, 2091 .instance_init = pnv_chip_power8_instance_init, 2092 .instance_size = sizeof(Pnv8Chip), 2093 }, 2094 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2095 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2096 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2097 pnv_chip_power8nvl_class_init), 2098 }; 2099 2100 DEFINE_TYPES(types) 2101