1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 44 #include "hw/ppc/xics.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/ppc/pnv_xscom.h" 47 #include "hw/ppc/pnv_pnor.h" 48 49 #include "hw/isa/isa.h" 50 #include "hw/boards.h" 51 #include "hw/char/serial.h" 52 #include "hw/rtc/mc146818rtc.h" 53 54 #include <libfdt.h> 55 56 #define FDT_MAX_SIZE (1 * MiB) 57 58 #define FW_FILE_NAME "skiboot.lid" 59 #define FW_LOAD_ADDR 0x0 60 #define FW_MAX_SIZE (4 * MiB) 61 62 #define KERNEL_LOAD_ADDR 0x20000000 63 #define KERNEL_MAX_SIZE (256 * MiB) 64 #define INITRD_LOAD_ADDR 0x60000000 65 #define INITRD_MAX_SIZE (256 * MiB) 66 67 static const char *pnv_chip_core_typename(const PnvChip *o) 68 { 69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 72 const char *core_type = object_class_get_name(object_class_by_name(s)); 73 g_free(s); 74 return core_type; 75 } 76 77 /* 78 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 79 * 4 * 4 sockets * 12 cores * 8 threads = 1536 80 * Let's make it 2^11 81 */ 82 #define MAX_CPUS 2048 83 84 /* 85 * Memory nodes are created by hostboot, one for each range of memory 86 * that has a different "affinity". In practice, it means one range 87 * per chip. 88 */ 89 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 90 { 91 char *mem_name; 92 uint64_t mem_reg_property[2]; 93 int off; 94 95 mem_reg_property[0] = cpu_to_be64(start); 96 mem_reg_property[1] = cpu_to_be64(size); 97 98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 99 off = fdt_add_subnode(fdt, 0, mem_name); 100 g_free(mem_name); 101 102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 104 sizeof(mem_reg_property)))); 105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 106 } 107 108 static int get_cpus_node(void *fdt) 109 { 110 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 111 112 if (cpus_offset < 0) { 113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 114 if (cpus_offset) { 115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 117 } 118 } 119 _FDT(cpus_offset); 120 return cpus_offset; 121 } 122 123 /* 124 * The PowerNV cores (and threads) need to use real HW ids and not an 125 * incremental index like it has been done on other platforms. This HW 126 * id is stored in the CPU PIR, it is used to create cpu nodes in the 127 * device tree, used in XSCOM to address cores and in interrupt 128 * servers. 129 */ 130 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 131 { 132 PowerPCCPU *cpu = pc->threads[0]; 133 CPUState *cs = CPU(cpu); 134 DeviceClass *dc = DEVICE_GET_CLASS(cs); 135 int smt_threads = CPU_CORE(pc)->nr_threads; 136 CPUPPCState *env = &cpu->env; 137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 138 uint32_t servers_prop[smt_threads]; 139 int i; 140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 141 0xffffffff, 0xffffffff}; 142 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 143 uint32_t cpufreq = 1000000000; 144 uint32_t page_sizes_prop[64]; 145 size_t page_sizes_prop_size; 146 const uint8_t pa_features[] = { 24, 0, 147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 151 int offset; 152 char *nodename; 153 int cpus_offset = get_cpus_node(fdt); 154 155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 156 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 157 _FDT(offset); 158 g_free(nodename); 159 160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 161 162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 168 env->dcache_line_size))); 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 170 env->dcache_line_size))); 171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 172 env->icache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 174 env->icache_line_size))); 175 176 if (pcc->l1_dcache_size) { 177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 178 pcc->l1_dcache_size))); 179 } else { 180 warn_report("Unknown L1 dcache size for cpu"); 181 } 182 if (pcc->l1_icache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 184 pcc->l1_icache_size))); 185 } else { 186 warn_report("Unknown L1 icache size for cpu"); 187 } 188 189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 192 cpu->hash64_opts->slb_size))); 193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 195 196 if (env->spr_cb[SPR_PURR].oea_read) { 197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 198 } 199 200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 202 segs, sizeof(segs)))); 203 } 204 205 /* 206 * Advertise VMX/VSX (vector extensions) if available 207 * 0 / no property == no vector extensions 208 * 1 == VMX / Altivec available 209 * 2 == VSX available 210 */ 211 if (env->insns_flags & PPC_ALTIVEC) { 212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 213 214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 215 } 216 217 /* 218 * Advertise DFP (Decimal Floating Point) if available 219 * 0 / no property == no DFP 220 * 1 == DFP available 221 */ 222 if (env->insns_flags2 & PPC2_DFP) { 223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 224 } 225 226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 227 sizeof(page_sizes_prop)); 228 if (page_sizes_prop_size) { 229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 230 page_sizes_prop, page_sizes_prop_size))); 231 } 232 233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 234 pa_features, sizeof(pa_features)))); 235 236 /* Build interrupt servers properties */ 237 for (i = 0; i < smt_threads; i++) { 238 servers_prop[i] = cpu_to_be32(pc->pir + i); 239 } 240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 241 servers_prop, sizeof(servers_prop)))); 242 } 243 244 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 245 uint32_t nr_threads) 246 { 247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 248 char *name; 249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 250 uint32_t irange[2], i, rsize; 251 uint64_t *reg; 252 int offset; 253 254 irange[0] = cpu_to_be32(pir); 255 irange[1] = cpu_to_be32(nr_threads); 256 257 rsize = sizeof(uint64_t) * 2 * nr_threads; 258 reg = g_malloc(rsize); 259 for (i = 0; i < nr_threads; i++) { 260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 261 reg[i * 2 + 1] = cpu_to_be64(0x1000); 262 } 263 264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 265 offset = fdt_add_subnode(fdt, 0, name); 266 _FDT(offset); 267 g_free(name); 268 269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 271 _FDT((fdt_setprop_string(fdt, offset, "device_type", 272 "PowerPC-External-Interrupt-Presentation"))); 273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 275 irange, sizeof(irange)))); 276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 278 g_free(reg); 279 } 280 281 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 282 { 283 const char *typename = pnv_chip_core_typename(chip); 284 size_t typesize = object_type_get_instance_size(typename); 285 int i; 286 287 pnv_dt_xscom(chip, fdt, 0); 288 289 for (i = 0; i < chip->nr_cores; i++) { 290 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 291 292 pnv_dt_core(chip, pnv_core, fdt); 293 294 /* Interrupt Control Presenters (ICP). One per core. */ 295 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 296 } 297 298 if (chip->ram_size) { 299 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 300 } 301 } 302 303 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 304 { 305 const char *typename = pnv_chip_core_typename(chip); 306 size_t typesize = object_type_get_instance_size(typename); 307 int i; 308 309 pnv_dt_xscom(chip, fdt, 0); 310 311 for (i = 0; i < chip->nr_cores; i++) { 312 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 313 314 pnv_dt_core(chip, pnv_core, fdt); 315 } 316 317 if (chip->ram_size) { 318 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 319 } 320 321 pnv_dt_lpc(chip, fdt, 0); 322 } 323 324 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 325 { 326 uint32_t io_base = d->ioport_id; 327 uint32_t io_regs[] = { 328 cpu_to_be32(1), 329 cpu_to_be32(io_base), 330 cpu_to_be32(2) 331 }; 332 char *name; 333 int node; 334 335 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 336 node = fdt_add_subnode(fdt, lpc_off, name); 337 _FDT(node); 338 g_free(name); 339 340 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 341 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 342 } 343 344 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 345 { 346 const char compatible[] = "ns16550\0pnpPNP,501"; 347 uint32_t io_base = d->ioport_id; 348 uint32_t io_regs[] = { 349 cpu_to_be32(1), 350 cpu_to_be32(io_base), 351 cpu_to_be32(8) 352 }; 353 char *name; 354 int node; 355 356 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 357 node = fdt_add_subnode(fdt, lpc_off, name); 358 _FDT(node); 359 g_free(name); 360 361 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 362 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 363 sizeof(compatible)))); 364 365 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 366 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 367 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 368 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 369 fdt_get_phandle(fdt, lpc_off)))); 370 371 /* This is needed by Linux */ 372 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 373 } 374 375 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 376 { 377 const char compatible[] = "bt\0ipmi-bt"; 378 uint32_t io_base; 379 uint32_t io_regs[] = { 380 cpu_to_be32(1), 381 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 382 cpu_to_be32(3) 383 }; 384 uint32_t irq; 385 char *name; 386 int node; 387 388 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 389 io_regs[1] = cpu_to_be32(io_base); 390 391 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 392 393 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 394 node = fdt_add_subnode(fdt, lpc_off, name); 395 _FDT(node); 396 g_free(name); 397 398 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 399 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 400 sizeof(compatible)))); 401 402 /* Mark it as reserved to avoid Linux trying to claim it */ 403 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 404 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 405 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 406 fdt_get_phandle(fdt, lpc_off)))); 407 } 408 409 typedef struct ForeachPopulateArgs { 410 void *fdt; 411 int offset; 412 } ForeachPopulateArgs; 413 414 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 415 { 416 ForeachPopulateArgs *args = opaque; 417 ISADevice *d = ISA_DEVICE(dev); 418 419 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 420 pnv_dt_rtc(d, args->fdt, args->offset); 421 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 422 pnv_dt_serial(d, args->fdt, args->offset); 423 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 424 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 425 } else { 426 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 427 d->ioport_id); 428 } 429 430 return 0; 431 } 432 433 /* 434 * The default LPC bus of a multichip system is on chip 0. It's 435 * recognized by the firmware (skiboot) using a "primary" property. 436 */ 437 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 438 { 439 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 440 ForeachPopulateArgs args = { 441 .fdt = fdt, 442 .offset = isa_offset, 443 }; 444 uint32_t phandle; 445 446 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 447 448 phandle = qemu_fdt_alloc_phandle(fdt); 449 assert(phandle > 0); 450 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 451 452 /* 453 * ISA devices are not necessarily parented to the ISA bus so we 454 * can not use object_child_foreach() 455 */ 456 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 457 &args); 458 } 459 460 static void pnv_dt_power_mgt(void *fdt) 461 { 462 int off; 463 464 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 465 off = fdt_add_subnode(fdt, off, "power-mgt"); 466 467 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 468 } 469 470 static void *pnv_dt_create(MachineState *machine) 471 { 472 const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 473 const char plat_compat9[] = "qemu,powernv9\0ibm,powernv"; 474 PnvMachineState *pnv = PNV_MACHINE(machine); 475 void *fdt; 476 char *buf; 477 int off; 478 int i; 479 480 fdt = g_malloc0(FDT_MAX_SIZE); 481 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 482 483 /* Root node */ 484 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 485 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 486 _FDT((fdt_setprop_string(fdt, 0, "model", 487 "IBM PowerNV (emulated by qemu)"))); 488 if (pnv_is_power9(pnv)) { 489 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, 490 sizeof(plat_compat9)))); 491 } else { 492 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8, 493 sizeof(plat_compat8)))); 494 } 495 496 497 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 498 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 499 if (qemu_uuid_set) { 500 _FDT((fdt_property_string(fdt, "system-id", buf))); 501 } 502 g_free(buf); 503 504 off = fdt_add_subnode(fdt, 0, "chosen"); 505 if (machine->kernel_cmdline) { 506 _FDT((fdt_setprop_string(fdt, off, "bootargs", 507 machine->kernel_cmdline))); 508 } 509 510 if (pnv->initrd_size) { 511 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 512 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 513 514 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 515 &start_prop, sizeof(start_prop)))); 516 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 517 &end_prop, sizeof(end_prop)))); 518 } 519 520 /* Populate device tree for each chip */ 521 for (i = 0; i < pnv->num_chips; i++) { 522 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 523 } 524 525 /* Populate ISA devices on chip 0 */ 526 pnv_dt_isa(pnv, fdt); 527 528 if (pnv->bmc) { 529 pnv_dt_bmc_sensors(pnv->bmc, fdt); 530 } 531 532 /* Create an extra node for power management on Power9 */ 533 if (pnv_is_power9(pnv)) { 534 pnv_dt_power_mgt(fdt); 535 } 536 537 return fdt; 538 } 539 540 static void pnv_powerdown_notify(Notifier *n, void *opaque) 541 { 542 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 543 544 if (pnv->bmc) { 545 pnv_bmc_powerdown(pnv->bmc); 546 } 547 } 548 549 static void pnv_reset(MachineState *machine) 550 { 551 PnvMachineState *pnv = PNV_MACHINE(machine); 552 void *fdt; 553 Object *obj; 554 555 qemu_devices_reset(); 556 557 /* 558 * OpenPOWER systems have a BMC, which can be defined on the 559 * command line with: 560 * 561 * -device ipmi-bmc-sim,id=bmc0 562 * 563 * This is the internal simulator but it could also be an external 564 * BMC. 565 */ 566 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); 567 if (obj) { 568 pnv->bmc = IPMI_BMC(obj); 569 } 570 571 fdt = pnv_dt_create(machine); 572 573 /* Pack resulting tree */ 574 _FDT((fdt_pack(fdt))); 575 576 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 577 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 578 } 579 580 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 581 { 582 Pnv8Chip *chip8 = PNV8_CHIP(chip); 583 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 584 } 585 586 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 587 { 588 Pnv8Chip *chip8 = PNV8_CHIP(chip); 589 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 590 } 591 592 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 593 { 594 Pnv9Chip *chip9 = PNV9_CHIP(chip); 595 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 596 } 597 598 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 599 { 600 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 601 } 602 603 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 604 { 605 Pnv8Chip *chip8 = PNV8_CHIP(chip); 606 607 ics_pic_print_info(&chip8->psi.ics, mon); 608 } 609 610 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 611 { 612 Pnv9Chip *chip9 = PNV9_CHIP(chip); 613 614 pnv_xive_pic_print_info(&chip9->xive, mon); 615 pnv_psi_pic_print_info(&chip9->psi, mon); 616 } 617 618 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 619 { 620 PowerPCCPUClass *ppc_default = 621 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 622 PowerPCCPUClass *ppc = 623 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 624 625 return ppc_default->pvr_match(ppc_default, ppc->pvr); 626 } 627 628 static void pnv_init(MachineState *machine) 629 { 630 PnvMachineState *pnv = PNV_MACHINE(machine); 631 MachineClass *mc = MACHINE_GET_CLASS(machine); 632 MemoryRegion *ram; 633 char *fw_filename; 634 long fw_size; 635 int i; 636 char *chip_typename; 637 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 638 DeviceState *dev; 639 640 /* allocate RAM */ 641 if (machine->ram_size < (1 * GiB)) { 642 warn_report("skiboot may not work with < 1GB of RAM"); 643 } 644 645 ram = g_new(MemoryRegion, 1); 646 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 647 machine->ram_size); 648 memory_region_add_subregion(get_system_memory(), 0, ram); 649 650 /* 651 * Create our simple PNOR device 652 */ 653 dev = qdev_create(NULL, TYPE_PNV_PNOR); 654 if (pnor) { 655 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 656 &error_abort); 657 } 658 qdev_init_nofail(dev); 659 pnv->pnor = PNV_PNOR(dev); 660 661 /* load skiboot firmware */ 662 if (bios_name == NULL) { 663 bios_name = FW_FILE_NAME; 664 } 665 666 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 667 if (!fw_filename) { 668 error_report("Could not find OPAL firmware '%s'", bios_name); 669 exit(1); 670 } 671 672 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 673 if (fw_size < 0) { 674 error_report("Could not load OPAL firmware '%s'", fw_filename); 675 exit(1); 676 } 677 g_free(fw_filename); 678 679 /* load kernel */ 680 if (machine->kernel_filename) { 681 long kernel_size; 682 683 kernel_size = load_image_targphys(machine->kernel_filename, 684 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 685 if (kernel_size < 0) { 686 error_report("Could not load kernel '%s'", 687 machine->kernel_filename); 688 exit(1); 689 } 690 } 691 692 /* load initrd */ 693 if (machine->initrd_filename) { 694 pnv->initrd_base = INITRD_LOAD_ADDR; 695 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 696 pnv->initrd_base, INITRD_MAX_SIZE); 697 if (pnv->initrd_size < 0) { 698 error_report("Could not load initial ram disk '%s'", 699 machine->initrd_filename); 700 exit(1); 701 } 702 } 703 704 /* 705 * Check compatibility of the specified CPU with the machine 706 * default. 707 */ 708 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 709 error_report("invalid CPU model '%s' for %s machine", 710 machine->cpu_type, mc->name); 711 exit(1); 712 } 713 714 /* Create the processor chips */ 715 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 716 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 717 i, machine->cpu_type); 718 if (!object_class_by_name(chip_typename)) { 719 error_report("invalid chip model '%.*s' for %s machine", 720 i, machine->cpu_type, mc->name); 721 exit(1); 722 } 723 724 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 725 for (i = 0; i < pnv->num_chips; i++) { 726 char chip_name[32]; 727 Object *chip = object_new(chip_typename); 728 729 pnv->chips[i] = PNV_CHIP(chip); 730 731 /* 732 * TODO: put all the memory in one node on chip 0 until we find a 733 * way to specify different ranges for each chip 734 */ 735 if (i == 0) { 736 object_property_set_int(chip, machine->ram_size, "ram-size", 737 &error_fatal); 738 } 739 740 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 741 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 742 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 743 &error_fatal); 744 object_property_set_int(chip, machine->smp.cores, 745 "nr-cores", &error_fatal); 746 object_property_set_bool(chip, true, "realized", &error_fatal); 747 } 748 g_free(chip_typename); 749 750 /* Instantiate ISA bus on chip 0 */ 751 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 752 753 /* Create serial port */ 754 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 755 756 /* Create an RTC ISA device too */ 757 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 758 759 /* 760 * OpenPOWER systems use a IPMI SEL Event message to notify the 761 * host to powerdown 762 */ 763 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 764 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 765 } 766 767 /* 768 * 0:21 Reserved - Read as zeros 769 * 22:24 Chip ID 770 * 25:28 Core number 771 * 29:31 Thread ID 772 */ 773 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 774 { 775 return (chip->chip_id << 7) | (core_id << 3); 776 } 777 778 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 779 Error **errp) 780 { 781 Error *local_err = NULL; 782 Object *obj; 783 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 784 785 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 786 &local_err); 787 if (local_err) { 788 error_propagate(errp, local_err); 789 return; 790 } 791 792 pnv_cpu->intc = obj; 793 } 794 795 796 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 797 { 798 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 799 800 icp_reset(ICP(pnv_cpu->intc)); 801 } 802 803 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 804 { 805 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 806 807 icp_destroy(ICP(pnv_cpu->intc)); 808 pnv_cpu->intc = NULL; 809 } 810 811 /* 812 * 0:48 Reserved - Read as zeroes 813 * 49:52 Node ID 814 * 53:55 Chip ID 815 * 56 Reserved - Read as zero 816 * 57:61 Core number 817 * 62:63 Thread ID 818 * 819 * We only care about the lower bits. uint32_t is fine for the moment. 820 */ 821 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 822 { 823 return (chip->chip_id << 8) | (core_id << 2); 824 } 825 826 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 827 Error **errp) 828 { 829 Pnv9Chip *chip9 = PNV9_CHIP(chip); 830 Error *local_err = NULL; 831 Object *obj; 832 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 833 834 /* 835 * The core creates its interrupt presenter but the XIVE interrupt 836 * controller object is initialized afterwards. Hopefully, it's 837 * only used at runtime. 838 */ 839 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); 840 if (local_err) { 841 error_propagate(errp, local_err); 842 return; 843 } 844 845 pnv_cpu->intc = obj; 846 } 847 848 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 849 { 850 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 851 852 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 853 } 854 855 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 856 { 857 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 858 859 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 860 pnv_cpu->intc = NULL; 861 } 862 863 /* 864 * Allowed core identifiers on a POWER8 Processor Chip : 865 * 866 * <EX0 reserved> 867 * EX1 - Venice only 868 * EX2 - Venice only 869 * EX3 - Venice only 870 * EX4 871 * EX5 872 * EX6 873 * <EX7,8 reserved> <reserved> 874 * EX9 - Venice only 875 * EX10 - Venice only 876 * EX11 - Venice only 877 * EX12 878 * EX13 879 * EX14 880 * <EX15 reserved> 881 */ 882 #define POWER8E_CORE_MASK (0x7070ull) 883 #define POWER8_CORE_MASK (0x7e7eull) 884 885 /* 886 * POWER9 has 24 cores, ids starting at 0x0 887 */ 888 #define POWER9_CORE_MASK (0xffffffffffffffull) 889 890 static void pnv_chip_power8_instance_init(Object *obj) 891 { 892 Pnv8Chip *chip8 = PNV8_CHIP(obj); 893 894 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 895 TYPE_PNV8_PSI, &error_abort, NULL); 896 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 897 OBJECT(qdev_get_machine()), &error_abort); 898 899 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 900 TYPE_PNV8_LPC, &error_abort, NULL); 901 object_property_add_const_link(OBJECT(&chip8->lpc), "psi", 902 OBJECT(&chip8->psi), &error_abort); 903 904 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 905 TYPE_PNV8_OCC, &error_abort, NULL); 906 object_property_add_const_link(OBJECT(&chip8->occ), "psi", 907 OBJECT(&chip8->psi), &error_abort); 908 909 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 910 TYPE_PNV8_HOMER, &error_abort, NULL); 911 object_property_add_const_link(OBJECT(&chip8->homer), "chip", obj, 912 &error_abort); 913 } 914 915 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 916 { 917 PnvChip *chip = PNV_CHIP(chip8); 918 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 919 const char *typename = pnv_chip_core_typename(chip); 920 size_t typesize = object_type_get_instance_size(typename); 921 int i, j; 922 char *name; 923 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 924 925 name = g_strdup_printf("icp-%x", chip->chip_id); 926 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 927 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 928 g_free(name); 929 930 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 931 932 /* Map the ICP registers for each thread */ 933 for (i = 0; i < chip->nr_cores; i++) { 934 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 935 int core_hwid = CPU_CORE(pnv_core)->core_id; 936 937 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 938 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 939 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 940 941 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 942 &icp->mmio); 943 } 944 } 945 } 946 947 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 948 { 949 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 950 PnvChip *chip = PNV_CHIP(dev); 951 Pnv8Chip *chip8 = PNV8_CHIP(dev); 952 Pnv8Psi *psi8 = &chip8->psi; 953 Error *local_err = NULL; 954 955 /* XSCOM bridge is first */ 956 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 957 if (local_err) { 958 error_propagate(errp, local_err); 959 return; 960 } 961 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 962 963 pcc->parent_realize(dev, &local_err); 964 if (local_err) { 965 error_propagate(errp, local_err); 966 return; 967 } 968 969 /* Processor Service Interface (PSI) Host Bridge */ 970 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 971 "bar", &error_fatal); 972 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 973 if (local_err) { 974 error_propagate(errp, local_err); 975 return; 976 } 977 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 978 &PNV_PSI(psi8)->xscom_regs); 979 980 /* Create LPC controller */ 981 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 982 &error_fatal); 983 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 984 985 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 986 (uint64_t) PNV_XSCOM_BASE(chip), 987 PNV_XSCOM_LPC_BASE); 988 989 /* 990 * Interrupt Management Area. This is the memory region holding 991 * all the Interrupt Control Presenter (ICP) registers 992 */ 993 pnv_chip_icp_realize(chip8, &local_err); 994 if (local_err) { 995 error_propagate(errp, local_err); 996 return; 997 } 998 999 /* Create the simplified OCC model */ 1000 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1001 if (local_err) { 1002 error_propagate(errp, local_err); 1003 return; 1004 } 1005 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1006 1007 /* OCC SRAM model */ 1008 memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip), 1009 &chip8->occ.sram_regs); 1010 1011 /* HOMER */ 1012 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1013 &local_err); 1014 if (local_err) { 1015 error_propagate(errp, local_err); 1016 return; 1017 } 1018 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1019 &chip8->homer.regs); 1020 } 1021 1022 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1023 { 1024 DeviceClass *dc = DEVICE_CLASS(klass); 1025 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1026 1027 k->chip_type = PNV_CHIP_POWER8E; 1028 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1029 k->cores_mask = POWER8E_CORE_MASK; 1030 k->core_pir = pnv_chip_core_pir_p8; 1031 k->intc_create = pnv_chip_power8_intc_create; 1032 k->intc_reset = pnv_chip_power8_intc_reset; 1033 k->intc_destroy = pnv_chip_power8_intc_destroy; 1034 k->isa_create = pnv_chip_power8_isa_create; 1035 k->dt_populate = pnv_chip_power8_dt_populate; 1036 k->pic_print_info = pnv_chip_power8_pic_print_info; 1037 dc->desc = "PowerNV Chip POWER8E"; 1038 1039 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1040 &k->parent_realize); 1041 } 1042 1043 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1044 { 1045 DeviceClass *dc = DEVICE_CLASS(klass); 1046 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1047 1048 k->chip_type = PNV_CHIP_POWER8; 1049 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1050 k->cores_mask = POWER8_CORE_MASK; 1051 k->core_pir = pnv_chip_core_pir_p8; 1052 k->intc_create = pnv_chip_power8_intc_create; 1053 k->intc_reset = pnv_chip_power8_intc_reset; 1054 k->intc_destroy = pnv_chip_power8_intc_destroy; 1055 k->isa_create = pnv_chip_power8_isa_create; 1056 k->dt_populate = pnv_chip_power8_dt_populate; 1057 k->pic_print_info = pnv_chip_power8_pic_print_info; 1058 dc->desc = "PowerNV Chip POWER8"; 1059 1060 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1061 &k->parent_realize); 1062 } 1063 1064 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1065 { 1066 DeviceClass *dc = DEVICE_CLASS(klass); 1067 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1068 1069 k->chip_type = PNV_CHIP_POWER8NVL; 1070 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1071 k->cores_mask = POWER8_CORE_MASK; 1072 k->core_pir = pnv_chip_core_pir_p8; 1073 k->intc_create = pnv_chip_power8_intc_create; 1074 k->intc_reset = pnv_chip_power8_intc_reset; 1075 k->intc_destroy = pnv_chip_power8_intc_destroy; 1076 k->isa_create = pnv_chip_power8nvl_isa_create; 1077 k->dt_populate = pnv_chip_power8_dt_populate; 1078 k->pic_print_info = pnv_chip_power8_pic_print_info; 1079 dc->desc = "PowerNV Chip POWER8NVL"; 1080 1081 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1082 &k->parent_realize); 1083 } 1084 1085 static void pnv_chip_power9_instance_init(Object *obj) 1086 { 1087 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1088 1089 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1090 TYPE_PNV_XIVE, &error_abort, NULL); 1091 object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj, 1092 &error_abort); 1093 1094 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1095 TYPE_PNV9_PSI, &error_abort, NULL); 1096 object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj, 1097 &error_abort); 1098 1099 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1100 TYPE_PNV9_LPC, &error_abort, NULL); 1101 object_property_add_const_link(OBJECT(&chip9->lpc), "psi", 1102 OBJECT(&chip9->psi), &error_abort); 1103 1104 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1105 TYPE_PNV9_OCC, &error_abort, NULL); 1106 object_property_add_const_link(OBJECT(&chip9->occ), "psi", 1107 OBJECT(&chip9->psi), &error_abort); 1108 1109 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1110 TYPE_PNV9_HOMER, &error_abort, NULL); 1111 object_property_add_const_link(OBJECT(&chip9->homer), "chip", obj, 1112 &error_abort); 1113 } 1114 1115 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1116 { 1117 PnvChip *chip = PNV_CHIP(chip9); 1118 const char *typename = pnv_chip_core_typename(chip); 1119 size_t typesize = object_type_get_instance_size(typename); 1120 int i; 1121 1122 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1123 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1124 1125 for (i = 0; i < chip9->nr_quads; i++) { 1126 char eq_name[32]; 1127 PnvQuad *eq = &chip9->quads[i]; 1128 PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize); 1129 int core_id = CPU_CORE(pnv_core)->core_id; 1130 1131 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1132 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1133 TYPE_PNV_QUAD, &error_fatal, NULL); 1134 1135 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1136 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1137 1138 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1139 &eq->xscom_regs); 1140 } 1141 } 1142 1143 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1144 { 1145 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1146 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1147 PnvChip *chip = PNV_CHIP(dev); 1148 Pnv9Psi *psi9 = &chip9->psi; 1149 Error *local_err = NULL; 1150 1151 /* XSCOM bridge is first */ 1152 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1153 if (local_err) { 1154 error_propagate(errp, local_err); 1155 return; 1156 } 1157 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1158 1159 pcc->parent_realize(dev, &local_err); 1160 if (local_err) { 1161 error_propagate(errp, local_err); 1162 return; 1163 } 1164 1165 pnv_chip_quad_realize(chip9, &local_err); 1166 if (local_err) { 1167 error_propagate(errp, local_err); 1168 return; 1169 } 1170 1171 /* XIVE interrupt controller (POWER9) */ 1172 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1173 "ic-bar", &error_fatal); 1174 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1175 "vc-bar", &error_fatal); 1176 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1177 "pc-bar", &error_fatal); 1178 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1179 "tm-bar", &error_fatal); 1180 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1181 &local_err); 1182 if (local_err) { 1183 error_propagate(errp, local_err); 1184 return; 1185 } 1186 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1187 &chip9->xive.xscom_regs); 1188 1189 /* Processor Service Interface (PSI) Host Bridge */ 1190 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1191 "bar", &error_fatal); 1192 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1193 if (local_err) { 1194 error_propagate(errp, local_err); 1195 return; 1196 } 1197 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1198 &PNV_PSI(psi9)->xscom_regs); 1199 1200 /* LPC */ 1201 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1202 if (local_err) { 1203 error_propagate(errp, local_err); 1204 return; 1205 } 1206 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1207 &chip9->lpc.xscom_regs); 1208 1209 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1210 (uint64_t) PNV9_LPCM_BASE(chip)); 1211 1212 /* Create the simplified OCC model */ 1213 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1214 if (local_err) { 1215 error_propagate(errp, local_err); 1216 return; 1217 } 1218 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1219 1220 /* OCC SRAM model */ 1221 memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip), 1222 &chip9->occ.sram_regs); 1223 1224 /* HOMER */ 1225 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1226 &local_err); 1227 if (local_err) { 1228 error_propagate(errp, local_err); 1229 return; 1230 } 1231 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1232 &chip9->homer.regs); 1233 } 1234 1235 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1236 { 1237 DeviceClass *dc = DEVICE_CLASS(klass); 1238 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1239 1240 k->chip_type = PNV_CHIP_POWER9; 1241 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1242 k->cores_mask = POWER9_CORE_MASK; 1243 k->core_pir = pnv_chip_core_pir_p9; 1244 k->intc_create = pnv_chip_power9_intc_create; 1245 k->intc_reset = pnv_chip_power9_intc_reset; 1246 k->intc_destroy = pnv_chip_power9_intc_destroy; 1247 k->isa_create = pnv_chip_power9_isa_create; 1248 k->dt_populate = pnv_chip_power9_dt_populate; 1249 k->pic_print_info = pnv_chip_power9_pic_print_info; 1250 dc->desc = "PowerNV Chip POWER9"; 1251 1252 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1253 &k->parent_realize); 1254 } 1255 1256 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1257 { 1258 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1259 int cores_max; 1260 1261 /* 1262 * No custom mask for this chip, let's use the default one from * 1263 * the chip class 1264 */ 1265 if (!chip->cores_mask) { 1266 chip->cores_mask = pcc->cores_mask; 1267 } 1268 1269 /* filter alien core ids ! some are reserved */ 1270 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1271 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1272 chip->cores_mask); 1273 return; 1274 } 1275 chip->cores_mask &= pcc->cores_mask; 1276 1277 /* now that we have a sane layout, let check the number of cores */ 1278 cores_max = ctpop64(chip->cores_mask); 1279 if (chip->nr_cores > cores_max) { 1280 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1281 cores_max); 1282 return; 1283 } 1284 } 1285 1286 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1287 { 1288 MachineState *ms = MACHINE(qdev_get_machine()); 1289 Error *error = NULL; 1290 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1291 const char *typename = pnv_chip_core_typename(chip); 1292 size_t typesize = object_type_get_instance_size(typename); 1293 int i, core_hwid; 1294 1295 if (!object_class_by_name(typename)) { 1296 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1297 return; 1298 } 1299 1300 /* Cores */ 1301 pnv_chip_core_sanitize(chip, &error); 1302 if (error) { 1303 error_propagate(errp, error); 1304 return; 1305 } 1306 1307 chip->cores = g_malloc0(typesize * chip->nr_cores); 1308 1309 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1310 && (i < chip->nr_cores); core_hwid++) { 1311 char core_name[32]; 1312 void *pnv_core = chip->cores + i * typesize; 1313 uint64_t xscom_core_base; 1314 1315 if (!(chip->cores_mask & (1ull << core_hwid))) { 1316 continue; 1317 } 1318 1319 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1320 object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize, 1321 typename, &error_fatal, NULL); 1322 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", 1323 &error_fatal); 1324 object_property_set_int(OBJECT(pnv_core), core_hwid, 1325 CPU_CORE_PROP_CORE_ID, &error_fatal); 1326 object_property_set_int(OBJECT(pnv_core), 1327 pcc->core_pir(chip, core_hwid), 1328 "pir", &error_fatal); 1329 object_property_add_const_link(OBJECT(pnv_core), "chip", 1330 OBJECT(chip), &error_fatal); 1331 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1332 &error_fatal); 1333 1334 /* Each core has an XSCOM MMIO region */ 1335 if (!pnv_chip_is_power9(chip)) { 1336 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); 1337 } else { 1338 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); 1339 } 1340 1341 pnv_xscom_add_subregion(chip, xscom_core_base, 1342 &PNV_CORE(pnv_core)->xscom_regs); 1343 i++; 1344 } 1345 } 1346 1347 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1348 { 1349 PnvChip *chip = PNV_CHIP(dev); 1350 Error *error = NULL; 1351 1352 /* Cores */ 1353 pnv_chip_core_realize(chip, &error); 1354 if (error) { 1355 error_propagate(errp, error); 1356 return; 1357 } 1358 } 1359 1360 static Property pnv_chip_properties[] = { 1361 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1362 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1363 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1364 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1365 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1366 DEFINE_PROP_END_OF_LIST(), 1367 }; 1368 1369 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1370 { 1371 DeviceClass *dc = DEVICE_CLASS(klass); 1372 1373 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1374 dc->realize = pnv_chip_realize; 1375 dc->props = pnv_chip_properties; 1376 dc->desc = "PowerNV Chip"; 1377 } 1378 1379 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1380 { 1381 PnvMachineState *pnv = PNV_MACHINE(xi); 1382 int i; 1383 1384 for (i = 0; i < pnv->num_chips; i++) { 1385 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1386 1387 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1388 return &chip8->psi.ics; 1389 } 1390 } 1391 return NULL; 1392 } 1393 1394 static void pnv_ics_resend(XICSFabric *xi) 1395 { 1396 PnvMachineState *pnv = PNV_MACHINE(xi); 1397 int i; 1398 1399 for (i = 0; i < pnv->num_chips; i++) { 1400 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1401 ics_resend(&chip8->psi.ics); 1402 } 1403 } 1404 1405 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1406 { 1407 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1408 1409 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1410 } 1411 1412 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1413 Monitor *mon) 1414 { 1415 PnvMachineState *pnv = PNV_MACHINE(obj); 1416 int i; 1417 CPUState *cs; 1418 1419 CPU_FOREACH(cs) { 1420 PowerPCCPU *cpu = POWERPC_CPU(cs); 1421 1422 if (pnv_chip_is_power9(pnv->chips[0])) { 1423 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1424 } else { 1425 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1426 } 1427 } 1428 1429 for (i = 0; i < pnv->num_chips; i++) { 1430 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1431 } 1432 } 1433 1434 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1435 void *opaque, Error **errp) 1436 { 1437 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1438 } 1439 1440 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1441 void *opaque, Error **errp) 1442 { 1443 PnvMachineState *pnv = PNV_MACHINE(obj); 1444 uint32_t num_chips; 1445 Error *local_err = NULL; 1446 1447 visit_type_uint32(v, name, &num_chips, &local_err); 1448 if (local_err) { 1449 error_propagate(errp, local_err); 1450 return; 1451 } 1452 1453 /* 1454 * TODO: should we decide on how many chips we can create based 1455 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1456 */ 1457 if (!is_power_of_2(num_chips) || num_chips > 4) { 1458 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1459 return; 1460 } 1461 1462 pnv->num_chips = num_chips; 1463 } 1464 1465 static void pnv_machine_instance_init(Object *obj) 1466 { 1467 PnvMachineState *pnv = PNV_MACHINE(obj); 1468 pnv->num_chips = 1; 1469 } 1470 1471 static void pnv_machine_class_props_init(ObjectClass *oc) 1472 { 1473 object_class_property_add(oc, "num-chips", "uint32", 1474 pnv_get_num_chips, pnv_set_num_chips, 1475 NULL, NULL, NULL); 1476 object_class_property_set_description(oc, "num-chips", 1477 "Specifies the number of processor chips", 1478 NULL); 1479 } 1480 1481 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1482 { 1483 MachineClass *mc = MACHINE_CLASS(oc); 1484 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1485 1486 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1487 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1488 1489 xic->icp_get = pnv_icp_get; 1490 xic->ics_get = pnv_ics_get; 1491 xic->ics_resend = pnv_ics_resend; 1492 } 1493 1494 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1495 { 1496 MachineClass *mc = MACHINE_CLASS(oc); 1497 1498 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1499 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1500 1501 mc->alias = "powernv"; 1502 } 1503 1504 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1505 { 1506 MachineClass *mc = MACHINE_CLASS(oc); 1507 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1508 1509 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1510 mc->init = pnv_init; 1511 mc->reset = pnv_reset; 1512 mc->max_cpus = MAX_CPUS; 1513 /* Pnv provides a AHCI device for storage */ 1514 mc->block_default_type = IF_IDE; 1515 mc->no_parallel = 1; 1516 mc->default_boot_order = NULL; 1517 /* 1518 * RAM defaults to less than 2048 for 32-bit hosts, and large 1519 * enough to fit the maximum initrd size at it's load address 1520 */ 1521 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1522 ispc->print_info = pnv_pic_print_info; 1523 1524 pnv_machine_class_props_init(oc); 1525 } 1526 1527 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1528 { \ 1529 .name = type, \ 1530 .class_init = class_initfn, \ 1531 .parent = TYPE_PNV8_CHIP, \ 1532 } 1533 1534 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1535 { \ 1536 .name = type, \ 1537 .class_init = class_initfn, \ 1538 .parent = TYPE_PNV9_CHIP, \ 1539 } 1540 1541 static const TypeInfo types[] = { 1542 { 1543 .name = MACHINE_TYPE_NAME("powernv9"), 1544 .parent = TYPE_PNV_MACHINE, 1545 .class_init = pnv_machine_power9_class_init, 1546 }, 1547 { 1548 .name = MACHINE_TYPE_NAME("powernv8"), 1549 .parent = TYPE_PNV_MACHINE, 1550 .class_init = pnv_machine_power8_class_init, 1551 .interfaces = (InterfaceInfo[]) { 1552 { TYPE_XICS_FABRIC }, 1553 { }, 1554 }, 1555 }, 1556 { 1557 .name = TYPE_PNV_MACHINE, 1558 .parent = TYPE_MACHINE, 1559 .abstract = true, 1560 .instance_size = sizeof(PnvMachineState), 1561 .instance_init = pnv_machine_instance_init, 1562 .class_init = pnv_machine_class_init, 1563 .interfaces = (InterfaceInfo[]) { 1564 { TYPE_INTERRUPT_STATS_PROVIDER }, 1565 { }, 1566 }, 1567 }, 1568 { 1569 .name = TYPE_PNV_CHIP, 1570 .parent = TYPE_SYS_BUS_DEVICE, 1571 .class_init = pnv_chip_class_init, 1572 .instance_size = sizeof(PnvChip), 1573 .class_size = sizeof(PnvChipClass), 1574 .abstract = true, 1575 }, 1576 1577 /* 1578 * P9 chip and variants 1579 */ 1580 { 1581 .name = TYPE_PNV9_CHIP, 1582 .parent = TYPE_PNV_CHIP, 1583 .instance_init = pnv_chip_power9_instance_init, 1584 .instance_size = sizeof(Pnv9Chip), 1585 }, 1586 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1587 1588 /* 1589 * P8 chip and variants 1590 */ 1591 { 1592 .name = TYPE_PNV8_CHIP, 1593 .parent = TYPE_PNV_CHIP, 1594 .instance_init = pnv_chip_power8_instance_init, 1595 .instance_size = sizeof(Pnv8Chip), 1596 }, 1597 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1598 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1599 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1600 pnv_chip_power8nvl_class_init), 1601 }; 1602 1603 DEFINE_TYPES(types) 1604