1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 44 #include "hw/ppc/xics.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/ppc/pnv_xscom.h" 47 #include "hw/ppc/pnv_pnor.h" 48 49 #include "hw/isa/isa.h" 50 #include "hw/boards.h" 51 #include "hw/char/serial.h" 52 #include "hw/rtc/mc146818rtc.h" 53 54 #include <libfdt.h> 55 56 #define FDT_MAX_SIZE (1 * MiB) 57 58 #define FW_FILE_NAME "skiboot.lid" 59 #define FW_LOAD_ADDR 0x0 60 #define FW_MAX_SIZE (4 * MiB) 61 62 #define KERNEL_LOAD_ADDR 0x20000000 63 #define KERNEL_MAX_SIZE (256 * MiB) 64 #define INITRD_LOAD_ADDR 0x60000000 65 #define INITRD_MAX_SIZE (256 * MiB) 66 67 static const char *pnv_chip_core_typename(const PnvChip *o) 68 { 69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 72 const char *core_type = object_class_get_name(object_class_by_name(s)); 73 g_free(s); 74 return core_type; 75 } 76 77 /* 78 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 79 * 4 * 4 sockets * 12 cores * 8 threads = 1536 80 * Let's make it 2^11 81 */ 82 #define MAX_CPUS 2048 83 84 /* 85 * Memory nodes are created by hostboot, one for each range of memory 86 * that has a different "affinity". In practice, it means one range 87 * per chip. 88 */ 89 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 90 { 91 char *mem_name; 92 uint64_t mem_reg_property[2]; 93 int off; 94 95 mem_reg_property[0] = cpu_to_be64(start); 96 mem_reg_property[1] = cpu_to_be64(size); 97 98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 99 off = fdt_add_subnode(fdt, 0, mem_name); 100 g_free(mem_name); 101 102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 104 sizeof(mem_reg_property)))); 105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 106 } 107 108 static int get_cpus_node(void *fdt) 109 { 110 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 111 112 if (cpus_offset < 0) { 113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 114 if (cpus_offset) { 115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 117 } 118 } 119 _FDT(cpus_offset); 120 return cpus_offset; 121 } 122 123 /* 124 * The PowerNV cores (and threads) need to use real HW ids and not an 125 * incremental index like it has been done on other platforms. This HW 126 * id is stored in the CPU PIR, it is used to create cpu nodes in the 127 * device tree, used in XSCOM to address cores and in interrupt 128 * servers. 129 */ 130 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 131 { 132 PowerPCCPU *cpu = pc->threads[0]; 133 CPUState *cs = CPU(cpu); 134 DeviceClass *dc = DEVICE_GET_CLASS(cs); 135 int smt_threads = CPU_CORE(pc)->nr_threads; 136 CPUPPCState *env = &cpu->env; 137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 138 uint32_t servers_prop[smt_threads]; 139 int i; 140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 141 0xffffffff, 0xffffffff}; 142 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 143 uint32_t cpufreq = 1000000000; 144 uint32_t page_sizes_prop[64]; 145 size_t page_sizes_prop_size; 146 const uint8_t pa_features[] = { 24, 0, 147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 151 int offset; 152 char *nodename; 153 int cpus_offset = get_cpus_node(fdt); 154 155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 156 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 157 _FDT(offset); 158 g_free(nodename); 159 160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 161 162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 168 env->dcache_line_size))); 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 170 env->dcache_line_size))); 171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 172 env->icache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 174 env->icache_line_size))); 175 176 if (pcc->l1_dcache_size) { 177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 178 pcc->l1_dcache_size))); 179 } else { 180 warn_report("Unknown L1 dcache size for cpu"); 181 } 182 if (pcc->l1_icache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 184 pcc->l1_icache_size))); 185 } else { 186 warn_report("Unknown L1 icache size for cpu"); 187 } 188 189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 192 cpu->hash64_opts->slb_size))); 193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 195 196 if (env->spr_cb[SPR_PURR].oea_read) { 197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 198 } 199 200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 202 segs, sizeof(segs)))); 203 } 204 205 /* 206 * Advertise VMX/VSX (vector extensions) if available 207 * 0 / no property == no vector extensions 208 * 1 == VMX / Altivec available 209 * 2 == VSX available 210 */ 211 if (env->insns_flags & PPC_ALTIVEC) { 212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 213 214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 215 } 216 217 /* 218 * Advertise DFP (Decimal Floating Point) if available 219 * 0 / no property == no DFP 220 * 1 == DFP available 221 */ 222 if (env->insns_flags2 & PPC2_DFP) { 223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 224 } 225 226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 227 sizeof(page_sizes_prop)); 228 if (page_sizes_prop_size) { 229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 230 page_sizes_prop, page_sizes_prop_size))); 231 } 232 233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 234 pa_features, sizeof(pa_features)))); 235 236 /* Build interrupt servers properties */ 237 for (i = 0; i < smt_threads; i++) { 238 servers_prop[i] = cpu_to_be32(pc->pir + i); 239 } 240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 241 servers_prop, sizeof(servers_prop)))); 242 } 243 244 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 245 uint32_t nr_threads) 246 { 247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 248 char *name; 249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 250 uint32_t irange[2], i, rsize; 251 uint64_t *reg; 252 int offset; 253 254 irange[0] = cpu_to_be32(pir); 255 irange[1] = cpu_to_be32(nr_threads); 256 257 rsize = sizeof(uint64_t) * 2 * nr_threads; 258 reg = g_malloc(rsize); 259 for (i = 0; i < nr_threads; i++) { 260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 261 reg[i * 2 + 1] = cpu_to_be64(0x1000); 262 } 263 264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 265 offset = fdt_add_subnode(fdt, 0, name); 266 _FDT(offset); 267 g_free(name); 268 269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 271 _FDT((fdt_setprop_string(fdt, offset, "device_type", 272 "PowerPC-External-Interrupt-Presentation"))); 273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 275 irange, sizeof(irange)))); 276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 278 g_free(reg); 279 } 280 281 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 282 { 283 int i; 284 285 pnv_dt_xscom(chip, fdt, 0); 286 287 for (i = 0; i < chip->nr_cores; i++) { 288 PnvCore *pnv_core = chip->cores[i]; 289 290 pnv_dt_core(chip, pnv_core, fdt); 291 292 /* Interrupt Control Presenters (ICP). One per core. */ 293 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 294 } 295 296 if (chip->ram_size) { 297 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 298 } 299 } 300 301 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 302 { 303 int i; 304 305 pnv_dt_xscom(chip, fdt, 0); 306 307 for (i = 0; i < chip->nr_cores; i++) { 308 PnvCore *pnv_core = chip->cores[i]; 309 310 pnv_dt_core(chip, pnv_core, fdt); 311 } 312 313 if (chip->ram_size) { 314 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 315 } 316 317 pnv_dt_lpc(chip, fdt, 0); 318 } 319 320 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 321 { 322 int i; 323 324 pnv_dt_xscom(chip, fdt, 0); 325 326 for (i = 0; i < chip->nr_cores; i++) { 327 PnvCore *pnv_core = chip->cores[i]; 328 329 pnv_dt_core(chip, pnv_core, fdt); 330 } 331 332 if (chip->ram_size) { 333 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 334 } 335 } 336 337 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 338 { 339 uint32_t io_base = d->ioport_id; 340 uint32_t io_regs[] = { 341 cpu_to_be32(1), 342 cpu_to_be32(io_base), 343 cpu_to_be32(2) 344 }; 345 char *name; 346 int node; 347 348 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 349 node = fdt_add_subnode(fdt, lpc_off, name); 350 _FDT(node); 351 g_free(name); 352 353 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 354 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 355 } 356 357 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 358 { 359 const char compatible[] = "ns16550\0pnpPNP,501"; 360 uint32_t io_base = d->ioport_id; 361 uint32_t io_regs[] = { 362 cpu_to_be32(1), 363 cpu_to_be32(io_base), 364 cpu_to_be32(8) 365 }; 366 char *name; 367 int node; 368 369 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 370 node = fdt_add_subnode(fdt, lpc_off, name); 371 _FDT(node); 372 g_free(name); 373 374 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 375 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 376 sizeof(compatible)))); 377 378 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 379 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 380 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 381 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 382 fdt_get_phandle(fdt, lpc_off)))); 383 384 /* This is needed by Linux */ 385 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 386 } 387 388 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 389 { 390 const char compatible[] = "bt\0ipmi-bt"; 391 uint32_t io_base; 392 uint32_t io_regs[] = { 393 cpu_to_be32(1), 394 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 395 cpu_to_be32(3) 396 }; 397 uint32_t irq; 398 char *name; 399 int node; 400 401 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 402 io_regs[1] = cpu_to_be32(io_base); 403 404 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 405 406 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 407 node = fdt_add_subnode(fdt, lpc_off, name); 408 _FDT(node); 409 g_free(name); 410 411 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 412 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 413 sizeof(compatible)))); 414 415 /* Mark it as reserved to avoid Linux trying to claim it */ 416 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 417 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 418 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 419 fdt_get_phandle(fdt, lpc_off)))); 420 } 421 422 typedef struct ForeachPopulateArgs { 423 void *fdt; 424 int offset; 425 } ForeachPopulateArgs; 426 427 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 428 { 429 ForeachPopulateArgs *args = opaque; 430 ISADevice *d = ISA_DEVICE(dev); 431 432 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 433 pnv_dt_rtc(d, args->fdt, args->offset); 434 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 435 pnv_dt_serial(d, args->fdt, args->offset); 436 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 437 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 438 } else { 439 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 440 d->ioport_id); 441 } 442 443 return 0; 444 } 445 446 /* 447 * The default LPC bus of a multichip system is on chip 0. It's 448 * recognized by the firmware (skiboot) using a "primary" property. 449 */ 450 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 451 { 452 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 453 ForeachPopulateArgs args = { 454 .fdt = fdt, 455 .offset = isa_offset, 456 }; 457 uint32_t phandle; 458 459 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 460 461 phandle = qemu_fdt_alloc_phandle(fdt); 462 assert(phandle > 0); 463 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 464 465 /* 466 * ISA devices are not necessarily parented to the ISA bus so we 467 * can not use object_child_foreach() 468 */ 469 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 470 &args); 471 } 472 473 static void pnv_dt_power_mgt(void *fdt) 474 { 475 int off; 476 477 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 478 off = fdt_add_subnode(fdt, off, "power-mgt"); 479 480 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 481 } 482 483 static void *pnv_dt_create(MachineState *machine) 484 { 485 const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 486 const char plat_compat9[] = "qemu,powernv9\0ibm,powernv"; 487 const char plat_compat10[] = "qemu,powernv10\0ibm,powernv"; 488 PnvMachineState *pnv = PNV_MACHINE(machine); 489 void *fdt; 490 char *buf; 491 int off; 492 int i; 493 494 fdt = g_malloc0(FDT_MAX_SIZE); 495 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 496 497 /* /qemu node */ 498 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 499 500 /* Root node */ 501 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 502 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 503 _FDT((fdt_setprop_string(fdt, 0, "model", 504 "IBM PowerNV (emulated by qemu)"))); 505 if (pnv_is_power10(pnv)) { 506 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat10, 507 sizeof(plat_compat10)))); 508 } else if (pnv_is_power9(pnv)) { 509 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, 510 sizeof(plat_compat9)))); 511 } else { 512 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8, 513 sizeof(plat_compat8)))); 514 } 515 516 517 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 518 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 519 if (qemu_uuid_set) { 520 _FDT((fdt_property_string(fdt, "system-id", buf))); 521 } 522 g_free(buf); 523 524 off = fdt_add_subnode(fdt, 0, "chosen"); 525 if (machine->kernel_cmdline) { 526 _FDT((fdt_setprop_string(fdt, off, "bootargs", 527 machine->kernel_cmdline))); 528 } 529 530 if (pnv->initrd_size) { 531 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 532 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 533 534 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 535 &start_prop, sizeof(start_prop)))); 536 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 537 &end_prop, sizeof(end_prop)))); 538 } 539 540 /* Populate device tree for each chip */ 541 for (i = 0; i < pnv->num_chips; i++) { 542 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 543 } 544 545 /* Populate ISA devices on chip 0 */ 546 pnv_dt_isa(pnv, fdt); 547 548 if (pnv->bmc) { 549 pnv_dt_bmc_sensors(pnv->bmc, fdt); 550 } 551 552 /* Create an extra node for power management on Power9 and Power10 */ 553 if (pnv_is_power9(pnv) || pnv_is_power10(pnv)) { 554 pnv_dt_power_mgt(fdt); 555 } 556 557 return fdt; 558 } 559 560 static void pnv_powerdown_notify(Notifier *n, void *opaque) 561 { 562 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 563 564 if (pnv->bmc) { 565 pnv_bmc_powerdown(pnv->bmc); 566 } 567 } 568 569 static void pnv_reset(MachineState *machine) 570 { 571 void *fdt; 572 573 qemu_devices_reset(); 574 575 fdt = pnv_dt_create(machine); 576 577 /* Pack resulting tree */ 578 _FDT((fdt_pack(fdt))); 579 580 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 581 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 582 } 583 584 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 585 { 586 Pnv8Chip *chip8 = PNV8_CHIP(chip); 587 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 588 } 589 590 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 591 { 592 Pnv8Chip *chip8 = PNV8_CHIP(chip); 593 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 594 } 595 596 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 597 { 598 Pnv9Chip *chip9 = PNV9_CHIP(chip); 599 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 600 } 601 602 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 603 { 604 error_setg(errp, "No ISA bus!"); 605 return NULL; 606 } 607 608 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 609 { 610 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 611 } 612 613 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 614 { 615 Pnv8Chip *chip8 = PNV8_CHIP(chip); 616 617 ics_pic_print_info(&chip8->psi.ics, mon); 618 } 619 620 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 621 { 622 Pnv9Chip *chip9 = PNV9_CHIP(chip); 623 624 pnv_xive_pic_print_info(&chip9->xive, mon); 625 pnv_psi_pic_print_info(&chip9->psi, mon); 626 } 627 628 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 629 { 630 PowerPCCPUClass *ppc_default = 631 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 632 PowerPCCPUClass *ppc = 633 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 634 635 return ppc_default->pvr_match(ppc_default, ppc->pvr); 636 } 637 638 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 639 { 640 Object *obj; 641 642 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 643 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 644 object_property_set_int(obj, irq, "irq", &error_fatal); 645 object_property_set_bool(obj, true, "realized", &error_fatal); 646 } 647 648 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 649 { 650 /* 651 * No interrupt controller yet 652 */; 653 } 654 655 static void pnv_init(MachineState *machine) 656 { 657 PnvMachineState *pnv = PNV_MACHINE(machine); 658 MachineClass *mc = MACHINE_GET_CLASS(machine); 659 MemoryRegion *ram; 660 char *fw_filename; 661 long fw_size; 662 int i; 663 char *chip_typename; 664 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 665 DeviceState *dev; 666 667 /* allocate RAM */ 668 if (machine->ram_size < (1 * GiB)) { 669 warn_report("skiboot may not work with < 1GB of RAM"); 670 } 671 672 ram = g_new(MemoryRegion, 1); 673 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 674 machine->ram_size); 675 memory_region_add_subregion(get_system_memory(), 0, ram); 676 677 /* 678 * Create our simple PNOR device 679 */ 680 dev = qdev_create(NULL, TYPE_PNV_PNOR); 681 if (pnor) { 682 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 683 &error_abort); 684 } 685 qdev_init_nofail(dev); 686 pnv->pnor = PNV_PNOR(dev); 687 688 /* load skiboot firmware */ 689 if (bios_name == NULL) { 690 bios_name = FW_FILE_NAME; 691 } 692 693 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 694 if (!fw_filename) { 695 error_report("Could not find OPAL firmware '%s'", bios_name); 696 exit(1); 697 } 698 699 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 700 if (fw_size < 0) { 701 error_report("Could not load OPAL firmware '%s'", fw_filename); 702 exit(1); 703 } 704 g_free(fw_filename); 705 706 /* load kernel */ 707 if (machine->kernel_filename) { 708 long kernel_size; 709 710 kernel_size = load_image_targphys(machine->kernel_filename, 711 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 712 if (kernel_size < 0) { 713 error_report("Could not load kernel '%s'", 714 machine->kernel_filename); 715 exit(1); 716 } 717 } 718 719 /* load initrd */ 720 if (machine->initrd_filename) { 721 pnv->initrd_base = INITRD_LOAD_ADDR; 722 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 723 pnv->initrd_base, INITRD_MAX_SIZE); 724 if (pnv->initrd_size < 0) { 725 error_report("Could not load initial ram disk '%s'", 726 machine->initrd_filename); 727 exit(1); 728 } 729 } 730 731 /* 732 * Check compatibility of the specified CPU with the machine 733 * default. 734 */ 735 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 736 error_report("invalid CPU model '%s' for %s machine", 737 machine->cpu_type, mc->name); 738 exit(1); 739 } 740 741 /* Create the processor chips */ 742 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 743 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 744 i, machine->cpu_type); 745 if (!object_class_by_name(chip_typename)) { 746 error_report("invalid chip model '%.*s' for %s machine", 747 i, machine->cpu_type, mc->name); 748 exit(1); 749 } 750 751 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 752 for (i = 0; i < pnv->num_chips; i++) { 753 char chip_name[32]; 754 Object *chip = object_new(chip_typename); 755 756 pnv->chips[i] = PNV_CHIP(chip); 757 758 /* 759 * TODO: put all the memory in one node on chip 0 until we find a 760 * way to specify different ranges for each chip 761 */ 762 if (i == 0) { 763 object_property_set_int(chip, machine->ram_size, "ram-size", 764 &error_fatal); 765 } 766 767 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 768 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 769 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 770 &error_fatal); 771 object_property_set_int(chip, machine->smp.cores, 772 "nr-cores", &error_fatal); 773 object_property_set_bool(chip, true, "realized", &error_fatal); 774 } 775 g_free(chip_typename); 776 777 /* Create the machine BMC simulator */ 778 pnv->bmc = pnv_bmc_create(); 779 780 /* Instantiate ISA bus on chip 0 */ 781 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 782 783 /* Create serial port */ 784 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 785 786 /* Create an RTC ISA device too */ 787 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 788 789 /* Create the IPMI BT device for communication with the BMC */ 790 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 791 792 /* 793 * OpenPOWER systems use a IPMI SEL Event message to notify the 794 * host to powerdown 795 */ 796 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 797 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 798 } 799 800 /* 801 * 0:21 Reserved - Read as zeros 802 * 22:24 Chip ID 803 * 25:28 Core number 804 * 29:31 Thread ID 805 */ 806 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 807 { 808 return (chip->chip_id << 7) | (core_id << 3); 809 } 810 811 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 812 Error **errp) 813 { 814 Error *local_err = NULL; 815 Object *obj; 816 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 817 818 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 819 &local_err); 820 if (local_err) { 821 error_propagate(errp, local_err); 822 return; 823 } 824 825 pnv_cpu->intc = obj; 826 } 827 828 829 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 830 { 831 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 832 833 icp_reset(ICP(pnv_cpu->intc)); 834 } 835 836 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 837 { 838 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 839 840 icp_destroy(ICP(pnv_cpu->intc)); 841 pnv_cpu->intc = NULL; 842 } 843 844 /* 845 * 0:48 Reserved - Read as zeroes 846 * 49:52 Node ID 847 * 53:55 Chip ID 848 * 56 Reserved - Read as zero 849 * 57:61 Core number 850 * 62:63 Thread ID 851 * 852 * We only care about the lower bits. uint32_t is fine for the moment. 853 */ 854 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 855 { 856 return (chip->chip_id << 8) | (core_id << 2); 857 } 858 859 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 860 { 861 return (chip->chip_id << 8) | (core_id << 2); 862 } 863 864 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 865 Error **errp) 866 { 867 Pnv9Chip *chip9 = PNV9_CHIP(chip); 868 Error *local_err = NULL; 869 Object *obj; 870 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 871 872 /* 873 * The core creates its interrupt presenter but the XIVE interrupt 874 * controller object is initialized afterwards. Hopefully, it's 875 * only used at runtime. 876 */ 877 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); 878 if (local_err) { 879 error_propagate(errp, local_err); 880 return; 881 } 882 883 pnv_cpu->intc = obj; 884 } 885 886 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 887 { 888 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 889 890 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 891 } 892 893 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 894 { 895 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 896 897 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 898 pnv_cpu->intc = NULL; 899 } 900 901 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 902 Error **errp) 903 { 904 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 905 906 /* Will be defined when the interrupt controller is */ 907 pnv_cpu->intc = NULL; 908 } 909 910 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 911 { 912 ; 913 } 914 915 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 916 { 917 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 918 919 pnv_cpu->intc = NULL; 920 } 921 922 /* 923 * Allowed core identifiers on a POWER8 Processor Chip : 924 * 925 * <EX0 reserved> 926 * EX1 - Venice only 927 * EX2 - Venice only 928 * EX3 - Venice only 929 * EX4 930 * EX5 931 * EX6 932 * <EX7,8 reserved> <reserved> 933 * EX9 - Venice only 934 * EX10 - Venice only 935 * EX11 - Venice only 936 * EX12 937 * EX13 938 * EX14 939 * <EX15 reserved> 940 */ 941 #define POWER8E_CORE_MASK (0x7070ull) 942 #define POWER8_CORE_MASK (0x7e7eull) 943 944 /* 945 * POWER9 has 24 cores, ids starting at 0x0 946 */ 947 #define POWER9_CORE_MASK (0xffffffffffffffull) 948 949 950 #define POWER10_CORE_MASK (0xffffffffffffffull) 951 952 static void pnv_chip_power8_instance_init(Object *obj) 953 { 954 Pnv8Chip *chip8 = PNV8_CHIP(obj); 955 956 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 957 TYPE_PNV8_PSI, &error_abort, NULL); 958 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 959 OBJECT(qdev_get_machine()), &error_abort); 960 961 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 962 TYPE_PNV8_LPC, &error_abort, NULL); 963 964 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 965 TYPE_PNV8_OCC, &error_abort, NULL); 966 967 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 968 TYPE_PNV8_HOMER, &error_abort, NULL); 969 } 970 971 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 972 { 973 PnvChip *chip = PNV_CHIP(chip8); 974 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 975 int i, j; 976 char *name; 977 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 978 979 name = g_strdup_printf("icp-%x", chip->chip_id); 980 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 981 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 982 g_free(name); 983 984 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 985 986 /* Map the ICP registers for each thread */ 987 for (i = 0; i < chip->nr_cores; i++) { 988 PnvCore *pnv_core = chip->cores[i]; 989 int core_hwid = CPU_CORE(pnv_core)->core_id; 990 991 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 992 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 993 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 994 995 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 996 &icp->mmio); 997 } 998 } 999 } 1000 1001 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1002 { 1003 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1004 PnvChip *chip = PNV_CHIP(dev); 1005 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1006 Pnv8Psi *psi8 = &chip8->psi; 1007 Error *local_err = NULL; 1008 1009 /* XSCOM bridge is first */ 1010 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1011 if (local_err) { 1012 error_propagate(errp, local_err); 1013 return; 1014 } 1015 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1016 1017 pcc->parent_realize(dev, &local_err); 1018 if (local_err) { 1019 error_propagate(errp, local_err); 1020 return; 1021 } 1022 1023 /* Processor Service Interface (PSI) Host Bridge */ 1024 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1025 "bar", &error_fatal); 1026 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 1027 if (local_err) { 1028 error_propagate(errp, local_err); 1029 return; 1030 } 1031 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1032 &PNV_PSI(psi8)->xscom_regs); 1033 1034 /* Create LPC controller */ 1035 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1036 &error_abort); 1037 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 1038 &error_fatal); 1039 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1040 1041 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1042 (uint64_t) PNV_XSCOM_BASE(chip), 1043 PNV_XSCOM_LPC_BASE); 1044 1045 /* 1046 * Interrupt Management Area. This is the memory region holding 1047 * all the Interrupt Control Presenter (ICP) registers 1048 */ 1049 pnv_chip_icp_realize(chip8, &local_err); 1050 if (local_err) { 1051 error_propagate(errp, local_err); 1052 return; 1053 } 1054 1055 /* Create the simplified OCC model */ 1056 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1057 &error_abort); 1058 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1059 if (local_err) { 1060 error_propagate(errp, local_err); 1061 return; 1062 } 1063 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1064 1065 /* OCC SRAM model */ 1066 memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip), 1067 &chip8->occ.sram_regs); 1068 1069 /* HOMER */ 1070 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1071 &error_abort); 1072 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1073 &local_err); 1074 if (local_err) { 1075 error_propagate(errp, local_err); 1076 return; 1077 } 1078 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1079 &chip8->homer.regs); 1080 } 1081 1082 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1083 { 1084 DeviceClass *dc = DEVICE_CLASS(klass); 1085 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1086 1087 k->chip_type = PNV_CHIP_POWER8E; 1088 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1089 k->cores_mask = POWER8E_CORE_MASK; 1090 k->core_pir = pnv_chip_core_pir_p8; 1091 k->intc_create = pnv_chip_power8_intc_create; 1092 k->intc_reset = pnv_chip_power8_intc_reset; 1093 k->intc_destroy = pnv_chip_power8_intc_destroy; 1094 k->isa_create = pnv_chip_power8_isa_create; 1095 k->dt_populate = pnv_chip_power8_dt_populate; 1096 k->pic_print_info = pnv_chip_power8_pic_print_info; 1097 dc->desc = "PowerNV Chip POWER8E"; 1098 1099 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1100 &k->parent_realize); 1101 } 1102 1103 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1104 { 1105 DeviceClass *dc = DEVICE_CLASS(klass); 1106 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1107 1108 k->chip_type = PNV_CHIP_POWER8; 1109 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1110 k->cores_mask = POWER8_CORE_MASK; 1111 k->core_pir = pnv_chip_core_pir_p8; 1112 k->intc_create = pnv_chip_power8_intc_create; 1113 k->intc_reset = pnv_chip_power8_intc_reset; 1114 k->intc_destroy = pnv_chip_power8_intc_destroy; 1115 k->isa_create = pnv_chip_power8_isa_create; 1116 k->dt_populate = pnv_chip_power8_dt_populate; 1117 k->pic_print_info = pnv_chip_power8_pic_print_info; 1118 dc->desc = "PowerNV Chip POWER8"; 1119 1120 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1121 &k->parent_realize); 1122 } 1123 1124 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1125 { 1126 DeviceClass *dc = DEVICE_CLASS(klass); 1127 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1128 1129 k->chip_type = PNV_CHIP_POWER8NVL; 1130 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1131 k->cores_mask = POWER8_CORE_MASK; 1132 k->core_pir = pnv_chip_core_pir_p8; 1133 k->intc_create = pnv_chip_power8_intc_create; 1134 k->intc_reset = pnv_chip_power8_intc_reset; 1135 k->intc_destroy = pnv_chip_power8_intc_destroy; 1136 k->isa_create = pnv_chip_power8nvl_isa_create; 1137 k->dt_populate = pnv_chip_power8_dt_populate; 1138 k->pic_print_info = pnv_chip_power8_pic_print_info; 1139 dc->desc = "PowerNV Chip POWER8NVL"; 1140 1141 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1142 &k->parent_realize); 1143 } 1144 1145 static void pnv_chip_power9_instance_init(Object *obj) 1146 { 1147 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1148 1149 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1150 TYPE_PNV_XIVE, &error_abort, NULL); 1151 1152 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1153 TYPE_PNV9_PSI, &error_abort, NULL); 1154 1155 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1156 TYPE_PNV9_LPC, &error_abort, NULL); 1157 1158 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1159 TYPE_PNV9_OCC, &error_abort, NULL); 1160 1161 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1162 TYPE_PNV9_HOMER, &error_abort, NULL); 1163 } 1164 1165 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1166 { 1167 PnvChip *chip = PNV_CHIP(chip9); 1168 int i; 1169 1170 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1171 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1172 1173 for (i = 0; i < chip9->nr_quads; i++) { 1174 char eq_name[32]; 1175 PnvQuad *eq = &chip9->quads[i]; 1176 PnvCore *pnv_core = chip->cores[i * 4]; 1177 int core_id = CPU_CORE(pnv_core)->core_id; 1178 1179 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1180 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1181 TYPE_PNV_QUAD, &error_fatal, NULL); 1182 1183 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1184 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1185 1186 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1187 &eq->xscom_regs); 1188 } 1189 } 1190 1191 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1192 { 1193 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1194 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1195 PnvChip *chip = PNV_CHIP(dev); 1196 Pnv9Psi *psi9 = &chip9->psi; 1197 Error *local_err = NULL; 1198 1199 /* XSCOM bridge is first */ 1200 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1201 if (local_err) { 1202 error_propagate(errp, local_err); 1203 return; 1204 } 1205 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1206 1207 pcc->parent_realize(dev, &local_err); 1208 if (local_err) { 1209 error_propagate(errp, local_err); 1210 return; 1211 } 1212 1213 pnv_chip_quad_realize(chip9, &local_err); 1214 if (local_err) { 1215 error_propagate(errp, local_err); 1216 return; 1217 } 1218 1219 /* XIVE interrupt controller (POWER9) */ 1220 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1221 "ic-bar", &error_fatal); 1222 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1223 "vc-bar", &error_fatal); 1224 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1225 "pc-bar", &error_fatal); 1226 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1227 "tm-bar", &error_fatal); 1228 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1229 &error_abort); 1230 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1231 &local_err); 1232 if (local_err) { 1233 error_propagate(errp, local_err); 1234 return; 1235 } 1236 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1237 &chip9->xive.xscom_regs); 1238 1239 /* Processor Service Interface (PSI) Host Bridge */ 1240 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1241 "bar", &error_fatal); 1242 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1243 if (local_err) { 1244 error_propagate(errp, local_err); 1245 return; 1246 } 1247 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1248 &PNV_PSI(psi9)->xscom_regs); 1249 1250 /* LPC */ 1251 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1252 &error_abort); 1253 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1254 if (local_err) { 1255 error_propagate(errp, local_err); 1256 return; 1257 } 1258 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1259 &chip9->lpc.xscom_regs); 1260 1261 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1262 (uint64_t) PNV9_LPCM_BASE(chip)); 1263 1264 /* Create the simplified OCC model */ 1265 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1266 &error_abort); 1267 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1268 if (local_err) { 1269 error_propagate(errp, local_err); 1270 return; 1271 } 1272 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1273 1274 /* OCC SRAM model */ 1275 memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip), 1276 &chip9->occ.sram_regs); 1277 1278 /* HOMER */ 1279 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1280 &error_abort); 1281 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1282 &local_err); 1283 if (local_err) { 1284 error_propagate(errp, local_err); 1285 return; 1286 } 1287 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1288 &chip9->homer.regs); 1289 } 1290 1291 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1292 { 1293 DeviceClass *dc = DEVICE_CLASS(klass); 1294 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1295 1296 k->chip_type = PNV_CHIP_POWER9; 1297 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1298 k->cores_mask = POWER9_CORE_MASK; 1299 k->core_pir = pnv_chip_core_pir_p9; 1300 k->intc_create = pnv_chip_power9_intc_create; 1301 k->intc_reset = pnv_chip_power9_intc_reset; 1302 k->intc_destroy = pnv_chip_power9_intc_destroy; 1303 k->isa_create = pnv_chip_power9_isa_create; 1304 k->dt_populate = pnv_chip_power9_dt_populate; 1305 k->pic_print_info = pnv_chip_power9_pic_print_info; 1306 dc->desc = "PowerNV Chip POWER9"; 1307 1308 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1309 &k->parent_realize); 1310 } 1311 1312 static void pnv_chip_power10_instance_init(Object *obj) 1313 { 1314 /* 1315 * No controllers yet 1316 */ 1317 ; 1318 } 1319 1320 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1321 { 1322 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1323 PnvChip *chip = PNV_CHIP(dev); 1324 Error *local_err = NULL; 1325 1326 /* XSCOM bridge is first */ 1327 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1328 if (local_err) { 1329 error_propagate(errp, local_err); 1330 return; 1331 } 1332 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1333 1334 pcc->parent_realize(dev, &local_err); 1335 if (local_err) { 1336 error_propagate(errp, local_err); 1337 return; 1338 } 1339 } 1340 1341 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1342 { 1343 DeviceClass *dc = DEVICE_CLASS(klass); 1344 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1345 1346 k->chip_type = PNV_CHIP_POWER10; 1347 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1348 k->cores_mask = POWER10_CORE_MASK; 1349 k->core_pir = pnv_chip_core_pir_p10; 1350 k->intc_create = pnv_chip_power10_intc_create; 1351 k->intc_reset = pnv_chip_power10_intc_reset; 1352 k->intc_destroy = pnv_chip_power10_intc_destroy; 1353 k->isa_create = pnv_chip_power10_isa_create; 1354 k->dt_populate = pnv_chip_power10_dt_populate; 1355 k->pic_print_info = pnv_chip_power10_pic_print_info; 1356 dc->desc = "PowerNV Chip POWER10"; 1357 1358 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1359 &k->parent_realize); 1360 } 1361 1362 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1363 { 1364 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1365 int cores_max; 1366 1367 /* 1368 * No custom mask for this chip, let's use the default one from * 1369 * the chip class 1370 */ 1371 if (!chip->cores_mask) { 1372 chip->cores_mask = pcc->cores_mask; 1373 } 1374 1375 /* filter alien core ids ! some are reserved */ 1376 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1377 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1378 chip->cores_mask); 1379 return; 1380 } 1381 chip->cores_mask &= pcc->cores_mask; 1382 1383 /* now that we have a sane layout, let check the number of cores */ 1384 cores_max = ctpop64(chip->cores_mask); 1385 if (chip->nr_cores > cores_max) { 1386 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1387 cores_max); 1388 return; 1389 } 1390 } 1391 1392 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1393 { 1394 MachineState *ms = MACHINE(qdev_get_machine()); 1395 Error *error = NULL; 1396 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1397 const char *typename = pnv_chip_core_typename(chip); 1398 int i, core_hwid; 1399 1400 if (!object_class_by_name(typename)) { 1401 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1402 return; 1403 } 1404 1405 /* Cores */ 1406 pnv_chip_core_sanitize(chip, &error); 1407 if (error) { 1408 error_propagate(errp, error); 1409 return; 1410 } 1411 1412 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1413 1414 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1415 && (i < chip->nr_cores); core_hwid++) { 1416 char core_name[32]; 1417 PnvCore *pnv_core; 1418 uint64_t xscom_core_base; 1419 1420 if (!(chip->cores_mask & (1ull << core_hwid))) { 1421 continue; 1422 } 1423 1424 pnv_core = PNV_CORE(object_new(typename)); 1425 1426 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1427 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1428 &error_abort); 1429 chip->cores[i] = pnv_core; 1430 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", 1431 &error_fatal); 1432 object_property_set_int(OBJECT(pnv_core), core_hwid, 1433 CPU_CORE_PROP_CORE_ID, &error_fatal); 1434 object_property_set_int(OBJECT(pnv_core), 1435 pcc->core_pir(chip, core_hwid), 1436 "pir", &error_fatal); 1437 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1438 &error_abort); 1439 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1440 &error_fatal); 1441 1442 /* Each core has an XSCOM MMIO region */ 1443 if (pnv_chip_is_power10(chip)) { 1444 xscom_core_base = PNV10_XSCOM_EC_BASE(core_hwid); 1445 } else if (pnv_chip_is_power9(chip)) { 1446 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); 1447 } else { 1448 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); 1449 } 1450 1451 pnv_xscom_add_subregion(chip, xscom_core_base, 1452 &pnv_core->xscom_regs); 1453 i++; 1454 } 1455 } 1456 1457 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1458 { 1459 PnvChip *chip = PNV_CHIP(dev); 1460 Error *error = NULL; 1461 1462 /* Cores */ 1463 pnv_chip_core_realize(chip, &error); 1464 if (error) { 1465 error_propagate(errp, error); 1466 return; 1467 } 1468 } 1469 1470 static Property pnv_chip_properties[] = { 1471 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1472 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1473 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1474 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1475 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1476 DEFINE_PROP_END_OF_LIST(), 1477 }; 1478 1479 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1480 { 1481 DeviceClass *dc = DEVICE_CLASS(klass); 1482 1483 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1484 dc->realize = pnv_chip_realize; 1485 dc->props = pnv_chip_properties; 1486 dc->desc = "PowerNV Chip"; 1487 } 1488 1489 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1490 { 1491 int i, j; 1492 1493 for (i = 0; i < chip->nr_cores; i++) { 1494 PnvCore *pc = chip->cores[i]; 1495 CPUCore *cc = CPU_CORE(pc); 1496 1497 for (j = 0; j < cc->nr_threads; j++) { 1498 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1499 return pc->threads[j]; 1500 } 1501 } 1502 } 1503 return NULL; 1504 } 1505 1506 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1507 { 1508 PnvMachineState *pnv = PNV_MACHINE(xi); 1509 int i; 1510 1511 for (i = 0; i < pnv->num_chips; i++) { 1512 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1513 1514 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1515 return &chip8->psi.ics; 1516 } 1517 } 1518 return NULL; 1519 } 1520 1521 static void pnv_ics_resend(XICSFabric *xi) 1522 { 1523 PnvMachineState *pnv = PNV_MACHINE(xi); 1524 int i; 1525 1526 for (i = 0; i < pnv->num_chips; i++) { 1527 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1528 ics_resend(&chip8->psi.ics); 1529 } 1530 } 1531 1532 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1533 { 1534 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1535 1536 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1537 } 1538 1539 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1540 Monitor *mon) 1541 { 1542 PnvMachineState *pnv = PNV_MACHINE(obj); 1543 int i; 1544 CPUState *cs; 1545 1546 CPU_FOREACH(cs) { 1547 PowerPCCPU *cpu = POWERPC_CPU(cs); 1548 1549 if (pnv_chip_is_power9(pnv->chips[0])) { 1550 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1551 } else { 1552 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1553 } 1554 } 1555 1556 for (i = 0; i < pnv->num_chips; i++) { 1557 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1558 } 1559 } 1560 1561 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1562 uint8_t nvt_blk, uint32_t nvt_idx, 1563 bool cam_ignore, uint8_t priority, 1564 uint32_t logic_serv, 1565 XiveTCTXMatch *match) 1566 { 1567 PnvMachineState *pnv = PNV_MACHINE(xfb); 1568 int total_count = 0; 1569 int i; 1570 1571 for (i = 0; i < pnv->num_chips; i++) { 1572 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1573 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1574 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1575 int count; 1576 1577 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1578 priority, logic_serv, match); 1579 1580 if (count < 0) { 1581 return count; 1582 } 1583 1584 total_count += count; 1585 } 1586 1587 return total_count; 1588 } 1589 1590 PnvChip *pnv_get_chip(uint32_t chip_id) 1591 { 1592 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1593 int i; 1594 1595 for (i = 0; i < pnv->num_chips; i++) { 1596 PnvChip *chip = pnv->chips[i]; 1597 if (chip->chip_id == chip_id) { 1598 return chip; 1599 } 1600 } 1601 return NULL; 1602 } 1603 1604 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1605 void *opaque, Error **errp) 1606 { 1607 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1608 } 1609 1610 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1611 void *opaque, Error **errp) 1612 { 1613 PnvMachineState *pnv = PNV_MACHINE(obj); 1614 uint32_t num_chips; 1615 Error *local_err = NULL; 1616 1617 visit_type_uint32(v, name, &num_chips, &local_err); 1618 if (local_err) { 1619 error_propagate(errp, local_err); 1620 return; 1621 } 1622 1623 /* 1624 * TODO: should we decide on how many chips we can create based 1625 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1626 */ 1627 if (!is_power_of_2(num_chips) || num_chips > 4) { 1628 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1629 return; 1630 } 1631 1632 pnv->num_chips = num_chips; 1633 } 1634 1635 static void pnv_machine_instance_init(Object *obj) 1636 { 1637 PnvMachineState *pnv = PNV_MACHINE(obj); 1638 pnv->num_chips = 1; 1639 } 1640 1641 static void pnv_machine_class_props_init(ObjectClass *oc) 1642 { 1643 object_class_property_add(oc, "num-chips", "uint32", 1644 pnv_get_num_chips, pnv_set_num_chips, 1645 NULL, NULL, NULL); 1646 object_class_property_set_description(oc, "num-chips", 1647 "Specifies the number of processor chips", 1648 NULL); 1649 } 1650 1651 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1652 { 1653 MachineClass *mc = MACHINE_CLASS(oc); 1654 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1655 1656 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1657 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1658 1659 xic->icp_get = pnv_icp_get; 1660 xic->ics_get = pnv_ics_get; 1661 xic->ics_resend = pnv_ics_resend; 1662 } 1663 1664 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1665 { 1666 MachineClass *mc = MACHINE_CLASS(oc); 1667 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1668 1669 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1670 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1671 xfc->match_nvt = pnv_match_nvt; 1672 1673 mc->alias = "powernv"; 1674 } 1675 1676 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1677 { 1678 MachineClass *mc = MACHINE_CLASS(oc); 1679 1680 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1681 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1682 } 1683 1684 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1685 { 1686 MachineClass *mc = MACHINE_CLASS(oc); 1687 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1688 1689 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1690 mc->init = pnv_init; 1691 mc->reset = pnv_reset; 1692 mc->max_cpus = MAX_CPUS; 1693 /* Pnv provides a AHCI device for storage */ 1694 mc->block_default_type = IF_IDE; 1695 mc->no_parallel = 1; 1696 mc->default_boot_order = NULL; 1697 /* 1698 * RAM defaults to less than 2048 for 32-bit hosts, and large 1699 * enough to fit the maximum initrd size at it's load address 1700 */ 1701 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1702 ispc->print_info = pnv_pic_print_info; 1703 1704 pnv_machine_class_props_init(oc); 1705 } 1706 1707 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1708 { \ 1709 .name = type, \ 1710 .class_init = class_initfn, \ 1711 .parent = TYPE_PNV8_CHIP, \ 1712 } 1713 1714 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1715 { \ 1716 .name = type, \ 1717 .class_init = class_initfn, \ 1718 .parent = TYPE_PNV9_CHIP, \ 1719 } 1720 1721 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 1722 { \ 1723 .name = type, \ 1724 .class_init = class_initfn, \ 1725 .parent = TYPE_PNV10_CHIP, \ 1726 } 1727 1728 static const TypeInfo types[] = { 1729 { 1730 .name = MACHINE_TYPE_NAME("powernv10"), 1731 .parent = TYPE_PNV_MACHINE, 1732 .class_init = pnv_machine_power10_class_init, 1733 }, 1734 { 1735 .name = MACHINE_TYPE_NAME("powernv9"), 1736 .parent = TYPE_PNV_MACHINE, 1737 .class_init = pnv_machine_power9_class_init, 1738 .interfaces = (InterfaceInfo[]) { 1739 { TYPE_XIVE_FABRIC }, 1740 { }, 1741 }, 1742 }, 1743 { 1744 .name = MACHINE_TYPE_NAME("powernv8"), 1745 .parent = TYPE_PNV_MACHINE, 1746 .class_init = pnv_machine_power8_class_init, 1747 .interfaces = (InterfaceInfo[]) { 1748 { TYPE_XICS_FABRIC }, 1749 { }, 1750 }, 1751 }, 1752 { 1753 .name = TYPE_PNV_MACHINE, 1754 .parent = TYPE_MACHINE, 1755 .abstract = true, 1756 .instance_size = sizeof(PnvMachineState), 1757 .instance_init = pnv_machine_instance_init, 1758 .class_init = pnv_machine_class_init, 1759 .interfaces = (InterfaceInfo[]) { 1760 { TYPE_INTERRUPT_STATS_PROVIDER }, 1761 { }, 1762 }, 1763 }, 1764 { 1765 .name = TYPE_PNV_CHIP, 1766 .parent = TYPE_SYS_BUS_DEVICE, 1767 .class_init = pnv_chip_class_init, 1768 .instance_size = sizeof(PnvChip), 1769 .class_size = sizeof(PnvChipClass), 1770 .abstract = true, 1771 }, 1772 1773 /* 1774 * P10 chip and variants 1775 */ 1776 { 1777 .name = TYPE_PNV10_CHIP, 1778 .parent = TYPE_PNV_CHIP, 1779 .instance_init = pnv_chip_power10_instance_init, 1780 .instance_size = sizeof(Pnv10Chip), 1781 }, 1782 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 1783 1784 /* 1785 * P9 chip and variants 1786 */ 1787 { 1788 .name = TYPE_PNV9_CHIP, 1789 .parent = TYPE_PNV_CHIP, 1790 .instance_init = pnv_chip_power9_instance_init, 1791 .instance_size = sizeof(Pnv9Chip), 1792 }, 1793 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1794 1795 /* 1796 * P8 chip and variants 1797 */ 1798 { 1799 .name = TYPE_PNV8_CHIP, 1800 .parent = TYPE_PNV_CHIP, 1801 .instance_init = pnv_chip_power8_instance_init, 1802 .instance_size = sizeof(Pnv8Chip), 1803 }, 1804 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1805 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1806 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1807 pnv_chip_power8nvl_class_init), 1808 }; 1809 1810 DEFINE_TYPES(types) 1811