1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci-host/pnv_phb.h" 47 #include "hw/pci-host/pnv_phb3.h" 48 #include "hw/pci-host/pnv_phb4.h" 49 50 #include "hw/ppc/xics.h" 51 #include "hw/qdev-properties.h" 52 #include "hw/ppc/pnv_chip.h" 53 #include "hw/ppc/pnv_xscom.h" 54 #include "hw/ppc/pnv_pnor.h" 55 56 #include "hw/isa/isa.h" 57 #include "hw/char/serial.h" 58 #include "hw/rtc/mc146818rtc.h" 59 60 #include <libfdt.h> 61 62 #define FDT_MAX_SIZE (1 * MiB) 63 64 #define FW_FILE_NAME "skiboot.lid" 65 #define FW_LOAD_ADDR 0x0 66 #define FW_MAX_SIZE (16 * MiB) 67 68 #define KERNEL_LOAD_ADDR 0x20000000 69 #define KERNEL_MAX_SIZE (128 * MiB) 70 #define INITRD_LOAD_ADDR 0x28000000 71 #define INITRD_MAX_SIZE (128 * MiB) 72 73 static const char *pnv_chip_core_typename(const PnvChip *o) 74 { 75 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 76 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 77 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 78 const char *core_type = object_class_get_name(object_class_by_name(s)); 79 g_free(s); 80 return core_type; 81 } 82 83 /* 84 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 85 * 4 * 4 sockets * 12 cores * 8 threads = 1536 86 * Let's make it 2^11 87 */ 88 #define MAX_CPUS 2048 89 90 /* 91 * Memory nodes are created by hostboot, one for each range of memory 92 * that has a different "affinity". In practice, it means one range 93 * per chip. 94 */ 95 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 96 { 97 char *mem_name; 98 uint64_t mem_reg_property[2]; 99 int off; 100 101 mem_reg_property[0] = cpu_to_be64(start); 102 mem_reg_property[1] = cpu_to_be64(size); 103 104 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 105 off = fdt_add_subnode(fdt, 0, mem_name); 106 g_free(mem_name); 107 108 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 109 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 110 sizeof(mem_reg_property)))); 111 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 112 } 113 114 static int get_cpus_node(void *fdt) 115 { 116 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 117 118 if (cpus_offset < 0) { 119 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 120 if (cpus_offset) { 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 123 } 124 } 125 _FDT(cpus_offset); 126 return cpus_offset; 127 } 128 129 /* 130 * The PowerNV cores (and threads) need to use real HW ids and not an 131 * incremental index like it has been done on other platforms. This HW 132 * id is stored in the CPU PIR, it is used to create cpu nodes in the 133 * device tree, used in XSCOM to address cores and in interrupt 134 * servers. 135 */ 136 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 137 { 138 PowerPCCPU *cpu = pc->threads[0]; 139 CPUState *cs = CPU(cpu); 140 DeviceClass *dc = DEVICE_GET_CLASS(cs); 141 int smt_threads = CPU_CORE(pc)->nr_threads; 142 CPUPPCState *env = &cpu->env; 143 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 145 int i; 146 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 147 0xffffffff, 0xffffffff}; 148 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 149 uint32_t cpufreq = 1000000000; 150 uint32_t page_sizes_prop[64]; 151 size_t page_sizes_prop_size; 152 const uint8_t pa_features[] = { 24, 0, 153 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 154 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 155 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 156 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 157 int offset; 158 char *nodename; 159 int cpus_offset = get_cpus_node(fdt); 160 161 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 162 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 163 _FDT(offset); 164 g_free(nodename); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 170 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 171 172 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 176 env->dcache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 178 env->icache_line_size))); 179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 180 env->icache_line_size))); 181 182 if (pcc->l1_dcache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 184 pcc->l1_dcache_size))); 185 } else { 186 warn_report("Unknown L1 dcache size for cpu"); 187 } 188 if (pcc->l1_icache_size) { 189 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 190 pcc->l1_icache_size))); 191 } else { 192 warn_report("Unknown L1 icache size for cpu"); 193 } 194 195 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 196 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 198 cpu->hash64_opts->slb_size))); 199 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 200 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 201 202 if (ppc_has_spr(cpu, SPR_PURR)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 204 } 205 206 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 207 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 208 segs, sizeof(segs)))); 209 } 210 211 /* 212 * Advertise VMX/VSX (vector extensions) if available 213 * 0 / no property == no vector extensions 214 * 1 == VMX / Altivec available 215 * 2 == VSX available 216 */ 217 if (env->insns_flags & PPC_ALTIVEC) { 218 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 219 220 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 221 } 222 223 /* 224 * Advertise DFP (Decimal Floating Point) if available 225 * 0 / no property == no DFP 226 * 1 == DFP available 227 */ 228 if (env->insns_flags2 & PPC2_DFP) { 229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 230 } 231 232 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 233 sizeof(page_sizes_prop)); 234 if (page_sizes_prop_size) { 235 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 236 page_sizes_prop, page_sizes_prop_size))); 237 } 238 239 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 240 pa_features, sizeof(pa_features)))); 241 242 /* Build interrupt servers properties */ 243 for (i = 0; i < smt_threads; i++) { 244 servers_prop[i] = cpu_to_be32(pc->pir + i); 245 } 246 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 247 servers_prop, sizeof(*servers_prop) * smt_threads))); 248 } 249 250 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 251 uint32_t nr_threads) 252 { 253 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 254 char *name; 255 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 256 uint32_t irange[2], i, rsize; 257 uint64_t *reg; 258 int offset; 259 260 irange[0] = cpu_to_be32(pir); 261 irange[1] = cpu_to_be32(nr_threads); 262 263 rsize = sizeof(uint64_t) * 2 * nr_threads; 264 reg = g_malloc(rsize); 265 for (i = 0; i < nr_threads; i++) { 266 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 267 reg[i * 2 + 1] = cpu_to_be64(0x1000); 268 } 269 270 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 271 offset = fdt_add_subnode(fdt, 0, name); 272 _FDT(offset); 273 g_free(name); 274 275 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 276 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 277 _FDT((fdt_setprop_string(fdt, offset, "device_type", 278 "PowerPC-External-Interrupt-Presentation"))); 279 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 280 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 281 irange, sizeof(irange)))); 282 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 283 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 284 g_free(reg); 285 } 286 287 static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb, 288 Error **errp) 289 { 290 PnvPHB *phb_base = phb->phb_base; 291 PnvPhb4PecState *pecs = NULL; 292 int chip_id = phb->chip_id; 293 int index = phb->phb_id; 294 int i, j; 295 296 if (phb_base->version == 4) { 297 Pnv9Chip *chip9 = PNV9_CHIP(chip); 298 299 pecs = chip9->pecs; 300 } else if (phb_base->version == 5) { 301 Pnv10Chip *chip10 = PNV10_CHIP(chip); 302 303 pecs = chip10->pecs; 304 } else { 305 g_assert_not_reached(); 306 } 307 308 for (i = 0; i < chip->num_pecs; i++) { 309 /* 310 * For each PEC, check the amount of phbs it supports 311 * and see if the given phb4 index matches an index. 312 */ 313 PnvPhb4PecState *pec = &pecs[i]; 314 315 for (j = 0; j < pec->num_phbs; j++) { 316 if (index == pnv_phb4_pec_get_phb_id(pec, j)) { 317 return pec; 318 } 319 } 320 } 321 error_setg(errp, 322 "pnv-phb4 chip-id %d index %d didn't match any existing PEC", 323 chip_id, index); 324 325 return NULL; 326 } 327 328 /* 329 * Adds a PnvPHB to the chip. Returns the parent obj of the 330 * PHB which varies with each version (phb version 3 is parented 331 * by the chip, version 4 and 5 are parented by the PEC 332 * device). 333 * 334 * TODO: for version 3 we're still parenting the PHB with the 335 * chip. We should parent with a (so far not implemented) 336 * PHB3 PEC device. 337 */ 338 Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp) 339 { 340 if (phb->version == 3) { 341 Pnv8Chip *chip8 = PNV8_CHIP(chip); 342 343 phb->chip = chip; 344 345 chip8->phbs[chip8->num_phbs] = phb; 346 chip8->num_phbs++; 347 348 return OBJECT(chip); 349 } 350 351 phb->pec = pnv_phb4_get_pec(chip, PNV_PHB4(phb->backend), errp); 352 353 return OBJECT(phb->pec); 354 } 355 356 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 357 { 358 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 359 int i; 360 361 pnv_dt_xscom(chip, fdt, 0, 362 cpu_to_be64(PNV_XSCOM_BASE(chip)), 363 cpu_to_be64(PNV_XSCOM_SIZE), 364 compat, sizeof(compat)); 365 366 for (i = 0; i < chip->nr_cores; i++) { 367 PnvCore *pnv_core = chip->cores[i]; 368 369 pnv_dt_core(chip, pnv_core, fdt); 370 371 /* Interrupt Control Presenters (ICP). One per core. */ 372 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 373 } 374 375 if (chip->ram_size) { 376 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 377 } 378 } 379 380 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 381 { 382 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 383 int i; 384 385 pnv_dt_xscom(chip, fdt, 0, 386 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 387 cpu_to_be64(PNV9_XSCOM_SIZE), 388 compat, sizeof(compat)); 389 390 for (i = 0; i < chip->nr_cores; i++) { 391 PnvCore *pnv_core = chip->cores[i]; 392 393 pnv_dt_core(chip, pnv_core, fdt); 394 } 395 396 if (chip->ram_size) { 397 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 398 } 399 400 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 401 } 402 403 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 404 { 405 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 406 int i; 407 408 pnv_dt_xscom(chip, fdt, 0, 409 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 410 cpu_to_be64(PNV10_XSCOM_SIZE), 411 compat, sizeof(compat)); 412 413 for (i = 0; i < chip->nr_cores; i++) { 414 PnvCore *pnv_core = chip->cores[i]; 415 416 pnv_dt_core(chip, pnv_core, fdt); 417 } 418 419 if (chip->ram_size) { 420 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 421 } 422 423 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 424 } 425 426 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 427 { 428 uint32_t io_base = d->ioport_id; 429 uint32_t io_regs[] = { 430 cpu_to_be32(1), 431 cpu_to_be32(io_base), 432 cpu_to_be32(2) 433 }; 434 char *name; 435 int node; 436 437 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 438 node = fdt_add_subnode(fdt, lpc_off, name); 439 _FDT(node); 440 g_free(name); 441 442 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 443 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 444 } 445 446 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 447 { 448 const char compatible[] = "ns16550\0pnpPNP,501"; 449 uint32_t io_base = d->ioport_id; 450 uint32_t io_regs[] = { 451 cpu_to_be32(1), 452 cpu_to_be32(io_base), 453 cpu_to_be32(8) 454 }; 455 uint32_t irq; 456 char *name; 457 int node; 458 459 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 460 461 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 462 node = fdt_add_subnode(fdt, lpc_off, name); 463 _FDT(node); 464 g_free(name); 465 466 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 467 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 468 sizeof(compatible)))); 469 470 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 471 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 472 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 473 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 474 fdt_get_phandle(fdt, lpc_off)))); 475 476 /* This is needed by Linux */ 477 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 478 } 479 480 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 481 { 482 const char compatible[] = "bt\0ipmi-bt"; 483 uint32_t io_base; 484 uint32_t io_regs[] = { 485 cpu_to_be32(1), 486 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 487 cpu_to_be32(3) 488 }; 489 uint32_t irq; 490 char *name; 491 int node; 492 493 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 494 io_regs[1] = cpu_to_be32(io_base); 495 496 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 497 498 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 499 node = fdt_add_subnode(fdt, lpc_off, name); 500 _FDT(node); 501 g_free(name); 502 503 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 504 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 505 sizeof(compatible)))); 506 507 /* Mark it as reserved to avoid Linux trying to claim it */ 508 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 509 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 510 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 511 fdt_get_phandle(fdt, lpc_off)))); 512 } 513 514 typedef struct ForeachPopulateArgs { 515 void *fdt; 516 int offset; 517 } ForeachPopulateArgs; 518 519 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 520 { 521 ForeachPopulateArgs *args = opaque; 522 ISADevice *d = ISA_DEVICE(dev); 523 524 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 525 pnv_dt_rtc(d, args->fdt, args->offset); 526 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 527 pnv_dt_serial(d, args->fdt, args->offset); 528 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 529 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 530 } else { 531 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 532 d->ioport_id); 533 } 534 535 return 0; 536 } 537 538 /* 539 * The default LPC bus of a multichip system is on chip 0. It's 540 * recognized by the firmware (skiboot) using a "primary" property. 541 */ 542 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 543 { 544 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 545 ForeachPopulateArgs args = { 546 .fdt = fdt, 547 .offset = isa_offset, 548 }; 549 uint32_t phandle; 550 551 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 552 553 phandle = qemu_fdt_alloc_phandle(fdt); 554 assert(phandle > 0); 555 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 556 557 /* 558 * ISA devices are not necessarily parented to the ISA bus so we 559 * can not use object_child_foreach() 560 */ 561 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 562 &args); 563 } 564 565 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 566 { 567 int off; 568 569 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 570 off = fdt_add_subnode(fdt, off, "power-mgt"); 571 572 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 573 } 574 575 static void *pnv_dt_create(MachineState *machine) 576 { 577 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 578 PnvMachineState *pnv = PNV_MACHINE(machine); 579 void *fdt; 580 char *buf; 581 int off; 582 int i; 583 584 fdt = g_malloc0(FDT_MAX_SIZE); 585 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 586 587 /* /qemu node */ 588 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 589 590 /* Root node */ 591 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 592 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 593 _FDT((fdt_setprop_string(fdt, 0, "model", 594 "IBM PowerNV (emulated by qemu)"))); 595 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 596 597 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 598 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 599 if (qemu_uuid_set) { 600 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 601 } 602 g_free(buf); 603 604 off = fdt_add_subnode(fdt, 0, "chosen"); 605 if (machine->kernel_cmdline) { 606 _FDT((fdt_setprop_string(fdt, off, "bootargs", 607 machine->kernel_cmdline))); 608 } 609 610 if (pnv->initrd_size) { 611 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 612 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 613 614 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 615 &start_prop, sizeof(start_prop)))); 616 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 617 &end_prop, sizeof(end_prop)))); 618 } 619 620 /* Populate device tree for each chip */ 621 for (i = 0; i < pnv->num_chips; i++) { 622 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 623 } 624 625 /* Populate ISA devices on chip 0 */ 626 pnv_dt_isa(pnv, fdt); 627 628 if (pnv->bmc) { 629 pnv_dt_bmc_sensors(pnv->bmc, fdt); 630 } 631 632 /* Create an extra node for power management on machines that support it */ 633 if (pmc->dt_power_mgt) { 634 pmc->dt_power_mgt(pnv, fdt); 635 } 636 637 return fdt; 638 } 639 640 static void pnv_powerdown_notify(Notifier *n, void *opaque) 641 { 642 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 643 644 if (pnv->bmc) { 645 pnv_bmc_powerdown(pnv->bmc); 646 } 647 } 648 649 static void pnv_reset(MachineState *machine, ShutdownCause reason) 650 { 651 PnvMachineState *pnv = PNV_MACHINE(machine); 652 IPMIBmc *bmc; 653 void *fdt; 654 655 qemu_devices_reset(reason); 656 657 /* 658 * The machine should provide by default an internal BMC simulator. 659 * If not, try to use the BMC device that was provided on the command 660 * line. 661 */ 662 bmc = pnv_bmc_find(&error_fatal); 663 if (!pnv->bmc) { 664 if (!bmc) { 665 if (!qtest_enabled()) { 666 warn_report("machine has no BMC device. Use '-device " 667 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 668 "to define one"); 669 } 670 } else { 671 pnv_bmc_set_pnor(bmc, pnv->pnor); 672 pnv->bmc = bmc; 673 } 674 } 675 676 fdt = pnv_dt_create(machine); 677 678 /* Pack resulting tree */ 679 _FDT((fdt_pack(fdt))); 680 681 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 682 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 683 684 /* 685 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 686 * the existing machine->fdt to avoid leaking it during 687 * a reset. 688 */ 689 g_free(machine->fdt); 690 machine->fdt = fdt; 691 } 692 693 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 694 { 695 Pnv8Chip *chip8 = PNV8_CHIP(chip); 696 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 697 698 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 699 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 700 } 701 702 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 703 { 704 Pnv8Chip *chip8 = PNV8_CHIP(chip); 705 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 706 707 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 708 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 709 } 710 711 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 712 { 713 Pnv9Chip *chip9 = PNV9_CHIP(chip); 714 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 715 716 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 717 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 718 } 719 720 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 721 { 722 Pnv10Chip *chip10 = PNV10_CHIP(chip); 723 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 724 725 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 726 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 727 } 728 729 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 730 { 731 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 732 } 733 734 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 735 { 736 Pnv8Chip *chip8 = PNV8_CHIP(chip); 737 int i; 738 739 ics_pic_print_info(&chip8->psi.ics, mon); 740 741 for (i = 0; i < chip8->num_phbs; i++) { 742 PnvPHB *phb = chip8->phbs[i]; 743 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 744 745 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 746 ics_pic_print_info(&phb3->lsis, mon); 747 } 748 } 749 750 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 751 { 752 Monitor *mon = opaque; 753 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 754 755 if (!phb) { 756 return 0; 757 } 758 759 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon); 760 761 return 0; 762 } 763 764 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 765 { 766 Pnv9Chip *chip9 = PNV9_CHIP(chip); 767 768 pnv_xive_pic_print_info(&chip9->xive, mon); 769 pnv_psi_pic_print_info(&chip9->psi, mon); 770 771 object_child_foreach_recursive(OBJECT(chip), 772 pnv_chip_power9_pic_print_info_child, mon); 773 } 774 775 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 776 uint32_t core_id) 777 { 778 return PNV_XSCOM_EX_BASE(core_id); 779 } 780 781 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 782 uint32_t core_id) 783 { 784 return PNV9_XSCOM_EC_BASE(core_id); 785 } 786 787 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 788 uint32_t core_id) 789 { 790 return PNV10_XSCOM_EC_BASE(core_id); 791 } 792 793 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 794 { 795 PowerPCCPUClass *ppc_default = 796 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 797 PowerPCCPUClass *ppc = 798 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 799 800 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 801 } 802 803 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 804 { 805 ISADevice *dev = isa_new("isa-ipmi-bt"); 806 807 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 808 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 809 isa_realize_and_unref(dev, bus, &error_fatal); 810 } 811 812 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 813 { 814 Pnv10Chip *chip10 = PNV10_CHIP(chip); 815 816 pnv_xive2_pic_print_info(&chip10->xive, mon); 817 pnv_psi_pic_print_info(&chip10->psi, mon); 818 819 object_child_foreach_recursive(OBJECT(chip), 820 pnv_chip_power9_pic_print_info_child, mon); 821 } 822 823 /* Always give the first 1GB to chip 0 else we won't boot */ 824 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 825 { 826 MachineState *machine = MACHINE(pnv); 827 uint64_t ram_per_chip; 828 829 assert(machine->ram_size >= 1 * GiB); 830 831 ram_per_chip = machine->ram_size / pnv->num_chips; 832 if (ram_per_chip >= 1 * GiB) { 833 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 834 } 835 836 assert(pnv->num_chips > 1); 837 838 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 839 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 840 } 841 842 static void pnv_init(MachineState *machine) 843 { 844 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 845 PnvMachineState *pnv = PNV_MACHINE(machine); 846 MachineClass *mc = MACHINE_GET_CLASS(machine); 847 char *fw_filename; 848 long fw_size; 849 uint64_t chip_ram_start = 0; 850 int i; 851 char *chip_typename; 852 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 853 DeviceState *dev; 854 855 if (kvm_enabled()) { 856 error_report("The powernv machine does not work with KVM acceleration"); 857 exit(EXIT_FAILURE); 858 } 859 860 /* allocate RAM */ 861 if (machine->ram_size < mc->default_ram_size) { 862 char *sz = size_to_str(mc->default_ram_size); 863 error_report("Invalid RAM size, should be bigger than %s", sz); 864 g_free(sz); 865 exit(EXIT_FAILURE); 866 } 867 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 868 869 /* 870 * Create our simple PNOR device 871 */ 872 dev = qdev_new(TYPE_PNV_PNOR); 873 if (pnor) { 874 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 875 } 876 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 877 pnv->pnor = PNV_PNOR(dev); 878 879 /* load skiboot firmware */ 880 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 881 if (!fw_filename) { 882 error_report("Could not find OPAL firmware '%s'", bios_name); 883 exit(1); 884 } 885 886 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 887 if (fw_size < 0) { 888 error_report("Could not load OPAL firmware '%s'", fw_filename); 889 exit(1); 890 } 891 g_free(fw_filename); 892 893 /* load kernel */ 894 if (machine->kernel_filename) { 895 long kernel_size; 896 897 kernel_size = load_image_targphys(machine->kernel_filename, 898 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 899 if (kernel_size < 0) { 900 error_report("Could not load kernel '%s'", 901 machine->kernel_filename); 902 exit(1); 903 } 904 } 905 906 /* load initrd */ 907 if (machine->initrd_filename) { 908 pnv->initrd_base = INITRD_LOAD_ADDR; 909 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 910 pnv->initrd_base, INITRD_MAX_SIZE); 911 if (pnv->initrd_size < 0) { 912 error_report("Could not load initial ram disk '%s'", 913 machine->initrd_filename); 914 exit(1); 915 } 916 } 917 918 /* MSIs are supported on this platform */ 919 msi_nonbroken = true; 920 921 /* 922 * Check compatibility of the specified CPU with the machine 923 * default. 924 */ 925 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 926 error_report("invalid CPU model '%s' for %s machine", 927 machine->cpu_type, mc->name); 928 exit(1); 929 } 930 931 /* Create the processor chips */ 932 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 933 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 934 i, machine->cpu_type); 935 if (!object_class_by_name(chip_typename)) { 936 error_report("invalid chip model '%.*s' for %s machine", 937 i, machine->cpu_type, mc->name); 938 exit(1); 939 } 940 941 pnv->num_chips = 942 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 943 /* 944 * TODO: should we decide on how many chips we can create based 945 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 946 */ 947 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 948 error_report("invalid number of chips: '%d'", pnv->num_chips); 949 error_printf( 950 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 951 exit(1); 952 } 953 954 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 955 for (i = 0; i < pnv->num_chips; i++) { 956 char chip_name[32]; 957 Object *chip = OBJECT(qdev_new(chip_typename)); 958 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 959 960 pnv->chips[i] = PNV_CHIP(chip); 961 962 /* Distribute RAM among the chips */ 963 object_property_set_int(chip, "ram-start", chip_ram_start, 964 &error_fatal); 965 object_property_set_int(chip, "ram-size", chip_ram_size, 966 &error_fatal); 967 chip_ram_start += chip_ram_size; 968 969 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 970 object_property_add_child(OBJECT(pnv), chip_name, chip); 971 object_property_set_int(chip, "chip-id", i, &error_fatal); 972 object_property_set_int(chip, "nr-cores", machine->smp.cores, 973 &error_fatal); 974 object_property_set_int(chip, "nr-threads", machine->smp.threads, 975 &error_fatal); 976 /* 977 * The POWER8 machine use the XICS interrupt interface. 978 * Propagate the XICS fabric to the chip and its controllers. 979 */ 980 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 981 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 982 } 983 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 984 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 985 &error_abort); 986 } 987 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 988 } 989 g_free(chip_typename); 990 991 /* Instantiate ISA bus on chip 0 */ 992 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 993 994 /* Create serial port */ 995 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 996 997 /* Create an RTC ISA device too */ 998 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 999 1000 /* 1001 * Create the machine BMC simulator and the IPMI BT device for 1002 * communication with the BMC 1003 */ 1004 if (defaults_enabled()) { 1005 pnv->bmc = pnv_bmc_create(pnv->pnor); 1006 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1007 } 1008 1009 /* 1010 * The PNOR is mapped on the LPC FW address space by the BMC. 1011 * Since we can not reach the remote BMC machine with LPC memops, 1012 * map it always for now. 1013 */ 1014 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1015 &pnv->pnor->mmio); 1016 1017 /* 1018 * OpenPOWER systems use a IPMI SEL Event message to notify the 1019 * host to powerdown 1020 */ 1021 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1022 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1023 } 1024 1025 /* 1026 * 0:21 Reserved - Read as zeros 1027 * 22:24 Chip ID 1028 * 25:28 Core number 1029 * 29:31 Thread ID 1030 */ 1031 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 1032 { 1033 return (chip->chip_id << 7) | (core_id << 3); 1034 } 1035 1036 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1037 Error **errp) 1038 { 1039 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1040 Error *local_err = NULL; 1041 Object *obj; 1042 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1043 1044 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1045 if (local_err) { 1046 error_propagate(errp, local_err); 1047 return; 1048 } 1049 1050 pnv_cpu->intc = obj; 1051 } 1052 1053 1054 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1055 { 1056 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1057 1058 icp_reset(ICP(pnv_cpu->intc)); 1059 } 1060 1061 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1062 { 1063 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1064 1065 icp_destroy(ICP(pnv_cpu->intc)); 1066 pnv_cpu->intc = NULL; 1067 } 1068 1069 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1070 Monitor *mon) 1071 { 1072 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1073 } 1074 1075 /* 1076 * 0:48 Reserved - Read as zeroes 1077 * 49:52 Node ID 1078 * 53:55 Chip ID 1079 * 56 Reserved - Read as zero 1080 * 57:61 Core number 1081 * 62:63 Thread ID 1082 * 1083 * We only care about the lower bits. uint32_t is fine for the moment. 1084 */ 1085 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 1086 { 1087 return (chip->chip_id << 8) | (core_id << 2); 1088 } 1089 1090 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1091 { 1092 return (chip->chip_id << 8) | (core_id << 2); 1093 } 1094 1095 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1096 Error **errp) 1097 { 1098 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1099 Error *local_err = NULL; 1100 Object *obj; 1101 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1102 1103 /* 1104 * The core creates its interrupt presenter but the XIVE interrupt 1105 * controller object is initialized afterwards. Hopefully, it's 1106 * only used at runtime. 1107 */ 1108 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1109 &local_err); 1110 if (local_err) { 1111 error_propagate(errp, local_err); 1112 return; 1113 } 1114 1115 pnv_cpu->intc = obj; 1116 } 1117 1118 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1119 { 1120 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1121 1122 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1123 } 1124 1125 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1126 { 1127 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1128 1129 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1130 pnv_cpu->intc = NULL; 1131 } 1132 1133 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1134 Monitor *mon) 1135 { 1136 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1137 } 1138 1139 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1140 Error **errp) 1141 { 1142 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1143 Error *local_err = NULL; 1144 Object *obj; 1145 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1146 1147 /* 1148 * The core creates its interrupt presenter but the XIVE2 interrupt 1149 * controller object is initialized afterwards. Hopefully, it's 1150 * only used at runtime. 1151 */ 1152 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1153 &local_err); 1154 if (local_err) { 1155 error_propagate(errp, local_err); 1156 return; 1157 } 1158 1159 pnv_cpu->intc = obj; 1160 } 1161 1162 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1163 { 1164 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1165 1166 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1167 } 1168 1169 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1170 { 1171 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1172 1173 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1174 pnv_cpu->intc = NULL; 1175 } 1176 1177 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1178 Monitor *mon) 1179 { 1180 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1181 } 1182 1183 /* 1184 * Allowed core identifiers on a POWER8 Processor Chip : 1185 * 1186 * <EX0 reserved> 1187 * EX1 - Venice only 1188 * EX2 - Venice only 1189 * EX3 - Venice only 1190 * EX4 1191 * EX5 1192 * EX6 1193 * <EX7,8 reserved> <reserved> 1194 * EX9 - Venice only 1195 * EX10 - Venice only 1196 * EX11 - Venice only 1197 * EX12 1198 * EX13 1199 * EX14 1200 * <EX15 reserved> 1201 */ 1202 #define POWER8E_CORE_MASK (0x7070ull) 1203 #define POWER8_CORE_MASK (0x7e7eull) 1204 1205 /* 1206 * POWER9 has 24 cores, ids starting at 0x0 1207 */ 1208 #define POWER9_CORE_MASK (0xffffffffffffffull) 1209 1210 1211 #define POWER10_CORE_MASK (0xffffffffffffffull) 1212 1213 static void pnv_chip_power8_instance_init(Object *obj) 1214 { 1215 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1216 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1217 int i; 1218 1219 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1220 (Object **)&chip8->xics, 1221 object_property_allow_set_link, 1222 OBJ_PROP_LINK_STRONG); 1223 1224 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1225 1226 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1227 1228 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1229 1230 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1231 1232 if (defaults_enabled()) { 1233 chip8->num_phbs = pcc->num_phbs; 1234 1235 for (i = 0; i < chip8->num_phbs; i++) { 1236 Object *phb = object_new(TYPE_PNV_PHB); 1237 1238 /* 1239 * We need the chip to parent the PHB to allow the DT 1240 * to build correctly (via pnv_xscom_dt()). 1241 * 1242 * TODO: the PHB should be parented by a PEC device that, at 1243 * this moment, is not modelled powernv8/phb3. 1244 */ 1245 object_property_add_child(obj, "phb[*]", phb); 1246 chip8->phbs[i] = PNV_PHB(phb); 1247 } 1248 } 1249 1250 } 1251 1252 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1253 { 1254 PnvChip *chip = PNV_CHIP(chip8); 1255 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1256 int i, j; 1257 char *name; 1258 1259 name = g_strdup_printf("icp-%x", chip->chip_id); 1260 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1261 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1262 g_free(name); 1263 1264 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1265 1266 /* Map the ICP registers for each thread */ 1267 for (i = 0; i < chip->nr_cores; i++) { 1268 PnvCore *pnv_core = chip->cores[i]; 1269 int core_hwid = CPU_CORE(pnv_core)->core_id; 1270 1271 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1272 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1273 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1274 1275 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1276 &icp->mmio); 1277 } 1278 } 1279 } 1280 1281 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1282 { 1283 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1284 PnvChip *chip = PNV_CHIP(dev); 1285 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1286 Pnv8Psi *psi8 = &chip8->psi; 1287 Error *local_err = NULL; 1288 int i; 1289 1290 assert(chip8->xics); 1291 1292 /* XSCOM bridge is first */ 1293 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1294 if (local_err) { 1295 error_propagate(errp, local_err); 1296 return; 1297 } 1298 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1299 1300 pcc->parent_realize(dev, &local_err); 1301 if (local_err) { 1302 error_propagate(errp, local_err); 1303 return; 1304 } 1305 1306 /* Processor Service Interface (PSI) Host Bridge */ 1307 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1308 &error_fatal); 1309 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1310 OBJECT(chip8->xics), &error_abort); 1311 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1312 return; 1313 } 1314 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1315 &PNV_PSI(psi8)->xscom_regs); 1316 1317 /* Create LPC controller */ 1318 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1319 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1320 1321 chip->fw_mr = &chip8->lpc.isa_fw; 1322 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1323 (uint64_t) PNV_XSCOM_BASE(chip), 1324 PNV_XSCOM_LPC_BASE); 1325 1326 /* 1327 * Interrupt Management Area. This is the memory region holding 1328 * all the Interrupt Control Presenter (ICP) registers 1329 */ 1330 pnv_chip_icp_realize(chip8, &local_err); 1331 if (local_err) { 1332 error_propagate(errp, local_err); 1333 return; 1334 } 1335 1336 /* Create the simplified OCC model */ 1337 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1338 return; 1339 } 1340 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1341 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1342 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); 1343 1344 /* OCC SRAM model */ 1345 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1346 &chip8->occ.sram_regs); 1347 1348 /* HOMER */ 1349 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1350 &error_abort); 1351 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1352 return; 1353 } 1354 /* Homer Xscom region */ 1355 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1356 1357 /* Homer mmio region */ 1358 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1359 &chip8->homer.regs); 1360 1361 /* PHB controllers */ 1362 for (i = 0; i < chip8->num_phbs; i++) { 1363 PnvPHB *phb = chip8->phbs[i]; 1364 1365 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1366 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1367 &error_fatal); 1368 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1369 &error_fatal); 1370 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1371 return; 1372 } 1373 } 1374 } 1375 1376 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1377 { 1378 addr &= (PNV_XSCOM_SIZE - 1); 1379 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1380 } 1381 1382 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1383 { 1384 DeviceClass *dc = DEVICE_CLASS(klass); 1385 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1386 1387 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1388 k->cores_mask = POWER8E_CORE_MASK; 1389 k->num_phbs = 3; 1390 k->core_pir = pnv_chip_core_pir_p8; 1391 k->intc_create = pnv_chip_power8_intc_create; 1392 k->intc_reset = pnv_chip_power8_intc_reset; 1393 k->intc_destroy = pnv_chip_power8_intc_destroy; 1394 k->intc_print_info = pnv_chip_power8_intc_print_info; 1395 k->isa_create = pnv_chip_power8_isa_create; 1396 k->dt_populate = pnv_chip_power8_dt_populate; 1397 k->pic_print_info = pnv_chip_power8_pic_print_info; 1398 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1399 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1400 dc->desc = "PowerNV Chip POWER8E"; 1401 1402 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1403 &k->parent_realize); 1404 } 1405 1406 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1407 { 1408 DeviceClass *dc = DEVICE_CLASS(klass); 1409 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1410 1411 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1412 k->cores_mask = POWER8_CORE_MASK; 1413 k->num_phbs = 3; 1414 k->core_pir = pnv_chip_core_pir_p8; 1415 k->intc_create = pnv_chip_power8_intc_create; 1416 k->intc_reset = pnv_chip_power8_intc_reset; 1417 k->intc_destroy = pnv_chip_power8_intc_destroy; 1418 k->intc_print_info = pnv_chip_power8_intc_print_info; 1419 k->isa_create = pnv_chip_power8_isa_create; 1420 k->dt_populate = pnv_chip_power8_dt_populate; 1421 k->pic_print_info = pnv_chip_power8_pic_print_info; 1422 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1423 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1424 dc->desc = "PowerNV Chip POWER8"; 1425 1426 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1427 &k->parent_realize); 1428 } 1429 1430 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1431 { 1432 DeviceClass *dc = DEVICE_CLASS(klass); 1433 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1434 1435 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1436 k->cores_mask = POWER8_CORE_MASK; 1437 k->num_phbs = 4; 1438 k->core_pir = pnv_chip_core_pir_p8; 1439 k->intc_create = pnv_chip_power8_intc_create; 1440 k->intc_reset = pnv_chip_power8_intc_reset; 1441 k->intc_destroy = pnv_chip_power8_intc_destroy; 1442 k->intc_print_info = pnv_chip_power8_intc_print_info; 1443 k->isa_create = pnv_chip_power8nvl_isa_create; 1444 k->dt_populate = pnv_chip_power8_dt_populate; 1445 k->pic_print_info = pnv_chip_power8_pic_print_info; 1446 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1447 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1448 dc->desc = "PowerNV Chip POWER8NVL"; 1449 1450 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1451 &k->parent_realize); 1452 } 1453 1454 static void pnv_chip_power9_instance_init(Object *obj) 1455 { 1456 PnvChip *chip = PNV_CHIP(obj); 1457 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1458 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1459 int i; 1460 1461 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1462 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1463 "xive-fabric"); 1464 1465 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1466 1467 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1468 1469 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1470 1471 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1472 1473 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1474 1475 /* Number of PECs is the chip default */ 1476 chip->num_pecs = pcc->num_pecs; 1477 1478 for (i = 0; i < chip->num_pecs; i++) { 1479 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1480 TYPE_PNV_PHB4_PEC); 1481 } 1482 } 1483 1484 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1485 PnvCore *pnv_core) 1486 { 1487 char eq_name[32]; 1488 int core_id = CPU_CORE(pnv_core)->core_id; 1489 1490 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1491 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1492 sizeof(*eq), TYPE_PNV_QUAD, 1493 &error_fatal, NULL); 1494 1495 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1496 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1497 } 1498 1499 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1500 { 1501 PnvChip *chip = PNV_CHIP(chip9); 1502 int i; 1503 1504 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1505 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1506 1507 for (i = 0; i < chip9->nr_quads; i++) { 1508 PnvQuad *eq = &chip9->quads[i]; 1509 1510 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1511 1512 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1513 &eq->xscom_regs); 1514 } 1515 } 1516 1517 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1518 { 1519 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1520 int i; 1521 1522 for (i = 0; i < chip->num_pecs; i++) { 1523 PnvPhb4PecState *pec = &chip9->pecs[i]; 1524 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1525 uint32_t pec_nest_base; 1526 uint32_t pec_pci_base; 1527 1528 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1529 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1530 &error_fatal); 1531 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1532 &error_fatal); 1533 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1534 return; 1535 } 1536 1537 pec_nest_base = pecc->xscom_nest_base(pec); 1538 pec_pci_base = pecc->xscom_pci_base(pec); 1539 1540 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1541 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1542 } 1543 } 1544 1545 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1546 { 1547 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1548 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1549 PnvChip *chip = PNV_CHIP(dev); 1550 Pnv9Psi *psi9 = &chip9->psi; 1551 Error *local_err = NULL; 1552 1553 /* XSCOM bridge is first */ 1554 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1555 if (local_err) { 1556 error_propagate(errp, local_err); 1557 return; 1558 } 1559 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1560 1561 pcc->parent_realize(dev, &local_err); 1562 if (local_err) { 1563 error_propagate(errp, local_err); 1564 return; 1565 } 1566 1567 pnv_chip_quad_realize(chip9, &local_err); 1568 if (local_err) { 1569 error_propagate(errp, local_err); 1570 return; 1571 } 1572 1573 /* XIVE interrupt controller (POWER9) */ 1574 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1575 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1576 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1577 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1578 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1579 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1580 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1581 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1582 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1583 &error_abort); 1584 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1585 return; 1586 } 1587 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1588 &chip9->xive.xscom_regs); 1589 1590 /* Processor Service Interface (PSI) Host Bridge */ 1591 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1592 &error_fatal); 1593 /* This is the only device with 4k ESB pages */ 1594 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1595 &error_fatal); 1596 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1597 return; 1598 } 1599 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1600 &PNV_PSI(psi9)->xscom_regs); 1601 1602 /* LPC */ 1603 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1604 return; 1605 } 1606 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1607 &chip9->lpc.xscom_regs); 1608 1609 chip->fw_mr = &chip9->lpc.isa_fw; 1610 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1611 (uint64_t) PNV9_LPCM_BASE(chip)); 1612 1613 /* Create the simplified OCC model */ 1614 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1615 return; 1616 } 1617 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1618 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1619 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); 1620 1621 /* OCC SRAM model */ 1622 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1623 &chip9->occ.sram_regs); 1624 1625 /* SBE */ 1626 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1627 return; 1628 } 1629 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1630 &chip9->sbe.xscom_ctrl_regs); 1631 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1632 &chip9->sbe.xscom_mbox_regs); 1633 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1634 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU)); 1635 1636 /* HOMER */ 1637 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1638 &error_abort); 1639 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1640 return; 1641 } 1642 /* Homer Xscom region */ 1643 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1644 1645 /* Homer mmio region */ 1646 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1647 &chip9->homer.regs); 1648 1649 /* PEC PHBs */ 1650 pnv_chip_power9_pec_realize(chip, &local_err); 1651 if (local_err) { 1652 error_propagate(errp, local_err); 1653 return; 1654 } 1655 } 1656 1657 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1658 { 1659 addr &= (PNV9_XSCOM_SIZE - 1); 1660 return addr >> 3; 1661 } 1662 1663 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1664 { 1665 DeviceClass *dc = DEVICE_CLASS(klass); 1666 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1667 1668 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1669 k->cores_mask = POWER9_CORE_MASK; 1670 k->core_pir = pnv_chip_core_pir_p9; 1671 k->intc_create = pnv_chip_power9_intc_create; 1672 k->intc_reset = pnv_chip_power9_intc_reset; 1673 k->intc_destroy = pnv_chip_power9_intc_destroy; 1674 k->intc_print_info = pnv_chip_power9_intc_print_info; 1675 k->isa_create = pnv_chip_power9_isa_create; 1676 k->dt_populate = pnv_chip_power9_dt_populate; 1677 k->pic_print_info = pnv_chip_power9_pic_print_info; 1678 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1679 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1680 dc->desc = "PowerNV Chip POWER9"; 1681 k->num_pecs = PNV9_CHIP_MAX_PEC; 1682 1683 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1684 &k->parent_realize); 1685 } 1686 1687 static void pnv_chip_power10_instance_init(Object *obj) 1688 { 1689 PnvChip *chip = PNV_CHIP(obj); 1690 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1691 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1692 int i; 1693 1694 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1695 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1696 "xive-fabric"); 1697 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1698 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1699 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1700 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1701 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1702 1703 chip->num_pecs = pcc->num_pecs; 1704 1705 for (i = 0; i < chip->num_pecs; i++) { 1706 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1707 TYPE_PNV_PHB5_PEC); 1708 } 1709 } 1710 1711 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1712 { 1713 PnvChip *chip = PNV_CHIP(chip10); 1714 int i; 1715 1716 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1717 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1718 1719 for (i = 0; i < chip10->nr_quads; i++) { 1720 PnvQuad *eq = &chip10->quads[i]; 1721 1722 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1723 1724 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1725 &eq->xscom_regs); 1726 } 1727 } 1728 1729 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1730 { 1731 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1732 int i; 1733 1734 for (i = 0; i < chip->num_pecs; i++) { 1735 PnvPhb4PecState *pec = &chip10->pecs[i]; 1736 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1737 uint32_t pec_nest_base; 1738 uint32_t pec_pci_base; 1739 1740 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1741 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1742 &error_fatal); 1743 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1744 &error_fatal); 1745 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1746 return; 1747 } 1748 1749 pec_nest_base = pecc->xscom_nest_base(pec); 1750 pec_pci_base = pecc->xscom_pci_base(pec); 1751 1752 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1753 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1754 } 1755 } 1756 1757 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1758 { 1759 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1760 PnvChip *chip = PNV_CHIP(dev); 1761 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1762 Error *local_err = NULL; 1763 1764 /* XSCOM bridge is first */ 1765 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1766 if (local_err) { 1767 error_propagate(errp, local_err); 1768 return; 1769 } 1770 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1771 1772 pcc->parent_realize(dev, &local_err); 1773 if (local_err) { 1774 error_propagate(errp, local_err); 1775 return; 1776 } 1777 1778 pnv_chip_power10_quad_realize(chip10, &local_err); 1779 if (local_err) { 1780 error_propagate(errp, local_err); 1781 return; 1782 } 1783 1784 /* XIVE2 interrupt controller (POWER10) */ 1785 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1786 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1787 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1788 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1789 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1790 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1791 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1792 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1793 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1794 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1795 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1796 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1797 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1798 &error_abort); 1799 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1800 return; 1801 } 1802 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1803 &chip10->xive.xscom_regs); 1804 1805 /* Processor Service Interface (PSI) Host Bridge */ 1806 object_property_set_int(OBJECT(&chip10->psi), "bar", 1807 PNV10_PSIHB_BASE(chip), &error_fatal); 1808 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1809 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1810 &error_fatal); 1811 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1812 return; 1813 } 1814 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1815 &PNV_PSI(&chip10->psi)->xscom_regs); 1816 1817 /* LPC */ 1818 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1819 return; 1820 } 1821 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1822 &chip10->lpc.xscom_regs); 1823 1824 chip->fw_mr = &chip10->lpc.isa_fw; 1825 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1826 (uint64_t) PNV10_LPCM_BASE(chip)); 1827 1828 /* Create the simplified OCC model */ 1829 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1830 return; 1831 } 1832 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1833 &chip10->occ.xscom_regs); 1834 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1835 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1836 1837 /* OCC SRAM model */ 1838 memory_region_add_subregion(get_system_memory(), 1839 PNV10_OCC_SENSOR_BASE(chip), 1840 &chip10->occ.sram_regs); 1841 1842 /* SBE */ 1843 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1844 return; 1845 } 1846 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1847 &chip10->sbe.xscom_ctrl_regs); 1848 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 1849 &chip10->sbe.xscom_mbox_regs); 1850 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 1851 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 1852 1853 /* HOMER */ 1854 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1855 &error_abort); 1856 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1857 return; 1858 } 1859 /* Homer Xscom region */ 1860 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1861 &chip10->homer.pba_regs); 1862 1863 /* Homer mmio region */ 1864 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1865 &chip10->homer.regs); 1866 1867 /* PHBs */ 1868 pnv_chip_power10_phb_realize(chip, &local_err); 1869 if (local_err) { 1870 error_propagate(errp, local_err); 1871 return; 1872 } 1873 } 1874 1875 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1876 { 1877 addr &= (PNV10_XSCOM_SIZE - 1); 1878 return addr >> 3; 1879 } 1880 1881 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1882 { 1883 DeviceClass *dc = DEVICE_CLASS(klass); 1884 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1885 1886 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1887 k->cores_mask = POWER10_CORE_MASK; 1888 k->core_pir = pnv_chip_core_pir_p10; 1889 k->intc_create = pnv_chip_power10_intc_create; 1890 k->intc_reset = pnv_chip_power10_intc_reset; 1891 k->intc_destroy = pnv_chip_power10_intc_destroy; 1892 k->intc_print_info = pnv_chip_power10_intc_print_info; 1893 k->isa_create = pnv_chip_power10_isa_create; 1894 k->dt_populate = pnv_chip_power10_dt_populate; 1895 k->pic_print_info = pnv_chip_power10_pic_print_info; 1896 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1897 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1898 dc->desc = "PowerNV Chip POWER10"; 1899 k->num_pecs = PNV10_CHIP_MAX_PEC; 1900 1901 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1902 &k->parent_realize); 1903 } 1904 1905 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1906 { 1907 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1908 int cores_max; 1909 1910 /* 1911 * No custom mask for this chip, let's use the default one from * 1912 * the chip class 1913 */ 1914 if (!chip->cores_mask) { 1915 chip->cores_mask = pcc->cores_mask; 1916 } 1917 1918 /* filter alien core ids ! some are reserved */ 1919 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1920 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1921 chip->cores_mask); 1922 return; 1923 } 1924 chip->cores_mask &= pcc->cores_mask; 1925 1926 /* now that we have a sane layout, let check the number of cores */ 1927 cores_max = ctpop64(chip->cores_mask); 1928 if (chip->nr_cores > cores_max) { 1929 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1930 cores_max); 1931 return; 1932 } 1933 } 1934 1935 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1936 { 1937 Error *error = NULL; 1938 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1939 const char *typename = pnv_chip_core_typename(chip); 1940 int i, core_hwid; 1941 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1942 1943 if (!object_class_by_name(typename)) { 1944 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1945 return; 1946 } 1947 1948 /* Cores */ 1949 pnv_chip_core_sanitize(chip, &error); 1950 if (error) { 1951 error_propagate(errp, error); 1952 return; 1953 } 1954 1955 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1956 1957 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1958 && (i < chip->nr_cores); core_hwid++) { 1959 char core_name[32]; 1960 PnvCore *pnv_core; 1961 uint64_t xscom_core_base; 1962 1963 if (!(chip->cores_mask & (1ull << core_hwid))) { 1964 continue; 1965 } 1966 1967 pnv_core = PNV_CORE(object_new(typename)); 1968 1969 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1970 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1971 chip->cores[i] = pnv_core; 1972 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1973 chip->nr_threads, &error_fatal); 1974 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1975 core_hwid, &error_fatal); 1976 object_property_set_int(OBJECT(pnv_core), "pir", 1977 pcc->core_pir(chip, core_hwid), &error_fatal); 1978 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1979 &error_fatal); 1980 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1981 &error_abort); 1982 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1983 1984 /* Each core has an XSCOM MMIO region */ 1985 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1986 1987 pnv_xscom_add_subregion(chip, xscom_core_base, 1988 &pnv_core->xscom_regs); 1989 i++; 1990 } 1991 } 1992 1993 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1994 { 1995 PnvChip *chip = PNV_CHIP(dev); 1996 Error *error = NULL; 1997 1998 /* Cores */ 1999 pnv_chip_core_realize(chip, &error); 2000 if (error) { 2001 error_propagate(errp, error); 2002 return; 2003 } 2004 } 2005 2006 static Property pnv_chip_properties[] = { 2007 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2008 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2009 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2010 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2011 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2012 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2013 DEFINE_PROP_END_OF_LIST(), 2014 }; 2015 2016 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2017 { 2018 DeviceClass *dc = DEVICE_CLASS(klass); 2019 2020 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2021 dc->realize = pnv_chip_realize; 2022 device_class_set_props(dc, pnv_chip_properties); 2023 dc->desc = "PowerNV Chip"; 2024 } 2025 2026 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2027 { 2028 int i, j; 2029 2030 for (i = 0; i < chip->nr_cores; i++) { 2031 PnvCore *pc = chip->cores[i]; 2032 CPUCore *cc = CPU_CORE(pc); 2033 2034 for (j = 0; j < cc->nr_threads; j++) { 2035 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2036 return pc->threads[j]; 2037 } 2038 } 2039 } 2040 return NULL; 2041 } 2042 2043 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2044 { 2045 PnvMachineState *pnv = PNV_MACHINE(xi); 2046 int i, j; 2047 2048 for (i = 0; i < pnv->num_chips; i++) { 2049 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2050 2051 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2052 return &chip8->psi.ics; 2053 } 2054 2055 for (j = 0; j < chip8->num_phbs; j++) { 2056 PnvPHB *phb = chip8->phbs[j]; 2057 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2058 2059 if (ics_valid_irq(&phb3->lsis, irq)) { 2060 return &phb3->lsis; 2061 } 2062 2063 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2064 return ICS(&phb3->msis); 2065 } 2066 } 2067 } 2068 return NULL; 2069 } 2070 2071 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2072 { 2073 int i; 2074 2075 for (i = 0; i < pnv->num_chips; i++) { 2076 PnvChip *chip = pnv->chips[i]; 2077 if (chip->chip_id == chip_id) { 2078 return chip; 2079 } 2080 } 2081 return NULL; 2082 } 2083 2084 static void pnv_ics_resend(XICSFabric *xi) 2085 { 2086 PnvMachineState *pnv = PNV_MACHINE(xi); 2087 int i, j; 2088 2089 for (i = 0; i < pnv->num_chips; i++) { 2090 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2091 2092 ics_resend(&chip8->psi.ics); 2093 2094 for (j = 0; j < chip8->num_phbs; j++) { 2095 PnvPHB *phb = chip8->phbs[j]; 2096 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2097 2098 ics_resend(&phb3->lsis); 2099 ics_resend(ICS(&phb3->msis)); 2100 } 2101 } 2102 } 2103 2104 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2105 { 2106 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2107 2108 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2109 } 2110 2111 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2112 Monitor *mon) 2113 { 2114 PnvMachineState *pnv = PNV_MACHINE(obj); 2115 int i; 2116 CPUState *cs; 2117 2118 CPU_FOREACH(cs) { 2119 PowerPCCPU *cpu = POWERPC_CPU(cs); 2120 2121 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2122 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2123 mon); 2124 } 2125 2126 for (i = 0; i < pnv->num_chips; i++) { 2127 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2128 } 2129 } 2130 2131 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2132 uint8_t nvt_blk, uint32_t nvt_idx, 2133 bool cam_ignore, uint8_t priority, 2134 uint32_t logic_serv, 2135 XiveTCTXMatch *match) 2136 { 2137 PnvMachineState *pnv = PNV_MACHINE(xfb); 2138 int total_count = 0; 2139 int i; 2140 2141 for (i = 0; i < pnv->num_chips; i++) { 2142 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2143 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2144 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2145 int count; 2146 2147 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2148 priority, logic_serv, match); 2149 2150 if (count < 0) { 2151 return count; 2152 } 2153 2154 total_count += count; 2155 } 2156 2157 return total_count; 2158 } 2159 2160 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2161 uint8_t nvt_blk, uint32_t nvt_idx, 2162 bool cam_ignore, uint8_t priority, 2163 uint32_t logic_serv, 2164 XiveTCTXMatch *match) 2165 { 2166 PnvMachineState *pnv = PNV_MACHINE(xfb); 2167 int total_count = 0; 2168 int i; 2169 2170 for (i = 0; i < pnv->num_chips; i++) { 2171 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2172 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2173 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2174 int count; 2175 2176 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2177 priority, logic_serv, match); 2178 2179 if (count < 0) { 2180 return count; 2181 } 2182 2183 total_count += count; 2184 } 2185 2186 return total_count; 2187 } 2188 2189 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2190 { 2191 MachineClass *mc = MACHINE_CLASS(oc); 2192 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2193 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2194 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2195 2196 static GlobalProperty phb_compat[] = { 2197 { TYPE_PNV_PHB, "version", "3" }, 2198 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2199 }; 2200 2201 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2202 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2203 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2204 2205 xic->icp_get = pnv_icp_get; 2206 xic->ics_get = pnv_ics_get; 2207 xic->ics_resend = pnv_ics_resend; 2208 2209 pmc->compat = compat; 2210 pmc->compat_size = sizeof(compat); 2211 2212 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2213 } 2214 2215 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2216 { 2217 MachineClass *mc = MACHINE_CLASS(oc); 2218 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2219 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2220 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2221 2222 static GlobalProperty phb_compat[] = { 2223 { TYPE_PNV_PHB, "version", "4" }, 2224 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2225 }; 2226 2227 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2228 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 2229 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2230 2231 xfc->match_nvt = pnv_match_nvt; 2232 2233 mc->alias = "powernv"; 2234 2235 pmc->compat = compat; 2236 pmc->compat_size = sizeof(compat); 2237 pmc->dt_power_mgt = pnv_dt_power_mgt; 2238 2239 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2240 } 2241 2242 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2243 { 2244 MachineClass *mc = MACHINE_CLASS(oc); 2245 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2246 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2247 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2248 2249 static GlobalProperty phb_compat[] = { 2250 { TYPE_PNV_PHB, "version", "5" }, 2251 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2252 }; 2253 2254 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2255 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2256 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2257 2258 pmc->compat = compat; 2259 pmc->compat_size = sizeof(compat); 2260 pmc->dt_power_mgt = pnv_dt_power_mgt; 2261 2262 xfc->match_nvt = pnv10_xive_match_nvt; 2263 2264 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2265 } 2266 2267 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2268 { 2269 PnvMachineState *pnv = PNV_MACHINE(obj); 2270 2271 return !!pnv->fw_load_addr; 2272 } 2273 2274 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2275 { 2276 PnvMachineState *pnv = PNV_MACHINE(obj); 2277 2278 if (value) { 2279 pnv->fw_load_addr = 0x8000000; 2280 } 2281 } 2282 2283 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2284 { 2285 PowerPCCPU *cpu = POWERPC_CPU(cs); 2286 CPUPPCState *env = &cpu->env; 2287 2288 cpu_synchronize_state(cs); 2289 ppc_cpu_do_system_reset(cs); 2290 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2291 /* 2292 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2293 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2294 * (PPC_BIT(43)). 2295 */ 2296 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2297 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2298 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2299 } 2300 } else { 2301 /* 2302 * For non-powersave system resets, SRR1[42:45] are defined to be 2303 * implementation-dependent. The POWER9 User Manual specifies that 2304 * an external (SCOM driven, which may come from a BMC nmi command or 2305 * another CPU requesting a NMI IPI) system reset exception should be 2306 * 0b0010 (PPC_BIT(44)). 2307 */ 2308 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2309 } 2310 } 2311 2312 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2313 { 2314 CPUState *cs; 2315 2316 CPU_FOREACH(cs) { 2317 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2318 } 2319 } 2320 2321 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2322 { 2323 MachineClass *mc = MACHINE_CLASS(oc); 2324 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2325 NMIClass *nc = NMI_CLASS(oc); 2326 2327 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2328 mc->init = pnv_init; 2329 mc->reset = pnv_reset; 2330 mc->max_cpus = MAX_CPUS; 2331 /* Pnv provides a AHCI device for storage */ 2332 mc->block_default_type = IF_IDE; 2333 mc->no_parallel = 1; 2334 mc->default_boot_order = NULL; 2335 /* 2336 * RAM defaults to less than 2048 for 32-bit hosts, and large 2337 * enough to fit the maximum initrd size at it's load address 2338 */ 2339 mc->default_ram_size = 1 * GiB; 2340 mc->default_ram_id = "pnv.ram"; 2341 ispc->print_info = pnv_pic_print_info; 2342 nc->nmi_monitor_handler = pnv_nmi; 2343 2344 object_class_property_add_bool(oc, "hb-mode", 2345 pnv_machine_get_hb, pnv_machine_set_hb); 2346 object_class_property_set_description(oc, "hb-mode", 2347 "Use a hostboot like boot loader"); 2348 } 2349 2350 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2351 { \ 2352 .name = type, \ 2353 .class_init = class_initfn, \ 2354 .parent = TYPE_PNV8_CHIP, \ 2355 } 2356 2357 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2358 { \ 2359 .name = type, \ 2360 .class_init = class_initfn, \ 2361 .parent = TYPE_PNV9_CHIP, \ 2362 } 2363 2364 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2365 { \ 2366 .name = type, \ 2367 .class_init = class_initfn, \ 2368 .parent = TYPE_PNV10_CHIP, \ 2369 } 2370 2371 static const TypeInfo types[] = { 2372 { 2373 .name = MACHINE_TYPE_NAME("powernv10"), 2374 .parent = TYPE_PNV_MACHINE, 2375 .class_init = pnv_machine_power10_class_init, 2376 .interfaces = (InterfaceInfo[]) { 2377 { TYPE_XIVE_FABRIC }, 2378 { }, 2379 }, 2380 }, 2381 { 2382 .name = MACHINE_TYPE_NAME("powernv9"), 2383 .parent = TYPE_PNV_MACHINE, 2384 .class_init = pnv_machine_power9_class_init, 2385 .interfaces = (InterfaceInfo[]) { 2386 { TYPE_XIVE_FABRIC }, 2387 { }, 2388 }, 2389 }, 2390 { 2391 .name = MACHINE_TYPE_NAME("powernv8"), 2392 .parent = TYPE_PNV_MACHINE, 2393 .class_init = pnv_machine_power8_class_init, 2394 .interfaces = (InterfaceInfo[]) { 2395 { TYPE_XICS_FABRIC }, 2396 { }, 2397 }, 2398 }, 2399 { 2400 .name = TYPE_PNV_MACHINE, 2401 .parent = TYPE_MACHINE, 2402 .abstract = true, 2403 .instance_size = sizeof(PnvMachineState), 2404 .class_init = pnv_machine_class_init, 2405 .class_size = sizeof(PnvMachineClass), 2406 .interfaces = (InterfaceInfo[]) { 2407 { TYPE_INTERRUPT_STATS_PROVIDER }, 2408 { TYPE_NMI }, 2409 { }, 2410 }, 2411 }, 2412 { 2413 .name = TYPE_PNV_CHIP, 2414 .parent = TYPE_SYS_BUS_DEVICE, 2415 .class_init = pnv_chip_class_init, 2416 .instance_size = sizeof(PnvChip), 2417 .class_size = sizeof(PnvChipClass), 2418 .abstract = true, 2419 }, 2420 2421 /* 2422 * P10 chip and variants 2423 */ 2424 { 2425 .name = TYPE_PNV10_CHIP, 2426 .parent = TYPE_PNV_CHIP, 2427 .instance_init = pnv_chip_power10_instance_init, 2428 .instance_size = sizeof(Pnv10Chip), 2429 }, 2430 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2431 2432 /* 2433 * P9 chip and variants 2434 */ 2435 { 2436 .name = TYPE_PNV9_CHIP, 2437 .parent = TYPE_PNV_CHIP, 2438 .instance_init = pnv_chip_power9_instance_init, 2439 .instance_size = sizeof(Pnv9Chip), 2440 }, 2441 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2442 2443 /* 2444 * P8 chip and variants 2445 */ 2446 { 2447 .name = TYPE_PNV8_CHIP, 2448 .parent = TYPE_PNV_CHIP, 2449 .instance_init = pnv_chip_power8_instance_init, 2450 .instance_size = sizeof(Pnv8Chip), 2451 }, 2452 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2453 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2454 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2455 pnv_chip_power8nvl_class_init), 2456 }; 2457 2458 DEFINE_TYPES(types) 2459