1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "hw/intc/intc.h" 42 #include "hw/ipmi/ipmi.h" 43 #include "target/ppc/mmu-hash64.h" 44 #include "hw/pci/msi.h" 45 #include "hw/pci-host/pnv_phb.h" 46 #include "hw/pci-host/pnv_phb3.h" 47 #include "hw/pci-host/pnv_phb4.h" 48 49 #include "hw/ppc/xics.h" 50 #include "hw/qdev-properties.h" 51 #include "hw/ppc/pnv_chip.h" 52 #include "hw/ppc/pnv_xscom.h" 53 #include "hw/ppc/pnv_pnor.h" 54 55 #include "hw/isa/isa.h" 56 #include "hw/char/serial.h" 57 #include "hw/rtc/mc146818rtc.h" 58 59 #include <libfdt.h> 60 61 #define FDT_MAX_SIZE (1 * MiB) 62 63 #define FW_FILE_NAME "skiboot.lid" 64 #define FW_LOAD_ADDR 0x0 65 #define FW_MAX_SIZE (16 * MiB) 66 67 #define KERNEL_LOAD_ADDR 0x20000000 68 #define KERNEL_MAX_SIZE (128 * MiB) 69 #define INITRD_LOAD_ADDR 0x28000000 70 #define INITRD_MAX_SIZE (128 * MiB) 71 72 static const char *pnv_chip_core_typename(const PnvChip *o) 73 { 74 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 75 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 76 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 77 const char *core_type = object_class_get_name(object_class_by_name(s)); 78 g_free(s); 79 return core_type; 80 } 81 82 /* 83 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 84 * 4 * 4 sockets * 12 cores * 8 threads = 1536 85 * Let's make it 2^11 86 */ 87 #define MAX_CPUS 2048 88 89 /* 90 * Memory nodes are created by hostboot, one for each range of memory 91 * that has a different "affinity". In practice, it means one range 92 * per chip. 93 */ 94 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 95 { 96 char *mem_name; 97 uint64_t mem_reg_property[2]; 98 int off; 99 100 mem_reg_property[0] = cpu_to_be64(start); 101 mem_reg_property[1] = cpu_to_be64(size); 102 103 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 104 off = fdt_add_subnode(fdt, 0, mem_name); 105 g_free(mem_name); 106 107 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 108 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 109 sizeof(mem_reg_property)))); 110 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 111 } 112 113 static int get_cpus_node(void *fdt) 114 { 115 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 116 117 if (cpus_offset < 0) { 118 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 119 if (cpus_offset) { 120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 122 } 123 } 124 _FDT(cpus_offset); 125 return cpus_offset; 126 } 127 128 /* 129 * The PowerNV cores (and threads) need to use real HW ids and not an 130 * incremental index like it has been done on other platforms. This HW 131 * id is stored in the CPU PIR, it is used to create cpu nodes in the 132 * device tree, used in XSCOM to address cores and in interrupt 133 * servers. 134 */ 135 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 136 { 137 PowerPCCPU *cpu = pc->threads[0]; 138 CPUState *cs = CPU(cpu); 139 DeviceClass *dc = DEVICE_GET_CLASS(cs); 140 int smt_threads = CPU_CORE(pc)->nr_threads; 141 CPUPPCState *env = &cpu->env; 142 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 143 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 145 int i; 146 uint32_t pir; 147 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 148 0xffffffff, 0xffffffff}; 149 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 150 uint32_t cpufreq = 1000000000; 151 uint32_t page_sizes_prop[64]; 152 size_t page_sizes_prop_size; 153 int offset; 154 char *nodename; 155 int cpus_offset = get_cpus_node(fdt); 156 157 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, NULL); 158 159 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 160 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 161 _FDT(offset); 162 g_free(nodename); 163 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 167 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 168 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 169 170 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 172 env->dcache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 176 env->icache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 178 env->icache_line_size))); 179 180 if (pcc->l1_dcache_size) { 181 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 182 pcc->l1_dcache_size))); 183 } else { 184 warn_report("Unknown L1 dcache size for cpu"); 185 } 186 if (pcc->l1_icache_size) { 187 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 188 pcc->l1_icache_size))); 189 } else { 190 warn_report("Unknown L1 icache size for cpu"); 191 } 192 193 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 195 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 196 cpu->hash64_opts->slb_size))); 197 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 198 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 199 200 if (ppc_has_spr(cpu, SPR_PURR)) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 202 } 203 204 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 205 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 206 segs, sizeof(segs)))); 207 } 208 209 /* 210 * Advertise VMX/VSX (vector extensions) if available 211 * 0 / no property == no vector extensions 212 * 1 == VMX / Altivec available 213 * 2 == VSX available 214 */ 215 if (env->insns_flags & PPC_ALTIVEC) { 216 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 217 218 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 219 } 220 221 /* 222 * Advertise DFP (Decimal Floating Point) if available 223 * 0 / no property == no DFP 224 * 1 == DFP available 225 */ 226 if (env->insns_flags2 & PPC2_DFP) { 227 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 228 } 229 230 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 231 sizeof(page_sizes_prop)); 232 if (page_sizes_prop_size) { 233 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 234 page_sizes_prop, page_sizes_prop_size))); 235 } 236 237 /* Build interrupt servers properties */ 238 for (i = 0; i < smt_threads; i++) { 239 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 240 servers_prop[i] = cpu_to_be32(pir); 241 } 242 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 243 servers_prop, sizeof(*servers_prop) * smt_threads))); 244 245 return offset; 246 } 247 248 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 249 uint32_t nr_threads) 250 { 251 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 252 uint32_t pir; 253 uint64_t addr; 254 char *name; 255 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 256 uint32_t irange[2], i, rsize; 257 uint64_t *reg; 258 int offset; 259 260 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); 261 addr = PNV_ICP_BASE(chip) | (pir << 12); 262 263 irange[0] = cpu_to_be32(pir); 264 irange[1] = cpu_to_be32(nr_threads); 265 266 rsize = sizeof(uint64_t) * 2 * nr_threads; 267 reg = g_malloc(rsize); 268 for (i = 0; i < nr_threads; i++) { 269 /* We know P8 PIR is linear with thread id */ 270 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 271 reg[i * 2 + 1] = cpu_to_be64(0x1000); 272 } 273 274 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 275 offset = fdt_add_subnode(fdt, 0, name); 276 _FDT(offset); 277 g_free(name); 278 279 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 280 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 281 _FDT((fdt_setprop_string(fdt, offset, "device_type", 282 "PowerPC-External-Interrupt-Presentation"))); 283 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 284 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 285 irange, sizeof(irange)))); 286 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 287 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 288 g_free(reg); 289 } 290 291 /* 292 * Adds a PnvPHB to the chip on P8. 293 * Implemented here, like for defaults PHBs 294 */ 295 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 296 { 297 Pnv8Chip *chip8 = PNV8_CHIP(chip); 298 299 phb->chip = chip; 300 301 chip8->phbs[chip8->num_phbs] = phb; 302 chip8->num_phbs++; 303 return chip; 304 } 305 306 /* 307 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 308 * HTM is always enabled because TCG does implement HTM, it's just a 309 * degenerate implementation. 310 */ 311 static const uint8_t pa_features_207[] = { 24, 0, 312 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 313 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 314 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 315 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 316 317 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 318 { 319 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 320 int i; 321 322 pnv_dt_xscom(chip, fdt, 0, 323 cpu_to_be64(PNV_XSCOM_BASE(chip)), 324 cpu_to_be64(PNV_XSCOM_SIZE), 325 compat, sizeof(compat)); 326 327 for (i = 0; i < chip->nr_cores; i++) { 328 PnvCore *pnv_core = chip->cores[i]; 329 int offset; 330 331 offset = pnv_dt_core(chip, pnv_core, fdt); 332 333 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 334 pa_features_207, sizeof(pa_features_207)))); 335 336 /* Interrupt Control Presenters (ICP). One per core. */ 337 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 338 } 339 340 if (chip->ram_size) { 341 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 342 } 343 } 344 345 /* 346 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 347 */ 348 static const uint8_t pa_features_300[] = { 66, 0, 349 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 350 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 351 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 352 /* 6: DS207 */ 353 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 354 /* 16: Vector */ 355 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 356 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 357 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 358 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 359 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 360 /* 32: LE atomic, 34: EBB + ext EBB */ 361 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 362 /* 40: Radix MMU */ 363 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 364 /* 42: PM, 44: PC RA, 46: SC vec'd */ 365 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 366 /* 48: SIMD, 50: QP BFP, 52: String */ 367 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 368 /* 54: DecFP, 56: DecI, 58: SHA */ 369 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 370 /* 60: NM atomic, 62: RNG */ 371 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 372 }; 373 374 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 375 { 376 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 377 int i; 378 379 pnv_dt_xscom(chip, fdt, 0, 380 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 381 cpu_to_be64(PNV9_XSCOM_SIZE), 382 compat, sizeof(compat)); 383 384 for (i = 0; i < chip->nr_cores; i++) { 385 PnvCore *pnv_core = chip->cores[i]; 386 int offset; 387 388 offset = pnv_dt_core(chip, pnv_core, fdt); 389 390 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 391 pa_features_300, sizeof(pa_features_300)))); 392 } 393 394 if (chip->ram_size) { 395 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 396 } 397 398 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 399 } 400 401 /* 402 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 403 * always disables copy/paste. 404 */ 405 static const uint8_t pa_features_31[] = { 74, 0, 406 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 407 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 408 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 409 /* 6: DS207 */ 410 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 411 /* 16: Vector */ 412 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 413 /* 18: Vec. Scalar, 20: Vec. XOR */ 414 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 415 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 416 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 417 /* 32: LE atomic, 34: EBB + ext EBB */ 418 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 419 /* 40: Radix MMU */ 420 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 421 /* 42: PM, 44: PC RA, 46: SC vec'd */ 422 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 423 /* 48: SIMD, 50: QP BFP, 52: String */ 424 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 425 /* 54: DecFP, 56: DecI, 58: SHA */ 426 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 427 /* 60: NM atomic, 62: RNG */ 428 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 429 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 430 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 431 /* 72: [P]HASHST/[P]HASHCHK */ 432 0x80, 0x00, /* 72 - 73 */ 433 }; 434 435 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 436 { 437 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 438 int i; 439 440 pnv_dt_xscom(chip, fdt, 0, 441 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 442 cpu_to_be64(PNV10_XSCOM_SIZE), 443 compat, sizeof(compat)); 444 445 for (i = 0; i < chip->nr_cores; i++) { 446 PnvCore *pnv_core = chip->cores[i]; 447 int offset; 448 449 offset = pnv_dt_core(chip, pnv_core, fdt); 450 451 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 452 pa_features_31, sizeof(pa_features_31)))); 453 } 454 455 if (chip->ram_size) { 456 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 457 } 458 459 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 460 } 461 462 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 463 { 464 uint32_t io_base = d->ioport_id; 465 uint32_t io_regs[] = { 466 cpu_to_be32(1), 467 cpu_to_be32(io_base), 468 cpu_to_be32(2) 469 }; 470 char *name; 471 int node; 472 473 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 474 node = fdt_add_subnode(fdt, lpc_off, name); 475 _FDT(node); 476 g_free(name); 477 478 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 479 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 480 } 481 482 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 483 { 484 const char compatible[] = "ns16550\0pnpPNP,501"; 485 uint32_t io_base = d->ioport_id; 486 uint32_t io_regs[] = { 487 cpu_to_be32(1), 488 cpu_to_be32(io_base), 489 cpu_to_be32(8) 490 }; 491 uint32_t irq; 492 char *name; 493 int node; 494 495 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 496 497 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 498 node = fdt_add_subnode(fdt, lpc_off, name); 499 _FDT(node); 500 g_free(name); 501 502 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 503 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 504 sizeof(compatible)))); 505 506 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 507 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 508 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 509 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 510 fdt_get_phandle(fdt, lpc_off)))); 511 512 /* This is needed by Linux */ 513 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 514 } 515 516 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 517 { 518 const char compatible[] = "bt\0ipmi-bt"; 519 uint32_t io_base; 520 uint32_t io_regs[] = { 521 cpu_to_be32(1), 522 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 523 cpu_to_be32(3) 524 }; 525 uint32_t irq; 526 char *name; 527 int node; 528 529 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 530 io_regs[1] = cpu_to_be32(io_base); 531 532 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 533 534 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 535 node = fdt_add_subnode(fdt, lpc_off, name); 536 _FDT(node); 537 g_free(name); 538 539 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 540 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 541 sizeof(compatible)))); 542 543 /* Mark it as reserved to avoid Linux trying to claim it */ 544 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 545 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 546 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 547 fdt_get_phandle(fdt, lpc_off)))); 548 } 549 550 typedef struct ForeachPopulateArgs { 551 void *fdt; 552 int offset; 553 } ForeachPopulateArgs; 554 555 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 556 { 557 ForeachPopulateArgs *args = opaque; 558 ISADevice *d = ISA_DEVICE(dev); 559 560 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 561 pnv_dt_rtc(d, args->fdt, args->offset); 562 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 563 pnv_dt_serial(d, args->fdt, args->offset); 564 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 565 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 566 } else { 567 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 568 d->ioport_id); 569 } 570 571 return 0; 572 } 573 574 /* 575 * The default LPC bus of a multichip system is on chip 0. It's 576 * recognized by the firmware (skiboot) using a "primary" property. 577 */ 578 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 579 { 580 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 581 ForeachPopulateArgs args = { 582 .fdt = fdt, 583 .offset = isa_offset, 584 }; 585 uint32_t phandle; 586 587 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 588 589 phandle = qemu_fdt_alloc_phandle(fdt); 590 assert(phandle > 0); 591 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 592 593 /* 594 * ISA devices are not necessarily parented to the ISA bus so we 595 * can not use object_child_foreach() 596 */ 597 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 598 &args); 599 } 600 601 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 602 { 603 int off; 604 605 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 606 off = fdt_add_subnode(fdt, off, "power-mgt"); 607 608 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 609 } 610 611 static void *pnv_dt_create(MachineState *machine) 612 { 613 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 614 PnvMachineState *pnv = PNV_MACHINE(machine); 615 void *fdt; 616 char *buf; 617 int off; 618 int i; 619 620 fdt = g_malloc0(FDT_MAX_SIZE); 621 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 622 623 /* /qemu node */ 624 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 625 626 /* Root node */ 627 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 628 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 629 _FDT((fdt_setprop_string(fdt, 0, "model", 630 "IBM PowerNV (emulated by qemu)"))); 631 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 632 633 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 634 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 635 if (qemu_uuid_set) { 636 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 637 } 638 g_free(buf); 639 640 off = fdt_add_subnode(fdt, 0, "chosen"); 641 if (machine->kernel_cmdline) { 642 _FDT((fdt_setprop_string(fdt, off, "bootargs", 643 machine->kernel_cmdline))); 644 } 645 646 if (pnv->initrd_size) { 647 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 648 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 649 650 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 651 &start_prop, sizeof(start_prop)))); 652 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 653 &end_prop, sizeof(end_prop)))); 654 } 655 656 /* Populate device tree for each chip */ 657 for (i = 0; i < pnv->num_chips; i++) { 658 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 659 } 660 661 /* Populate ISA devices on chip 0 */ 662 pnv_dt_isa(pnv, fdt); 663 664 if (pnv->bmc) { 665 pnv_dt_bmc_sensors(pnv->bmc, fdt); 666 } 667 668 /* Create an extra node for power management on machines that support it */ 669 if (pmc->dt_power_mgt) { 670 pmc->dt_power_mgt(pnv, fdt); 671 } 672 673 return fdt; 674 } 675 676 static void pnv_powerdown_notify(Notifier *n, void *opaque) 677 { 678 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 679 680 if (pnv->bmc) { 681 pnv_bmc_powerdown(pnv->bmc); 682 } 683 } 684 685 static void pnv_reset(MachineState *machine, ShutdownCause reason) 686 { 687 PnvMachineState *pnv = PNV_MACHINE(machine); 688 IPMIBmc *bmc; 689 void *fdt; 690 691 qemu_devices_reset(reason); 692 693 /* 694 * The machine should provide by default an internal BMC simulator. 695 * If not, try to use the BMC device that was provided on the command 696 * line. 697 */ 698 bmc = pnv_bmc_find(&error_fatal); 699 if (!pnv->bmc) { 700 if (!bmc) { 701 if (!qtest_enabled()) { 702 warn_report("machine has no BMC device. Use '-device " 703 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 704 "to define one"); 705 } 706 } else { 707 pnv_bmc_set_pnor(bmc, pnv->pnor); 708 pnv->bmc = bmc; 709 } 710 } 711 712 fdt = pnv_dt_create(machine); 713 714 /* Pack resulting tree */ 715 _FDT((fdt_pack(fdt))); 716 717 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 718 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 719 720 /* 721 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 722 * the existing machine->fdt to avoid leaking it during 723 * a reset. 724 */ 725 g_free(machine->fdt); 726 machine->fdt = fdt; 727 } 728 729 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 730 { 731 Pnv8Chip *chip8 = PNV8_CHIP(chip); 732 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 733 734 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 735 736 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 737 } 738 739 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 740 { 741 Pnv8Chip *chip8 = PNV8_CHIP(chip); 742 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 743 744 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 745 746 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 747 } 748 749 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 750 { 751 Pnv9Chip *chip9 = PNV9_CHIP(chip); 752 qemu_irq irq; 753 754 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 755 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq); 756 757 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0); 758 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); 759 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1); 760 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); 761 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2); 762 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); 763 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3); 764 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); 765 766 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 767 } 768 769 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 770 { 771 Pnv10Chip *chip10 = PNV10_CHIP(chip); 772 qemu_irq irq; 773 774 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 775 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq); 776 777 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0); 778 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); 779 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1); 780 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); 781 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2); 782 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); 783 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3); 784 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); 785 786 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 787 } 788 789 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 790 { 791 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 792 } 793 794 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf) 795 { 796 Pnv8Chip *chip8 = PNV8_CHIP(chip); 797 int i; 798 799 ics_pic_print_info(&chip8->psi.ics, buf); 800 801 for (i = 0; i < chip8->num_phbs; i++) { 802 PnvPHB *phb = chip8->phbs[i]; 803 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 804 805 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 806 ics_pic_print_info(&phb3->lsis, buf); 807 } 808 } 809 810 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 811 { 812 GString *buf = opaque; 813 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 814 815 if (!phb) { 816 return 0; 817 } 818 819 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 820 821 return 0; 822 } 823 824 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf) 825 { 826 Pnv9Chip *chip9 = PNV9_CHIP(chip); 827 828 pnv_xive_pic_print_info(&chip9->xive, buf); 829 pnv_psi_pic_print_info(&chip9->psi, buf); 830 object_child_foreach_recursive(OBJECT(chip), 831 pnv_chip_power9_pic_print_info_child, buf); 832 } 833 834 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 835 uint32_t core_id) 836 { 837 return PNV_XSCOM_EX_BASE(core_id); 838 } 839 840 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 841 uint32_t core_id) 842 { 843 return PNV9_XSCOM_EC_BASE(core_id); 844 } 845 846 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 847 uint32_t core_id) 848 { 849 return PNV10_XSCOM_EC_BASE(core_id); 850 } 851 852 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 853 { 854 PowerPCCPUClass *ppc_default = 855 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 856 PowerPCCPUClass *ppc = 857 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 858 859 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 860 } 861 862 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 863 { 864 ISADevice *dev = isa_new("isa-ipmi-bt"); 865 866 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 867 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 868 isa_realize_and_unref(dev, bus, &error_fatal); 869 } 870 871 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf) 872 { 873 Pnv10Chip *chip10 = PNV10_CHIP(chip); 874 875 pnv_xive2_pic_print_info(&chip10->xive, buf); 876 pnv_psi_pic_print_info(&chip10->psi, buf); 877 object_child_foreach_recursive(OBJECT(chip), 878 pnv_chip_power9_pic_print_info_child, buf); 879 } 880 881 /* Always give the first 1GB to chip 0 else we won't boot */ 882 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 883 { 884 MachineState *machine = MACHINE(pnv); 885 uint64_t ram_per_chip; 886 887 assert(machine->ram_size >= 1 * GiB); 888 889 ram_per_chip = machine->ram_size / pnv->num_chips; 890 if (ram_per_chip >= 1 * GiB) { 891 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 892 } 893 894 assert(pnv->num_chips > 1); 895 896 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 897 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 898 } 899 900 static void pnv_init(MachineState *machine) 901 { 902 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 903 PnvMachineState *pnv = PNV_MACHINE(machine); 904 MachineClass *mc = MACHINE_GET_CLASS(machine); 905 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 906 int max_smt_threads = pmc->max_smt_threads; 907 char *fw_filename; 908 long fw_size; 909 uint64_t chip_ram_start = 0; 910 int i; 911 char *chip_typename; 912 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 913 DeviceState *dev; 914 915 if (kvm_enabled()) { 916 error_report("machine %s does not support the KVM accelerator", 917 mc->name); 918 exit(EXIT_FAILURE); 919 } 920 921 /* allocate RAM */ 922 if (machine->ram_size < mc->default_ram_size) { 923 char *sz = size_to_str(mc->default_ram_size); 924 error_report("Invalid RAM size, should be bigger than %s", sz); 925 g_free(sz); 926 exit(EXIT_FAILURE); 927 } 928 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 929 930 /* 931 * Create our simple PNOR device 932 */ 933 dev = qdev_new(TYPE_PNV_PNOR); 934 if (pnor) { 935 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 936 } 937 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 938 pnv->pnor = PNV_PNOR(dev); 939 940 /* load skiboot firmware */ 941 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 942 if (!fw_filename) { 943 error_report("Could not find OPAL firmware '%s'", bios_name); 944 exit(1); 945 } 946 947 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 948 if (fw_size < 0) { 949 error_report("Could not load OPAL firmware '%s'", fw_filename); 950 exit(1); 951 } 952 g_free(fw_filename); 953 954 /* load kernel */ 955 if (machine->kernel_filename) { 956 long kernel_size; 957 958 kernel_size = load_image_targphys(machine->kernel_filename, 959 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 960 if (kernel_size < 0) { 961 error_report("Could not load kernel '%s'", 962 machine->kernel_filename); 963 exit(1); 964 } 965 } 966 967 /* load initrd */ 968 if (machine->initrd_filename) { 969 pnv->initrd_base = INITRD_LOAD_ADDR; 970 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 971 pnv->initrd_base, INITRD_MAX_SIZE); 972 if (pnv->initrd_size < 0) { 973 error_report("Could not load initial ram disk '%s'", 974 machine->initrd_filename); 975 exit(1); 976 } 977 } 978 979 /* MSIs are supported on this platform */ 980 msi_nonbroken = true; 981 982 /* 983 * Check compatibility of the specified CPU with the machine 984 * default. 985 */ 986 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 987 error_report("invalid CPU model '%s' for %s machine", 988 machine->cpu_type, mc->name); 989 exit(1); 990 } 991 992 /* Create the processor chips */ 993 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 994 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 995 i, machine->cpu_type); 996 if (!object_class_by_name(chip_typename)) { 997 error_report("invalid chip model '%.*s' for %s machine", 998 i, machine->cpu_type, mc->name); 999 exit(1); 1000 } 1001 1002 pnv->num_chips = 1003 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 1004 1005 if (machine->smp.threads > max_smt_threads) { 1006 error_report("Cannot support more than %d threads/core " 1007 "on %s machine", max_smt_threads, mc->desc); 1008 exit(1); 1009 } 1010 1011 if (!is_power_of_2(machine->smp.threads)) { 1012 error_report("Cannot support %d threads/core on a powernv" 1013 "machine because it must be a power of 2", 1014 machine->smp.threads); 1015 exit(1); 1016 } 1017 1018 /* 1019 * TODO: should we decide on how many chips we can create based 1020 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1021 */ 1022 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1023 error_report("invalid number of chips: '%d'", pnv->num_chips); 1024 error_printf( 1025 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1026 exit(1); 1027 } 1028 1029 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1030 for (i = 0; i < pnv->num_chips; i++) { 1031 char chip_name[32]; 1032 Object *chip = OBJECT(qdev_new(chip_typename)); 1033 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1034 1035 pnv->chips[i] = PNV_CHIP(chip); 1036 1037 /* Distribute RAM among the chips */ 1038 object_property_set_int(chip, "ram-start", chip_ram_start, 1039 &error_fatal); 1040 object_property_set_int(chip, "ram-size", chip_ram_size, 1041 &error_fatal); 1042 chip_ram_start += chip_ram_size; 1043 1044 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1045 object_property_add_child(OBJECT(pnv), chip_name, chip); 1046 object_property_set_int(chip, "chip-id", i, &error_fatal); 1047 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1048 &error_fatal); 1049 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1050 &error_fatal); 1051 /* 1052 * The POWER8 machine use the XICS interrupt interface. 1053 * Propagate the XICS fabric to the chip and its controllers. 1054 */ 1055 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1056 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1057 } 1058 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1059 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1060 &error_abort); 1061 } 1062 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1063 } 1064 g_free(chip_typename); 1065 1066 /* Instantiate ISA bus on chip 0 */ 1067 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1068 1069 /* Create serial port */ 1070 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1071 1072 /* Create an RTC ISA device too */ 1073 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1074 1075 /* 1076 * Create the machine BMC simulator and the IPMI BT device for 1077 * communication with the BMC 1078 */ 1079 if (defaults_enabled()) { 1080 pnv->bmc = pnv_bmc_create(pnv->pnor); 1081 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1082 } 1083 1084 /* 1085 * The PNOR is mapped on the LPC FW address space by the BMC. 1086 * Since we can not reach the remote BMC machine with LPC memops, 1087 * map it always for now. 1088 */ 1089 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1090 &pnv->pnor->mmio); 1091 1092 /* 1093 * OpenPOWER systems use a IPMI SEL Event message to notify the 1094 * host to powerdown 1095 */ 1096 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1097 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1098 1099 /* 1100 * Create/Connect any machine-specific I2C devices 1101 */ 1102 if (pmc->i2c_init) { 1103 pmc->i2c_init(pnv); 1104 } 1105 } 1106 1107 /* 1108 * 0:21 Reserved - Read as zeros 1109 * 22:24 Chip ID 1110 * 25:28 Core number 1111 * 29:31 Thread ID 1112 */ 1113 static void pnv_get_pir_tir_p8(PnvChip *chip, 1114 uint32_t core_id, uint32_t thread_id, 1115 uint32_t *pir, uint32_t *tir) 1116 { 1117 if (pir) { 1118 *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id; 1119 } 1120 if (tir) { 1121 *tir = thread_id; 1122 } 1123 } 1124 1125 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1126 Error **errp) 1127 { 1128 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1129 Error *local_err = NULL; 1130 Object *obj; 1131 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1132 1133 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1134 if (local_err) { 1135 error_propagate(errp, local_err); 1136 return; 1137 } 1138 1139 pnv_cpu->intc = obj; 1140 } 1141 1142 1143 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1144 { 1145 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1146 1147 icp_reset(ICP(pnv_cpu->intc)); 1148 } 1149 1150 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1151 { 1152 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1153 1154 icp_destroy(ICP(pnv_cpu->intc)); 1155 pnv_cpu->intc = NULL; 1156 } 1157 1158 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1159 GString *buf) 1160 { 1161 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1162 } 1163 1164 /* 1165 * 0:48 Reserved - Read as zeroes 1166 * 49:52 Node ID 1167 * 53:55 Chip ID 1168 * 56 Reserved - Read as zero 1169 * 57:61 Core number 1170 * 62:63 Thread ID 1171 * 1172 * We only care about the lower bits. uint32_t is fine for the moment. 1173 */ 1174 static void pnv_get_pir_tir_p9(PnvChip *chip, 1175 uint32_t core_id, uint32_t thread_id, 1176 uint32_t *pir, uint32_t *tir) 1177 { 1178 if (pir) { 1179 if (chip->nr_threads == 8) { 1180 *pir = (chip->chip_id << 8) | ((thread_id & 1) << 2) | 1181 (core_id << 3) | (thread_id >> 1); 1182 } else { 1183 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1184 } 1185 } 1186 if (tir) { 1187 *tir = thread_id; 1188 } 1189 } 1190 1191 /* 1192 * 0:48 Reserved - Read as zeroes 1193 * 49:52 Node ID 1194 * 53:55 Chip ID 1195 * 56 Reserved - Read as zero 1196 * 57:59 Quad ID 1197 * 60 Core Chiplet Pair ID 1198 * 61:63 Thread/Core Chiplet ID t0-t2 1199 * 1200 * We only care about the lower bits. uint32_t is fine for the moment. 1201 */ 1202 static void pnv_get_pir_tir_p10(PnvChip *chip, 1203 uint32_t core_id, uint32_t thread_id, 1204 uint32_t *pir, uint32_t *tir) 1205 { 1206 if (pir) { 1207 if (chip->nr_threads == 8) { 1208 *pir = (chip->chip_id << 8) | ((core_id / 4) << 4) | 1209 ((core_id % 2) << 3) | thread_id; 1210 } else { 1211 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1212 } 1213 } 1214 if (tir) { 1215 *tir = thread_id; 1216 } 1217 } 1218 1219 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1220 Error **errp) 1221 { 1222 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1223 Error *local_err = NULL; 1224 Object *obj; 1225 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1226 1227 /* 1228 * The core creates its interrupt presenter but the XIVE interrupt 1229 * controller object is initialized afterwards. Hopefully, it's 1230 * only used at runtime. 1231 */ 1232 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1233 &local_err); 1234 if (local_err) { 1235 error_propagate(errp, local_err); 1236 return; 1237 } 1238 1239 pnv_cpu->intc = obj; 1240 } 1241 1242 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1243 { 1244 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1245 1246 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1247 } 1248 1249 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1250 { 1251 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1252 1253 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1254 pnv_cpu->intc = NULL; 1255 } 1256 1257 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1258 GString *buf) 1259 { 1260 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1261 } 1262 1263 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1264 Error **errp) 1265 { 1266 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1267 Error *local_err = NULL; 1268 Object *obj; 1269 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1270 1271 /* 1272 * The core creates its interrupt presenter but the XIVE2 interrupt 1273 * controller object is initialized afterwards. Hopefully, it's 1274 * only used at runtime. 1275 */ 1276 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1277 &local_err); 1278 if (local_err) { 1279 error_propagate(errp, local_err); 1280 return; 1281 } 1282 1283 pnv_cpu->intc = obj; 1284 } 1285 1286 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1287 { 1288 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1289 1290 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1291 } 1292 1293 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1294 { 1295 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1296 1297 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1298 pnv_cpu->intc = NULL; 1299 } 1300 1301 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1302 GString *buf) 1303 { 1304 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1305 } 1306 1307 /* 1308 * Allowed core identifiers on a POWER8 Processor Chip : 1309 * 1310 * <EX0 reserved> 1311 * EX1 - Venice only 1312 * EX2 - Venice only 1313 * EX3 - Venice only 1314 * EX4 1315 * EX5 1316 * EX6 1317 * <EX7,8 reserved> <reserved> 1318 * EX9 - Venice only 1319 * EX10 - Venice only 1320 * EX11 - Venice only 1321 * EX12 1322 * EX13 1323 * EX14 1324 * <EX15 reserved> 1325 */ 1326 #define POWER8E_CORE_MASK (0x7070ull) 1327 #define POWER8_CORE_MASK (0x7e7eull) 1328 1329 /* 1330 * POWER9 has 24 cores, ids starting at 0x0 1331 */ 1332 #define POWER9_CORE_MASK (0xffffffffffffffull) 1333 1334 1335 #define POWER10_CORE_MASK (0xffffffffffffffull) 1336 1337 static void pnv_chip_power8_instance_init(Object *obj) 1338 { 1339 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1340 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1341 int i; 1342 1343 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1344 (Object **)&chip8->xics, 1345 object_property_allow_set_link, 1346 OBJ_PROP_LINK_STRONG); 1347 1348 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1349 1350 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1351 1352 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1353 1354 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1355 1356 if (defaults_enabled()) { 1357 chip8->num_phbs = pcc->num_phbs; 1358 1359 for (i = 0; i < chip8->num_phbs; i++) { 1360 Object *phb = object_new(TYPE_PNV_PHB); 1361 1362 /* 1363 * We need the chip to parent the PHB to allow the DT 1364 * to build correctly (via pnv_xscom_dt()). 1365 * 1366 * TODO: the PHB should be parented by a PEC device that, at 1367 * this moment, is not modelled powernv8/phb3. 1368 */ 1369 object_property_add_child(obj, "phb[*]", phb); 1370 chip8->phbs[i] = PNV_PHB(phb); 1371 } 1372 } 1373 1374 } 1375 1376 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1377 { 1378 PnvChip *chip = PNV_CHIP(chip8); 1379 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1380 int i, j; 1381 char *name; 1382 1383 name = g_strdup_printf("icp-%x", chip->chip_id); 1384 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1385 g_free(name); 1386 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1387 &chip8->icp_mmio); 1388 1389 /* Map the ICP registers for each thread */ 1390 for (i = 0; i < chip->nr_cores; i++) { 1391 PnvCore *pnv_core = chip->cores[i]; 1392 int core_hwid = CPU_CORE(pnv_core)->core_id; 1393 1394 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1395 uint32_t pir; 1396 PnvICPState *icp; 1397 1398 pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL); 1399 icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1400 1401 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1402 &icp->mmio); 1403 } 1404 } 1405 } 1406 1407 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1408 { 1409 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1410 PnvChip *chip = PNV_CHIP(dev); 1411 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1412 Pnv8Psi *psi8 = &chip8->psi; 1413 Error *local_err = NULL; 1414 int i; 1415 1416 assert(chip8->xics); 1417 1418 /* XSCOM bridge is first */ 1419 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1420 1421 pcc->parent_realize(dev, &local_err); 1422 if (local_err) { 1423 error_propagate(errp, local_err); 1424 return; 1425 } 1426 1427 /* Processor Service Interface (PSI) Host Bridge */ 1428 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1429 &error_fatal); 1430 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1431 OBJECT(chip8->xics), &error_abort); 1432 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1433 return; 1434 } 1435 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1436 &PNV_PSI(psi8)->xscom_regs); 1437 1438 /* Create LPC controller */ 1439 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1440 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1441 1442 chip->fw_mr = &chip8->lpc.isa_fw; 1443 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1444 (uint64_t) PNV_XSCOM_BASE(chip), 1445 PNV_XSCOM_LPC_BASE); 1446 1447 /* 1448 * Interrupt Management Area. This is the memory region holding 1449 * all the Interrupt Control Presenter (ICP) registers 1450 */ 1451 pnv_chip_icp_realize(chip8, &local_err); 1452 if (local_err) { 1453 error_propagate(errp, local_err); 1454 return; 1455 } 1456 1457 /* Create the simplified OCC model */ 1458 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1459 return; 1460 } 1461 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1462 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1463 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1464 1465 /* OCC SRAM model */ 1466 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1467 &chip8->occ.sram_regs); 1468 1469 /* HOMER */ 1470 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1471 &error_abort); 1472 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1473 return; 1474 } 1475 /* Homer Xscom region */ 1476 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1477 1478 /* Homer mmio region */ 1479 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1480 &chip8->homer.regs); 1481 1482 /* PHB controllers */ 1483 for (i = 0; i < chip8->num_phbs; i++) { 1484 PnvPHB *phb = chip8->phbs[i]; 1485 1486 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1487 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1488 &error_fatal); 1489 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1490 &error_fatal); 1491 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1492 return; 1493 } 1494 } 1495 } 1496 1497 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1498 { 1499 addr &= (PNV_XSCOM_SIZE - 1); 1500 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1501 } 1502 1503 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1504 { 1505 DeviceClass *dc = DEVICE_CLASS(klass); 1506 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1507 1508 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1509 k->cores_mask = POWER8E_CORE_MASK; 1510 k->num_phbs = 3; 1511 k->get_pir_tir = pnv_get_pir_tir_p8; 1512 k->intc_create = pnv_chip_power8_intc_create; 1513 k->intc_reset = pnv_chip_power8_intc_reset; 1514 k->intc_destroy = pnv_chip_power8_intc_destroy; 1515 k->intc_print_info = pnv_chip_power8_intc_print_info; 1516 k->isa_create = pnv_chip_power8_isa_create; 1517 k->dt_populate = pnv_chip_power8_dt_populate; 1518 k->pic_print_info = pnv_chip_power8_pic_print_info; 1519 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1520 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1521 dc->desc = "PowerNV Chip POWER8E"; 1522 1523 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1524 &k->parent_realize); 1525 } 1526 1527 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1528 { 1529 DeviceClass *dc = DEVICE_CLASS(klass); 1530 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1531 1532 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1533 k->cores_mask = POWER8_CORE_MASK; 1534 k->num_phbs = 3; 1535 k->get_pir_tir = pnv_get_pir_tir_p8; 1536 k->intc_create = pnv_chip_power8_intc_create; 1537 k->intc_reset = pnv_chip_power8_intc_reset; 1538 k->intc_destroy = pnv_chip_power8_intc_destroy; 1539 k->intc_print_info = pnv_chip_power8_intc_print_info; 1540 k->isa_create = pnv_chip_power8_isa_create; 1541 k->dt_populate = pnv_chip_power8_dt_populate; 1542 k->pic_print_info = pnv_chip_power8_pic_print_info; 1543 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1544 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1545 dc->desc = "PowerNV Chip POWER8"; 1546 1547 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1548 &k->parent_realize); 1549 } 1550 1551 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1552 { 1553 DeviceClass *dc = DEVICE_CLASS(klass); 1554 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1555 1556 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1557 k->cores_mask = POWER8_CORE_MASK; 1558 k->num_phbs = 4; 1559 k->get_pir_tir = pnv_get_pir_tir_p8; 1560 k->intc_create = pnv_chip_power8_intc_create; 1561 k->intc_reset = pnv_chip_power8_intc_reset; 1562 k->intc_destroy = pnv_chip_power8_intc_destroy; 1563 k->intc_print_info = pnv_chip_power8_intc_print_info; 1564 k->isa_create = pnv_chip_power8nvl_isa_create; 1565 k->dt_populate = pnv_chip_power8_dt_populate; 1566 k->pic_print_info = pnv_chip_power8_pic_print_info; 1567 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1568 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1569 dc->desc = "PowerNV Chip POWER8NVL"; 1570 1571 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1572 &k->parent_realize); 1573 } 1574 1575 static void pnv_chip_power9_instance_init(Object *obj) 1576 { 1577 PnvChip *chip = PNV_CHIP(obj); 1578 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1579 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1580 int i; 1581 1582 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU); 1583 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1584 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1585 "xive-fabric"); 1586 1587 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1588 1589 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1590 1591 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1592 1593 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1594 1595 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1596 1597 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1598 1599 /* Number of PECs is the chip default */ 1600 chip->num_pecs = pcc->num_pecs; 1601 1602 for (i = 0; i < chip->num_pecs; i++) { 1603 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1604 TYPE_PNV_PHB4_PEC); 1605 } 1606 1607 for (i = 0; i < pcc->i2c_num_engines; i++) { 1608 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1609 } 1610 } 1611 1612 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1613 PnvCore *pnv_core, 1614 const char *type) 1615 { 1616 char eq_name[32]; 1617 int core_id = CPU_CORE(pnv_core)->core_id; 1618 1619 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1620 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1621 sizeof(*eq), type, 1622 &error_fatal, NULL); 1623 1624 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1625 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1626 } 1627 1628 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1629 { 1630 PnvChip *chip = PNV_CHIP(chip9); 1631 int i; 1632 1633 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1634 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1635 1636 for (i = 0; i < chip9->nr_quads; i++) { 1637 PnvQuad *eq = &chip9->quads[i]; 1638 1639 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1640 PNV_QUAD_TYPE_NAME("power9")); 1641 1642 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1643 &eq->xscom_regs); 1644 } 1645 } 1646 1647 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1648 { 1649 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1650 int i; 1651 1652 for (i = 0; i < chip->num_pecs; i++) { 1653 PnvPhb4PecState *pec = &chip9->pecs[i]; 1654 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1655 uint32_t pec_nest_base; 1656 uint32_t pec_pci_base; 1657 1658 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1659 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1660 &error_fatal); 1661 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1662 &error_fatal); 1663 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1664 return; 1665 } 1666 1667 pec_nest_base = pecc->xscom_nest_base(pec); 1668 pec_pci_base = pecc->xscom_pci_base(pec); 1669 1670 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1671 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1672 } 1673 } 1674 1675 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1676 { 1677 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1678 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1679 PnvChip *chip = PNV_CHIP(dev); 1680 Pnv9Psi *psi9 = &chip9->psi; 1681 Error *local_err = NULL; 1682 int i; 1683 1684 /* XSCOM bridge is first */ 1685 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1686 1687 pcc->parent_realize(dev, &local_err); 1688 if (local_err) { 1689 error_propagate(errp, local_err); 1690 return; 1691 } 1692 1693 /* ADU */ 1694 object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc), 1695 &error_abort); 1696 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { 1697 return; 1698 } 1699 pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE, 1700 &chip9->adu.xscom_regs); 1701 1702 pnv_chip_quad_realize(chip9, &local_err); 1703 if (local_err) { 1704 error_propagate(errp, local_err); 1705 return; 1706 } 1707 1708 /* XIVE interrupt controller (POWER9) */ 1709 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1710 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1711 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1712 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1713 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1714 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1715 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1716 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1717 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1718 &error_abort); 1719 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1720 return; 1721 } 1722 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1723 &chip9->xive.xscom_regs); 1724 1725 /* Processor Service Interface (PSI) Host Bridge */ 1726 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1727 &error_fatal); 1728 /* This is the only device with 4k ESB pages */ 1729 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1730 &error_fatal); 1731 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1732 return; 1733 } 1734 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1735 &PNV_PSI(psi9)->xscom_regs); 1736 1737 /* LPC */ 1738 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1739 return; 1740 } 1741 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1742 &chip9->lpc.xscom_regs); 1743 1744 chip->fw_mr = &chip9->lpc.isa_fw; 1745 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1746 (uint64_t) PNV9_LPCM_BASE(chip)); 1747 1748 /* ChipTOD */ 1749 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1750 chip->chip_id == 0, &error_abort); 1751 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1752 chip->chip_id == 1, &error_abort); 1753 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1754 &error_abort); 1755 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1756 return; 1757 } 1758 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1759 &chip9->chiptod.xscom_regs); 1760 1761 /* Create the simplified OCC model */ 1762 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1763 return; 1764 } 1765 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1766 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1767 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1768 1769 /* OCC SRAM model */ 1770 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1771 &chip9->occ.sram_regs); 1772 1773 /* SBE */ 1774 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1775 return; 1776 } 1777 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1778 &chip9->sbe.xscom_ctrl_regs); 1779 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1780 &chip9->sbe.xscom_mbox_regs); 1781 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1782 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1783 1784 /* HOMER */ 1785 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1786 &error_abort); 1787 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1788 return; 1789 } 1790 /* Homer Xscom region */ 1791 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1792 1793 /* Homer mmio region */ 1794 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1795 &chip9->homer.regs); 1796 1797 /* PEC PHBs */ 1798 pnv_chip_power9_pec_realize(chip, &local_err); 1799 if (local_err) { 1800 error_propagate(errp, local_err); 1801 return; 1802 } 1803 1804 /* 1805 * I2C 1806 */ 1807 for (i = 0; i < pcc->i2c_num_engines; i++) { 1808 Object *obj = OBJECT(&chip9->i2c[i]); 1809 1810 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1811 object_property_set_int(obj, "num-busses", 1812 pcc->i2c_ports_per_engine[i], 1813 &error_fatal); 1814 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1815 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1816 return; 1817 } 1818 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1819 (chip9->i2c[i].engine - 1) * 1820 PNV9_XSCOM_I2CM_SIZE, 1821 &chip9->i2c[i].xscom_regs); 1822 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1823 qdev_get_gpio_in(DEVICE(psi9), 1824 PSIHB9_IRQ_SBE_I2C)); 1825 } 1826 } 1827 1828 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1829 { 1830 addr &= (PNV9_XSCOM_SIZE - 1); 1831 return addr >> 3; 1832 } 1833 1834 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1835 { 1836 DeviceClass *dc = DEVICE_CLASS(klass); 1837 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1838 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1839 1840 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1841 k->cores_mask = POWER9_CORE_MASK; 1842 k->get_pir_tir = pnv_get_pir_tir_p9; 1843 k->intc_create = pnv_chip_power9_intc_create; 1844 k->intc_reset = pnv_chip_power9_intc_reset; 1845 k->intc_destroy = pnv_chip_power9_intc_destroy; 1846 k->intc_print_info = pnv_chip_power9_intc_print_info; 1847 k->isa_create = pnv_chip_power9_isa_create; 1848 k->dt_populate = pnv_chip_power9_dt_populate; 1849 k->pic_print_info = pnv_chip_power9_pic_print_info; 1850 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1851 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1852 dc->desc = "PowerNV Chip POWER9"; 1853 k->num_pecs = PNV9_CHIP_MAX_PEC; 1854 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1855 k->i2c_ports_per_engine = i2c_ports_per_engine; 1856 1857 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1858 &k->parent_realize); 1859 } 1860 1861 static void pnv_chip_power10_instance_init(Object *obj) 1862 { 1863 PnvChip *chip = PNV_CHIP(obj); 1864 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1865 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1866 int i; 1867 1868 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); 1869 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1870 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1871 "xive-fabric"); 1872 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1873 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1874 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1875 TYPE_PNV10_CHIPTOD); 1876 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1877 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1878 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1879 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1880 TYPE_PNV_N1_CHIPLET); 1881 1882 chip->num_pecs = pcc->num_pecs; 1883 1884 for (i = 0; i < chip->num_pecs; i++) { 1885 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1886 TYPE_PNV_PHB5_PEC); 1887 } 1888 1889 for (i = 0; i < pcc->i2c_num_engines; i++) { 1890 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1891 } 1892 } 1893 1894 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1895 { 1896 PnvChip *chip = PNV_CHIP(chip10); 1897 int i; 1898 1899 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1900 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1901 1902 for (i = 0; i < chip10->nr_quads; i++) { 1903 PnvQuad *eq = &chip10->quads[i]; 1904 1905 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1906 PNV_QUAD_TYPE_NAME("power10")); 1907 1908 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1909 &eq->xscom_regs); 1910 1911 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1912 &eq->xscom_qme_regs); 1913 } 1914 } 1915 1916 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1917 { 1918 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1919 int i; 1920 1921 for (i = 0; i < chip->num_pecs; i++) { 1922 PnvPhb4PecState *pec = &chip10->pecs[i]; 1923 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1924 uint32_t pec_nest_base; 1925 uint32_t pec_pci_base; 1926 1927 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1928 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1929 &error_fatal); 1930 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1931 &error_fatal); 1932 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1933 return; 1934 } 1935 1936 pec_nest_base = pecc->xscom_nest_base(pec); 1937 pec_pci_base = pecc->xscom_pci_base(pec); 1938 1939 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1940 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1941 } 1942 } 1943 1944 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1945 { 1946 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1947 PnvChip *chip = PNV_CHIP(dev); 1948 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1949 Error *local_err = NULL; 1950 int i; 1951 1952 /* XSCOM bridge is first */ 1953 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 1954 1955 pcc->parent_realize(dev, &local_err); 1956 if (local_err) { 1957 error_propagate(errp, local_err); 1958 return; 1959 } 1960 1961 /* ADU */ 1962 object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc), 1963 &error_abort); 1964 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { 1965 return; 1966 } 1967 pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE, 1968 &chip10->adu.xscom_regs); 1969 1970 pnv_chip_power10_quad_realize(chip10, &local_err); 1971 if (local_err) { 1972 error_propagate(errp, local_err); 1973 return; 1974 } 1975 1976 /* XIVE2 interrupt controller (POWER10) */ 1977 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1978 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1979 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1980 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1981 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1982 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1983 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1984 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1985 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1986 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1987 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1988 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1989 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1990 &error_abort); 1991 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1992 return; 1993 } 1994 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1995 &chip10->xive.xscom_regs); 1996 1997 /* Processor Service Interface (PSI) Host Bridge */ 1998 object_property_set_int(OBJECT(&chip10->psi), "bar", 1999 PNV10_PSIHB_BASE(chip), &error_fatal); 2000 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 2001 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 2002 &error_fatal); 2003 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 2004 return; 2005 } 2006 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 2007 &PNV_PSI(&chip10->psi)->xscom_regs); 2008 2009 /* LPC */ 2010 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 2011 return; 2012 } 2013 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 2014 &chip10->lpc.xscom_regs); 2015 2016 chip->fw_mr = &chip10->lpc.isa_fw; 2017 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 2018 (uint64_t) PNV10_LPCM_BASE(chip)); 2019 2020 /* ChipTOD */ 2021 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 2022 chip->chip_id == 0, &error_abort); 2023 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 2024 chip->chip_id == 1, &error_abort); 2025 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 2026 &error_abort); 2027 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 2028 return; 2029 } 2030 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 2031 &chip10->chiptod.xscom_regs); 2032 2033 /* Create the simplified OCC model */ 2034 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 2035 return; 2036 } 2037 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 2038 &chip10->occ.xscom_regs); 2039 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 2040 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 2041 2042 /* OCC SRAM model */ 2043 memory_region_add_subregion(get_system_memory(), 2044 PNV10_OCC_SENSOR_BASE(chip), 2045 &chip10->occ.sram_regs); 2046 2047 /* SBE */ 2048 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 2049 return; 2050 } 2051 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2052 &chip10->sbe.xscom_ctrl_regs); 2053 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2054 &chip10->sbe.xscom_mbox_regs); 2055 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2056 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2057 2058 /* HOMER */ 2059 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2060 &error_abort); 2061 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2062 return; 2063 } 2064 /* Homer Xscom region */ 2065 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2066 &chip10->homer.pba_regs); 2067 2068 /* Homer mmio region */ 2069 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 2070 &chip10->homer.regs); 2071 2072 /* N1 chiplet */ 2073 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2074 return; 2075 } 2076 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2077 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2078 2079 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2080 &chip10->n1_chiplet.xscom_pb_eq_mr); 2081 2082 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2083 &chip10->n1_chiplet.xscom_pb_es_mr); 2084 2085 /* PHBs */ 2086 pnv_chip_power10_phb_realize(chip, &local_err); 2087 if (local_err) { 2088 error_propagate(errp, local_err); 2089 return; 2090 } 2091 2092 2093 /* 2094 * I2C 2095 */ 2096 for (i = 0; i < pcc->i2c_num_engines; i++) { 2097 Object *obj = OBJECT(&chip10->i2c[i]); 2098 2099 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2100 object_property_set_int(obj, "num-busses", 2101 pcc->i2c_ports_per_engine[i], 2102 &error_fatal); 2103 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2104 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2105 return; 2106 } 2107 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2108 (chip10->i2c[i].engine - 1) * 2109 PNV10_XSCOM_I2CM_SIZE, 2110 &chip10->i2c[i].xscom_regs); 2111 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2112 qdev_get_gpio_in(DEVICE(&chip10->psi), 2113 PSIHB9_IRQ_SBE_I2C)); 2114 } 2115 2116 } 2117 2118 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2119 { 2120 int i; 2121 for (i = 0; i < pnv->num_chips; i++) { 2122 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2123 2124 /* 2125 * Add a PCA9552 I2C device for PCIe hotplug control 2126 * to engine 2, bus 1, address 0x63 2127 */ 2128 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2129 "pca9552", 0x63); 2130 2131 /* 2132 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2133 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2134 * after hypervisor code sets a SLOTx_EN pin high. 2135 */ 2136 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2137 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2138 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2139 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2140 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2141 2142 /* 2143 * Add a PCA9554 I2C device for cable card presence detection 2144 * to engine 2, bus 1, address 0x25 2145 */ 2146 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2147 } 2148 } 2149 2150 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2151 { 2152 addr &= (PNV10_XSCOM_SIZE - 1); 2153 return addr >> 3; 2154 } 2155 2156 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2157 { 2158 DeviceClass *dc = DEVICE_CLASS(klass); 2159 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2160 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2161 2162 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */ 2163 k->cores_mask = POWER10_CORE_MASK; 2164 k->get_pir_tir = pnv_get_pir_tir_p10; 2165 k->intc_create = pnv_chip_power10_intc_create; 2166 k->intc_reset = pnv_chip_power10_intc_reset; 2167 k->intc_destroy = pnv_chip_power10_intc_destroy; 2168 k->intc_print_info = pnv_chip_power10_intc_print_info; 2169 k->isa_create = pnv_chip_power10_isa_create; 2170 k->dt_populate = pnv_chip_power10_dt_populate; 2171 k->pic_print_info = pnv_chip_power10_pic_print_info; 2172 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2173 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2174 dc->desc = "PowerNV Chip POWER10"; 2175 k->num_pecs = PNV10_CHIP_MAX_PEC; 2176 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2177 k->i2c_ports_per_engine = i2c_ports_per_engine; 2178 2179 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2180 &k->parent_realize); 2181 } 2182 2183 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 2184 { 2185 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2186 int cores_max; 2187 2188 /* 2189 * No custom mask for this chip, let's use the default one from * 2190 * the chip class 2191 */ 2192 if (!chip->cores_mask) { 2193 chip->cores_mask = pcc->cores_mask; 2194 } 2195 2196 /* filter alien core ids ! some are reserved */ 2197 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2198 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2199 chip->cores_mask); 2200 return; 2201 } 2202 chip->cores_mask &= pcc->cores_mask; 2203 2204 /* now that we have a sane layout, let check the number of cores */ 2205 cores_max = ctpop64(chip->cores_mask); 2206 if (chip->nr_cores > cores_max) { 2207 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2208 cores_max); 2209 return; 2210 } 2211 } 2212 2213 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2214 { 2215 Error *error = NULL; 2216 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2217 const char *typename = pnv_chip_core_typename(chip); 2218 int i, core_hwid; 2219 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2220 2221 if (!object_class_by_name(typename)) { 2222 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2223 return; 2224 } 2225 2226 /* Cores */ 2227 pnv_chip_core_sanitize(chip, &error); 2228 if (error) { 2229 error_propagate(errp, error); 2230 return; 2231 } 2232 2233 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2234 2235 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2236 && (i < chip->nr_cores); core_hwid++) { 2237 char core_name[32]; 2238 PnvCore *pnv_core; 2239 uint64_t xscom_core_base; 2240 2241 if (!(chip->cores_mask & (1ull << core_hwid))) { 2242 continue; 2243 } 2244 2245 pnv_core = PNV_CORE(object_new(typename)); 2246 2247 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2248 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2249 chip->cores[i] = pnv_core; 2250 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2251 chip->nr_threads, &error_fatal); 2252 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2253 core_hwid, &error_fatal); 2254 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2255 &error_fatal); 2256 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2257 &error_fatal); 2258 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2259 &error_abort); 2260 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2261 2262 /* Each core has an XSCOM MMIO region */ 2263 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2264 2265 pnv_xscom_add_subregion(chip, xscom_core_base, 2266 &pnv_core->xscom_regs); 2267 i++; 2268 } 2269 } 2270 2271 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2272 { 2273 PnvChip *chip = PNV_CHIP(dev); 2274 Error *error = NULL; 2275 2276 /* Cores */ 2277 pnv_chip_core_realize(chip, &error); 2278 if (error) { 2279 error_propagate(errp, error); 2280 return; 2281 } 2282 } 2283 2284 static Property pnv_chip_properties[] = { 2285 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2286 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2287 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2288 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2289 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2290 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2291 DEFINE_PROP_END_OF_LIST(), 2292 }; 2293 2294 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2295 { 2296 DeviceClass *dc = DEVICE_CLASS(klass); 2297 2298 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2299 dc->realize = pnv_chip_realize; 2300 device_class_set_props(dc, pnv_chip_properties); 2301 dc->desc = "PowerNV Chip"; 2302 } 2303 2304 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2305 { 2306 int i; 2307 2308 for (i = 0; i < chip->nr_cores; i++) { 2309 PnvCore *pc = chip->cores[i]; 2310 CPUCore *cc = CPU_CORE(pc); 2311 2312 if (cc->core_id == core_id) { 2313 return pc; 2314 } 2315 } 2316 return NULL; 2317 } 2318 2319 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2320 { 2321 int i, j; 2322 2323 for (i = 0; i < chip->nr_cores; i++) { 2324 PnvCore *pc = chip->cores[i]; 2325 CPUCore *cc = CPU_CORE(pc); 2326 2327 for (j = 0; j < cc->nr_threads; j++) { 2328 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2329 return pc->threads[j]; 2330 } 2331 } 2332 } 2333 return NULL; 2334 } 2335 2336 static void pnv_chip_foreach_cpu(PnvChip *chip, 2337 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque), 2338 void *opaque) 2339 { 2340 int i, j; 2341 2342 for (i = 0; i < chip->nr_cores; i++) { 2343 PnvCore *pc = chip->cores[i]; 2344 2345 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) { 2346 fn(chip, pc->threads[j], opaque); 2347 } 2348 } 2349 } 2350 2351 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2352 { 2353 PnvMachineState *pnv = PNV_MACHINE(xi); 2354 int i, j; 2355 2356 for (i = 0; i < pnv->num_chips; i++) { 2357 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2358 2359 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2360 return &chip8->psi.ics; 2361 } 2362 2363 for (j = 0; j < chip8->num_phbs; j++) { 2364 PnvPHB *phb = chip8->phbs[j]; 2365 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2366 2367 if (ics_valid_irq(&phb3->lsis, irq)) { 2368 return &phb3->lsis; 2369 } 2370 2371 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2372 return ICS(&phb3->msis); 2373 } 2374 } 2375 } 2376 return NULL; 2377 } 2378 2379 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2380 { 2381 int i; 2382 2383 for (i = 0; i < pnv->num_chips; i++) { 2384 PnvChip *chip = pnv->chips[i]; 2385 if (chip->chip_id == chip_id) { 2386 return chip; 2387 } 2388 } 2389 return NULL; 2390 } 2391 2392 static void pnv_ics_resend(XICSFabric *xi) 2393 { 2394 PnvMachineState *pnv = PNV_MACHINE(xi); 2395 int i, j; 2396 2397 for (i = 0; i < pnv->num_chips; i++) { 2398 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2399 2400 ics_resend(&chip8->psi.ics); 2401 2402 for (j = 0; j < chip8->num_phbs; j++) { 2403 PnvPHB *phb = chip8->phbs[j]; 2404 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2405 2406 ics_resend(&phb3->lsis); 2407 ics_resend(ICS(&phb3->msis)); 2408 } 2409 } 2410 } 2411 2412 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2413 { 2414 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2415 2416 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2417 } 2418 2419 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 2420 void *opaque) 2421 { 2422 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); 2423 } 2424 2425 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf) 2426 { 2427 PnvMachineState *pnv = PNV_MACHINE(obj); 2428 int i; 2429 2430 for (i = 0; i < pnv->num_chips; i++) { 2431 PnvChip *chip = pnv->chips[i]; 2432 2433 /* First CPU presenters */ 2434 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf); 2435 2436 /* Then other devices, PHB, PSI, XIVE */ 2437 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); 2438 } 2439 } 2440 2441 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2442 uint8_t nvt_blk, uint32_t nvt_idx, 2443 bool cam_ignore, uint8_t priority, 2444 uint32_t logic_serv, 2445 XiveTCTXMatch *match) 2446 { 2447 PnvMachineState *pnv = PNV_MACHINE(xfb); 2448 int total_count = 0; 2449 int i; 2450 2451 for (i = 0; i < pnv->num_chips; i++) { 2452 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2453 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2454 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2455 int count; 2456 2457 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2458 priority, logic_serv, match); 2459 2460 if (count < 0) { 2461 return count; 2462 } 2463 2464 total_count += count; 2465 } 2466 2467 return total_count; 2468 } 2469 2470 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2471 uint8_t nvt_blk, uint32_t nvt_idx, 2472 bool cam_ignore, uint8_t priority, 2473 uint32_t logic_serv, 2474 XiveTCTXMatch *match) 2475 { 2476 PnvMachineState *pnv = PNV_MACHINE(xfb); 2477 int total_count = 0; 2478 int i; 2479 2480 for (i = 0; i < pnv->num_chips; i++) { 2481 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2482 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2483 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2484 int count; 2485 2486 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2487 priority, logic_serv, match); 2488 2489 if (count < 0) { 2490 return count; 2491 } 2492 2493 total_count += count; 2494 } 2495 2496 return total_count; 2497 } 2498 2499 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2500 { 2501 MachineClass *mc = MACHINE_CLASS(oc); 2502 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2503 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2504 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2505 2506 static GlobalProperty phb_compat[] = { 2507 { TYPE_PNV_PHB, "version", "3" }, 2508 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2509 }; 2510 2511 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2512 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2513 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2514 2515 xic->icp_get = pnv_icp_get; 2516 xic->ics_get = pnv_ics_get; 2517 xic->ics_resend = pnv_ics_resend; 2518 2519 pmc->compat = compat; 2520 pmc->compat_size = sizeof(compat); 2521 pmc->max_smt_threads = 8; 2522 2523 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2524 } 2525 2526 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2527 { 2528 MachineClass *mc = MACHINE_CLASS(oc); 2529 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2530 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2531 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2532 2533 static GlobalProperty phb_compat[] = { 2534 { TYPE_PNV_PHB, "version", "4" }, 2535 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2536 }; 2537 2538 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2539 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2540 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2541 2542 xfc->match_nvt = pnv_match_nvt; 2543 2544 pmc->compat = compat; 2545 pmc->compat_size = sizeof(compat); 2546 pmc->max_smt_threads = 4; 2547 pmc->dt_power_mgt = pnv_dt_power_mgt; 2548 2549 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2550 } 2551 2552 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2553 { 2554 MachineClass *mc = MACHINE_CLASS(oc); 2555 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2556 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2557 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2558 2559 static GlobalProperty phb_compat[] = { 2560 { TYPE_PNV_PHB, "version", "5" }, 2561 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2562 }; 2563 2564 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2565 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2566 2567 mc->alias = "powernv"; 2568 2569 pmc->compat = compat; 2570 pmc->compat_size = sizeof(compat); 2571 pmc->max_smt_threads = 4; 2572 pmc->dt_power_mgt = pnv_dt_power_mgt; 2573 2574 xfc->match_nvt = pnv10_xive_match_nvt; 2575 2576 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2577 } 2578 2579 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2580 { 2581 MachineClass *mc = MACHINE_CLASS(oc); 2582 2583 pnv_machine_p10_common_class_init(oc, data); 2584 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2585 } 2586 2587 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2588 { 2589 MachineClass *mc = MACHINE_CLASS(oc); 2590 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2591 2592 pnv_machine_p10_common_class_init(oc, data); 2593 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2594 pmc->i2c_init = pnv_rainier_i2c_init; 2595 } 2596 2597 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2598 { 2599 PnvMachineState *pnv = PNV_MACHINE(obj); 2600 2601 return !!pnv->fw_load_addr; 2602 } 2603 2604 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2605 { 2606 PnvMachineState *pnv = PNV_MACHINE(obj); 2607 2608 if (value) { 2609 pnv->fw_load_addr = 0x8000000; 2610 } 2611 } 2612 2613 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2614 { 2615 CPUPPCState *env = cpu_env(cs); 2616 2617 cpu_synchronize_state(cs); 2618 ppc_cpu_do_system_reset(cs); 2619 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2620 /* 2621 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2622 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2623 * (PPC_BIT(43)). 2624 */ 2625 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2626 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2627 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2628 } 2629 } else { 2630 /* 2631 * For non-powersave system resets, SRR1[42:45] are defined to be 2632 * implementation-dependent. The POWER9 User Manual specifies that 2633 * an external (SCOM driven, which may come from a BMC nmi command or 2634 * another CPU requesting a NMI IPI) system reset exception should be 2635 * 0b0010 (PPC_BIT(44)). 2636 */ 2637 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2638 } 2639 } 2640 2641 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque) 2642 { 2643 async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2644 } 2645 2646 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2647 { 2648 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2649 int i; 2650 2651 for (i = 0; i < pnv->num_chips; i++) { 2652 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL); 2653 } 2654 } 2655 2656 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2657 { 2658 MachineClass *mc = MACHINE_CLASS(oc); 2659 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2660 NMIClass *nc = NMI_CLASS(oc); 2661 2662 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2663 mc->init = pnv_init; 2664 mc->reset = pnv_reset; 2665 mc->max_cpus = MAX_CPUS; 2666 /* Pnv provides a AHCI device for storage */ 2667 mc->block_default_type = IF_IDE; 2668 mc->no_parallel = 1; 2669 mc->default_boot_order = NULL; 2670 /* 2671 * RAM defaults to less than 2048 for 32-bit hosts, and large 2672 * enough to fit the maximum initrd size at it's load address 2673 */ 2674 mc->default_ram_size = 1 * GiB; 2675 mc->default_ram_id = "pnv.ram"; 2676 ispc->print_info = pnv_pic_print_info; 2677 nc->nmi_monitor_handler = pnv_nmi; 2678 2679 object_class_property_add_bool(oc, "hb-mode", 2680 pnv_machine_get_hb, pnv_machine_set_hb); 2681 object_class_property_set_description(oc, "hb-mode", 2682 "Use a hostboot like boot loader"); 2683 } 2684 2685 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2686 { \ 2687 .name = type, \ 2688 .class_init = class_initfn, \ 2689 .parent = TYPE_PNV8_CHIP, \ 2690 } 2691 2692 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2693 { \ 2694 .name = type, \ 2695 .class_init = class_initfn, \ 2696 .parent = TYPE_PNV9_CHIP, \ 2697 } 2698 2699 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2700 { \ 2701 .name = type, \ 2702 .class_init = class_initfn, \ 2703 .parent = TYPE_PNV10_CHIP, \ 2704 } 2705 2706 static const TypeInfo types[] = { 2707 { 2708 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2709 .parent = MACHINE_TYPE_NAME("powernv10"), 2710 .class_init = pnv_machine_p10_rainier_class_init, 2711 }, 2712 { 2713 .name = MACHINE_TYPE_NAME("powernv10"), 2714 .parent = TYPE_PNV_MACHINE, 2715 .class_init = pnv_machine_power10_class_init, 2716 .interfaces = (InterfaceInfo[]) { 2717 { TYPE_XIVE_FABRIC }, 2718 { }, 2719 }, 2720 }, 2721 { 2722 .name = MACHINE_TYPE_NAME("powernv9"), 2723 .parent = TYPE_PNV_MACHINE, 2724 .class_init = pnv_machine_power9_class_init, 2725 .interfaces = (InterfaceInfo[]) { 2726 { TYPE_XIVE_FABRIC }, 2727 { }, 2728 }, 2729 }, 2730 { 2731 .name = MACHINE_TYPE_NAME("powernv8"), 2732 .parent = TYPE_PNV_MACHINE, 2733 .class_init = pnv_machine_power8_class_init, 2734 .interfaces = (InterfaceInfo[]) { 2735 { TYPE_XICS_FABRIC }, 2736 { }, 2737 }, 2738 }, 2739 { 2740 .name = TYPE_PNV_MACHINE, 2741 .parent = TYPE_MACHINE, 2742 .abstract = true, 2743 .instance_size = sizeof(PnvMachineState), 2744 .class_init = pnv_machine_class_init, 2745 .class_size = sizeof(PnvMachineClass), 2746 .interfaces = (InterfaceInfo[]) { 2747 { TYPE_INTERRUPT_STATS_PROVIDER }, 2748 { TYPE_NMI }, 2749 { }, 2750 }, 2751 }, 2752 { 2753 .name = TYPE_PNV_CHIP, 2754 .parent = TYPE_SYS_BUS_DEVICE, 2755 .class_init = pnv_chip_class_init, 2756 .instance_size = sizeof(PnvChip), 2757 .class_size = sizeof(PnvChipClass), 2758 .abstract = true, 2759 }, 2760 2761 /* 2762 * P10 chip and variants 2763 */ 2764 { 2765 .name = TYPE_PNV10_CHIP, 2766 .parent = TYPE_PNV_CHIP, 2767 .instance_init = pnv_chip_power10_instance_init, 2768 .instance_size = sizeof(Pnv10Chip), 2769 }, 2770 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2771 2772 /* 2773 * P9 chip and variants 2774 */ 2775 { 2776 .name = TYPE_PNV9_CHIP, 2777 .parent = TYPE_PNV_CHIP, 2778 .instance_init = pnv_chip_power9_instance_init, 2779 .instance_size = sizeof(Pnv9Chip), 2780 }, 2781 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2782 2783 /* 2784 * P8 chip and variants 2785 */ 2786 { 2787 .name = TYPE_PNV8_CHIP, 2788 .parent = TYPE_PNV_CHIP, 2789 .instance_init = pnv_chip_power8_instance_init, 2790 .instance_size = sizeof(Pnv8Chip), 2791 }, 2792 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2793 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2794 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2795 pnv_chip_power8nvl_class_init), 2796 }; 2797 2798 DEFINE_TYPES(types) 2799