1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci-host/pnv_phb.h" 47 #include "hw/pci-host/pnv_phb3.h" 48 #include "hw/pci-host/pnv_phb4.h" 49 50 #include "hw/ppc/xics.h" 51 #include "hw/qdev-properties.h" 52 #include "hw/ppc/pnv_chip.h" 53 #include "hw/ppc/pnv_xscom.h" 54 #include "hw/ppc/pnv_pnor.h" 55 56 #include "hw/isa/isa.h" 57 #include "hw/char/serial.h" 58 #include "hw/rtc/mc146818rtc.h" 59 60 #include <libfdt.h> 61 62 #define FDT_MAX_SIZE (1 * MiB) 63 64 #define FW_FILE_NAME "skiboot.lid" 65 #define FW_LOAD_ADDR 0x0 66 #define FW_MAX_SIZE (16 * MiB) 67 68 #define KERNEL_LOAD_ADDR 0x20000000 69 #define KERNEL_MAX_SIZE (128 * MiB) 70 #define INITRD_LOAD_ADDR 0x28000000 71 #define INITRD_MAX_SIZE (128 * MiB) 72 73 static const char *pnv_chip_core_typename(const PnvChip *o) 74 { 75 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 76 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 77 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 78 const char *core_type = object_class_get_name(object_class_by_name(s)); 79 g_free(s); 80 return core_type; 81 } 82 83 /* 84 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 85 * 4 * 4 sockets * 12 cores * 8 threads = 1536 86 * Let's make it 2^11 87 */ 88 #define MAX_CPUS 2048 89 90 /* 91 * Memory nodes are created by hostboot, one for each range of memory 92 * that has a different "affinity". In practice, it means one range 93 * per chip. 94 */ 95 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 96 { 97 char *mem_name; 98 uint64_t mem_reg_property[2]; 99 int off; 100 101 mem_reg_property[0] = cpu_to_be64(start); 102 mem_reg_property[1] = cpu_to_be64(size); 103 104 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 105 off = fdt_add_subnode(fdt, 0, mem_name); 106 g_free(mem_name); 107 108 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 109 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 110 sizeof(mem_reg_property)))); 111 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 112 } 113 114 static int get_cpus_node(void *fdt) 115 { 116 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 117 118 if (cpus_offset < 0) { 119 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 120 if (cpus_offset) { 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 123 } 124 } 125 _FDT(cpus_offset); 126 return cpus_offset; 127 } 128 129 /* 130 * The PowerNV cores (and threads) need to use real HW ids and not an 131 * incremental index like it has been done on other platforms. This HW 132 * id is stored in the CPU PIR, it is used to create cpu nodes in the 133 * device tree, used in XSCOM to address cores and in interrupt 134 * servers. 135 */ 136 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 137 { 138 PowerPCCPU *cpu = pc->threads[0]; 139 CPUState *cs = CPU(cpu); 140 DeviceClass *dc = DEVICE_GET_CLASS(cs); 141 int smt_threads = CPU_CORE(pc)->nr_threads; 142 CPUPPCState *env = &cpu->env; 143 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 145 int i; 146 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 147 0xffffffff, 0xffffffff}; 148 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 149 uint32_t cpufreq = 1000000000; 150 uint32_t page_sizes_prop[64]; 151 size_t page_sizes_prop_size; 152 int offset; 153 char *nodename; 154 int cpus_offset = get_cpus_node(fdt); 155 156 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 157 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 158 _FDT(offset); 159 g_free(nodename); 160 161 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 165 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 166 167 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 168 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 169 env->dcache_line_size))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 173 env->icache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 175 env->icache_line_size))); 176 177 if (pcc->l1_dcache_size) { 178 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 179 pcc->l1_dcache_size))); 180 } else { 181 warn_report("Unknown L1 dcache size for cpu"); 182 } 183 if (pcc->l1_icache_size) { 184 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 185 pcc->l1_icache_size))); 186 } else { 187 warn_report("Unknown L1 icache size for cpu"); 188 } 189 190 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 192 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 193 cpu->hash64_opts->slb_size))); 194 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 195 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 196 197 if (ppc_has_spr(cpu, SPR_PURR)) { 198 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 199 } 200 201 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 202 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 203 segs, sizeof(segs)))); 204 } 205 206 /* 207 * Advertise VMX/VSX (vector extensions) if available 208 * 0 / no property == no vector extensions 209 * 1 == VMX / Altivec available 210 * 2 == VSX available 211 */ 212 if (env->insns_flags & PPC_ALTIVEC) { 213 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 214 215 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 216 } 217 218 /* 219 * Advertise DFP (Decimal Floating Point) if available 220 * 0 / no property == no DFP 221 * 1 == DFP available 222 */ 223 if (env->insns_flags2 & PPC2_DFP) { 224 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 225 } 226 227 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 228 sizeof(page_sizes_prop)); 229 if (page_sizes_prop_size) { 230 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 231 page_sizes_prop, page_sizes_prop_size))); 232 } 233 234 /* Build interrupt servers properties */ 235 for (i = 0; i < smt_threads; i++) { 236 servers_prop[i] = cpu_to_be32(pc->pir + i); 237 } 238 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 239 servers_prop, sizeof(*servers_prop) * smt_threads))); 240 241 return offset; 242 } 243 244 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 245 uint32_t nr_threads) 246 { 247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 248 char *name; 249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 250 uint32_t irange[2], i, rsize; 251 uint64_t *reg; 252 int offset; 253 254 irange[0] = cpu_to_be32(pir); 255 irange[1] = cpu_to_be32(nr_threads); 256 257 rsize = sizeof(uint64_t) * 2 * nr_threads; 258 reg = g_malloc(rsize); 259 for (i = 0; i < nr_threads; i++) { 260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 261 reg[i * 2 + 1] = cpu_to_be64(0x1000); 262 } 263 264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 265 offset = fdt_add_subnode(fdt, 0, name); 266 _FDT(offset); 267 g_free(name); 268 269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 271 _FDT((fdt_setprop_string(fdt, offset, "device_type", 272 "PowerPC-External-Interrupt-Presentation"))); 273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 275 irange, sizeof(irange)))); 276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 278 g_free(reg); 279 } 280 281 /* 282 * Adds a PnvPHB to the chip on P8. 283 * Implemented here, like for defaults PHBs 284 */ 285 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 286 { 287 Pnv8Chip *chip8 = PNV8_CHIP(chip); 288 289 phb->chip = chip; 290 291 chip8->phbs[chip8->num_phbs] = phb; 292 chip8->num_phbs++; 293 return chip; 294 } 295 296 /* 297 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 298 * HTM is always enabled because TCG does implement HTM, it's just a 299 * degenerate implementation. 300 */ 301 static const uint8_t pa_features_207[] = { 24, 0, 302 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 303 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 304 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 305 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 306 307 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 308 { 309 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 310 int i; 311 312 pnv_dt_xscom(chip, fdt, 0, 313 cpu_to_be64(PNV_XSCOM_BASE(chip)), 314 cpu_to_be64(PNV_XSCOM_SIZE), 315 compat, sizeof(compat)); 316 317 for (i = 0; i < chip->nr_cores; i++) { 318 PnvCore *pnv_core = chip->cores[i]; 319 int offset; 320 321 offset = pnv_dt_core(chip, pnv_core, fdt); 322 323 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 324 pa_features_207, sizeof(pa_features_207)))); 325 326 /* Interrupt Control Presenters (ICP). One per core. */ 327 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 328 } 329 330 if (chip->ram_size) { 331 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 332 } 333 } 334 335 /* 336 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 337 */ 338 static const uint8_t pa_features_300[] = { 66, 0, 339 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 340 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 341 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 342 /* 6: DS207 */ 343 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 344 /* 16: Vector */ 345 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 346 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 347 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 348 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 349 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 350 /* 32: LE atomic, 34: EBB + ext EBB */ 351 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 352 /* 40: Radix MMU */ 353 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 354 /* 42: PM, 44: PC RA, 46: SC vec'd */ 355 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 356 /* 48: SIMD, 50: QP BFP, 52: String */ 357 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 358 /* 54: DecFP, 56: DecI, 58: SHA */ 359 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 360 /* 60: NM atomic, 62: RNG */ 361 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 362 }; 363 364 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 365 { 366 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 367 int i; 368 369 pnv_dt_xscom(chip, fdt, 0, 370 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 371 cpu_to_be64(PNV9_XSCOM_SIZE), 372 compat, sizeof(compat)); 373 374 for (i = 0; i < chip->nr_cores; i++) { 375 PnvCore *pnv_core = chip->cores[i]; 376 int offset; 377 378 offset = pnv_dt_core(chip, pnv_core, fdt); 379 380 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 381 pa_features_300, sizeof(pa_features_300)))); 382 } 383 384 if (chip->ram_size) { 385 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 386 } 387 388 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 389 } 390 391 /* 392 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 393 * always disables copy/paste. 394 */ 395 static const uint8_t pa_features_31[] = { 74, 0, 396 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 397 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 398 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 399 /* 6: DS207 */ 400 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 401 /* 16: Vector */ 402 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 403 /* 18: Vec. Scalar, 20: Vec. XOR */ 404 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 405 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 406 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 407 /* 32: LE atomic, 34: EBB + ext EBB */ 408 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 409 /* 40: Radix MMU */ 410 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 411 /* 42: PM, 44: PC RA, 46: SC vec'd */ 412 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 413 /* 48: SIMD, 50: QP BFP, 52: String */ 414 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 415 /* 54: DecFP, 56: DecI, 58: SHA */ 416 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 417 /* 60: NM atomic, 62: RNG */ 418 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 419 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 420 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 421 /* 72: [P]HASHST/[P]HASHCHK */ 422 0x80, 0x00, /* 72 - 73 */ 423 }; 424 425 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 426 { 427 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 428 int i; 429 430 pnv_dt_xscom(chip, fdt, 0, 431 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 432 cpu_to_be64(PNV10_XSCOM_SIZE), 433 compat, sizeof(compat)); 434 435 for (i = 0; i < chip->nr_cores; i++) { 436 PnvCore *pnv_core = chip->cores[i]; 437 int offset; 438 439 offset = pnv_dt_core(chip, pnv_core, fdt); 440 441 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 442 pa_features_31, sizeof(pa_features_31)))); 443 } 444 445 if (chip->ram_size) { 446 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 447 } 448 449 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 450 } 451 452 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 453 { 454 uint32_t io_base = d->ioport_id; 455 uint32_t io_regs[] = { 456 cpu_to_be32(1), 457 cpu_to_be32(io_base), 458 cpu_to_be32(2) 459 }; 460 char *name; 461 int node; 462 463 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 464 node = fdt_add_subnode(fdt, lpc_off, name); 465 _FDT(node); 466 g_free(name); 467 468 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 469 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 470 } 471 472 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 473 { 474 const char compatible[] = "ns16550\0pnpPNP,501"; 475 uint32_t io_base = d->ioport_id; 476 uint32_t io_regs[] = { 477 cpu_to_be32(1), 478 cpu_to_be32(io_base), 479 cpu_to_be32(8) 480 }; 481 uint32_t irq; 482 char *name; 483 int node; 484 485 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 486 487 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 488 node = fdt_add_subnode(fdt, lpc_off, name); 489 _FDT(node); 490 g_free(name); 491 492 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 493 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 494 sizeof(compatible)))); 495 496 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 497 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 498 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 499 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 500 fdt_get_phandle(fdt, lpc_off)))); 501 502 /* This is needed by Linux */ 503 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 504 } 505 506 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 507 { 508 const char compatible[] = "bt\0ipmi-bt"; 509 uint32_t io_base; 510 uint32_t io_regs[] = { 511 cpu_to_be32(1), 512 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 513 cpu_to_be32(3) 514 }; 515 uint32_t irq; 516 char *name; 517 int node; 518 519 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 520 io_regs[1] = cpu_to_be32(io_base); 521 522 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 523 524 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 525 node = fdt_add_subnode(fdt, lpc_off, name); 526 _FDT(node); 527 g_free(name); 528 529 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 530 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 531 sizeof(compatible)))); 532 533 /* Mark it as reserved to avoid Linux trying to claim it */ 534 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 535 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 536 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 537 fdt_get_phandle(fdt, lpc_off)))); 538 } 539 540 typedef struct ForeachPopulateArgs { 541 void *fdt; 542 int offset; 543 } ForeachPopulateArgs; 544 545 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 546 { 547 ForeachPopulateArgs *args = opaque; 548 ISADevice *d = ISA_DEVICE(dev); 549 550 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 551 pnv_dt_rtc(d, args->fdt, args->offset); 552 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 553 pnv_dt_serial(d, args->fdt, args->offset); 554 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 555 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 556 } else { 557 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 558 d->ioport_id); 559 } 560 561 return 0; 562 } 563 564 /* 565 * The default LPC bus of a multichip system is on chip 0. It's 566 * recognized by the firmware (skiboot) using a "primary" property. 567 */ 568 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 569 { 570 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 571 ForeachPopulateArgs args = { 572 .fdt = fdt, 573 .offset = isa_offset, 574 }; 575 uint32_t phandle; 576 577 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 578 579 phandle = qemu_fdt_alloc_phandle(fdt); 580 assert(phandle > 0); 581 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 582 583 /* 584 * ISA devices are not necessarily parented to the ISA bus so we 585 * can not use object_child_foreach() 586 */ 587 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 588 &args); 589 } 590 591 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 592 { 593 int off; 594 595 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 596 off = fdt_add_subnode(fdt, off, "power-mgt"); 597 598 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 599 } 600 601 static void *pnv_dt_create(MachineState *machine) 602 { 603 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 604 PnvMachineState *pnv = PNV_MACHINE(machine); 605 void *fdt; 606 char *buf; 607 int off; 608 int i; 609 610 fdt = g_malloc0(FDT_MAX_SIZE); 611 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 612 613 /* /qemu node */ 614 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 615 616 /* Root node */ 617 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 618 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 619 _FDT((fdt_setprop_string(fdt, 0, "model", 620 "IBM PowerNV (emulated by qemu)"))); 621 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 622 623 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 624 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 625 if (qemu_uuid_set) { 626 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 627 } 628 g_free(buf); 629 630 off = fdt_add_subnode(fdt, 0, "chosen"); 631 if (machine->kernel_cmdline) { 632 _FDT((fdt_setprop_string(fdt, off, "bootargs", 633 machine->kernel_cmdline))); 634 } 635 636 if (pnv->initrd_size) { 637 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 638 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 639 640 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 641 &start_prop, sizeof(start_prop)))); 642 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 643 &end_prop, sizeof(end_prop)))); 644 } 645 646 /* Populate device tree for each chip */ 647 for (i = 0; i < pnv->num_chips; i++) { 648 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 649 } 650 651 /* Populate ISA devices on chip 0 */ 652 pnv_dt_isa(pnv, fdt); 653 654 if (pnv->bmc) { 655 pnv_dt_bmc_sensors(pnv->bmc, fdt); 656 } 657 658 /* Create an extra node for power management on machines that support it */ 659 if (pmc->dt_power_mgt) { 660 pmc->dt_power_mgt(pnv, fdt); 661 } 662 663 return fdt; 664 } 665 666 static void pnv_powerdown_notify(Notifier *n, void *opaque) 667 { 668 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 669 670 if (pnv->bmc) { 671 pnv_bmc_powerdown(pnv->bmc); 672 } 673 } 674 675 static void pnv_reset(MachineState *machine, ShutdownCause reason) 676 { 677 PnvMachineState *pnv = PNV_MACHINE(machine); 678 IPMIBmc *bmc; 679 void *fdt; 680 681 qemu_devices_reset(reason); 682 683 /* 684 * The machine should provide by default an internal BMC simulator. 685 * If not, try to use the BMC device that was provided on the command 686 * line. 687 */ 688 bmc = pnv_bmc_find(&error_fatal); 689 if (!pnv->bmc) { 690 if (!bmc) { 691 if (!qtest_enabled()) { 692 warn_report("machine has no BMC device. Use '-device " 693 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 694 "to define one"); 695 } 696 } else { 697 pnv_bmc_set_pnor(bmc, pnv->pnor); 698 pnv->bmc = bmc; 699 } 700 } 701 702 fdt = pnv_dt_create(machine); 703 704 /* Pack resulting tree */ 705 _FDT((fdt_pack(fdt))); 706 707 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 708 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 709 710 /* 711 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 712 * the existing machine->fdt to avoid leaking it during 713 * a reset. 714 */ 715 g_free(machine->fdt); 716 machine->fdt = fdt; 717 } 718 719 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 720 { 721 Pnv8Chip *chip8 = PNV8_CHIP(chip); 722 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 723 724 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 725 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 726 } 727 728 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 729 { 730 Pnv8Chip *chip8 = PNV8_CHIP(chip); 731 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 732 733 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 734 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 735 } 736 737 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 738 { 739 Pnv9Chip *chip9 = PNV9_CHIP(chip); 740 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 741 742 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 743 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 744 } 745 746 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 747 { 748 Pnv10Chip *chip10 = PNV10_CHIP(chip); 749 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 750 751 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 752 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 753 } 754 755 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 756 { 757 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 758 } 759 760 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 761 { 762 Pnv8Chip *chip8 = PNV8_CHIP(chip); 763 int i; 764 765 ics_pic_print_info(&chip8->psi.ics, mon); 766 767 for (i = 0; i < chip8->num_phbs; i++) { 768 PnvPHB *phb = chip8->phbs[i]; 769 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 770 771 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 772 ics_pic_print_info(&phb3->lsis, mon); 773 } 774 } 775 776 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 777 { 778 Monitor *mon = opaque; 779 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 780 781 if (!phb) { 782 return 0; 783 } 784 785 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon); 786 787 return 0; 788 } 789 790 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 791 { 792 Pnv9Chip *chip9 = PNV9_CHIP(chip); 793 794 pnv_xive_pic_print_info(&chip9->xive, mon); 795 pnv_psi_pic_print_info(&chip9->psi, mon); 796 797 object_child_foreach_recursive(OBJECT(chip), 798 pnv_chip_power9_pic_print_info_child, mon); 799 } 800 801 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 802 uint32_t core_id) 803 { 804 return PNV_XSCOM_EX_BASE(core_id); 805 } 806 807 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 808 uint32_t core_id) 809 { 810 return PNV9_XSCOM_EC_BASE(core_id); 811 } 812 813 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 814 uint32_t core_id) 815 { 816 return PNV10_XSCOM_EC_BASE(core_id); 817 } 818 819 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 820 { 821 PowerPCCPUClass *ppc_default = 822 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 823 PowerPCCPUClass *ppc = 824 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 825 826 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 827 } 828 829 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 830 { 831 ISADevice *dev = isa_new("isa-ipmi-bt"); 832 833 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 834 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 835 isa_realize_and_unref(dev, bus, &error_fatal); 836 } 837 838 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 839 { 840 Pnv10Chip *chip10 = PNV10_CHIP(chip); 841 842 pnv_xive2_pic_print_info(&chip10->xive, mon); 843 pnv_psi_pic_print_info(&chip10->psi, mon); 844 845 object_child_foreach_recursive(OBJECT(chip), 846 pnv_chip_power9_pic_print_info_child, mon); 847 } 848 849 /* Always give the first 1GB to chip 0 else we won't boot */ 850 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 851 { 852 MachineState *machine = MACHINE(pnv); 853 uint64_t ram_per_chip; 854 855 assert(machine->ram_size >= 1 * GiB); 856 857 ram_per_chip = machine->ram_size / pnv->num_chips; 858 if (ram_per_chip >= 1 * GiB) { 859 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 860 } 861 862 assert(pnv->num_chips > 1); 863 864 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 865 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 866 } 867 868 static void pnv_init(MachineState *machine) 869 { 870 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 871 PnvMachineState *pnv = PNV_MACHINE(machine); 872 MachineClass *mc = MACHINE_GET_CLASS(machine); 873 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 874 char *fw_filename; 875 long fw_size; 876 uint64_t chip_ram_start = 0; 877 int i; 878 char *chip_typename; 879 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 880 DeviceState *dev; 881 882 if (kvm_enabled()) { 883 error_report("machine %s does not support the KVM accelerator", 884 mc->name); 885 exit(EXIT_FAILURE); 886 } 887 888 /* allocate RAM */ 889 if (machine->ram_size < mc->default_ram_size) { 890 char *sz = size_to_str(mc->default_ram_size); 891 error_report("Invalid RAM size, should be bigger than %s", sz); 892 g_free(sz); 893 exit(EXIT_FAILURE); 894 } 895 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 896 897 /* 898 * Create our simple PNOR device 899 */ 900 dev = qdev_new(TYPE_PNV_PNOR); 901 if (pnor) { 902 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 903 } 904 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 905 pnv->pnor = PNV_PNOR(dev); 906 907 /* load skiboot firmware */ 908 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 909 if (!fw_filename) { 910 error_report("Could not find OPAL firmware '%s'", bios_name); 911 exit(1); 912 } 913 914 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 915 if (fw_size < 0) { 916 error_report("Could not load OPAL firmware '%s'", fw_filename); 917 exit(1); 918 } 919 g_free(fw_filename); 920 921 /* load kernel */ 922 if (machine->kernel_filename) { 923 long kernel_size; 924 925 kernel_size = load_image_targphys(machine->kernel_filename, 926 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 927 if (kernel_size < 0) { 928 error_report("Could not load kernel '%s'", 929 machine->kernel_filename); 930 exit(1); 931 } 932 } 933 934 /* load initrd */ 935 if (machine->initrd_filename) { 936 pnv->initrd_base = INITRD_LOAD_ADDR; 937 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 938 pnv->initrd_base, INITRD_MAX_SIZE); 939 if (pnv->initrd_size < 0) { 940 error_report("Could not load initial ram disk '%s'", 941 machine->initrd_filename); 942 exit(1); 943 } 944 } 945 946 /* MSIs are supported on this platform */ 947 msi_nonbroken = true; 948 949 /* 950 * Check compatibility of the specified CPU with the machine 951 * default. 952 */ 953 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 954 error_report("invalid CPU model '%s' for %s machine", 955 machine->cpu_type, mc->name); 956 exit(1); 957 } 958 959 /* Create the processor chips */ 960 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 961 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 962 i, machine->cpu_type); 963 if (!object_class_by_name(chip_typename)) { 964 error_report("invalid chip model '%.*s' for %s machine", 965 i, machine->cpu_type, mc->name); 966 exit(1); 967 } 968 969 pnv->num_chips = 970 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 971 972 if (machine->smp.threads > 8) { 973 error_report("Cannot support more than 8 threads/core " 974 "on a powernv machine"); 975 exit(1); 976 } 977 if (!is_power_of_2(machine->smp.threads)) { 978 error_report("Cannot support %d threads/core on a powernv" 979 "machine because it must be a power of 2", 980 machine->smp.threads); 981 exit(1); 982 } 983 /* 984 * TODO: should we decide on how many chips we can create based 985 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 986 */ 987 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 988 error_report("invalid number of chips: '%d'", pnv->num_chips); 989 error_printf( 990 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 991 exit(1); 992 } 993 994 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 995 for (i = 0; i < pnv->num_chips; i++) { 996 char chip_name[32]; 997 Object *chip = OBJECT(qdev_new(chip_typename)); 998 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 999 1000 pnv->chips[i] = PNV_CHIP(chip); 1001 1002 /* Distribute RAM among the chips */ 1003 object_property_set_int(chip, "ram-start", chip_ram_start, 1004 &error_fatal); 1005 object_property_set_int(chip, "ram-size", chip_ram_size, 1006 &error_fatal); 1007 chip_ram_start += chip_ram_size; 1008 1009 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1010 object_property_add_child(OBJECT(pnv), chip_name, chip); 1011 object_property_set_int(chip, "chip-id", i, &error_fatal); 1012 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1013 &error_fatal); 1014 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1015 &error_fatal); 1016 /* 1017 * The POWER8 machine use the XICS interrupt interface. 1018 * Propagate the XICS fabric to the chip and its controllers. 1019 */ 1020 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1021 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1022 } 1023 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1024 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1025 &error_abort); 1026 } 1027 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1028 } 1029 g_free(chip_typename); 1030 1031 /* Instantiate ISA bus on chip 0 */ 1032 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1033 1034 /* Create serial port */ 1035 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1036 1037 /* Create an RTC ISA device too */ 1038 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1039 1040 /* 1041 * Create the machine BMC simulator and the IPMI BT device for 1042 * communication with the BMC 1043 */ 1044 if (defaults_enabled()) { 1045 pnv->bmc = pnv_bmc_create(pnv->pnor); 1046 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1047 } 1048 1049 /* 1050 * The PNOR is mapped on the LPC FW address space by the BMC. 1051 * Since we can not reach the remote BMC machine with LPC memops, 1052 * map it always for now. 1053 */ 1054 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1055 &pnv->pnor->mmio); 1056 1057 /* 1058 * OpenPOWER systems use a IPMI SEL Event message to notify the 1059 * host to powerdown 1060 */ 1061 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1062 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1063 1064 /* 1065 * Create/Connect any machine-specific I2C devices 1066 */ 1067 if (pmc->i2c_init) { 1068 pmc->i2c_init(pnv); 1069 } 1070 } 1071 1072 /* 1073 * 0:21 Reserved - Read as zeros 1074 * 22:24 Chip ID 1075 * 25:28 Core number 1076 * 29:31 Thread ID 1077 */ 1078 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 1079 { 1080 return (chip->chip_id << 7) | (core_id << 3); 1081 } 1082 1083 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1084 Error **errp) 1085 { 1086 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1087 Error *local_err = NULL; 1088 Object *obj; 1089 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1090 1091 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1092 if (local_err) { 1093 error_propagate(errp, local_err); 1094 return; 1095 } 1096 1097 pnv_cpu->intc = obj; 1098 } 1099 1100 1101 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1102 { 1103 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1104 1105 icp_reset(ICP(pnv_cpu->intc)); 1106 } 1107 1108 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1109 { 1110 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1111 1112 icp_destroy(ICP(pnv_cpu->intc)); 1113 pnv_cpu->intc = NULL; 1114 } 1115 1116 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1117 Monitor *mon) 1118 { 1119 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1120 } 1121 1122 /* 1123 * 0:48 Reserved - Read as zeroes 1124 * 49:52 Node ID 1125 * 53:55 Chip ID 1126 * 56 Reserved - Read as zero 1127 * 57:61 Core number 1128 * 62:63 Thread ID 1129 * 1130 * We only care about the lower bits. uint32_t is fine for the moment. 1131 */ 1132 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 1133 { 1134 return (chip->chip_id << 8) | (core_id << 2); 1135 } 1136 1137 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1138 { 1139 return (chip->chip_id << 8) | (core_id << 2); 1140 } 1141 1142 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1143 Error **errp) 1144 { 1145 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1146 Error *local_err = NULL; 1147 Object *obj; 1148 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1149 1150 /* 1151 * The core creates its interrupt presenter but the XIVE interrupt 1152 * controller object is initialized afterwards. Hopefully, it's 1153 * only used at runtime. 1154 */ 1155 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1156 &local_err); 1157 if (local_err) { 1158 error_propagate(errp, local_err); 1159 return; 1160 } 1161 1162 pnv_cpu->intc = obj; 1163 } 1164 1165 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1166 { 1167 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1168 1169 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1170 } 1171 1172 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1173 { 1174 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1175 1176 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1177 pnv_cpu->intc = NULL; 1178 } 1179 1180 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1181 Monitor *mon) 1182 { 1183 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1184 } 1185 1186 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1187 Error **errp) 1188 { 1189 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1190 Error *local_err = NULL; 1191 Object *obj; 1192 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1193 1194 /* 1195 * The core creates its interrupt presenter but the XIVE2 interrupt 1196 * controller object is initialized afterwards. Hopefully, it's 1197 * only used at runtime. 1198 */ 1199 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1200 &local_err); 1201 if (local_err) { 1202 error_propagate(errp, local_err); 1203 return; 1204 } 1205 1206 pnv_cpu->intc = obj; 1207 } 1208 1209 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1210 { 1211 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1212 1213 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1214 } 1215 1216 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1217 { 1218 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1219 1220 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1221 pnv_cpu->intc = NULL; 1222 } 1223 1224 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1225 Monitor *mon) 1226 { 1227 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1228 } 1229 1230 /* 1231 * Allowed core identifiers on a POWER8 Processor Chip : 1232 * 1233 * <EX0 reserved> 1234 * EX1 - Venice only 1235 * EX2 - Venice only 1236 * EX3 - Venice only 1237 * EX4 1238 * EX5 1239 * EX6 1240 * <EX7,8 reserved> <reserved> 1241 * EX9 - Venice only 1242 * EX10 - Venice only 1243 * EX11 - Venice only 1244 * EX12 1245 * EX13 1246 * EX14 1247 * <EX15 reserved> 1248 */ 1249 #define POWER8E_CORE_MASK (0x7070ull) 1250 #define POWER8_CORE_MASK (0x7e7eull) 1251 1252 /* 1253 * POWER9 has 24 cores, ids starting at 0x0 1254 */ 1255 #define POWER9_CORE_MASK (0xffffffffffffffull) 1256 1257 1258 #define POWER10_CORE_MASK (0xffffffffffffffull) 1259 1260 static void pnv_chip_power8_instance_init(Object *obj) 1261 { 1262 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1263 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1264 int i; 1265 1266 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1267 (Object **)&chip8->xics, 1268 object_property_allow_set_link, 1269 OBJ_PROP_LINK_STRONG); 1270 1271 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1272 1273 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1274 1275 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1276 1277 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1278 1279 if (defaults_enabled()) { 1280 chip8->num_phbs = pcc->num_phbs; 1281 1282 for (i = 0; i < chip8->num_phbs; i++) { 1283 Object *phb = object_new(TYPE_PNV_PHB); 1284 1285 /* 1286 * We need the chip to parent the PHB to allow the DT 1287 * to build correctly (via pnv_xscom_dt()). 1288 * 1289 * TODO: the PHB should be parented by a PEC device that, at 1290 * this moment, is not modelled powernv8/phb3. 1291 */ 1292 object_property_add_child(obj, "phb[*]", phb); 1293 chip8->phbs[i] = PNV_PHB(phb); 1294 } 1295 } 1296 1297 } 1298 1299 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1300 { 1301 PnvChip *chip = PNV_CHIP(chip8); 1302 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1303 int i, j; 1304 char *name; 1305 1306 name = g_strdup_printf("icp-%x", chip->chip_id); 1307 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1308 g_free(name); 1309 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1310 &chip8->icp_mmio); 1311 1312 /* Map the ICP registers for each thread */ 1313 for (i = 0; i < chip->nr_cores; i++) { 1314 PnvCore *pnv_core = chip->cores[i]; 1315 int core_hwid = CPU_CORE(pnv_core)->core_id; 1316 1317 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1318 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1319 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1320 1321 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1322 &icp->mmio); 1323 } 1324 } 1325 } 1326 1327 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1328 { 1329 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1330 PnvChip *chip = PNV_CHIP(dev); 1331 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1332 Pnv8Psi *psi8 = &chip8->psi; 1333 Error *local_err = NULL; 1334 int i; 1335 1336 assert(chip8->xics); 1337 1338 /* XSCOM bridge is first */ 1339 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1340 1341 pcc->parent_realize(dev, &local_err); 1342 if (local_err) { 1343 error_propagate(errp, local_err); 1344 return; 1345 } 1346 1347 /* Processor Service Interface (PSI) Host Bridge */ 1348 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1349 &error_fatal); 1350 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1351 OBJECT(chip8->xics), &error_abort); 1352 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1353 return; 1354 } 1355 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1356 &PNV_PSI(psi8)->xscom_regs); 1357 1358 /* Create LPC controller */ 1359 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1360 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1361 1362 chip->fw_mr = &chip8->lpc.isa_fw; 1363 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1364 (uint64_t) PNV_XSCOM_BASE(chip), 1365 PNV_XSCOM_LPC_BASE); 1366 1367 /* 1368 * Interrupt Management Area. This is the memory region holding 1369 * all the Interrupt Control Presenter (ICP) registers 1370 */ 1371 pnv_chip_icp_realize(chip8, &local_err); 1372 if (local_err) { 1373 error_propagate(errp, local_err); 1374 return; 1375 } 1376 1377 /* Create the simplified OCC model */ 1378 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1379 return; 1380 } 1381 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1382 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1383 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); 1384 1385 /* OCC SRAM model */ 1386 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1387 &chip8->occ.sram_regs); 1388 1389 /* HOMER */ 1390 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1391 &error_abort); 1392 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1393 return; 1394 } 1395 /* Homer Xscom region */ 1396 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1397 1398 /* Homer mmio region */ 1399 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1400 &chip8->homer.regs); 1401 1402 /* PHB controllers */ 1403 for (i = 0; i < chip8->num_phbs; i++) { 1404 PnvPHB *phb = chip8->phbs[i]; 1405 1406 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1407 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1408 &error_fatal); 1409 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1410 &error_fatal); 1411 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1412 return; 1413 } 1414 } 1415 } 1416 1417 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1418 { 1419 addr &= (PNV_XSCOM_SIZE - 1); 1420 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1421 } 1422 1423 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1424 { 1425 DeviceClass *dc = DEVICE_CLASS(klass); 1426 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1427 1428 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1429 k->cores_mask = POWER8E_CORE_MASK; 1430 k->num_phbs = 3; 1431 k->core_pir = pnv_chip_core_pir_p8; 1432 k->intc_create = pnv_chip_power8_intc_create; 1433 k->intc_reset = pnv_chip_power8_intc_reset; 1434 k->intc_destroy = pnv_chip_power8_intc_destroy; 1435 k->intc_print_info = pnv_chip_power8_intc_print_info; 1436 k->isa_create = pnv_chip_power8_isa_create; 1437 k->dt_populate = pnv_chip_power8_dt_populate; 1438 k->pic_print_info = pnv_chip_power8_pic_print_info; 1439 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1440 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1441 dc->desc = "PowerNV Chip POWER8E"; 1442 1443 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1444 &k->parent_realize); 1445 } 1446 1447 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1448 { 1449 DeviceClass *dc = DEVICE_CLASS(klass); 1450 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1451 1452 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1453 k->cores_mask = POWER8_CORE_MASK; 1454 k->num_phbs = 3; 1455 k->core_pir = pnv_chip_core_pir_p8; 1456 k->intc_create = pnv_chip_power8_intc_create; 1457 k->intc_reset = pnv_chip_power8_intc_reset; 1458 k->intc_destroy = pnv_chip_power8_intc_destroy; 1459 k->intc_print_info = pnv_chip_power8_intc_print_info; 1460 k->isa_create = pnv_chip_power8_isa_create; 1461 k->dt_populate = pnv_chip_power8_dt_populate; 1462 k->pic_print_info = pnv_chip_power8_pic_print_info; 1463 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1464 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1465 dc->desc = "PowerNV Chip POWER8"; 1466 1467 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1468 &k->parent_realize); 1469 } 1470 1471 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1472 { 1473 DeviceClass *dc = DEVICE_CLASS(klass); 1474 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1475 1476 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1477 k->cores_mask = POWER8_CORE_MASK; 1478 k->num_phbs = 4; 1479 k->core_pir = pnv_chip_core_pir_p8; 1480 k->intc_create = pnv_chip_power8_intc_create; 1481 k->intc_reset = pnv_chip_power8_intc_reset; 1482 k->intc_destroy = pnv_chip_power8_intc_destroy; 1483 k->intc_print_info = pnv_chip_power8_intc_print_info; 1484 k->isa_create = pnv_chip_power8nvl_isa_create; 1485 k->dt_populate = pnv_chip_power8_dt_populate; 1486 k->pic_print_info = pnv_chip_power8_pic_print_info; 1487 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1488 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1489 dc->desc = "PowerNV Chip POWER8NVL"; 1490 1491 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1492 &k->parent_realize); 1493 } 1494 1495 static void pnv_chip_power9_instance_init(Object *obj) 1496 { 1497 PnvChip *chip = PNV_CHIP(obj); 1498 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1499 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1500 int i; 1501 1502 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1503 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1504 "xive-fabric"); 1505 1506 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1507 1508 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1509 1510 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1511 1512 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1513 1514 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1515 1516 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1517 1518 /* Number of PECs is the chip default */ 1519 chip->num_pecs = pcc->num_pecs; 1520 1521 for (i = 0; i < chip->num_pecs; i++) { 1522 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1523 TYPE_PNV_PHB4_PEC); 1524 } 1525 1526 for (i = 0; i < pcc->i2c_num_engines; i++) { 1527 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1528 } 1529 } 1530 1531 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1532 PnvCore *pnv_core, 1533 const char *type) 1534 { 1535 char eq_name[32]; 1536 int core_id = CPU_CORE(pnv_core)->core_id; 1537 1538 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1539 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1540 sizeof(*eq), type, 1541 &error_fatal, NULL); 1542 1543 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1544 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1545 } 1546 1547 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1548 { 1549 PnvChip *chip = PNV_CHIP(chip9); 1550 int i; 1551 1552 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1553 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1554 1555 for (i = 0; i < chip9->nr_quads; i++) { 1556 PnvQuad *eq = &chip9->quads[i]; 1557 1558 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1559 PNV_QUAD_TYPE_NAME("power9")); 1560 1561 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1562 &eq->xscom_regs); 1563 } 1564 } 1565 1566 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1567 { 1568 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1569 int i; 1570 1571 for (i = 0; i < chip->num_pecs; i++) { 1572 PnvPhb4PecState *pec = &chip9->pecs[i]; 1573 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1574 uint32_t pec_nest_base; 1575 uint32_t pec_pci_base; 1576 1577 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1578 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1579 &error_fatal); 1580 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1581 &error_fatal); 1582 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1583 return; 1584 } 1585 1586 pec_nest_base = pecc->xscom_nest_base(pec); 1587 pec_pci_base = pecc->xscom_pci_base(pec); 1588 1589 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1590 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1591 } 1592 } 1593 1594 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1595 { 1596 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1597 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1598 PnvChip *chip = PNV_CHIP(dev); 1599 Pnv9Psi *psi9 = &chip9->psi; 1600 Error *local_err = NULL; 1601 int i; 1602 1603 /* XSCOM bridge is first */ 1604 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1605 1606 pcc->parent_realize(dev, &local_err); 1607 if (local_err) { 1608 error_propagate(errp, local_err); 1609 return; 1610 } 1611 1612 pnv_chip_quad_realize(chip9, &local_err); 1613 if (local_err) { 1614 error_propagate(errp, local_err); 1615 return; 1616 } 1617 1618 /* XIVE interrupt controller (POWER9) */ 1619 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1620 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1621 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1622 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1623 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1624 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1625 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1626 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1627 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1628 &error_abort); 1629 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1630 return; 1631 } 1632 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1633 &chip9->xive.xscom_regs); 1634 1635 /* Processor Service Interface (PSI) Host Bridge */ 1636 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1637 &error_fatal); 1638 /* This is the only device with 4k ESB pages */ 1639 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1640 &error_fatal); 1641 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1642 return; 1643 } 1644 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1645 &PNV_PSI(psi9)->xscom_regs); 1646 1647 /* LPC */ 1648 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1649 return; 1650 } 1651 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1652 &chip9->lpc.xscom_regs); 1653 1654 chip->fw_mr = &chip9->lpc.isa_fw; 1655 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1656 (uint64_t) PNV9_LPCM_BASE(chip)); 1657 1658 /* ChipTOD */ 1659 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1660 chip->chip_id == 0, &error_abort); 1661 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1662 chip->chip_id == 1, &error_abort); 1663 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1664 &error_abort); 1665 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1666 return; 1667 } 1668 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1669 &chip9->chiptod.xscom_regs); 1670 1671 /* Create the simplified OCC model */ 1672 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1673 return; 1674 } 1675 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1676 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1677 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); 1678 1679 /* OCC SRAM model */ 1680 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1681 &chip9->occ.sram_regs); 1682 1683 /* SBE */ 1684 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1685 return; 1686 } 1687 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1688 &chip9->sbe.xscom_ctrl_regs); 1689 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1690 &chip9->sbe.xscom_mbox_regs); 1691 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1692 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU)); 1693 1694 /* HOMER */ 1695 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1696 &error_abort); 1697 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1698 return; 1699 } 1700 /* Homer Xscom region */ 1701 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1702 1703 /* Homer mmio region */ 1704 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1705 &chip9->homer.regs); 1706 1707 /* PEC PHBs */ 1708 pnv_chip_power9_pec_realize(chip, &local_err); 1709 if (local_err) { 1710 error_propagate(errp, local_err); 1711 return; 1712 } 1713 1714 /* 1715 * I2C 1716 */ 1717 for (i = 0; i < pcc->i2c_num_engines; i++) { 1718 Object *obj = OBJECT(&chip9->i2c[i]); 1719 1720 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1721 object_property_set_int(obj, "num-busses", 1722 pcc->i2c_ports_per_engine[i], 1723 &error_fatal); 1724 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1725 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1726 return; 1727 } 1728 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1729 (chip9->i2c[i].engine - 1) * 1730 PNV9_XSCOM_I2CM_SIZE, 1731 &chip9->i2c[i].xscom_regs); 1732 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1733 qdev_get_gpio_in(DEVICE(&chip9->psi), 1734 PSIHB9_IRQ_SBE_I2C)); 1735 } 1736 } 1737 1738 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1739 { 1740 addr &= (PNV9_XSCOM_SIZE - 1); 1741 return addr >> 3; 1742 } 1743 1744 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1745 { 1746 DeviceClass *dc = DEVICE_CLASS(klass); 1747 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1748 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1749 1750 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1751 k->cores_mask = POWER9_CORE_MASK; 1752 k->core_pir = pnv_chip_core_pir_p9; 1753 k->intc_create = pnv_chip_power9_intc_create; 1754 k->intc_reset = pnv_chip_power9_intc_reset; 1755 k->intc_destroy = pnv_chip_power9_intc_destroy; 1756 k->intc_print_info = pnv_chip_power9_intc_print_info; 1757 k->isa_create = pnv_chip_power9_isa_create; 1758 k->dt_populate = pnv_chip_power9_dt_populate; 1759 k->pic_print_info = pnv_chip_power9_pic_print_info; 1760 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1761 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1762 dc->desc = "PowerNV Chip POWER9"; 1763 k->num_pecs = PNV9_CHIP_MAX_PEC; 1764 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1765 k->i2c_ports_per_engine = i2c_ports_per_engine; 1766 1767 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1768 &k->parent_realize); 1769 } 1770 1771 static void pnv_chip_power10_instance_init(Object *obj) 1772 { 1773 PnvChip *chip = PNV_CHIP(obj); 1774 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1775 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1776 int i; 1777 1778 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1779 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1780 "xive-fabric"); 1781 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1782 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1783 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1784 TYPE_PNV10_CHIPTOD); 1785 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1786 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1787 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1788 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1789 TYPE_PNV_N1_CHIPLET); 1790 1791 chip->num_pecs = pcc->num_pecs; 1792 1793 for (i = 0; i < chip->num_pecs; i++) { 1794 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1795 TYPE_PNV_PHB5_PEC); 1796 } 1797 1798 for (i = 0; i < pcc->i2c_num_engines; i++) { 1799 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1800 } 1801 } 1802 1803 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1804 { 1805 PnvChip *chip = PNV_CHIP(chip10); 1806 int i; 1807 1808 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1809 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1810 1811 for (i = 0; i < chip10->nr_quads; i++) { 1812 PnvQuad *eq = &chip10->quads[i]; 1813 1814 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1815 PNV_QUAD_TYPE_NAME("power10")); 1816 1817 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1818 &eq->xscom_regs); 1819 1820 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1821 &eq->xscom_qme_regs); 1822 } 1823 } 1824 1825 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1826 { 1827 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1828 int i; 1829 1830 for (i = 0; i < chip->num_pecs; i++) { 1831 PnvPhb4PecState *pec = &chip10->pecs[i]; 1832 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1833 uint32_t pec_nest_base; 1834 uint32_t pec_pci_base; 1835 1836 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1837 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1838 &error_fatal); 1839 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1840 &error_fatal); 1841 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1842 return; 1843 } 1844 1845 pec_nest_base = pecc->xscom_nest_base(pec); 1846 pec_pci_base = pecc->xscom_pci_base(pec); 1847 1848 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1849 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1850 } 1851 } 1852 1853 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1854 { 1855 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1856 PnvChip *chip = PNV_CHIP(dev); 1857 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1858 Error *local_err = NULL; 1859 int i; 1860 1861 /* XSCOM bridge is first */ 1862 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 1863 1864 pcc->parent_realize(dev, &local_err); 1865 if (local_err) { 1866 error_propagate(errp, local_err); 1867 return; 1868 } 1869 1870 pnv_chip_power10_quad_realize(chip10, &local_err); 1871 if (local_err) { 1872 error_propagate(errp, local_err); 1873 return; 1874 } 1875 1876 /* XIVE2 interrupt controller (POWER10) */ 1877 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1878 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1879 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1880 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1881 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1882 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1883 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1884 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1885 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1886 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1887 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1888 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1889 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1890 &error_abort); 1891 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1892 return; 1893 } 1894 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1895 &chip10->xive.xscom_regs); 1896 1897 /* Processor Service Interface (PSI) Host Bridge */ 1898 object_property_set_int(OBJECT(&chip10->psi), "bar", 1899 PNV10_PSIHB_BASE(chip), &error_fatal); 1900 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1901 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1902 &error_fatal); 1903 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1904 return; 1905 } 1906 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1907 &PNV_PSI(&chip10->psi)->xscom_regs); 1908 1909 /* LPC */ 1910 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1911 return; 1912 } 1913 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1914 &chip10->lpc.xscom_regs); 1915 1916 chip->fw_mr = &chip10->lpc.isa_fw; 1917 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1918 (uint64_t) PNV10_LPCM_BASE(chip)); 1919 1920 /* ChipTOD */ 1921 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 1922 chip->chip_id == 0, &error_abort); 1923 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 1924 chip->chip_id == 1, &error_abort); 1925 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 1926 &error_abort); 1927 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 1928 return; 1929 } 1930 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 1931 &chip10->chiptod.xscom_regs); 1932 1933 /* Create the simplified OCC model */ 1934 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1935 return; 1936 } 1937 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1938 &chip10->occ.xscom_regs); 1939 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1940 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1941 1942 /* OCC SRAM model */ 1943 memory_region_add_subregion(get_system_memory(), 1944 PNV10_OCC_SENSOR_BASE(chip), 1945 &chip10->occ.sram_regs); 1946 1947 /* SBE */ 1948 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1949 return; 1950 } 1951 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1952 &chip10->sbe.xscom_ctrl_regs); 1953 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 1954 &chip10->sbe.xscom_mbox_regs); 1955 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 1956 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 1957 1958 /* HOMER */ 1959 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1960 &error_abort); 1961 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1962 return; 1963 } 1964 /* Homer Xscom region */ 1965 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1966 &chip10->homer.pba_regs); 1967 1968 /* Homer mmio region */ 1969 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1970 &chip10->homer.regs); 1971 1972 /* N1 chiplet */ 1973 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 1974 return; 1975 } 1976 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 1977 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 1978 1979 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 1980 &chip10->n1_chiplet.xscom_pb_eq_mr); 1981 1982 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 1983 &chip10->n1_chiplet.xscom_pb_es_mr); 1984 1985 /* PHBs */ 1986 pnv_chip_power10_phb_realize(chip, &local_err); 1987 if (local_err) { 1988 error_propagate(errp, local_err); 1989 return; 1990 } 1991 1992 1993 /* 1994 * I2C 1995 */ 1996 for (i = 0; i < pcc->i2c_num_engines; i++) { 1997 Object *obj = OBJECT(&chip10->i2c[i]); 1998 1999 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2000 object_property_set_int(obj, "num-busses", 2001 pcc->i2c_ports_per_engine[i], 2002 &error_fatal); 2003 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2004 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2005 return; 2006 } 2007 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2008 (chip10->i2c[i].engine - 1) * 2009 PNV10_XSCOM_I2CM_SIZE, 2010 &chip10->i2c[i].xscom_regs); 2011 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2012 qdev_get_gpio_in(DEVICE(&chip10->psi), 2013 PSIHB9_IRQ_SBE_I2C)); 2014 } 2015 2016 } 2017 2018 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2019 { 2020 int i; 2021 for (i = 0; i < pnv->num_chips; i++) { 2022 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2023 2024 /* 2025 * Add a PCA9552 I2C device for PCIe hotplug control 2026 * to engine 2, bus 1, address 0x63 2027 */ 2028 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2029 "pca9552", 0x63); 2030 2031 /* 2032 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2033 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2034 * after hypervisor code sets a SLOTx_EN pin high. 2035 */ 2036 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2037 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2038 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2039 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2040 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2041 2042 /* 2043 * Add a PCA9554 I2C device for cable card presence detection 2044 * to engine 2, bus 1, address 0x25 2045 */ 2046 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2047 } 2048 } 2049 2050 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2051 { 2052 addr &= (PNV10_XSCOM_SIZE - 1); 2053 return addr >> 3; 2054 } 2055 2056 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2057 { 2058 DeviceClass *dc = DEVICE_CLASS(klass); 2059 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2060 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2061 2062 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 2063 k->cores_mask = POWER10_CORE_MASK; 2064 k->core_pir = pnv_chip_core_pir_p10; 2065 k->intc_create = pnv_chip_power10_intc_create; 2066 k->intc_reset = pnv_chip_power10_intc_reset; 2067 k->intc_destroy = pnv_chip_power10_intc_destroy; 2068 k->intc_print_info = pnv_chip_power10_intc_print_info; 2069 k->isa_create = pnv_chip_power10_isa_create; 2070 k->dt_populate = pnv_chip_power10_dt_populate; 2071 k->pic_print_info = pnv_chip_power10_pic_print_info; 2072 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2073 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2074 dc->desc = "PowerNV Chip POWER10"; 2075 k->num_pecs = PNV10_CHIP_MAX_PEC; 2076 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2077 k->i2c_ports_per_engine = i2c_ports_per_engine; 2078 2079 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2080 &k->parent_realize); 2081 } 2082 2083 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 2084 { 2085 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2086 int cores_max; 2087 2088 /* 2089 * No custom mask for this chip, let's use the default one from * 2090 * the chip class 2091 */ 2092 if (!chip->cores_mask) { 2093 chip->cores_mask = pcc->cores_mask; 2094 } 2095 2096 /* filter alien core ids ! some are reserved */ 2097 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2098 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2099 chip->cores_mask); 2100 return; 2101 } 2102 chip->cores_mask &= pcc->cores_mask; 2103 2104 /* now that we have a sane layout, let check the number of cores */ 2105 cores_max = ctpop64(chip->cores_mask); 2106 if (chip->nr_cores > cores_max) { 2107 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2108 cores_max); 2109 return; 2110 } 2111 } 2112 2113 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2114 { 2115 Error *error = NULL; 2116 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2117 const char *typename = pnv_chip_core_typename(chip); 2118 int i, core_hwid; 2119 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2120 2121 if (!object_class_by_name(typename)) { 2122 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2123 return; 2124 } 2125 2126 /* Cores */ 2127 pnv_chip_core_sanitize(chip, &error); 2128 if (error) { 2129 error_propagate(errp, error); 2130 return; 2131 } 2132 2133 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2134 2135 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2136 && (i < chip->nr_cores); core_hwid++) { 2137 char core_name[32]; 2138 PnvCore *pnv_core; 2139 uint64_t xscom_core_base; 2140 2141 if (!(chip->cores_mask & (1ull << core_hwid))) { 2142 continue; 2143 } 2144 2145 pnv_core = PNV_CORE(object_new(typename)); 2146 2147 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2148 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2149 chip->cores[i] = pnv_core; 2150 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2151 chip->nr_threads, &error_fatal); 2152 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2153 core_hwid, &error_fatal); 2154 object_property_set_int(OBJECT(pnv_core), "pir", 2155 pcc->core_pir(chip, core_hwid), &error_fatal); 2156 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2157 &error_fatal); 2158 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2159 &error_abort); 2160 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2161 2162 /* Each core has an XSCOM MMIO region */ 2163 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2164 2165 pnv_xscom_add_subregion(chip, xscom_core_base, 2166 &pnv_core->xscom_regs); 2167 i++; 2168 } 2169 } 2170 2171 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2172 { 2173 PnvChip *chip = PNV_CHIP(dev); 2174 Error *error = NULL; 2175 2176 /* Cores */ 2177 pnv_chip_core_realize(chip, &error); 2178 if (error) { 2179 error_propagate(errp, error); 2180 return; 2181 } 2182 } 2183 2184 static Property pnv_chip_properties[] = { 2185 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2186 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2187 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2188 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2189 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2190 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2191 DEFINE_PROP_END_OF_LIST(), 2192 }; 2193 2194 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2195 { 2196 DeviceClass *dc = DEVICE_CLASS(klass); 2197 2198 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2199 dc->realize = pnv_chip_realize; 2200 device_class_set_props(dc, pnv_chip_properties); 2201 dc->desc = "PowerNV Chip"; 2202 } 2203 2204 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2205 { 2206 int i; 2207 2208 for (i = 0; i < chip->nr_cores; i++) { 2209 PnvCore *pc = chip->cores[i]; 2210 CPUCore *cc = CPU_CORE(pc); 2211 2212 if (cc->core_id == core_id) { 2213 return pc; 2214 } 2215 } 2216 return NULL; 2217 } 2218 2219 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2220 { 2221 int i, j; 2222 2223 for (i = 0; i < chip->nr_cores; i++) { 2224 PnvCore *pc = chip->cores[i]; 2225 CPUCore *cc = CPU_CORE(pc); 2226 2227 for (j = 0; j < cc->nr_threads; j++) { 2228 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2229 return pc->threads[j]; 2230 } 2231 } 2232 } 2233 return NULL; 2234 } 2235 2236 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2237 { 2238 PnvMachineState *pnv = PNV_MACHINE(xi); 2239 int i, j; 2240 2241 for (i = 0; i < pnv->num_chips; i++) { 2242 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2243 2244 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2245 return &chip8->psi.ics; 2246 } 2247 2248 for (j = 0; j < chip8->num_phbs; j++) { 2249 PnvPHB *phb = chip8->phbs[j]; 2250 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2251 2252 if (ics_valid_irq(&phb3->lsis, irq)) { 2253 return &phb3->lsis; 2254 } 2255 2256 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2257 return ICS(&phb3->msis); 2258 } 2259 } 2260 } 2261 return NULL; 2262 } 2263 2264 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2265 { 2266 int i; 2267 2268 for (i = 0; i < pnv->num_chips; i++) { 2269 PnvChip *chip = pnv->chips[i]; 2270 if (chip->chip_id == chip_id) { 2271 return chip; 2272 } 2273 } 2274 return NULL; 2275 } 2276 2277 static void pnv_ics_resend(XICSFabric *xi) 2278 { 2279 PnvMachineState *pnv = PNV_MACHINE(xi); 2280 int i, j; 2281 2282 for (i = 0; i < pnv->num_chips; i++) { 2283 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2284 2285 ics_resend(&chip8->psi.ics); 2286 2287 for (j = 0; j < chip8->num_phbs; j++) { 2288 PnvPHB *phb = chip8->phbs[j]; 2289 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2290 2291 ics_resend(&phb3->lsis); 2292 ics_resend(ICS(&phb3->msis)); 2293 } 2294 } 2295 } 2296 2297 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2298 { 2299 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2300 2301 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2302 } 2303 2304 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2305 Monitor *mon) 2306 { 2307 PnvMachineState *pnv = PNV_MACHINE(obj); 2308 int i; 2309 CPUState *cs; 2310 2311 CPU_FOREACH(cs) { 2312 PowerPCCPU *cpu = POWERPC_CPU(cs); 2313 2314 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2315 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2316 mon); 2317 } 2318 2319 for (i = 0; i < pnv->num_chips; i++) { 2320 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2321 } 2322 } 2323 2324 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2325 uint8_t nvt_blk, uint32_t nvt_idx, 2326 bool cam_ignore, uint8_t priority, 2327 uint32_t logic_serv, 2328 XiveTCTXMatch *match) 2329 { 2330 PnvMachineState *pnv = PNV_MACHINE(xfb); 2331 int total_count = 0; 2332 int i; 2333 2334 for (i = 0; i < pnv->num_chips; i++) { 2335 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2336 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2337 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2338 int count; 2339 2340 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2341 priority, logic_serv, match); 2342 2343 if (count < 0) { 2344 return count; 2345 } 2346 2347 total_count += count; 2348 } 2349 2350 return total_count; 2351 } 2352 2353 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2354 uint8_t nvt_blk, uint32_t nvt_idx, 2355 bool cam_ignore, uint8_t priority, 2356 uint32_t logic_serv, 2357 XiveTCTXMatch *match) 2358 { 2359 PnvMachineState *pnv = PNV_MACHINE(xfb); 2360 int total_count = 0; 2361 int i; 2362 2363 for (i = 0; i < pnv->num_chips; i++) { 2364 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2365 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2366 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2367 int count; 2368 2369 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2370 priority, logic_serv, match); 2371 2372 if (count < 0) { 2373 return count; 2374 } 2375 2376 total_count += count; 2377 } 2378 2379 return total_count; 2380 } 2381 2382 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2383 { 2384 MachineClass *mc = MACHINE_CLASS(oc); 2385 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2386 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2387 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2388 2389 static GlobalProperty phb_compat[] = { 2390 { TYPE_PNV_PHB, "version", "3" }, 2391 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2392 }; 2393 2394 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2395 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2396 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2397 2398 xic->icp_get = pnv_icp_get; 2399 xic->ics_get = pnv_ics_get; 2400 xic->ics_resend = pnv_ics_resend; 2401 2402 pmc->compat = compat; 2403 pmc->compat_size = sizeof(compat); 2404 2405 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2406 } 2407 2408 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2409 { 2410 MachineClass *mc = MACHINE_CLASS(oc); 2411 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2412 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2413 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2414 2415 static GlobalProperty phb_compat[] = { 2416 { TYPE_PNV_PHB, "version", "4" }, 2417 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2418 }; 2419 2420 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2421 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2422 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2423 2424 xfc->match_nvt = pnv_match_nvt; 2425 2426 pmc->compat = compat; 2427 pmc->compat_size = sizeof(compat); 2428 pmc->dt_power_mgt = pnv_dt_power_mgt; 2429 2430 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2431 } 2432 2433 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2434 { 2435 MachineClass *mc = MACHINE_CLASS(oc); 2436 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2437 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2438 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2439 2440 static GlobalProperty phb_compat[] = { 2441 { TYPE_PNV_PHB, "version", "5" }, 2442 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2443 }; 2444 2445 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2446 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2447 2448 mc->alias = "powernv"; 2449 2450 pmc->compat = compat; 2451 pmc->compat_size = sizeof(compat); 2452 pmc->dt_power_mgt = pnv_dt_power_mgt; 2453 2454 xfc->match_nvt = pnv10_xive_match_nvt; 2455 2456 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2457 } 2458 2459 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2460 { 2461 MachineClass *mc = MACHINE_CLASS(oc); 2462 2463 pnv_machine_p10_common_class_init(oc, data); 2464 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2465 } 2466 2467 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2468 { 2469 MachineClass *mc = MACHINE_CLASS(oc); 2470 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2471 2472 pnv_machine_p10_common_class_init(oc, data); 2473 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2474 pmc->i2c_init = pnv_rainier_i2c_init; 2475 } 2476 2477 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2478 { 2479 PnvMachineState *pnv = PNV_MACHINE(obj); 2480 2481 return !!pnv->fw_load_addr; 2482 } 2483 2484 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2485 { 2486 PnvMachineState *pnv = PNV_MACHINE(obj); 2487 2488 if (value) { 2489 pnv->fw_load_addr = 0x8000000; 2490 } 2491 } 2492 2493 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2494 { 2495 PowerPCCPU *cpu = POWERPC_CPU(cs); 2496 CPUPPCState *env = &cpu->env; 2497 2498 cpu_synchronize_state(cs); 2499 ppc_cpu_do_system_reset(cs); 2500 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2501 /* 2502 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2503 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2504 * (PPC_BIT(43)). 2505 */ 2506 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2507 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2508 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2509 } 2510 } else { 2511 /* 2512 * For non-powersave system resets, SRR1[42:45] are defined to be 2513 * implementation-dependent. The POWER9 User Manual specifies that 2514 * an external (SCOM driven, which may come from a BMC nmi command or 2515 * another CPU requesting a NMI IPI) system reset exception should be 2516 * 0b0010 (PPC_BIT(44)). 2517 */ 2518 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2519 } 2520 } 2521 2522 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2523 { 2524 CPUState *cs; 2525 2526 CPU_FOREACH(cs) { 2527 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2528 } 2529 } 2530 2531 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2532 { 2533 MachineClass *mc = MACHINE_CLASS(oc); 2534 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2535 NMIClass *nc = NMI_CLASS(oc); 2536 2537 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2538 mc->init = pnv_init; 2539 mc->reset = pnv_reset; 2540 mc->max_cpus = MAX_CPUS; 2541 /* Pnv provides a AHCI device for storage */ 2542 mc->block_default_type = IF_IDE; 2543 mc->no_parallel = 1; 2544 mc->default_boot_order = NULL; 2545 /* 2546 * RAM defaults to less than 2048 for 32-bit hosts, and large 2547 * enough to fit the maximum initrd size at it's load address 2548 */ 2549 mc->default_ram_size = 1 * GiB; 2550 mc->default_ram_id = "pnv.ram"; 2551 ispc->print_info = pnv_pic_print_info; 2552 nc->nmi_monitor_handler = pnv_nmi; 2553 2554 object_class_property_add_bool(oc, "hb-mode", 2555 pnv_machine_get_hb, pnv_machine_set_hb); 2556 object_class_property_set_description(oc, "hb-mode", 2557 "Use a hostboot like boot loader"); 2558 } 2559 2560 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2561 { \ 2562 .name = type, \ 2563 .class_init = class_initfn, \ 2564 .parent = TYPE_PNV8_CHIP, \ 2565 } 2566 2567 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2568 { \ 2569 .name = type, \ 2570 .class_init = class_initfn, \ 2571 .parent = TYPE_PNV9_CHIP, \ 2572 } 2573 2574 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2575 { \ 2576 .name = type, \ 2577 .class_init = class_initfn, \ 2578 .parent = TYPE_PNV10_CHIP, \ 2579 } 2580 2581 static const TypeInfo types[] = { 2582 { 2583 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2584 .parent = MACHINE_TYPE_NAME("powernv10"), 2585 .class_init = pnv_machine_p10_rainier_class_init, 2586 }, 2587 { 2588 .name = MACHINE_TYPE_NAME("powernv10"), 2589 .parent = TYPE_PNV_MACHINE, 2590 .class_init = pnv_machine_power10_class_init, 2591 .interfaces = (InterfaceInfo[]) { 2592 { TYPE_XIVE_FABRIC }, 2593 { }, 2594 }, 2595 }, 2596 { 2597 .name = MACHINE_TYPE_NAME("powernv9"), 2598 .parent = TYPE_PNV_MACHINE, 2599 .class_init = pnv_machine_power9_class_init, 2600 .interfaces = (InterfaceInfo[]) { 2601 { TYPE_XIVE_FABRIC }, 2602 { }, 2603 }, 2604 }, 2605 { 2606 .name = MACHINE_TYPE_NAME("powernv8"), 2607 .parent = TYPE_PNV_MACHINE, 2608 .class_init = pnv_machine_power8_class_init, 2609 .interfaces = (InterfaceInfo[]) { 2610 { TYPE_XICS_FABRIC }, 2611 { }, 2612 }, 2613 }, 2614 { 2615 .name = TYPE_PNV_MACHINE, 2616 .parent = TYPE_MACHINE, 2617 .abstract = true, 2618 .instance_size = sizeof(PnvMachineState), 2619 .class_init = pnv_machine_class_init, 2620 .class_size = sizeof(PnvMachineClass), 2621 .interfaces = (InterfaceInfo[]) { 2622 { TYPE_INTERRUPT_STATS_PROVIDER }, 2623 { TYPE_NMI }, 2624 { }, 2625 }, 2626 }, 2627 { 2628 .name = TYPE_PNV_CHIP, 2629 .parent = TYPE_SYS_BUS_DEVICE, 2630 .class_init = pnv_chip_class_init, 2631 .instance_size = sizeof(PnvChip), 2632 .class_size = sizeof(PnvChipClass), 2633 .abstract = true, 2634 }, 2635 2636 /* 2637 * P10 chip and variants 2638 */ 2639 { 2640 .name = TYPE_PNV10_CHIP, 2641 .parent = TYPE_PNV_CHIP, 2642 .instance_init = pnv_chip_power10_instance_init, 2643 .instance_size = sizeof(Pnv10Chip), 2644 }, 2645 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2646 2647 /* 2648 * P9 chip and variants 2649 */ 2650 { 2651 .name = TYPE_PNV9_CHIP, 2652 .parent = TYPE_PNV_CHIP, 2653 .instance_init = pnv_chip_power9_instance_init, 2654 .instance_size = sizeof(Pnv9Chip), 2655 }, 2656 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2657 2658 /* 2659 * P8 chip and variants 2660 */ 2661 { 2662 .name = TYPE_PNV8_CHIP, 2663 .parent = TYPE_PNV_CHIP, 2664 .instance_init = pnv_chip_power8_instance_init, 2665 .instance_size = sizeof(Pnv8Chip), 2666 }, 2667 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2668 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2669 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2670 pnv_chip_power8nvl_class_init), 2671 }; 2672 2673 DEFINE_TYPES(types) 2674