1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci-host/pnv_phb.h" 47 48 #include "hw/ppc/xics.h" 49 #include "hw/qdev-properties.h" 50 #include "hw/ppc/pnv_xscom.h" 51 #include "hw/ppc/pnv_pnor.h" 52 53 #include "hw/isa/isa.h" 54 #include "hw/char/serial.h" 55 #include "hw/rtc/mc146818rtc.h" 56 57 #include <libfdt.h> 58 59 #define FDT_MAX_SIZE (1 * MiB) 60 61 #define FW_FILE_NAME "skiboot.lid" 62 #define FW_LOAD_ADDR 0x0 63 #define FW_MAX_SIZE (16 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x20000000 66 #define KERNEL_MAX_SIZE (128 * MiB) 67 #define INITRD_LOAD_ADDR 0x28000000 68 #define INITRD_MAX_SIZE (128 * MiB) 69 70 static const char *pnv_chip_core_typename(const PnvChip *o) 71 { 72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 75 const char *core_type = object_class_get_name(object_class_by_name(s)); 76 g_free(s); 77 return core_type; 78 } 79 80 /* 81 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 82 * 4 * 4 sockets * 12 cores * 8 threads = 1536 83 * Let's make it 2^11 84 */ 85 #define MAX_CPUS 2048 86 87 /* 88 * Memory nodes are created by hostboot, one for each range of memory 89 * that has a different "affinity". In practice, it means one range 90 * per chip. 91 */ 92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 93 { 94 char *mem_name; 95 uint64_t mem_reg_property[2]; 96 int off; 97 98 mem_reg_property[0] = cpu_to_be64(start); 99 mem_reg_property[1] = cpu_to_be64(size); 100 101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 102 off = fdt_add_subnode(fdt, 0, mem_name); 103 g_free(mem_name); 104 105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 107 sizeof(mem_reg_property)))); 108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 109 } 110 111 static int get_cpus_node(void *fdt) 112 { 113 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 114 115 if (cpus_offset < 0) { 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 117 if (cpus_offset) { 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 120 } 121 } 122 _FDT(cpus_offset); 123 return cpus_offset; 124 } 125 126 /* 127 * The PowerNV cores (and threads) need to use real HW ids and not an 128 * incremental index like it has been done on other platforms. This HW 129 * id is stored in the CPU PIR, it is used to create cpu nodes in the 130 * device tree, used in XSCOM to address cores and in interrupt 131 * servers. 132 */ 133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 134 { 135 PowerPCCPU *cpu = pc->threads[0]; 136 CPUState *cs = CPU(cpu); 137 DeviceClass *dc = DEVICE_GET_CLASS(cs); 138 int smt_threads = CPU_CORE(pc)->nr_threads; 139 CPUPPCState *env = &cpu->env; 140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 141 uint32_t servers_prop[smt_threads]; 142 int i; 143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 144 0xffffffff, 0xffffffff}; 145 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 146 uint32_t cpufreq = 1000000000; 147 uint32_t page_sizes_prop[64]; 148 size_t page_sizes_prop_size; 149 const uint8_t pa_features[] = { 24, 0, 150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 154 int offset; 155 char *nodename; 156 int cpus_offset = get_cpus_node(fdt); 157 158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 159 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 160 _FDT(offset); 161 g_free(nodename); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 175 env->icache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 177 env->icache_line_size))); 178 179 if (pcc->l1_dcache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 181 pcc->l1_dcache_size))); 182 } else { 183 warn_report("Unknown L1 dcache size for cpu"); 184 } 185 if (pcc->l1_icache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 187 pcc->l1_icache_size))); 188 } else { 189 warn_report("Unknown L1 icache size for cpu"); 190 } 191 192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 195 cpu->hash64_opts->slb_size))); 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 198 199 if (ppc_has_spr(cpu, SPR_PURR)) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 201 } 202 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 205 segs, sizeof(segs)))); 206 } 207 208 /* 209 * Advertise VMX/VSX (vector extensions) if available 210 * 0 / no property == no vector extensions 211 * 1 == VMX / Altivec available 212 * 2 == VSX available 213 */ 214 if (env->insns_flags & PPC_ALTIVEC) { 215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 216 217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 218 } 219 220 /* 221 * Advertise DFP (Decimal Floating Point) if available 222 * 0 / no property == no DFP 223 * 1 == DFP available 224 */ 225 if (env->insns_flags2 & PPC2_DFP) { 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 227 } 228 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 230 sizeof(page_sizes_prop)); 231 if (page_sizes_prop_size) { 232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 233 page_sizes_prop, page_sizes_prop_size))); 234 } 235 236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 237 pa_features, sizeof(pa_features)))); 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pc->pir + i); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(servers_prop)))); 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 248 uint32_t nr_threads) 249 { 250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 251 char *name; 252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 253 uint32_t irange[2], i, rsize; 254 uint64_t *reg; 255 int offset; 256 257 irange[0] = cpu_to_be32(pir); 258 irange[1] = cpu_to_be32(nr_threads); 259 260 rsize = sizeof(uint64_t) * 2 * nr_threads; 261 reg = g_malloc(rsize); 262 for (i = 0; i < nr_threads; i++) { 263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 264 reg[i * 2 + 1] = cpu_to_be64(0x1000); 265 } 266 267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 268 offset = fdt_add_subnode(fdt, 0, name); 269 _FDT(offset); 270 g_free(name); 271 272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 274 _FDT((fdt_setprop_string(fdt, offset, "device_type", 275 "PowerPC-External-Interrupt-Presentation"))); 276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 278 irange, sizeof(irange)))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 281 g_free(reg); 282 } 283 284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 285 { 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 287 int i; 288 289 pnv_dt_xscom(chip, fdt, 0, 290 cpu_to_be64(PNV_XSCOM_BASE(chip)), 291 cpu_to_be64(PNV_XSCOM_SIZE), 292 compat, sizeof(compat)); 293 294 for (i = 0; i < chip->nr_cores; i++) { 295 PnvCore *pnv_core = chip->cores[i]; 296 297 pnv_dt_core(chip, pnv_core, fdt); 298 299 /* Interrupt Control Presenters (ICP). One per core. */ 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 301 } 302 303 if (chip->ram_size) { 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 305 } 306 } 307 308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 309 { 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 311 int i; 312 313 pnv_dt_xscom(chip, fdt, 0, 314 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 315 cpu_to_be64(PNV9_XSCOM_SIZE), 316 compat, sizeof(compat)); 317 318 for (i = 0; i < chip->nr_cores; i++) { 319 PnvCore *pnv_core = chip->cores[i]; 320 321 pnv_dt_core(chip, pnv_core, fdt); 322 } 323 324 if (chip->ram_size) { 325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 326 } 327 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 329 } 330 331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 332 { 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 334 int i; 335 336 pnv_dt_xscom(chip, fdt, 0, 337 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 338 cpu_to_be64(PNV10_XSCOM_SIZE), 339 compat, sizeof(compat)); 340 341 for (i = 0; i < chip->nr_cores; i++) { 342 PnvCore *pnv_core = chip->cores[i]; 343 344 pnv_dt_core(chip, pnv_core, fdt); 345 } 346 347 if (chip->ram_size) { 348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 349 } 350 351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 352 } 353 354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 355 { 356 uint32_t io_base = d->ioport_id; 357 uint32_t io_regs[] = { 358 cpu_to_be32(1), 359 cpu_to_be32(io_base), 360 cpu_to_be32(2) 361 }; 362 char *name; 363 int node; 364 365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 366 node = fdt_add_subnode(fdt, lpc_off, name); 367 _FDT(node); 368 g_free(name); 369 370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 372 } 373 374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 375 { 376 const char compatible[] = "ns16550\0pnpPNP,501"; 377 uint32_t io_base = d->ioport_id; 378 uint32_t io_regs[] = { 379 cpu_to_be32(1), 380 cpu_to_be32(io_base), 381 cpu_to_be32(8) 382 }; 383 uint32_t irq; 384 char *name; 385 int node; 386 387 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 388 389 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 390 node = fdt_add_subnode(fdt, lpc_off, name); 391 _FDT(node); 392 g_free(name); 393 394 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 395 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 396 sizeof(compatible)))); 397 398 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 399 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 400 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 401 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 402 fdt_get_phandle(fdt, lpc_off)))); 403 404 /* This is needed by Linux */ 405 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 406 } 407 408 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 409 { 410 const char compatible[] = "bt\0ipmi-bt"; 411 uint32_t io_base; 412 uint32_t io_regs[] = { 413 cpu_to_be32(1), 414 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 415 cpu_to_be32(3) 416 }; 417 uint32_t irq; 418 char *name; 419 int node; 420 421 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 422 io_regs[1] = cpu_to_be32(io_base); 423 424 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 425 426 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 427 node = fdt_add_subnode(fdt, lpc_off, name); 428 _FDT(node); 429 g_free(name); 430 431 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 432 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 433 sizeof(compatible)))); 434 435 /* Mark it as reserved to avoid Linux trying to claim it */ 436 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 437 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 438 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 439 fdt_get_phandle(fdt, lpc_off)))); 440 } 441 442 typedef struct ForeachPopulateArgs { 443 void *fdt; 444 int offset; 445 } ForeachPopulateArgs; 446 447 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 448 { 449 ForeachPopulateArgs *args = opaque; 450 ISADevice *d = ISA_DEVICE(dev); 451 452 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 453 pnv_dt_rtc(d, args->fdt, args->offset); 454 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 455 pnv_dt_serial(d, args->fdt, args->offset); 456 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 457 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 458 } else { 459 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 460 d->ioport_id); 461 } 462 463 return 0; 464 } 465 466 /* 467 * The default LPC bus of a multichip system is on chip 0. It's 468 * recognized by the firmware (skiboot) using a "primary" property. 469 */ 470 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 471 { 472 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 473 ForeachPopulateArgs args = { 474 .fdt = fdt, 475 .offset = isa_offset, 476 }; 477 uint32_t phandle; 478 479 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 480 481 phandle = qemu_fdt_alloc_phandle(fdt); 482 assert(phandle > 0); 483 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 484 485 /* 486 * ISA devices are not necessarily parented to the ISA bus so we 487 * can not use object_child_foreach() 488 */ 489 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 490 &args); 491 } 492 493 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 494 { 495 int off; 496 497 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 498 off = fdt_add_subnode(fdt, off, "power-mgt"); 499 500 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 501 } 502 503 static void *pnv_dt_create(MachineState *machine) 504 { 505 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 506 PnvMachineState *pnv = PNV_MACHINE(machine); 507 void *fdt; 508 char *buf; 509 int off; 510 int i; 511 512 fdt = g_malloc0(FDT_MAX_SIZE); 513 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 514 515 /* /qemu node */ 516 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 517 518 /* Root node */ 519 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 520 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 521 _FDT((fdt_setprop_string(fdt, 0, "model", 522 "IBM PowerNV (emulated by qemu)"))); 523 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 524 525 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 526 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 527 if (qemu_uuid_set) { 528 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 529 } 530 g_free(buf); 531 532 off = fdt_add_subnode(fdt, 0, "chosen"); 533 if (machine->kernel_cmdline) { 534 _FDT((fdt_setprop_string(fdt, off, "bootargs", 535 machine->kernel_cmdline))); 536 } 537 538 if (pnv->initrd_size) { 539 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 540 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 541 542 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 543 &start_prop, sizeof(start_prop)))); 544 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 545 &end_prop, sizeof(end_prop)))); 546 } 547 548 /* Populate device tree for each chip */ 549 for (i = 0; i < pnv->num_chips; i++) { 550 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 551 } 552 553 /* Populate ISA devices on chip 0 */ 554 pnv_dt_isa(pnv, fdt); 555 556 if (pnv->bmc) { 557 pnv_dt_bmc_sensors(pnv->bmc, fdt); 558 } 559 560 /* Create an extra node for power management on machines that support it */ 561 if (pmc->dt_power_mgt) { 562 pmc->dt_power_mgt(pnv, fdt); 563 } 564 565 return fdt; 566 } 567 568 static void pnv_powerdown_notify(Notifier *n, void *opaque) 569 { 570 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 571 572 if (pnv->bmc) { 573 pnv_bmc_powerdown(pnv->bmc); 574 } 575 } 576 577 static void pnv_reset(MachineState *machine) 578 { 579 PnvMachineState *pnv = PNV_MACHINE(machine); 580 IPMIBmc *bmc; 581 void *fdt; 582 583 qemu_devices_reset(); 584 585 /* 586 * The machine should provide by default an internal BMC simulator. 587 * If not, try to use the BMC device that was provided on the command 588 * line. 589 */ 590 bmc = pnv_bmc_find(&error_fatal); 591 if (!pnv->bmc) { 592 if (!bmc) { 593 if (!qtest_enabled()) { 594 warn_report("machine has no BMC device. Use '-device " 595 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 596 "to define one"); 597 } 598 } else { 599 pnv_bmc_set_pnor(bmc, pnv->pnor); 600 pnv->bmc = bmc; 601 } 602 } 603 604 fdt = pnv_dt_create(machine); 605 606 /* Pack resulting tree */ 607 _FDT((fdt_pack(fdt))); 608 609 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 610 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 611 612 g_free(fdt); 613 } 614 615 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 616 { 617 Pnv8Chip *chip8 = PNV8_CHIP(chip); 618 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 619 620 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 621 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 622 } 623 624 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 625 { 626 Pnv8Chip *chip8 = PNV8_CHIP(chip); 627 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 628 629 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 630 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 631 } 632 633 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 634 { 635 Pnv9Chip *chip9 = PNV9_CHIP(chip); 636 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 637 638 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 639 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 640 } 641 642 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 643 { 644 Pnv10Chip *chip10 = PNV10_CHIP(chip); 645 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 646 647 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 648 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 649 } 650 651 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 652 { 653 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 654 } 655 656 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 657 { 658 Pnv8Chip *chip8 = PNV8_CHIP(chip); 659 int i; 660 661 ics_pic_print_info(&chip8->psi.ics, mon); 662 663 for (i = 0; i < chip8->num_phbs; i++) { 664 PnvPHB *phb = &chip8->phbs[i]; 665 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 666 667 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 668 ics_pic_print_info(&phb3->lsis, mon); 669 } 670 } 671 672 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 673 { 674 Monitor *mon = opaque; 675 PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4); 676 677 if (phb4) { 678 pnv_phb4_pic_print_info(phb4, mon); 679 } 680 return 0; 681 } 682 683 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 684 { 685 Pnv9Chip *chip9 = PNV9_CHIP(chip); 686 687 pnv_xive_pic_print_info(&chip9->xive, mon); 688 pnv_psi_pic_print_info(&chip9->psi, mon); 689 690 object_child_foreach_recursive(OBJECT(chip), 691 pnv_chip_power9_pic_print_info_child, mon); 692 } 693 694 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 695 uint32_t core_id) 696 { 697 return PNV_XSCOM_EX_BASE(core_id); 698 } 699 700 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 701 uint32_t core_id) 702 { 703 return PNV9_XSCOM_EC_BASE(core_id); 704 } 705 706 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 707 uint32_t core_id) 708 { 709 return PNV10_XSCOM_EC_BASE(core_id); 710 } 711 712 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 713 { 714 PowerPCCPUClass *ppc_default = 715 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 716 PowerPCCPUClass *ppc = 717 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 718 719 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 720 } 721 722 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 723 { 724 ISADevice *dev = isa_new("isa-ipmi-bt"); 725 726 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 727 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 728 isa_realize_and_unref(dev, bus, &error_fatal); 729 } 730 731 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 732 { 733 Pnv10Chip *chip10 = PNV10_CHIP(chip); 734 735 pnv_xive2_pic_print_info(&chip10->xive, mon); 736 pnv_psi_pic_print_info(&chip10->psi, mon); 737 738 object_child_foreach_recursive(OBJECT(chip), 739 pnv_chip_power9_pic_print_info_child, mon); 740 } 741 742 /* Always give the first 1GB to chip 0 else we won't boot */ 743 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 744 { 745 MachineState *machine = MACHINE(pnv); 746 uint64_t ram_per_chip; 747 748 assert(machine->ram_size >= 1 * GiB); 749 750 ram_per_chip = machine->ram_size / pnv->num_chips; 751 if (ram_per_chip >= 1 * GiB) { 752 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 753 } 754 755 assert(pnv->num_chips > 1); 756 757 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 758 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 759 } 760 761 static void pnv_init(MachineState *machine) 762 { 763 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 764 PnvMachineState *pnv = PNV_MACHINE(machine); 765 MachineClass *mc = MACHINE_GET_CLASS(machine); 766 char *fw_filename; 767 long fw_size; 768 uint64_t chip_ram_start = 0; 769 int i; 770 char *chip_typename; 771 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 772 DeviceState *dev; 773 774 if (kvm_enabled()) { 775 error_report("The powernv machine does not work with KVM acceleration"); 776 exit(EXIT_FAILURE); 777 } 778 779 /* allocate RAM */ 780 if (machine->ram_size < mc->default_ram_size) { 781 char *sz = size_to_str(mc->default_ram_size); 782 error_report("Invalid RAM size, should be bigger than %s", sz); 783 g_free(sz); 784 exit(EXIT_FAILURE); 785 } 786 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 787 788 /* 789 * Create our simple PNOR device 790 */ 791 dev = qdev_new(TYPE_PNV_PNOR); 792 if (pnor) { 793 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 794 } 795 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 796 pnv->pnor = PNV_PNOR(dev); 797 798 /* load skiboot firmware */ 799 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 800 if (!fw_filename) { 801 error_report("Could not find OPAL firmware '%s'", bios_name); 802 exit(1); 803 } 804 805 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 806 if (fw_size < 0) { 807 error_report("Could not load OPAL firmware '%s'", fw_filename); 808 exit(1); 809 } 810 g_free(fw_filename); 811 812 /* load kernel */ 813 if (machine->kernel_filename) { 814 long kernel_size; 815 816 kernel_size = load_image_targphys(machine->kernel_filename, 817 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 818 if (kernel_size < 0) { 819 error_report("Could not load kernel '%s'", 820 machine->kernel_filename); 821 exit(1); 822 } 823 } 824 825 /* load initrd */ 826 if (machine->initrd_filename) { 827 pnv->initrd_base = INITRD_LOAD_ADDR; 828 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 829 pnv->initrd_base, INITRD_MAX_SIZE); 830 if (pnv->initrd_size < 0) { 831 error_report("Could not load initial ram disk '%s'", 832 machine->initrd_filename); 833 exit(1); 834 } 835 } 836 837 /* MSIs are supported on this platform */ 838 msi_nonbroken = true; 839 840 /* 841 * Check compatibility of the specified CPU with the machine 842 * default. 843 */ 844 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 845 error_report("invalid CPU model '%s' for %s machine", 846 machine->cpu_type, mc->name); 847 exit(1); 848 } 849 850 /* Create the processor chips */ 851 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 852 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 853 i, machine->cpu_type); 854 if (!object_class_by_name(chip_typename)) { 855 error_report("invalid chip model '%.*s' for %s machine", 856 i, machine->cpu_type, mc->name); 857 exit(1); 858 } 859 860 pnv->num_chips = 861 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 862 /* 863 * TODO: should we decide on how many chips we can create based 864 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 865 */ 866 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 867 error_report("invalid number of chips: '%d'", pnv->num_chips); 868 error_printf( 869 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 870 exit(1); 871 } 872 873 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 874 for (i = 0; i < pnv->num_chips; i++) { 875 char chip_name[32]; 876 Object *chip = OBJECT(qdev_new(chip_typename)); 877 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 878 879 pnv->chips[i] = PNV_CHIP(chip); 880 881 /* Distribute RAM among the chips */ 882 object_property_set_int(chip, "ram-start", chip_ram_start, 883 &error_fatal); 884 object_property_set_int(chip, "ram-size", chip_ram_size, 885 &error_fatal); 886 chip_ram_start += chip_ram_size; 887 888 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 889 object_property_add_child(OBJECT(pnv), chip_name, chip); 890 object_property_set_int(chip, "chip-id", i, &error_fatal); 891 object_property_set_int(chip, "nr-cores", machine->smp.cores, 892 &error_fatal); 893 object_property_set_int(chip, "nr-threads", machine->smp.threads, 894 &error_fatal); 895 /* 896 * The POWER8 machine use the XICS interrupt interface. 897 * Propagate the XICS fabric to the chip and its controllers. 898 */ 899 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 900 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 901 } 902 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 903 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 904 &error_abort); 905 } 906 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 907 } 908 g_free(chip_typename); 909 910 /* Instantiate ISA bus on chip 0 */ 911 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 912 913 /* Create serial port */ 914 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 915 916 /* Create an RTC ISA device too */ 917 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 918 919 /* 920 * Create the machine BMC simulator and the IPMI BT device for 921 * communication with the BMC 922 */ 923 if (defaults_enabled()) { 924 pnv->bmc = pnv_bmc_create(pnv->pnor); 925 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 926 } 927 928 /* 929 * The PNOR is mapped on the LPC FW address space by the BMC. 930 * Since we can not reach the remote BMC machine with LPC memops, 931 * map it always for now. 932 */ 933 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 934 &pnv->pnor->mmio); 935 936 /* 937 * OpenPOWER systems use a IPMI SEL Event message to notify the 938 * host to powerdown 939 */ 940 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 941 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 942 } 943 944 /* 945 * 0:21 Reserved - Read as zeros 946 * 22:24 Chip ID 947 * 25:28 Core number 948 * 29:31 Thread ID 949 */ 950 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 951 { 952 return (chip->chip_id << 7) | (core_id << 3); 953 } 954 955 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 956 Error **errp) 957 { 958 Pnv8Chip *chip8 = PNV8_CHIP(chip); 959 Error *local_err = NULL; 960 Object *obj; 961 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 962 963 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 964 if (local_err) { 965 error_propagate(errp, local_err); 966 return; 967 } 968 969 pnv_cpu->intc = obj; 970 } 971 972 973 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 974 { 975 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 976 977 icp_reset(ICP(pnv_cpu->intc)); 978 } 979 980 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 981 { 982 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 983 984 icp_destroy(ICP(pnv_cpu->intc)); 985 pnv_cpu->intc = NULL; 986 } 987 988 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 989 Monitor *mon) 990 { 991 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 992 } 993 994 /* 995 * 0:48 Reserved - Read as zeroes 996 * 49:52 Node ID 997 * 53:55 Chip ID 998 * 56 Reserved - Read as zero 999 * 57:61 Core number 1000 * 62:63 Thread ID 1001 * 1002 * We only care about the lower bits. uint32_t is fine for the moment. 1003 */ 1004 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 1005 { 1006 return (chip->chip_id << 8) | (core_id << 2); 1007 } 1008 1009 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1010 { 1011 return (chip->chip_id << 8) | (core_id << 2); 1012 } 1013 1014 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1015 Error **errp) 1016 { 1017 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1018 Error *local_err = NULL; 1019 Object *obj; 1020 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1021 1022 /* 1023 * The core creates its interrupt presenter but the XIVE interrupt 1024 * controller object is initialized afterwards. Hopefully, it's 1025 * only used at runtime. 1026 */ 1027 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1028 &local_err); 1029 if (local_err) { 1030 error_propagate(errp, local_err); 1031 return; 1032 } 1033 1034 pnv_cpu->intc = obj; 1035 } 1036 1037 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1038 { 1039 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1040 1041 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1042 } 1043 1044 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1045 { 1046 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1047 1048 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1049 pnv_cpu->intc = NULL; 1050 } 1051 1052 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1053 Monitor *mon) 1054 { 1055 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1056 } 1057 1058 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1059 Error **errp) 1060 { 1061 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1062 Error *local_err = NULL; 1063 Object *obj; 1064 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1065 1066 /* 1067 * The core creates its interrupt presenter but the XIVE2 interrupt 1068 * controller object is initialized afterwards. Hopefully, it's 1069 * only used at runtime. 1070 */ 1071 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1072 &local_err); 1073 if (local_err) { 1074 error_propagate(errp, local_err); 1075 return; 1076 } 1077 1078 pnv_cpu->intc = obj; 1079 } 1080 1081 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1082 { 1083 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1084 1085 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1086 } 1087 1088 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1089 { 1090 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1091 1092 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1093 pnv_cpu->intc = NULL; 1094 } 1095 1096 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1097 Monitor *mon) 1098 { 1099 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1100 } 1101 1102 /* 1103 * Allowed core identifiers on a POWER8 Processor Chip : 1104 * 1105 * <EX0 reserved> 1106 * EX1 - Venice only 1107 * EX2 - Venice only 1108 * EX3 - Venice only 1109 * EX4 1110 * EX5 1111 * EX6 1112 * <EX7,8 reserved> <reserved> 1113 * EX9 - Venice only 1114 * EX10 - Venice only 1115 * EX11 - Venice only 1116 * EX12 1117 * EX13 1118 * EX14 1119 * <EX15 reserved> 1120 */ 1121 #define POWER8E_CORE_MASK (0x7070ull) 1122 #define POWER8_CORE_MASK (0x7e7eull) 1123 1124 /* 1125 * POWER9 has 24 cores, ids starting at 0x0 1126 */ 1127 #define POWER9_CORE_MASK (0xffffffffffffffull) 1128 1129 1130 #define POWER10_CORE_MASK (0xffffffffffffffull) 1131 1132 static void pnv_chip_power8_instance_init(Object *obj) 1133 { 1134 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1135 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1136 int i; 1137 1138 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1139 (Object **)&chip8->xics, 1140 object_property_allow_set_link, 1141 OBJ_PROP_LINK_STRONG); 1142 1143 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1144 1145 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1146 1147 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1148 1149 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1150 1151 chip8->num_phbs = pcc->num_phbs; 1152 1153 for (i = 0; i < chip8->num_phbs; i++) { 1154 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB); 1155 } 1156 1157 } 1158 1159 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1160 { 1161 PnvChip *chip = PNV_CHIP(chip8); 1162 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1163 int i, j; 1164 char *name; 1165 1166 name = g_strdup_printf("icp-%x", chip->chip_id); 1167 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1168 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1169 g_free(name); 1170 1171 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1172 1173 /* Map the ICP registers for each thread */ 1174 for (i = 0; i < chip->nr_cores; i++) { 1175 PnvCore *pnv_core = chip->cores[i]; 1176 int core_hwid = CPU_CORE(pnv_core)->core_id; 1177 1178 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1179 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1180 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1181 1182 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1183 &icp->mmio); 1184 } 1185 } 1186 } 1187 1188 /* 1189 * Attach a root port device. 1190 * 1191 * 'index' will be used both as a PCIE slot value and to calculate 1192 * QOM id. 'chip_id' is going to be used as PCIE chassis for the 1193 * root port. 1194 */ 1195 void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, 1196 int index, int chip_id) 1197 { 1198 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name); 1199 g_autofree char *default_id = g_strdup_printf("%s[%d]", name, index); 1200 const char *dev_id = DEVICE(root)->id; 1201 1202 object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id, 1203 OBJECT(root)); 1204 1205 /* Set unique chassis/slot values for the root port */ 1206 qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id); 1207 qdev_prop_set_uint16(DEVICE(root), "slot", index); 1208 1209 pci_realize_and_unref(root, pci->bus, &error_fatal); 1210 } 1211 1212 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1213 { 1214 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1215 PnvChip *chip = PNV_CHIP(dev); 1216 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1217 Pnv8Psi *psi8 = &chip8->psi; 1218 Error *local_err = NULL; 1219 int i; 1220 1221 assert(chip8->xics); 1222 1223 /* XSCOM bridge is first */ 1224 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1225 if (local_err) { 1226 error_propagate(errp, local_err); 1227 return; 1228 } 1229 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1230 1231 pcc->parent_realize(dev, &local_err); 1232 if (local_err) { 1233 error_propagate(errp, local_err); 1234 return; 1235 } 1236 1237 /* Processor Service Interface (PSI) Host Bridge */ 1238 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1239 &error_fatal); 1240 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1241 OBJECT(chip8->xics), &error_abort); 1242 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1243 return; 1244 } 1245 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1246 &PNV_PSI(psi8)->xscom_regs); 1247 1248 /* Create LPC controller */ 1249 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1250 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1251 1252 chip->fw_mr = &chip8->lpc.isa_fw; 1253 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1254 (uint64_t) PNV_XSCOM_BASE(chip), 1255 PNV_XSCOM_LPC_BASE); 1256 1257 /* 1258 * Interrupt Management Area. This is the memory region holding 1259 * all the Interrupt Control Presenter (ICP) registers 1260 */ 1261 pnv_chip_icp_realize(chip8, &local_err); 1262 if (local_err) { 1263 error_propagate(errp, local_err); 1264 return; 1265 } 1266 1267 /* Create the simplified OCC model */ 1268 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1269 return; 1270 } 1271 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1272 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1273 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); 1274 1275 /* OCC SRAM model */ 1276 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1277 &chip8->occ.sram_regs); 1278 1279 /* HOMER */ 1280 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1281 &error_abort); 1282 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1283 return; 1284 } 1285 /* Homer Xscom region */ 1286 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1287 1288 /* Homer mmio region */ 1289 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1290 &chip8->homer.regs); 1291 1292 /* PHB controllers */ 1293 for (i = 0; i < chip8->num_phbs; i++) { 1294 PnvPHB *phb = &chip8->phbs[i]; 1295 1296 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1297 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1298 &error_fatal); 1299 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1300 &error_fatal); 1301 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1302 return; 1303 } 1304 } 1305 } 1306 1307 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1308 { 1309 addr &= (PNV_XSCOM_SIZE - 1); 1310 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1311 } 1312 1313 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1314 { 1315 DeviceClass *dc = DEVICE_CLASS(klass); 1316 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1317 1318 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1319 k->cores_mask = POWER8E_CORE_MASK; 1320 k->num_phbs = 3; 1321 k->core_pir = pnv_chip_core_pir_p8; 1322 k->intc_create = pnv_chip_power8_intc_create; 1323 k->intc_reset = pnv_chip_power8_intc_reset; 1324 k->intc_destroy = pnv_chip_power8_intc_destroy; 1325 k->intc_print_info = pnv_chip_power8_intc_print_info; 1326 k->isa_create = pnv_chip_power8_isa_create; 1327 k->dt_populate = pnv_chip_power8_dt_populate; 1328 k->pic_print_info = pnv_chip_power8_pic_print_info; 1329 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1330 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1331 dc->desc = "PowerNV Chip POWER8E"; 1332 1333 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1334 &k->parent_realize); 1335 } 1336 1337 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1338 { 1339 DeviceClass *dc = DEVICE_CLASS(klass); 1340 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1341 1342 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1343 k->cores_mask = POWER8_CORE_MASK; 1344 k->num_phbs = 3; 1345 k->core_pir = pnv_chip_core_pir_p8; 1346 k->intc_create = pnv_chip_power8_intc_create; 1347 k->intc_reset = pnv_chip_power8_intc_reset; 1348 k->intc_destroy = pnv_chip_power8_intc_destroy; 1349 k->intc_print_info = pnv_chip_power8_intc_print_info; 1350 k->isa_create = pnv_chip_power8_isa_create; 1351 k->dt_populate = pnv_chip_power8_dt_populate; 1352 k->pic_print_info = pnv_chip_power8_pic_print_info; 1353 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1354 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1355 dc->desc = "PowerNV Chip POWER8"; 1356 1357 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1358 &k->parent_realize); 1359 } 1360 1361 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1362 { 1363 DeviceClass *dc = DEVICE_CLASS(klass); 1364 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1365 1366 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1367 k->cores_mask = POWER8_CORE_MASK; 1368 k->num_phbs = 4; 1369 k->core_pir = pnv_chip_core_pir_p8; 1370 k->intc_create = pnv_chip_power8_intc_create; 1371 k->intc_reset = pnv_chip_power8_intc_reset; 1372 k->intc_destroy = pnv_chip_power8_intc_destroy; 1373 k->intc_print_info = pnv_chip_power8_intc_print_info; 1374 k->isa_create = pnv_chip_power8nvl_isa_create; 1375 k->dt_populate = pnv_chip_power8_dt_populate; 1376 k->pic_print_info = pnv_chip_power8_pic_print_info; 1377 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1378 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1379 dc->desc = "PowerNV Chip POWER8NVL"; 1380 1381 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1382 &k->parent_realize); 1383 } 1384 1385 static void pnv_chip_power9_instance_init(Object *obj) 1386 { 1387 PnvChip *chip = PNV_CHIP(obj); 1388 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1389 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1390 int i; 1391 1392 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1393 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1394 "xive-fabric"); 1395 1396 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1397 1398 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1399 1400 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1401 1402 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1403 1404 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1405 1406 /* Number of PECs is the chip default */ 1407 chip->num_pecs = pcc->num_pecs; 1408 1409 for (i = 0; i < chip->num_pecs; i++) { 1410 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1411 TYPE_PNV_PHB4_PEC); 1412 } 1413 } 1414 1415 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1416 PnvCore *pnv_core) 1417 { 1418 char eq_name[32]; 1419 int core_id = CPU_CORE(pnv_core)->core_id; 1420 1421 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1422 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1423 sizeof(*eq), TYPE_PNV_QUAD, 1424 &error_fatal, NULL); 1425 1426 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1427 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1428 } 1429 1430 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1431 { 1432 PnvChip *chip = PNV_CHIP(chip9); 1433 int i; 1434 1435 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1436 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1437 1438 for (i = 0; i < chip9->nr_quads; i++) { 1439 PnvQuad *eq = &chip9->quads[i]; 1440 1441 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1442 1443 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1444 &eq->xscom_regs); 1445 } 1446 } 1447 1448 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1449 { 1450 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1451 int i; 1452 1453 for (i = 0; i < chip->num_pecs; i++) { 1454 PnvPhb4PecState *pec = &chip9->pecs[i]; 1455 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1456 uint32_t pec_nest_base; 1457 uint32_t pec_pci_base; 1458 1459 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1460 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1461 &error_fatal); 1462 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1463 &error_fatal); 1464 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1465 return; 1466 } 1467 1468 pec_nest_base = pecc->xscom_nest_base(pec); 1469 pec_pci_base = pecc->xscom_pci_base(pec); 1470 1471 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1472 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1473 } 1474 } 1475 1476 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1477 { 1478 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1479 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1480 PnvChip *chip = PNV_CHIP(dev); 1481 Pnv9Psi *psi9 = &chip9->psi; 1482 Error *local_err = NULL; 1483 1484 /* XSCOM bridge is first */ 1485 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1486 if (local_err) { 1487 error_propagate(errp, local_err); 1488 return; 1489 } 1490 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1491 1492 pcc->parent_realize(dev, &local_err); 1493 if (local_err) { 1494 error_propagate(errp, local_err); 1495 return; 1496 } 1497 1498 pnv_chip_quad_realize(chip9, &local_err); 1499 if (local_err) { 1500 error_propagate(errp, local_err); 1501 return; 1502 } 1503 1504 /* XIVE interrupt controller (POWER9) */ 1505 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1506 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1507 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1508 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1509 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1510 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1511 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1512 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1513 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1514 &error_abort); 1515 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1516 return; 1517 } 1518 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1519 &chip9->xive.xscom_regs); 1520 1521 /* Processor Service Interface (PSI) Host Bridge */ 1522 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1523 &error_fatal); 1524 /* This is the only device with 4k ESB pages */ 1525 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1526 &error_fatal); 1527 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1528 return; 1529 } 1530 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1531 &PNV_PSI(psi9)->xscom_regs); 1532 1533 /* LPC */ 1534 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1535 return; 1536 } 1537 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1538 &chip9->lpc.xscom_regs); 1539 1540 chip->fw_mr = &chip9->lpc.isa_fw; 1541 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1542 (uint64_t) PNV9_LPCM_BASE(chip)); 1543 1544 /* Create the simplified OCC model */ 1545 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1546 return; 1547 } 1548 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1549 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1550 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); 1551 1552 /* OCC SRAM model */ 1553 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1554 &chip9->occ.sram_regs); 1555 1556 /* SBE */ 1557 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1558 return; 1559 } 1560 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1561 &chip9->sbe.xscom_ctrl_regs); 1562 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1563 &chip9->sbe.xscom_mbox_regs); 1564 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1565 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU)); 1566 1567 /* HOMER */ 1568 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1569 &error_abort); 1570 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1571 return; 1572 } 1573 /* Homer Xscom region */ 1574 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1575 1576 /* Homer mmio region */ 1577 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1578 &chip9->homer.regs); 1579 1580 /* PEC PHBs */ 1581 pnv_chip_power9_pec_realize(chip, &local_err); 1582 if (local_err) { 1583 error_propagate(errp, local_err); 1584 return; 1585 } 1586 } 1587 1588 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1589 { 1590 addr &= (PNV9_XSCOM_SIZE - 1); 1591 return addr >> 3; 1592 } 1593 1594 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1595 { 1596 DeviceClass *dc = DEVICE_CLASS(klass); 1597 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1598 1599 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1600 k->cores_mask = POWER9_CORE_MASK; 1601 k->core_pir = pnv_chip_core_pir_p9; 1602 k->intc_create = pnv_chip_power9_intc_create; 1603 k->intc_reset = pnv_chip_power9_intc_reset; 1604 k->intc_destroy = pnv_chip_power9_intc_destroy; 1605 k->intc_print_info = pnv_chip_power9_intc_print_info; 1606 k->isa_create = pnv_chip_power9_isa_create; 1607 k->dt_populate = pnv_chip_power9_dt_populate; 1608 k->pic_print_info = pnv_chip_power9_pic_print_info; 1609 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1610 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1611 dc->desc = "PowerNV Chip POWER9"; 1612 k->num_pecs = PNV9_CHIP_MAX_PEC; 1613 1614 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1615 &k->parent_realize); 1616 } 1617 1618 static void pnv_chip_power10_instance_init(Object *obj) 1619 { 1620 PnvChip *chip = PNV_CHIP(obj); 1621 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1622 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1623 int i; 1624 1625 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1626 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1627 "xive-fabric"); 1628 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1629 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1630 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1631 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1632 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1633 1634 chip->num_pecs = pcc->num_pecs; 1635 1636 for (i = 0; i < chip->num_pecs; i++) { 1637 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1638 TYPE_PNV_PHB5_PEC); 1639 } 1640 } 1641 1642 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1643 { 1644 PnvChip *chip = PNV_CHIP(chip10); 1645 int i; 1646 1647 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1648 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1649 1650 for (i = 0; i < chip10->nr_quads; i++) { 1651 PnvQuad *eq = &chip10->quads[i]; 1652 1653 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1654 1655 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1656 &eq->xscom_regs); 1657 } 1658 } 1659 1660 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1661 { 1662 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1663 int i; 1664 1665 for (i = 0; i < chip->num_pecs; i++) { 1666 PnvPhb4PecState *pec = &chip10->pecs[i]; 1667 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1668 uint32_t pec_nest_base; 1669 uint32_t pec_pci_base; 1670 1671 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1672 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1673 &error_fatal); 1674 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1675 &error_fatal); 1676 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1677 return; 1678 } 1679 1680 pec_nest_base = pecc->xscom_nest_base(pec); 1681 pec_pci_base = pecc->xscom_pci_base(pec); 1682 1683 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1684 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1685 } 1686 } 1687 1688 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1689 { 1690 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1691 PnvChip *chip = PNV_CHIP(dev); 1692 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1693 Error *local_err = NULL; 1694 1695 /* XSCOM bridge is first */ 1696 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1697 if (local_err) { 1698 error_propagate(errp, local_err); 1699 return; 1700 } 1701 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1702 1703 pcc->parent_realize(dev, &local_err); 1704 if (local_err) { 1705 error_propagate(errp, local_err); 1706 return; 1707 } 1708 1709 pnv_chip_power10_quad_realize(chip10, &local_err); 1710 if (local_err) { 1711 error_propagate(errp, local_err); 1712 return; 1713 } 1714 1715 /* XIVE2 interrupt controller (POWER10) */ 1716 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1717 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1718 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1719 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1720 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1721 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1722 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1723 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1724 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1725 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1726 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1727 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1728 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1729 &error_abort); 1730 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1731 return; 1732 } 1733 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1734 &chip10->xive.xscom_regs); 1735 1736 /* Processor Service Interface (PSI) Host Bridge */ 1737 object_property_set_int(OBJECT(&chip10->psi), "bar", 1738 PNV10_PSIHB_BASE(chip), &error_fatal); 1739 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1740 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1741 &error_fatal); 1742 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1743 return; 1744 } 1745 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1746 &PNV_PSI(&chip10->psi)->xscom_regs); 1747 1748 /* LPC */ 1749 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1750 return; 1751 } 1752 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1753 &chip10->lpc.xscom_regs); 1754 1755 chip->fw_mr = &chip10->lpc.isa_fw; 1756 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1757 (uint64_t) PNV10_LPCM_BASE(chip)); 1758 1759 /* Create the simplified OCC model */ 1760 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1761 return; 1762 } 1763 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1764 &chip10->occ.xscom_regs); 1765 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1766 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1767 1768 /* OCC SRAM model */ 1769 memory_region_add_subregion(get_system_memory(), 1770 PNV10_OCC_SENSOR_BASE(chip), 1771 &chip10->occ.sram_regs); 1772 1773 /* SBE */ 1774 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1775 return; 1776 } 1777 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1778 &chip10->sbe.xscom_ctrl_regs); 1779 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 1780 &chip10->sbe.xscom_mbox_regs); 1781 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 1782 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 1783 1784 /* HOMER */ 1785 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1786 &error_abort); 1787 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1788 return; 1789 } 1790 /* Homer Xscom region */ 1791 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1792 &chip10->homer.pba_regs); 1793 1794 /* Homer mmio region */ 1795 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1796 &chip10->homer.regs); 1797 1798 /* PHBs */ 1799 pnv_chip_power10_phb_realize(chip, &local_err); 1800 if (local_err) { 1801 error_propagate(errp, local_err); 1802 return; 1803 } 1804 } 1805 1806 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1807 { 1808 addr &= (PNV10_XSCOM_SIZE - 1); 1809 return addr >> 3; 1810 } 1811 1812 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1813 { 1814 DeviceClass *dc = DEVICE_CLASS(klass); 1815 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1816 1817 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1818 k->cores_mask = POWER10_CORE_MASK; 1819 k->core_pir = pnv_chip_core_pir_p10; 1820 k->intc_create = pnv_chip_power10_intc_create; 1821 k->intc_reset = pnv_chip_power10_intc_reset; 1822 k->intc_destroy = pnv_chip_power10_intc_destroy; 1823 k->intc_print_info = pnv_chip_power10_intc_print_info; 1824 k->isa_create = pnv_chip_power10_isa_create; 1825 k->dt_populate = pnv_chip_power10_dt_populate; 1826 k->pic_print_info = pnv_chip_power10_pic_print_info; 1827 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1828 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1829 dc->desc = "PowerNV Chip POWER10"; 1830 k->num_pecs = PNV10_CHIP_MAX_PEC; 1831 1832 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1833 &k->parent_realize); 1834 } 1835 1836 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1837 { 1838 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1839 int cores_max; 1840 1841 /* 1842 * No custom mask for this chip, let's use the default one from * 1843 * the chip class 1844 */ 1845 if (!chip->cores_mask) { 1846 chip->cores_mask = pcc->cores_mask; 1847 } 1848 1849 /* filter alien core ids ! some are reserved */ 1850 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1851 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1852 chip->cores_mask); 1853 return; 1854 } 1855 chip->cores_mask &= pcc->cores_mask; 1856 1857 /* now that we have a sane layout, let check the number of cores */ 1858 cores_max = ctpop64(chip->cores_mask); 1859 if (chip->nr_cores > cores_max) { 1860 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1861 cores_max); 1862 return; 1863 } 1864 } 1865 1866 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1867 { 1868 Error *error = NULL; 1869 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1870 const char *typename = pnv_chip_core_typename(chip); 1871 int i, core_hwid; 1872 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1873 1874 if (!object_class_by_name(typename)) { 1875 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1876 return; 1877 } 1878 1879 /* Cores */ 1880 pnv_chip_core_sanitize(chip, &error); 1881 if (error) { 1882 error_propagate(errp, error); 1883 return; 1884 } 1885 1886 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1887 1888 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1889 && (i < chip->nr_cores); core_hwid++) { 1890 char core_name[32]; 1891 PnvCore *pnv_core; 1892 uint64_t xscom_core_base; 1893 1894 if (!(chip->cores_mask & (1ull << core_hwid))) { 1895 continue; 1896 } 1897 1898 pnv_core = PNV_CORE(object_new(typename)); 1899 1900 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1901 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1902 chip->cores[i] = pnv_core; 1903 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1904 chip->nr_threads, &error_fatal); 1905 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1906 core_hwid, &error_fatal); 1907 object_property_set_int(OBJECT(pnv_core), "pir", 1908 pcc->core_pir(chip, core_hwid), &error_fatal); 1909 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1910 &error_fatal); 1911 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1912 &error_abort); 1913 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1914 1915 /* Each core has an XSCOM MMIO region */ 1916 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1917 1918 pnv_xscom_add_subregion(chip, xscom_core_base, 1919 &pnv_core->xscom_regs); 1920 i++; 1921 } 1922 } 1923 1924 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1925 { 1926 PnvChip *chip = PNV_CHIP(dev); 1927 Error *error = NULL; 1928 1929 /* Cores */ 1930 pnv_chip_core_realize(chip, &error); 1931 if (error) { 1932 error_propagate(errp, error); 1933 return; 1934 } 1935 } 1936 1937 static Property pnv_chip_properties[] = { 1938 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1939 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1940 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1941 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1942 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1943 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1944 DEFINE_PROP_END_OF_LIST(), 1945 }; 1946 1947 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1948 { 1949 DeviceClass *dc = DEVICE_CLASS(klass); 1950 1951 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1952 dc->realize = pnv_chip_realize; 1953 device_class_set_props(dc, pnv_chip_properties); 1954 dc->desc = "PowerNV Chip"; 1955 } 1956 1957 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1958 { 1959 int i, j; 1960 1961 for (i = 0; i < chip->nr_cores; i++) { 1962 PnvCore *pc = chip->cores[i]; 1963 CPUCore *cc = CPU_CORE(pc); 1964 1965 for (j = 0; j < cc->nr_threads; j++) { 1966 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1967 return pc->threads[j]; 1968 } 1969 } 1970 } 1971 return NULL; 1972 } 1973 1974 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1975 { 1976 PnvMachineState *pnv = PNV_MACHINE(xi); 1977 int i, j; 1978 1979 for (i = 0; i < pnv->num_chips; i++) { 1980 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1981 1982 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1983 return &chip8->psi.ics; 1984 } 1985 1986 for (j = 0; j < chip8->num_phbs; j++) { 1987 PnvPHB *phb = &chip8->phbs[j]; 1988 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 1989 1990 if (ics_valid_irq(&phb3->lsis, irq)) { 1991 return &phb3->lsis; 1992 } 1993 1994 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 1995 return ICS(&phb3->msis); 1996 } 1997 } 1998 } 1999 return NULL; 2000 } 2001 2002 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2003 { 2004 int i; 2005 2006 for (i = 0; i < pnv->num_chips; i++) { 2007 PnvChip *chip = pnv->chips[i]; 2008 if (chip->chip_id == chip_id) { 2009 return chip; 2010 } 2011 } 2012 return NULL; 2013 } 2014 2015 static void pnv_ics_resend(XICSFabric *xi) 2016 { 2017 PnvMachineState *pnv = PNV_MACHINE(xi); 2018 int i, j; 2019 2020 for (i = 0; i < pnv->num_chips; i++) { 2021 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2022 2023 ics_resend(&chip8->psi.ics); 2024 2025 for (j = 0; j < chip8->num_phbs; j++) { 2026 PnvPHB *phb = &chip8->phbs[j]; 2027 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2028 2029 ics_resend(&phb3->lsis); 2030 ics_resend(ICS(&phb3->msis)); 2031 } 2032 } 2033 } 2034 2035 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2036 { 2037 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2038 2039 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2040 } 2041 2042 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2043 Monitor *mon) 2044 { 2045 PnvMachineState *pnv = PNV_MACHINE(obj); 2046 int i; 2047 CPUState *cs; 2048 2049 CPU_FOREACH(cs) { 2050 PowerPCCPU *cpu = POWERPC_CPU(cs); 2051 2052 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2053 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2054 mon); 2055 } 2056 2057 for (i = 0; i < pnv->num_chips; i++) { 2058 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2059 } 2060 } 2061 2062 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2063 uint8_t nvt_blk, uint32_t nvt_idx, 2064 bool cam_ignore, uint8_t priority, 2065 uint32_t logic_serv, 2066 XiveTCTXMatch *match) 2067 { 2068 PnvMachineState *pnv = PNV_MACHINE(xfb); 2069 int total_count = 0; 2070 int i; 2071 2072 for (i = 0; i < pnv->num_chips; i++) { 2073 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2074 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2075 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2076 int count; 2077 2078 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2079 priority, logic_serv, match); 2080 2081 if (count < 0) { 2082 return count; 2083 } 2084 2085 total_count += count; 2086 } 2087 2088 return total_count; 2089 } 2090 2091 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2092 uint8_t nvt_blk, uint32_t nvt_idx, 2093 bool cam_ignore, uint8_t priority, 2094 uint32_t logic_serv, 2095 XiveTCTXMatch *match) 2096 { 2097 PnvMachineState *pnv = PNV_MACHINE(xfb); 2098 int total_count = 0; 2099 int i; 2100 2101 for (i = 0; i < pnv->num_chips; i++) { 2102 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2103 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2104 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2105 int count; 2106 2107 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2108 priority, logic_serv, match); 2109 2110 if (count < 0) { 2111 return count; 2112 } 2113 2114 total_count += count; 2115 } 2116 2117 return total_count; 2118 } 2119 2120 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2121 { 2122 MachineClass *mc = MACHINE_CLASS(oc); 2123 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2124 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2125 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2126 2127 static GlobalProperty phb_compat[] = { 2128 { TYPE_PNV_PHB, "version", "3" }, 2129 }; 2130 2131 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2132 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2133 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2134 2135 xic->icp_get = pnv_icp_get; 2136 xic->ics_get = pnv_ics_get; 2137 xic->ics_resend = pnv_ics_resend; 2138 2139 pmc->compat = compat; 2140 pmc->compat_size = sizeof(compat); 2141 } 2142 2143 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2144 { 2145 MachineClass *mc = MACHINE_CLASS(oc); 2146 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2147 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2148 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2149 2150 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2151 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 2152 xfc->match_nvt = pnv_match_nvt; 2153 2154 mc->alias = "powernv"; 2155 2156 pmc->compat = compat; 2157 pmc->compat_size = sizeof(compat); 2158 pmc->dt_power_mgt = pnv_dt_power_mgt; 2159 } 2160 2161 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2162 { 2163 MachineClass *mc = MACHINE_CLASS(oc); 2164 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2165 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2166 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2167 2168 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2169 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2170 2171 pmc->compat = compat; 2172 pmc->compat_size = sizeof(compat); 2173 pmc->dt_power_mgt = pnv_dt_power_mgt; 2174 2175 xfc->match_nvt = pnv10_xive_match_nvt; 2176 } 2177 2178 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2179 { 2180 PnvMachineState *pnv = PNV_MACHINE(obj); 2181 2182 return !!pnv->fw_load_addr; 2183 } 2184 2185 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2186 { 2187 PnvMachineState *pnv = PNV_MACHINE(obj); 2188 2189 if (value) { 2190 pnv->fw_load_addr = 0x8000000; 2191 } 2192 } 2193 2194 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2195 { 2196 PowerPCCPU *cpu = POWERPC_CPU(cs); 2197 CPUPPCState *env = &cpu->env; 2198 2199 cpu_synchronize_state(cs); 2200 ppc_cpu_do_system_reset(cs); 2201 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2202 /* 2203 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2204 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2205 * (PPC_BIT(43)). 2206 */ 2207 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2208 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2209 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2210 } 2211 } else { 2212 /* 2213 * For non-powersave system resets, SRR1[42:45] are defined to be 2214 * implementation-dependent. The POWER9 User Manual specifies that 2215 * an external (SCOM driven, which may come from a BMC nmi command or 2216 * another CPU requesting a NMI IPI) system reset exception should be 2217 * 0b0010 (PPC_BIT(44)). 2218 */ 2219 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2220 } 2221 } 2222 2223 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2224 { 2225 CPUState *cs; 2226 2227 CPU_FOREACH(cs) { 2228 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2229 } 2230 } 2231 2232 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2233 { 2234 MachineClass *mc = MACHINE_CLASS(oc); 2235 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2236 NMIClass *nc = NMI_CLASS(oc); 2237 2238 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2239 mc->init = pnv_init; 2240 mc->reset = pnv_reset; 2241 mc->max_cpus = MAX_CPUS; 2242 /* Pnv provides a AHCI device for storage */ 2243 mc->block_default_type = IF_IDE; 2244 mc->no_parallel = 1; 2245 mc->default_boot_order = NULL; 2246 /* 2247 * RAM defaults to less than 2048 for 32-bit hosts, and large 2248 * enough to fit the maximum initrd size at it's load address 2249 */ 2250 mc->default_ram_size = 1 * GiB; 2251 mc->default_ram_id = "pnv.ram"; 2252 ispc->print_info = pnv_pic_print_info; 2253 nc->nmi_monitor_handler = pnv_nmi; 2254 2255 object_class_property_add_bool(oc, "hb-mode", 2256 pnv_machine_get_hb, pnv_machine_set_hb); 2257 object_class_property_set_description(oc, "hb-mode", 2258 "Use a hostboot like boot loader"); 2259 } 2260 2261 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2262 { \ 2263 .name = type, \ 2264 .class_init = class_initfn, \ 2265 .parent = TYPE_PNV8_CHIP, \ 2266 } 2267 2268 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2269 { \ 2270 .name = type, \ 2271 .class_init = class_initfn, \ 2272 .parent = TYPE_PNV9_CHIP, \ 2273 } 2274 2275 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2276 { \ 2277 .name = type, \ 2278 .class_init = class_initfn, \ 2279 .parent = TYPE_PNV10_CHIP, \ 2280 } 2281 2282 static const TypeInfo types[] = { 2283 { 2284 .name = MACHINE_TYPE_NAME("powernv10"), 2285 .parent = TYPE_PNV_MACHINE, 2286 .class_init = pnv_machine_power10_class_init, 2287 .interfaces = (InterfaceInfo[]) { 2288 { TYPE_XIVE_FABRIC }, 2289 { }, 2290 }, 2291 }, 2292 { 2293 .name = MACHINE_TYPE_NAME("powernv9"), 2294 .parent = TYPE_PNV_MACHINE, 2295 .class_init = pnv_machine_power9_class_init, 2296 .interfaces = (InterfaceInfo[]) { 2297 { TYPE_XIVE_FABRIC }, 2298 { }, 2299 }, 2300 }, 2301 { 2302 .name = MACHINE_TYPE_NAME("powernv8"), 2303 .parent = TYPE_PNV_MACHINE, 2304 .class_init = pnv_machine_power8_class_init, 2305 .interfaces = (InterfaceInfo[]) { 2306 { TYPE_XICS_FABRIC }, 2307 { }, 2308 }, 2309 }, 2310 { 2311 .name = TYPE_PNV_MACHINE, 2312 .parent = TYPE_MACHINE, 2313 .abstract = true, 2314 .instance_size = sizeof(PnvMachineState), 2315 .class_init = pnv_machine_class_init, 2316 .class_size = sizeof(PnvMachineClass), 2317 .interfaces = (InterfaceInfo[]) { 2318 { TYPE_INTERRUPT_STATS_PROVIDER }, 2319 { TYPE_NMI }, 2320 { }, 2321 }, 2322 }, 2323 { 2324 .name = TYPE_PNV_CHIP, 2325 .parent = TYPE_SYS_BUS_DEVICE, 2326 .class_init = pnv_chip_class_init, 2327 .instance_size = sizeof(PnvChip), 2328 .class_size = sizeof(PnvChipClass), 2329 .abstract = true, 2330 }, 2331 2332 /* 2333 * P10 chip and variants 2334 */ 2335 { 2336 .name = TYPE_PNV10_CHIP, 2337 .parent = TYPE_PNV_CHIP, 2338 .instance_init = pnv_chip_power10_instance_init, 2339 .instance_size = sizeof(Pnv10Chip), 2340 }, 2341 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2342 2343 /* 2344 * P9 chip and variants 2345 */ 2346 { 2347 .name = TYPE_PNV9_CHIP, 2348 .parent = TYPE_PNV_CHIP, 2349 .instance_init = pnv_chip_power9_instance_init, 2350 .instance_size = sizeof(Pnv9Chip), 2351 }, 2352 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2353 2354 /* 2355 * P8 chip and variants 2356 */ 2357 { 2358 .name = TYPE_PNV8_CHIP, 2359 .parent = TYPE_PNV_CHIP, 2360 .instance_init = pnv_chip_power8_instance_init, 2361 .instance_size = sizeof(Pnv8Chip), 2362 }, 2363 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2364 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2365 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2366 pnv_chip_power8nvl_class_init), 2367 }; 2368 2369 DEFINE_TYPES(types) 2370