1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci-host/pnv_phb.h" 47 #include "hw/pci-host/pnv_phb3.h" 48 #include "hw/pci-host/pnv_phb4.h" 49 50 #include "hw/ppc/xics.h" 51 #include "hw/qdev-properties.h" 52 #include "hw/ppc/pnv_chip.h" 53 #include "hw/ppc/pnv_xscom.h" 54 #include "hw/ppc/pnv_pnor.h" 55 56 #include "hw/isa/isa.h" 57 #include "hw/char/serial.h" 58 #include "hw/rtc/mc146818rtc.h" 59 60 #include <libfdt.h> 61 62 #define FDT_MAX_SIZE (1 * MiB) 63 64 #define FW_FILE_NAME "skiboot.lid" 65 #define FW_LOAD_ADDR 0x0 66 #define FW_MAX_SIZE (16 * MiB) 67 68 #define KERNEL_LOAD_ADDR 0x20000000 69 #define KERNEL_MAX_SIZE (128 * MiB) 70 #define INITRD_LOAD_ADDR 0x28000000 71 #define INITRD_MAX_SIZE (128 * MiB) 72 73 static const char *pnv_chip_core_typename(const PnvChip *o) 74 { 75 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 76 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 77 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 78 const char *core_type = object_class_get_name(object_class_by_name(s)); 79 g_free(s); 80 return core_type; 81 } 82 83 /* 84 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 85 * 4 * 4 sockets * 12 cores * 8 threads = 1536 86 * Let's make it 2^11 87 */ 88 #define MAX_CPUS 2048 89 90 /* 91 * Memory nodes are created by hostboot, one for each range of memory 92 * that has a different "affinity". In practice, it means one range 93 * per chip. 94 */ 95 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 96 { 97 char *mem_name; 98 uint64_t mem_reg_property[2]; 99 int off; 100 101 mem_reg_property[0] = cpu_to_be64(start); 102 mem_reg_property[1] = cpu_to_be64(size); 103 104 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 105 off = fdt_add_subnode(fdt, 0, mem_name); 106 g_free(mem_name); 107 108 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 109 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 110 sizeof(mem_reg_property)))); 111 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 112 } 113 114 static int get_cpus_node(void *fdt) 115 { 116 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 117 118 if (cpus_offset < 0) { 119 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 120 if (cpus_offset) { 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 123 } 124 } 125 _FDT(cpus_offset); 126 return cpus_offset; 127 } 128 129 /* 130 * The PowerNV cores (and threads) need to use real HW ids and not an 131 * incremental index like it has been done on other platforms. This HW 132 * id is stored in the CPU PIR, it is used to create cpu nodes in the 133 * device tree, used in XSCOM to address cores and in interrupt 134 * servers. 135 */ 136 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 137 { 138 PowerPCCPU *cpu = pc->threads[0]; 139 CPUState *cs = CPU(cpu); 140 DeviceClass *dc = DEVICE_GET_CLASS(cs); 141 int smt_threads = CPU_CORE(pc)->nr_threads; 142 CPUPPCState *env = &cpu->env; 143 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 145 int i; 146 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 147 0xffffffff, 0xffffffff}; 148 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 149 uint32_t cpufreq = 1000000000; 150 uint32_t page_sizes_prop[64]; 151 size_t page_sizes_prop_size; 152 const uint8_t pa_features[] = { 24, 0, 153 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 154 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 155 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 156 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 157 int offset; 158 char *nodename; 159 int cpus_offset = get_cpus_node(fdt); 160 161 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 162 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 163 _FDT(offset); 164 g_free(nodename); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 170 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 171 172 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 176 env->dcache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 178 env->icache_line_size))); 179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 180 env->icache_line_size))); 181 182 if (pcc->l1_dcache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 184 pcc->l1_dcache_size))); 185 } else { 186 warn_report("Unknown L1 dcache size for cpu"); 187 } 188 if (pcc->l1_icache_size) { 189 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 190 pcc->l1_icache_size))); 191 } else { 192 warn_report("Unknown L1 icache size for cpu"); 193 } 194 195 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 196 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 198 cpu->hash64_opts->slb_size))); 199 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 200 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 201 202 if (ppc_has_spr(cpu, SPR_PURR)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 204 } 205 206 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 207 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 208 segs, sizeof(segs)))); 209 } 210 211 /* 212 * Advertise VMX/VSX (vector extensions) if available 213 * 0 / no property == no vector extensions 214 * 1 == VMX / Altivec available 215 * 2 == VSX available 216 */ 217 if (env->insns_flags & PPC_ALTIVEC) { 218 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 219 220 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 221 } 222 223 /* 224 * Advertise DFP (Decimal Floating Point) if available 225 * 0 / no property == no DFP 226 * 1 == DFP available 227 */ 228 if (env->insns_flags2 & PPC2_DFP) { 229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 230 } 231 232 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 233 sizeof(page_sizes_prop)); 234 if (page_sizes_prop_size) { 235 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 236 page_sizes_prop, page_sizes_prop_size))); 237 } 238 239 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 240 pa_features, sizeof(pa_features)))); 241 242 /* Build interrupt servers properties */ 243 for (i = 0; i < smt_threads; i++) { 244 servers_prop[i] = cpu_to_be32(pc->pir + i); 245 } 246 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 247 servers_prop, sizeof(*servers_prop) * smt_threads))); 248 } 249 250 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 251 uint32_t nr_threads) 252 { 253 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 254 char *name; 255 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 256 uint32_t irange[2], i, rsize; 257 uint64_t *reg; 258 int offset; 259 260 irange[0] = cpu_to_be32(pir); 261 irange[1] = cpu_to_be32(nr_threads); 262 263 rsize = sizeof(uint64_t) * 2 * nr_threads; 264 reg = g_malloc(rsize); 265 for (i = 0; i < nr_threads; i++) { 266 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 267 reg[i * 2 + 1] = cpu_to_be64(0x1000); 268 } 269 270 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 271 offset = fdt_add_subnode(fdt, 0, name); 272 _FDT(offset); 273 g_free(name); 274 275 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 276 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 277 _FDT((fdt_setprop_string(fdt, offset, "device_type", 278 "PowerPC-External-Interrupt-Presentation"))); 279 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 280 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 281 irange, sizeof(irange)))); 282 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 283 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 284 g_free(reg); 285 } 286 287 /* 288 * Adds a PnvPHB to the chip on P8. 289 * Implemented here, like for defaults PHBs 290 */ 291 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 292 { 293 Pnv8Chip *chip8 = PNV8_CHIP(chip); 294 295 phb->chip = chip; 296 297 chip8->phbs[chip8->num_phbs] = phb; 298 chip8->num_phbs++; 299 return chip; 300 } 301 302 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 303 { 304 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 305 int i; 306 307 pnv_dt_xscom(chip, fdt, 0, 308 cpu_to_be64(PNV_XSCOM_BASE(chip)), 309 cpu_to_be64(PNV_XSCOM_SIZE), 310 compat, sizeof(compat)); 311 312 for (i = 0; i < chip->nr_cores; i++) { 313 PnvCore *pnv_core = chip->cores[i]; 314 315 pnv_dt_core(chip, pnv_core, fdt); 316 317 /* Interrupt Control Presenters (ICP). One per core. */ 318 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 319 } 320 321 if (chip->ram_size) { 322 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 323 } 324 } 325 326 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 327 { 328 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 329 int i; 330 331 pnv_dt_xscom(chip, fdt, 0, 332 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 333 cpu_to_be64(PNV9_XSCOM_SIZE), 334 compat, sizeof(compat)); 335 336 for (i = 0; i < chip->nr_cores; i++) { 337 PnvCore *pnv_core = chip->cores[i]; 338 339 pnv_dt_core(chip, pnv_core, fdt); 340 } 341 342 if (chip->ram_size) { 343 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 344 } 345 346 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 347 } 348 349 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 350 { 351 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 352 int i; 353 354 pnv_dt_xscom(chip, fdt, 0, 355 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 356 cpu_to_be64(PNV10_XSCOM_SIZE), 357 compat, sizeof(compat)); 358 359 for (i = 0; i < chip->nr_cores; i++) { 360 PnvCore *pnv_core = chip->cores[i]; 361 362 pnv_dt_core(chip, pnv_core, fdt); 363 } 364 365 if (chip->ram_size) { 366 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 367 } 368 369 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 370 } 371 372 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 373 { 374 uint32_t io_base = d->ioport_id; 375 uint32_t io_regs[] = { 376 cpu_to_be32(1), 377 cpu_to_be32(io_base), 378 cpu_to_be32(2) 379 }; 380 char *name; 381 int node; 382 383 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 384 node = fdt_add_subnode(fdt, lpc_off, name); 385 _FDT(node); 386 g_free(name); 387 388 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 389 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 390 } 391 392 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 393 { 394 const char compatible[] = "ns16550\0pnpPNP,501"; 395 uint32_t io_base = d->ioport_id; 396 uint32_t io_regs[] = { 397 cpu_to_be32(1), 398 cpu_to_be32(io_base), 399 cpu_to_be32(8) 400 }; 401 uint32_t irq; 402 char *name; 403 int node; 404 405 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 406 407 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 408 node = fdt_add_subnode(fdt, lpc_off, name); 409 _FDT(node); 410 g_free(name); 411 412 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 413 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 414 sizeof(compatible)))); 415 416 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 417 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 418 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 419 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 420 fdt_get_phandle(fdt, lpc_off)))); 421 422 /* This is needed by Linux */ 423 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 424 } 425 426 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 427 { 428 const char compatible[] = "bt\0ipmi-bt"; 429 uint32_t io_base; 430 uint32_t io_regs[] = { 431 cpu_to_be32(1), 432 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 433 cpu_to_be32(3) 434 }; 435 uint32_t irq; 436 char *name; 437 int node; 438 439 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 440 io_regs[1] = cpu_to_be32(io_base); 441 442 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 443 444 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 445 node = fdt_add_subnode(fdt, lpc_off, name); 446 _FDT(node); 447 g_free(name); 448 449 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 450 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 451 sizeof(compatible)))); 452 453 /* Mark it as reserved to avoid Linux trying to claim it */ 454 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 455 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 456 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 457 fdt_get_phandle(fdt, lpc_off)))); 458 } 459 460 typedef struct ForeachPopulateArgs { 461 void *fdt; 462 int offset; 463 } ForeachPopulateArgs; 464 465 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 466 { 467 ForeachPopulateArgs *args = opaque; 468 ISADevice *d = ISA_DEVICE(dev); 469 470 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 471 pnv_dt_rtc(d, args->fdt, args->offset); 472 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 473 pnv_dt_serial(d, args->fdt, args->offset); 474 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 475 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 476 } else { 477 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 478 d->ioport_id); 479 } 480 481 return 0; 482 } 483 484 /* 485 * The default LPC bus of a multichip system is on chip 0. It's 486 * recognized by the firmware (skiboot) using a "primary" property. 487 */ 488 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 489 { 490 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 491 ForeachPopulateArgs args = { 492 .fdt = fdt, 493 .offset = isa_offset, 494 }; 495 uint32_t phandle; 496 497 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 498 499 phandle = qemu_fdt_alloc_phandle(fdt); 500 assert(phandle > 0); 501 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 502 503 /* 504 * ISA devices are not necessarily parented to the ISA bus so we 505 * can not use object_child_foreach() 506 */ 507 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 508 &args); 509 } 510 511 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 512 { 513 int off; 514 515 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 516 off = fdt_add_subnode(fdt, off, "power-mgt"); 517 518 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 519 } 520 521 static void *pnv_dt_create(MachineState *machine) 522 { 523 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 524 PnvMachineState *pnv = PNV_MACHINE(machine); 525 void *fdt; 526 char *buf; 527 int off; 528 int i; 529 530 fdt = g_malloc0(FDT_MAX_SIZE); 531 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 532 533 /* /qemu node */ 534 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 535 536 /* Root node */ 537 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 538 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 539 _FDT((fdt_setprop_string(fdt, 0, "model", 540 "IBM PowerNV (emulated by qemu)"))); 541 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 542 543 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 544 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 545 if (qemu_uuid_set) { 546 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 547 } 548 g_free(buf); 549 550 off = fdt_add_subnode(fdt, 0, "chosen"); 551 if (machine->kernel_cmdline) { 552 _FDT((fdt_setprop_string(fdt, off, "bootargs", 553 machine->kernel_cmdline))); 554 } 555 556 if (pnv->initrd_size) { 557 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 558 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 559 560 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 561 &start_prop, sizeof(start_prop)))); 562 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 563 &end_prop, sizeof(end_prop)))); 564 } 565 566 /* Populate device tree for each chip */ 567 for (i = 0; i < pnv->num_chips; i++) { 568 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 569 } 570 571 /* Populate ISA devices on chip 0 */ 572 pnv_dt_isa(pnv, fdt); 573 574 if (pnv->bmc) { 575 pnv_dt_bmc_sensors(pnv->bmc, fdt); 576 } 577 578 /* Create an extra node for power management on machines that support it */ 579 if (pmc->dt_power_mgt) { 580 pmc->dt_power_mgt(pnv, fdt); 581 } 582 583 return fdt; 584 } 585 586 static void pnv_powerdown_notify(Notifier *n, void *opaque) 587 { 588 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 589 590 if (pnv->bmc) { 591 pnv_bmc_powerdown(pnv->bmc); 592 } 593 } 594 595 static void pnv_reset(MachineState *machine, ShutdownCause reason) 596 { 597 PnvMachineState *pnv = PNV_MACHINE(machine); 598 IPMIBmc *bmc; 599 void *fdt; 600 601 qemu_devices_reset(reason); 602 603 /* 604 * The machine should provide by default an internal BMC simulator. 605 * If not, try to use the BMC device that was provided on the command 606 * line. 607 */ 608 bmc = pnv_bmc_find(&error_fatal); 609 if (!pnv->bmc) { 610 if (!bmc) { 611 if (!qtest_enabled()) { 612 warn_report("machine has no BMC device. Use '-device " 613 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 614 "to define one"); 615 } 616 } else { 617 pnv_bmc_set_pnor(bmc, pnv->pnor); 618 pnv->bmc = bmc; 619 } 620 } 621 622 fdt = pnv_dt_create(machine); 623 624 /* Pack resulting tree */ 625 _FDT((fdt_pack(fdt))); 626 627 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 628 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 629 630 /* 631 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 632 * the existing machine->fdt to avoid leaking it during 633 * a reset. 634 */ 635 g_free(machine->fdt); 636 machine->fdt = fdt; 637 } 638 639 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 640 { 641 Pnv8Chip *chip8 = PNV8_CHIP(chip); 642 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 643 644 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 645 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 646 } 647 648 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 649 { 650 Pnv8Chip *chip8 = PNV8_CHIP(chip); 651 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 652 653 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 654 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 655 } 656 657 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 658 { 659 Pnv9Chip *chip9 = PNV9_CHIP(chip); 660 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 661 662 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 663 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 664 } 665 666 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 667 { 668 Pnv10Chip *chip10 = PNV10_CHIP(chip); 669 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 670 671 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 672 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 673 } 674 675 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 676 { 677 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 678 } 679 680 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 681 { 682 Pnv8Chip *chip8 = PNV8_CHIP(chip); 683 int i; 684 685 ics_pic_print_info(&chip8->psi.ics, mon); 686 687 for (i = 0; i < chip8->num_phbs; i++) { 688 PnvPHB *phb = chip8->phbs[i]; 689 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 690 691 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 692 ics_pic_print_info(&phb3->lsis, mon); 693 } 694 } 695 696 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 697 { 698 Monitor *mon = opaque; 699 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 700 701 if (!phb) { 702 return 0; 703 } 704 705 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon); 706 707 return 0; 708 } 709 710 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 711 { 712 Pnv9Chip *chip9 = PNV9_CHIP(chip); 713 714 pnv_xive_pic_print_info(&chip9->xive, mon); 715 pnv_psi_pic_print_info(&chip9->psi, mon); 716 717 object_child_foreach_recursive(OBJECT(chip), 718 pnv_chip_power9_pic_print_info_child, mon); 719 } 720 721 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 722 uint32_t core_id) 723 { 724 return PNV_XSCOM_EX_BASE(core_id); 725 } 726 727 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 728 uint32_t core_id) 729 { 730 return PNV9_XSCOM_EC_BASE(core_id); 731 } 732 733 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 734 uint32_t core_id) 735 { 736 return PNV10_XSCOM_EC_BASE(core_id); 737 } 738 739 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 740 { 741 PowerPCCPUClass *ppc_default = 742 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 743 PowerPCCPUClass *ppc = 744 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 745 746 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 747 } 748 749 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 750 { 751 ISADevice *dev = isa_new("isa-ipmi-bt"); 752 753 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 754 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 755 isa_realize_and_unref(dev, bus, &error_fatal); 756 } 757 758 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 759 { 760 Pnv10Chip *chip10 = PNV10_CHIP(chip); 761 762 pnv_xive2_pic_print_info(&chip10->xive, mon); 763 pnv_psi_pic_print_info(&chip10->psi, mon); 764 765 object_child_foreach_recursive(OBJECT(chip), 766 pnv_chip_power9_pic_print_info_child, mon); 767 } 768 769 /* Always give the first 1GB to chip 0 else we won't boot */ 770 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 771 { 772 MachineState *machine = MACHINE(pnv); 773 uint64_t ram_per_chip; 774 775 assert(machine->ram_size >= 1 * GiB); 776 777 ram_per_chip = machine->ram_size / pnv->num_chips; 778 if (ram_per_chip >= 1 * GiB) { 779 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 780 } 781 782 assert(pnv->num_chips > 1); 783 784 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 785 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 786 } 787 788 static void pnv_init(MachineState *machine) 789 { 790 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 791 PnvMachineState *pnv = PNV_MACHINE(machine); 792 MachineClass *mc = MACHINE_GET_CLASS(machine); 793 char *fw_filename; 794 long fw_size; 795 uint64_t chip_ram_start = 0; 796 int i; 797 char *chip_typename; 798 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 799 DeviceState *dev; 800 801 if (kvm_enabled()) { 802 error_report("machine %s does not support the KVM accelerator", 803 mc->name); 804 exit(EXIT_FAILURE); 805 } 806 807 /* allocate RAM */ 808 if (machine->ram_size < mc->default_ram_size) { 809 char *sz = size_to_str(mc->default_ram_size); 810 error_report("Invalid RAM size, should be bigger than %s", sz); 811 g_free(sz); 812 exit(EXIT_FAILURE); 813 } 814 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 815 816 /* 817 * Create our simple PNOR device 818 */ 819 dev = qdev_new(TYPE_PNV_PNOR); 820 if (pnor) { 821 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 822 } 823 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 824 pnv->pnor = PNV_PNOR(dev); 825 826 /* load skiboot firmware */ 827 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 828 if (!fw_filename) { 829 error_report("Could not find OPAL firmware '%s'", bios_name); 830 exit(1); 831 } 832 833 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 834 if (fw_size < 0) { 835 error_report("Could not load OPAL firmware '%s'", fw_filename); 836 exit(1); 837 } 838 g_free(fw_filename); 839 840 /* load kernel */ 841 if (machine->kernel_filename) { 842 long kernel_size; 843 844 kernel_size = load_image_targphys(machine->kernel_filename, 845 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 846 if (kernel_size < 0) { 847 error_report("Could not load kernel '%s'", 848 machine->kernel_filename); 849 exit(1); 850 } 851 } 852 853 /* load initrd */ 854 if (machine->initrd_filename) { 855 pnv->initrd_base = INITRD_LOAD_ADDR; 856 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 857 pnv->initrd_base, INITRD_MAX_SIZE); 858 if (pnv->initrd_size < 0) { 859 error_report("Could not load initial ram disk '%s'", 860 machine->initrd_filename); 861 exit(1); 862 } 863 } 864 865 /* MSIs are supported on this platform */ 866 msi_nonbroken = true; 867 868 /* 869 * Check compatibility of the specified CPU with the machine 870 * default. 871 */ 872 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 873 error_report("invalid CPU model '%s' for %s machine", 874 machine->cpu_type, mc->name); 875 exit(1); 876 } 877 878 /* Create the processor chips */ 879 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 880 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 881 i, machine->cpu_type); 882 if (!object_class_by_name(chip_typename)) { 883 error_report("invalid chip model '%.*s' for %s machine", 884 i, machine->cpu_type, mc->name); 885 exit(1); 886 } 887 888 pnv->num_chips = 889 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 890 /* 891 * TODO: should we decide on how many chips we can create based 892 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 893 */ 894 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 895 error_report("invalid number of chips: '%d'", pnv->num_chips); 896 error_printf( 897 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 898 exit(1); 899 } 900 901 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 902 for (i = 0; i < pnv->num_chips; i++) { 903 char chip_name[32]; 904 Object *chip = OBJECT(qdev_new(chip_typename)); 905 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 906 907 pnv->chips[i] = PNV_CHIP(chip); 908 909 /* Distribute RAM among the chips */ 910 object_property_set_int(chip, "ram-start", chip_ram_start, 911 &error_fatal); 912 object_property_set_int(chip, "ram-size", chip_ram_size, 913 &error_fatal); 914 chip_ram_start += chip_ram_size; 915 916 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 917 object_property_add_child(OBJECT(pnv), chip_name, chip); 918 object_property_set_int(chip, "chip-id", i, &error_fatal); 919 object_property_set_int(chip, "nr-cores", machine->smp.cores, 920 &error_fatal); 921 object_property_set_int(chip, "nr-threads", machine->smp.threads, 922 &error_fatal); 923 /* 924 * The POWER8 machine use the XICS interrupt interface. 925 * Propagate the XICS fabric to the chip and its controllers. 926 */ 927 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 928 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 929 } 930 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 931 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 932 &error_abort); 933 } 934 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 935 } 936 g_free(chip_typename); 937 938 /* Instantiate ISA bus on chip 0 */ 939 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 940 941 /* Create serial port */ 942 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 943 944 /* Create an RTC ISA device too */ 945 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 946 947 /* 948 * Create the machine BMC simulator and the IPMI BT device for 949 * communication with the BMC 950 */ 951 if (defaults_enabled()) { 952 pnv->bmc = pnv_bmc_create(pnv->pnor); 953 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 954 } 955 956 /* 957 * The PNOR is mapped on the LPC FW address space by the BMC. 958 * Since we can not reach the remote BMC machine with LPC memops, 959 * map it always for now. 960 */ 961 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 962 &pnv->pnor->mmio); 963 964 /* 965 * OpenPOWER systems use a IPMI SEL Event message to notify the 966 * host to powerdown 967 */ 968 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 969 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 970 } 971 972 /* 973 * 0:21 Reserved - Read as zeros 974 * 22:24 Chip ID 975 * 25:28 Core number 976 * 29:31 Thread ID 977 */ 978 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 979 { 980 return (chip->chip_id << 7) | (core_id << 3); 981 } 982 983 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 984 Error **errp) 985 { 986 Pnv8Chip *chip8 = PNV8_CHIP(chip); 987 Error *local_err = NULL; 988 Object *obj; 989 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 990 991 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 992 if (local_err) { 993 error_propagate(errp, local_err); 994 return; 995 } 996 997 pnv_cpu->intc = obj; 998 } 999 1000 1001 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1002 { 1003 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1004 1005 icp_reset(ICP(pnv_cpu->intc)); 1006 } 1007 1008 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1009 { 1010 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1011 1012 icp_destroy(ICP(pnv_cpu->intc)); 1013 pnv_cpu->intc = NULL; 1014 } 1015 1016 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1017 Monitor *mon) 1018 { 1019 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1020 } 1021 1022 /* 1023 * 0:48 Reserved - Read as zeroes 1024 * 49:52 Node ID 1025 * 53:55 Chip ID 1026 * 56 Reserved - Read as zero 1027 * 57:61 Core number 1028 * 62:63 Thread ID 1029 * 1030 * We only care about the lower bits. uint32_t is fine for the moment. 1031 */ 1032 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 1033 { 1034 return (chip->chip_id << 8) | (core_id << 2); 1035 } 1036 1037 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1038 { 1039 return (chip->chip_id << 8) | (core_id << 2); 1040 } 1041 1042 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1043 Error **errp) 1044 { 1045 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1046 Error *local_err = NULL; 1047 Object *obj; 1048 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1049 1050 /* 1051 * The core creates its interrupt presenter but the XIVE interrupt 1052 * controller object is initialized afterwards. Hopefully, it's 1053 * only used at runtime. 1054 */ 1055 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1056 &local_err); 1057 if (local_err) { 1058 error_propagate(errp, local_err); 1059 return; 1060 } 1061 1062 pnv_cpu->intc = obj; 1063 } 1064 1065 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1066 { 1067 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1068 1069 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1070 } 1071 1072 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1073 { 1074 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1075 1076 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1077 pnv_cpu->intc = NULL; 1078 } 1079 1080 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1081 Monitor *mon) 1082 { 1083 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1084 } 1085 1086 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1087 Error **errp) 1088 { 1089 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1090 Error *local_err = NULL; 1091 Object *obj; 1092 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1093 1094 /* 1095 * The core creates its interrupt presenter but the XIVE2 interrupt 1096 * controller object is initialized afterwards. Hopefully, it's 1097 * only used at runtime. 1098 */ 1099 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1100 &local_err); 1101 if (local_err) { 1102 error_propagate(errp, local_err); 1103 return; 1104 } 1105 1106 pnv_cpu->intc = obj; 1107 } 1108 1109 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1110 { 1111 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1112 1113 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1114 } 1115 1116 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1117 { 1118 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1119 1120 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1121 pnv_cpu->intc = NULL; 1122 } 1123 1124 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1125 Monitor *mon) 1126 { 1127 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1128 } 1129 1130 /* 1131 * Allowed core identifiers on a POWER8 Processor Chip : 1132 * 1133 * <EX0 reserved> 1134 * EX1 - Venice only 1135 * EX2 - Venice only 1136 * EX3 - Venice only 1137 * EX4 1138 * EX5 1139 * EX6 1140 * <EX7,8 reserved> <reserved> 1141 * EX9 - Venice only 1142 * EX10 - Venice only 1143 * EX11 - Venice only 1144 * EX12 1145 * EX13 1146 * EX14 1147 * <EX15 reserved> 1148 */ 1149 #define POWER8E_CORE_MASK (0x7070ull) 1150 #define POWER8_CORE_MASK (0x7e7eull) 1151 1152 /* 1153 * POWER9 has 24 cores, ids starting at 0x0 1154 */ 1155 #define POWER9_CORE_MASK (0xffffffffffffffull) 1156 1157 1158 #define POWER10_CORE_MASK (0xffffffffffffffull) 1159 1160 static void pnv_chip_power8_instance_init(Object *obj) 1161 { 1162 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1163 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1164 int i; 1165 1166 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1167 (Object **)&chip8->xics, 1168 object_property_allow_set_link, 1169 OBJ_PROP_LINK_STRONG); 1170 1171 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1172 1173 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1174 1175 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1176 1177 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1178 1179 if (defaults_enabled()) { 1180 chip8->num_phbs = pcc->num_phbs; 1181 1182 for (i = 0; i < chip8->num_phbs; i++) { 1183 Object *phb = object_new(TYPE_PNV_PHB); 1184 1185 /* 1186 * We need the chip to parent the PHB to allow the DT 1187 * to build correctly (via pnv_xscom_dt()). 1188 * 1189 * TODO: the PHB should be parented by a PEC device that, at 1190 * this moment, is not modelled powernv8/phb3. 1191 */ 1192 object_property_add_child(obj, "phb[*]", phb); 1193 chip8->phbs[i] = PNV_PHB(phb); 1194 } 1195 } 1196 1197 } 1198 1199 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1200 { 1201 PnvChip *chip = PNV_CHIP(chip8); 1202 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1203 int i, j; 1204 char *name; 1205 1206 name = g_strdup_printf("icp-%x", chip->chip_id); 1207 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1208 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1209 g_free(name); 1210 1211 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1212 1213 /* Map the ICP registers for each thread */ 1214 for (i = 0; i < chip->nr_cores; i++) { 1215 PnvCore *pnv_core = chip->cores[i]; 1216 int core_hwid = CPU_CORE(pnv_core)->core_id; 1217 1218 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1219 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1220 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1221 1222 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1223 &icp->mmio); 1224 } 1225 } 1226 } 1227 1228 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1229 { 1230 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1231 PnvChip *chip = PNV_CHIP(dev); 1232 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1233 Pnv8Psi *psi8 = &chip8->psi; 1234 Error *local_err = NULL; 1235 int i; 1236 1237 assert(chip8->xics); 1238 1239 /* XSCOM bridge is first */ 1240 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1241 if (local_err) { 1242 error_propagate(errp, local_err); 1243 return; 1244 } 1245 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1246 1247 pcc->parent_realize(dev, &local_err); 1248 if (local_err) { 1249 error_propagate(errp, local_err); 1250 return; 1251 } 1252 1253 /* Processor Service Interface (PSI) Host Bridge */ 1254 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1255 &error_fatal); 1256 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1257 OBJECT(chip8->xics), &error_abort); 1258 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1259 return; 1260 } 1261 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1262 &PNV_PSI(psi8)->xscom_regs); 1263 1264 /* Create LPC controller */ 1265 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1266 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1267 1268 chip->fw_mr = &chip8->lpc.isa_fw; 1269 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1270 (uint64_t) PNV_XSCOM_BASE(chip), 1271 PNV_XSCOM_LPC_BASE); 1272 1273 /* 1274 * Interrupt Management Area. This is the memory region holding 1275 * all the Interrupt Control Presenter (ICP) registers 1276 */ 1277 pnv_chip_icp_realize(chip8, &local_err); 1278 if (local_err) { 1279 error_propagate(errp, local_err); 1280 return; 1281 } 1282 1283 /* Create the simplified OCC model */ 1284 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1285 return; 1286 } 1287 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1288 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1289 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); 1290 1291 /* OCC SRAM model */ 1292 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1293 &chip8->occ.sram_regs); 1294 1295 /* HOMER */ 1296 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1297 &error_abort); 1298 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1299 return; 1300 } 1301 /* Homer Xscom region */ 1302 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1303 1304 /* Homer mmio region */ 1305 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1306 &chip8->homer.regs); 1307 1308 /* PHB controllers */ 1309 for (i = 0; i < chip8->num_phbs; i++) { 1310 PnvPHB *phb = chip8->phbs[i]; 1311 1312 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1313 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1314 &error_fatal); 1315 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1316 &error_fatal); 1317 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1318 return; 1319 } 1320 } 1321 } 1322 1323 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1324 { 1325 addr &= (PNV_XSCOM_SIZE - 1); 1326 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1327 } 1328 1329 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1330 { 1331 DeviceClass *dc = DEVICE_CLASS(klass); 1332 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1333 1334 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1335 k->cores_mask = POWER8E_CORE_MASK; 1336 k->num_phbs = 3; 1337 k->core_pir = pnv_chip_core_pir_p8; 1338 k->intc_create = pnv_chip_power8_intc_create; 1339 k->intc_reset = pnv_chip_power8_intc_reset; 1340 k->intc_destroy = pnv_chip_power8_intc_destroy; 1341 k->intc_print_info = pnv_chip_power8_intc_print_info; 1342 k->isa_create = pnv_chip_power8_isa_create; 1343 k->dt_populate = pnv_chip_power8_dt_populate; 1344 k->pic_print_info = pnv_chip_power8_pic_print_info; 1345 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1346 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1347 dc->desc = "PowerNV Chip POWER8E"; 1348 1349 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1350 &k->parent_realize); 1351 } 1352 1353 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1354 { 1355 DeviceClass *dc = DEVICE_CLASS(klass); 1356 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1357 1358 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1359 k->cores_mask = POWER8_CORE_MASK; 1360 k->num_phbs = 3; 1361 k->core_pir = pnv_chip_core_pir_p8; 1362 k->intc_create = pnv_chip_power8_intc_create; 1363 k->intc_reset = pnv_chip_power8_intc_reset; 1364 k->intc_destroy = pnv_chip_power8_intc_destroy; 1365 k->intc_print_info = pnv_chip_power8_intc_print_info; 1366 k->isa_create = pnv_chip_power8_isa_create; 1367 k->dt_populate = pnv_chip_power8_dt_populate; 1368 k->pic_print_info = pnv_chip_power8_pic_print_info; 1369 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1370 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1371 dc->desc = "PowerNV Chip POWER8"; 1372 1373 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1374 &k->parent_realize); 1375 } 1376 1377 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1378 { 1379 DeviceClass *dc = DEVICE_CLASS(klass); 1380 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1381 1382 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1383 k->cores_mask = POWER8_CORE_MASK; 1384 k->num_phbs = 4; 1385 k->core_pir = pnv_chip_core_pir_p8; 1386 k->intc_create = pnv_chip_power8_intc_create; 1387 k->intc_reset = pnv_chip_power8_intc_reset; 1388 k->intc_destroy = pnv_chip_power8_intc_destroy; 1389 k->intc_print_info = pnv_chip_power8_intc_print_info; 1390 k->isa_create = pnv_chip_power8nvl_isa_create; 1391 k->dt_populate = pnv_chip_power8_dt_populate; 1392 k->pic_print_info = pnv_chip_power8_pic_print_info; 1393 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1394 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1395 dc->desc = "PowerNV Chip POWER8NVL"; 1396 1397 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1398 &k->parent_realize); 1399 } 1400 1401 static void pnv_chip_power9_instance_init(Object *obj) 1402 { 1403 PnvChip *chip = PNV_CHIP(obj); 1404 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1405 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1406 int i; 1407 1408 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1409 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1410 "xive-fabric"); 1411 1412 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1413 1414 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1415 1416 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1417 1418 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1419 1420 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1421 1422 /* Number of PECs is the chip default */ 1423 chip->num_pecs = pcc->num_pecs; 1424 1425 for (i = 0; i < chip->num_pecs; i++) { 1426 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1427 TYPE_PNV_PHB4_PEC); 1428 } 1429 } 1430 1431 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1432 PnvCore *pnv_core) 1433 { 1434 char eq_name[32]; 1435 int core_id = CPU_CORE(pnv_core)->core_id; 1436 1437 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1438 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1439 sizeof(*eq), TYPE_PNV_QUAD, 1440 &error_fatal, NULL); 1441 1442 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1443 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1444 } 1445 1446 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1447 { 1448 PnvChip *chip = PNV_CHIP(chip9); 1449 int i; 1450 1451 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1452 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1453 1454 for (i = 0; i < chip9->nr_quads; i++) { 1455 PnvQuad *eq = &chip9->quads[i]; 1456 1457 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1458 1459 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1460 &eq->xscom_regs); 1461 } 1462 } 1463 1464 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1465 { 1466 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1467 int i; 1468 1469 for (i = 0; i < chip->num_pecs; i++) { 1470 PnvPhb4PecState *pec = &chip9->pecs[i]; 1471 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1472 uint32_t pec_nest_base; 1473 uint32_t pec_pci_base; 1474 1475 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1476 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1477 &error_fatal); 1478 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1479 &error_fatal); 1480 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1481 return; 1482 } 1483 1484 pec_nest_base = pecc->xscom_nest_base(pec); 1485 pec_pci_base = pecc->xscom_pci_base(pec); 1486 1487 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1488 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1489 } 1490 } 1491 1492 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1493 { 1494 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1495 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1496 PnvChip *chip = PNV_CHIP(dev); 1497 Pnv9Psi *psi9 = &chip9->psi; 1498 Error *local_err = NULL; 1499 1500 /* XSCOM bridge is first */ 1501 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1502 if (local_err) { 1503 error_propagate(errp, local_err); 1504 return; 1505 } 1506 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1507 1508 pcc->parent_realize(dev, &local_err); 1509 if (local_err) { 1510 error_propagate(errp, local_err); 1511 return; 1512 } 1513 1514 pnv_chip_quad_realize(chip9, &local_err); 1515 if (local_err) { 1516 error_propagate(errp, local_err); 1517 return; 1518 } 1519 1520 /* XIVE interrupt controller (POWER9) */ 1521 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1522 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1523 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1524 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1525 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1526 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1527 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1528 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1529 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1530 &error_abort); 1531 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1532 return; 1533 } 1534 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1535 &chip9->xive.xscom_regs); 1536 1537 /* Processor Service Interface (PSI) Host Bridge */ 1538 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1539 &error_fatal); 1540 /* This is the only device with 4k ESB pages */ 1541 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1542 &error_fatal); 1543 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1544 return; 1545 } 1546 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1547 &PNV_PSI(psi9)->xscom_regs); 1548 1549 /* LPC */ 1550 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1551 return; 1552 } 1553 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1554 &chip9->lpc.xscom_regs); 1555 1556 chip->fw_mr = &chip9->lpc.isa_fw; 1557 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1558 (uint64_t) PNV9_LPCM_BASE(chip)); 1559 1560 /* Create the simplified OCC model */ 1561 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1562 return; 1563 } 1564 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1565 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1566 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); 1567 1568 /* OCC SRAM model */ 1569 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1570 &chip9->occ.sram_regs); 1571 1572 /* SBE */ 1573 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1574 return; 1575 } 1576 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1577 &chip9->sbe.xscom_ctrl_regs); 1578 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1579 &chip9->sbe.xscom_mbox_regs); 1580 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1581 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU)); 1582 1583 /* HOMER */ 1584 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1585 &error_abort); 1586 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1587 return; 1588 } 1589 /* Homer Xscom region */ 1590 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1591 1592 /* Homer mmio region */ 1593 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1594 &chip9->homer.regs); 1595 1596 /* PEC PHBs */ 1597 pnv_chip_power9_pec_realize(chip, &local_err); 1598 if (local_err) { 1599 error_propagate(errp, local_err); 1600 return; 1601 } 1602 } 1603 1604 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1605 { 1606 addr &= (PNV9_XSCOM_SIZE - 1); 1607 return addr >> 3; 1608 } 1609 1610 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1611 { 1612 DeviceClass *dc = DEVICE_CLASS(klass); 1613 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1614 1615 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1616 k->cores_mask = POWER9_CORE_MASK; 1617 k->core_pir = pnv_chip_core_pir_p9; 1618 k->intc_create = pnv_chip_power9_intc_create; 1619 k->intc_reset = pnv_chip_power9_intc_reset; 1620 k->intc_destroy = pnv_chip_power9_intc_destroy; 1621 k->intc_print_info = pnv_chip_power9_intc_print_info; 1622 k->isa_create = pnv_chip_power9_isa_create; 1623 k->dt_populate = pnv_chip_power9_dt_populate; 1624 k->pic_print_info = pnv_chip_power9_pic_print_info; 1625 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1626 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1627 dc->desc = "PowerNV Chip POWER9"; 1628 k->num_pecs = PNV9_CHIP_MAX_PEC; 1629 1630 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1631 &k->parent_realize); 1632 } 1633 1634 static void pnv_chip_power10_instance_init(Object *obj) 1635 { 1636 PnvChip *chip = PNV_CHIP(obj); 1637 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1638 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1639 int i; 1640 1641 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1642 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1643 "xive-fabric"); 1644 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1645 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1646 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1647 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1648 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1649 1650 chip->num_pecs = pcc->num_pecs; 1651 1652 for (i = 0; i < chip->num_pecs; i++) { 1653 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1654 TYPE_PNV_PHB5_PEC); 1655 } 1656 } 1657 1658 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1659 { 1660 PnvChip *chip = PNV_CHIP(chip10); 1661 int i; 1662 1663 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1664 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1665 1666 for (i = 0; i < chip10->nr_quads; i++) { 1667 PnvQuad *eq = &chip10->quads[i]; 1668 1669 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1670 1671 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1672 &eq->xscom_regs); 1673 } 1674 } 1675 1676 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1677 { 1678 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1679 int i; 1680 1681 for (i = 0; i < chip->num_pecs; i++) { 1682 PnvPhb4PecState *pec = &chip10->pecs[i]; 1683 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1684 uint32_t pec_nest_base; 1685 uint32_t pec_pci_base; 1686 1687 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1688 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1689 &error_fatal); 1690 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1691 &error_fatal); 1692 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1693 return; 1694 } 1695 1696 pec_nest_base = pecc->xscom_nest_base(pec); 1697 pec_pci_base = pecc->xscom_pci_base(pec); 1698 1699 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1700 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1701 } 1702 } 1703 1704 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1705 { 1706 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1707 PnvChip *chip = PNV_CHIP(dev); 1708 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1709 Error *local_err = NULL; 1710 1711 /* XSCOM bridge is first */ 1712 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1713 if (local_err) { 1714 error_propagate(errp, local_err); 1715 return; 1716 } 1717 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1718 1719 pcc->parent_realize(dev, &local_err); 1720 if (local_err) { 1721 error_propagate(errp, local_err); 1722 return; 1723 } 1724 1725 pnv_chip_power10_quad_realize(chip10, &local_err); 1726 if (local_err) { 1727 error_propagate(errp, local_err); 1728 return; 1729 } 1730 1731 /* XIVE2 interrupt controller (POWER10) */ 1732 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1733 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1734 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1735 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1736 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1737 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1738 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1739 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1740 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1741 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1742 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1743 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1744 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1745 &error_abort); 1746 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1747 return; 1748 } 1749 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1750 &chip10->xive.xscom_regs); 1751 1752 /* Processor Service Interface (PSI) Host Bridge */ 1753 object_property_set_int(OBJECT(&chip10->psi), "bar", 1754 PNV10_PSIHB_BASE(chip), &error_fatal); 1755 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1756 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1757 &error_fatal); 1758 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1759 return; 1760 } 1761 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1762 &PNV_PSI(&chip10->psi)->xscom_regs); 1763 1764 /* LPC */ 1765 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1766 return; 1767 } 1768 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1769 &chip10->lpc.xscom_regs); 1770 1771 chip->fw_mr = &chip10->lpc.isa_fw; 1772 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1773 (uint64_t) PNV10_LPCM_BASE(chip)); 1774 1775 /* Create the simplified OCC model */ 1776 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1777 return; 1778 } 1779 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1780 &chip10->occ.xscom_regs); 1781 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1782 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1783 1784 /* OCC SRAM model */ 1785 memory_region_add_subregion(get_system_memory(), 1786 PNV10_OCC_SENSOR_BASE(chip), 1787 &chip10->occ.sram_regs); 1788 1789 /* SBE */ 1790 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1791 return; 1792 } 1793 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1794 &chip10->sbe.xscom_ctrl_regs); 1795 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 1796 &chip10->sbe.xscom_mbox_regs); 1797 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 1798 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 1799 1800 /* HOMER */ 1801 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1802 &error_abort); 1803 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1804 return; 1805 } 1806 /* Homer Xscom region */ 1807 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1808 &chip10->homer.pba_regs); 1809 1810 /* Homer mmio region */ 1811 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1812 &chip10->homer.regs); 1813 1814 /* PHBs */ 1815 pnv_chip_power10_phb_realize(chip, &local_err); 1816 if (local_err) { 1817 error_propagate(errp, local_err); 1818 return; 1819 } 1820 } 1821 1822 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1823 { 1824 addr &= (PNV10_XSCOM_SIZE - 1); 1825 return addr >> 3; 1826 } 1827 1828 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1829 { 1830 DeviceClass *dc = DEVICE_CLASS(klass); 1831 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1832 1833 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1834 k->cores_mask = POWER10_CORE_MASK; 1835 k->core_pir = pnv_chip_core_pir_p10; 1836 k->intc_create = pnv_chip_power10_intc_create; 1837 k->intc_reset = pnv_chip_power10_intc_reset; 1838 k->intc_destroy = pnv_chip_power10_intc_destroy; 1839 k->intc_print_info = pnv_chip_power10_intc_print_info; 1840 k->isa_create = pnv_chip_power10_isa_create; 1841 k->dt_populate = pnv_chip_power10_dt_populate; 1842 k->pic_print_info = pnv_chip_power10_pic_print_info; 1843 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1844 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1845 dc->desc = "PowerNV Chip POWER10"; 1846 k->num_pecs = PNV10_CHIP_MAX_PEC; 1847 1848 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1849 &k->parent_realize); 1850 } 1851 1852 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1853 { 1854 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1855 int cores_max; 1856 1857 /* 1858 * No custom mask for this chip, let's use the default one from * 1859 * the chip class 1860 */ 1861 if (!chip->cores_mask) { 1862 chip->cores_mask = pcc->cores_mask; 1863 } 1864 1865 /* filter alien core ids ! some are reserved */ 1866 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1867 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1868 chip->cores_mask); 1869 return; 1870 } 1871 chip->cores_mask &= pcc->cores_mask; 1872 1873 /* now that we have a sane layout, let check the number of cores */ 1874 cores_max = ctpop64(chip->cores_mask); 1875 if (chip->nr_cores > cores_max) { 1876 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1877 cores_max); 1878 return; 1879 } 1880 } 1881 1882 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1883 { 1884 Error *error = NULL; 1885 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1886 const char *typename = pnv_chip_core_typename(chip); 1887 int i, core_hwid; 1888 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1889 1890 if (!object_class_by_name(typename)) { 1891 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1892 return; 1893 } 1894 1895 /* Cores */ 1896 pnv_chip_core_sanitize(chip, &error); 1897 if (error) { 1898 error_propagate(errp, error); 1899 return; 1900 } 1901 1902 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1903 1904 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1905 && (i < chip->nr_cores); core_hwid++) { 1906 char core_name[32]; 1907 PnvCore *pnv_core; 1908 uint64_t xscom_core_base; 1909 1910 if (!(chip->cores_mask & (1ull << core_hwid))) { 1911 continue; 1912 } 1913 1914 pnv_core = PNV_CORE(object_new(typename)); 1915 1916 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1917 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1918 chip->cores[i] = pnv_core; 1919 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1920 chip->nr_threads, &error_fatal); 1921 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1922 core_hwid, &error_fatal); 1923 object_property_set_int(OBJECT(pnv_core), "pir", 1924 pcc->core_pir(chip, core_hwid), &error_fatal); 1925 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1926 &error_fatal); 1927 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1928 &error_abort); 1929 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1930 1931 /* Each core has an XSCOM MMIO region */ 1932 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1933 1934 pnv_xscom_add_subregion(chip, xscom_core_base, 1935 &pnv_core->xscom_regs); 1936 i++; 1937 } 1938 } 1939 1940 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1941 { 1942 PnvChip *chip = PNV_CHIP(dev); 1943 Error *error = NULL; 1944 1945 /* Cores */ 1946 pnv_chip_core_realize(chip, &error); 1947 if (error) { 1948 error_propagate(errp, error); 1949 return; 1950 } 1951 } 1952 1953 static Property pnv_chip_properties[] = { 1954 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1955 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1956 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1957 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1958 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1959 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1960 DEFINE_PROP_END_OF_LIST(), 1961 }; 1962 1963 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1964 { 1965 DeviceClass *dc = DEVICE_CLASS(klass); 1966 1967 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1968 dc->realize = pnv_chip_realize; 1969 device_class_set_props(dc, pnv_chip_properties); 1970 dc->desc = "PowerNV Chip"; 1971 } 1972 1973 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1974 { 1975 int i, j; 1976 1977 for (i = 0; i < chip->nr_cores; i++) { 1978 PnvCore *pc = chip->cores[i]; 1979 CPUCore *cc = CPU_CORE(pc); 1980 1981 for (j = 0; j < cc->nr_threads; j++) { 1982 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1983 return pc->threads[j]; 1984 } 1985 } 1986 } 1987 return NULL; 1988 } 1989 1990 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1991 { 1992 PnvMachineState *pnv = PNV_MACHINE(xi); 1993 int i, j; 1994 1995 for (i = 0; i < pnv->num_chips; i++) { 1996 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1997 1998 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1999 return &chip8->psi.ics; 2000 } 2001 2002 for (j = 0; j < chip8->num_phbs; j++) { 2003 PnvPHB *phb = chip8->phbs[j]; 2004 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2005 2006 if (ics_valid_irq(&phb3->lsis, irq)) { 2007 return &phb3->lsis; 2008 } 2009 2010 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2011 return ICS(&phb3->msis); 2012 } 2013 } 2014 } 2015 return NULL; 2016 } 2017 2018 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2019 { 2020 int i; 2021 2022 for (i = 0; i < pnv->num_chips; i++) { 2023 PnvChip *chip = pnv->chips[i]; 2024 if (chip->chip_id == chip_id) { 2025 return chip; 2026 } 2027 } 2028 return NULL; 2029 } 2030 2031 static void pnv_ics_resend(XICSFabric *xi) 2032 { 2033 PnvMachineState *pnv = PNV_MACHINE(xi); 2034 int i, j; 2035 2036 for (i = 0; i < pnv->num_chips; i++) { 2037 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2038 2039 ics_resend(&chip8->psi.ics); 2040 2041 for (j = 0; j < chip8->num_phbs; j++) { 2042 PnvPHB *phb = chip8->phbs[j]; 2043 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2044 2045 ics_resend(&phb3->lsis); 2046 ics_resend(ICS(&phb3->msis)); 2047 } 2048 } 2049 } 2050 2051 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2052 { 2053 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2054 2055 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2056 } 2057 2058 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2059 Monitor *mon) 2060 { 2061 PnvMachineState *pnv = PNV_MACHINE(obj); 2062 int i; 2063 CPUState *cs; 2064 2065 CPU_FOREACH(cs) { 2066 PowerPCCPU *cpu = POWERPC_CPU(cs); 2067 2068 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2069 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2070 mon); 2071 } 2072 2073 for (i = 0; i < pnv->num_chips; i++) { 2074 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2075 } 2076 } 2077 2078 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2079 uint8_t nvt_blk, uint32_t nvt_idx, 2080 bool cam_ignore, uint8_t priority, 2081 uint32_t logic_serv, 2082 XiveTCTXMatch *match) 2083 { 2084 PnvMachineState *pnv = PNV_MACHINE(xfb); 2085 int total_count = 0; 2086 int i; 2087 2088 for (i = 0; i < pnv->num_chips; i++) { 2089 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2090 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2091 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2092 int count; 2093 2094 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2095 priority, logic_serv, match); 2096 2097 if (count < 0) { 2098 return count; 2099 } 2100 2101 total_count += count; 2102 } 2103 2104 return total_count; 2105 } 2106 2107 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2108 uint8_t nvt_blk, uint32_t nvt_idx, 2109 bool cam_ignore, uint8_t priority, 2110 uint32_t logic_serv, 2111 XiveTCTXMatch *match) 2112 { 2113 PnvMachineState *pnv = PNV_MACHINE(xfb); 2114 int total_count = 0; 2115 int i; 2116 2117 for (i = 0; i < pnv->num_chips; i++) { 2118 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2119 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2120 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2121 int count; 2122 2123 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2124 priority, logic_serv, match); 2125 2126 if (count < 0) { 2127 return count; 2128 } 2129 2130 total_count += count; 2131 } 2132 2133 return total_count; 2134 } 2135 2136 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2137 { 2138 MachineClass *mc = MACHINE_CLASS(oc); 2139 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2140 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2141 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2142 2143 static GlobalProperty phb_compat[] = { 2144 { TYPE_PNV_PHB, "version", "3" }, 2145 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2146 }; 2147 2148 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2149 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2150 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2151 2152 xic->icp_get = pnv_icp_get; 2153 xic->ics_get = pnv_ics_get; 2154 xic->ics_resend = pnv_ics_resend; 2155 2156 pmc->compat = compat; 2157 pmc->compat_size = sizeof(compat); 2158 2159 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2160 } 2161 2162 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2163 { 2164 MachineClass *mc = MACHINE_CLASS(oc); 2165 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2166 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2167 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2168 2169 static GlobalProperty phb_compat[] = { 2170 { TYPE_PNV_PHB, "version", "4" }, 2171 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2172 }; 2173 2174 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2175 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2176 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2177 2178 xfc->match_nvt = pnv_match_nvt; 2179 2180 mc->alias = "powernv"; 2181 2182 pmc->compat = compat; 2183 pmc->compat_size = sizeof(compat); 2184 pmc->dt_power_mgt = pnv_dt_power_mgt; 2185 2186 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2187 } 2188 2189 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2190 { 2191 MachineClass *mc = MACHINE_CLASS(oc); 2192 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2193 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2194 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2195 2196 static GlobalProperty phb_compat[] = { 2197 { TYPE_PNV_PHB, "version", "5" }, 2198 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2199 }; 2200 2201 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2202 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2203 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2204 2205 pmc->compat = compat; 2206 pmc->compat_size = sizeof(compat); 2207 pmc->dt_power_mgt = pnv_dt_power_mgt; 2208 2209 xfc->match_nvt = pnv10_xive_match_nvt; 2210 2211 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2212 } 2213 2214 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2215 { 2216 PnvMachineState *pnv = PNV_MACHINE(obj); 2217 2218 return !!pnv->fw_load_addr; 2219 } 2220 2221 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2222 { 2223 PnvMachineState *pnv = PNV_MACHINE(obj); 2224 2225 if (value) { 2226 pnv->fw_load_addr = 0x8000000; 2227 } 2228 } 2229 2230 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2231 { 2232 PowerPCCPU *cpu = POWERPC_CPU(cs); 2233 CPUPPCState *env = &cpu->env; 2234 2235 cpu_synchronize_state(cs); 2236 ppc_cpu_do_system_reset(cs); 2237 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2238 /* 2239 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2240 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2241 * (PPC_BIT(43)). 2242 */ 2243 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2244 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2245 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2246 } 2247 } else { 2248 /* 2249 * For non-powersave system resets, SRR1[42:45] are defined to be 2250 * implementation-dependent. The POWER9 User Manual specifies that 2251 * an external (SCOM driven, which may come from a BMC nmi command or 2252 * another CPU requesting a NMI IPI) system reset exception should be 2253 * 0b0010 (PPC_BIT(44)). 2254 */ 2255 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2256 } 2257 } 2258 2259 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2260 { 2261 CPUState *cs; 2262 2263 CPU_FOREACH(cs) { 2264 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2265 } 2266 } 2267 2268 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2269 { 2270 MachineClass *mc = MACHINE_CLASS(oc); 2271 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2272 NMIClass *nc = NMI_CLASS(oc); 2273 2274 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2275 mc->init = pnv_init; 2276 mc->reset = pnv_reset; 2277 mc->max_cpus = MAX_CPUS; 2278 /* Pnv provides a AHCI device for storage */ 2279 mc->block_default_type = IF_IDE; 2280 mc->no_parallel = 1; 2281 mc->default_boot_order = NULL; 2282 /* 2283 * RAM defaults to less than 2048 for 32-bit hosts, and large 2284 * enough to fit the maximum initrd size at it's load address 2285 */ 2286 mc->default_ram_size = 1 * GiB; 2287 mc->default_ram_id = "pnv.ram"; 2288 ispc->print_info = pnv_pic_print_info; 2289 nc->nmi_monitor_handler = pnv_nmi; 2290 2291 object_class_property_add_bool(oc, "hb-mode", 2292 pnv_machine_get_hb, pnv_machine_set_hb); 2293 object_class_property_set_description(oc, "hb-mode", 2294 "Use a hostboot like boot loader"); 2295 } 2296 2297 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2298 { \ 2299 .name = type, \ 2300 .class_init = class_initfn, \ 2301 .parent = TYPE_PNV8_CHIP, \ 2302 } 2303 2304 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2305 { \ 2306 .name = type, \ 2307 .class_init = class_initfn, \ 2308 .parent = TYPE_PNV9_CHIP, \ 2309 } 2310 2311 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2312 { \ 2313 .name = type, \ 2314 .class_init = class_initfn, \ 2315 .parent = TYPE_PNV10_CHIP, \ 2316 } 2317 2318 static const TypeInfo types[] = { 2319 { 2320 .name = MACHINE_TYPE_NAME("powernv10"), 2321 .parent = TYPE_PNV_MACHINE, 2322 .class_init = pnv_machine_power10_class_init, 2323 .interfaces = (InterfaceInfo[]) { 2324 { TYPE_XIVE_FABRIC }, 2325 { }, 2326 }, 2327 }, 2328 { 2329 .name = MACHINE_TYPE_NAME("powernv9"), 2330 .parent = TYPE_PNV_MACHINE, 2331 .class_init = pnv_machine_power9_class_init, 2332 .interfaces = (InterfaceInfo[]) { 2333 { TYPE_XIVE_FABRIC }, 2334 { }, 2335 }, 2336 }, 2337 { 2338 .name = MACHINE_TYPE_NAME("powernv8"), 2339 .parent = TYPE_PNV_MACHINE, 2340 .class_init = pnv_machine_power8_class_init, 2341 .interfaces = (InterfaceInfo[]) { 2342 { TYPE_XICS_FABRIC }, 2343 { }, 2344 }, 2345 }, 2346 { 2347 .name = TYPE_PNV_MACHINE, 2348 .parent = TYPE_MACHINE, 2349 .abstract = true, 2350 .instance_size = sizeof(PnvMachineState), 2351 .class_init = pnv_machine_class_init, 2352 .class_size = sizeof(PnvMachineClass), 2353 .interfaces = (InterfaceInfo[]) { 2354 { TYPE_INTERRUPT_STATS_PROVIDER }, 2355 { TYPE_NMI }, 2356 { }, 2357 }, 2358 }, 2359 { 2360 .name = TYPE_PNV_CHIP, 2361 .parent = TYPE_SYS_BUS_DEVICE, 2362 .class_init = pnv_chip_class_init, 2363 .instance_size = sizeof(PnvChip), 2364 .class_size = sizeof(PnvChipClass), 2365 .abstract = true, 2366 }, 2367 2368 /* 2369 * P10 chip and variants 2370 */ 2371 { 2372 .name = TYPE_PNV10_CHIP, 2373 .parent = TYPE_PNV_CHIP, 2374 .instance_init = pnv_chip_power10_instance_init, 2375 .instance_size = sizeof(Pnv10Chip), 2376 }, 2377 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2378 2379 /* 2380 * P9 chip and variants 2381 */ 2382 { 2383 .name = TYPE_PNV9_CHIP, 2384 .parent = TYPE_PNV_CHIP, 2385 .instance_init = pnv_chip_power9_instance_init, 2386 .instance_size = sizeof(Pnv9Chip), 2387 }, 2388 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2389 2390 /* 2391 * P8 chip and variants 2392 */ 2393 { 2394 .name = TYPE_PNV8_CHIP, 2395 .parent = TYPE_PNV_CHIP, 2396 .instance_init = pnv_chip_power8_instance_init, 2397 .instance_size = sizeof(Pnv8Chip), 2398 }, 2399 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2400 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2401 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2402 pnv_chip_power8nvl_class_init), 2403 }; 2404 2405 DEFINE_TYPES(types) 2406