1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci-host/pnv_phb.h" 47 #include "hw/pci-host/pnv_phb3.h" 48 #include "hw/pci-host/pnv_phb4.h" 49 50 #include "hw/ppc/xics.h" 51 #include "hw/qdev-properties.h" 52 #include "hw/ppc/pnv_chip.h" 53 #include "hw/ppc/pnv_xscom.h" 54 #include "hw/ppc/pnv_pnor.h" 55 56 #include "hw/isa/isa.h" 57 #include "hw/char/serial.h" 58 #include "hw/rtc/mc146818rtc.h" 59 60 #include <libfdt.h> 61 62 #define FDT_MAX_SIZE (1 * MiB) 63 64 #define FW_FILE_NAME "skiboot.lid" 65 #define FW_LOAD_ADDR 0x0 66 #define FW_MAX_SIZE (16 * MiB) 67 68 #define KERNEL_LOAD_ADDR 0x20000000 69 #define KERNEL_MAX_SIZE (128 * MiB) 70 #define INITRD_LOAD_ADDR 0x28000000 71 #define INITRD_MAX_SIZE (128 * MiB) 72 73 static const char *pnv_chip_core_typename(const PnvChip *o) 74 { 75 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 76 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 77 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 78 const char *core_type = object_class_get_name(object_class_by_name(s)); 79 g_free(s); 80 return core_type; 81 } 82 83 /* 84 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 85 * 4 * 4 sockets * 12 cores * 8 threads = 1536 86 * Let's make it 2^11 87 */ 88 #define MAX_CPUS 2048 89 90 /* 91 * Memory nodes are created by hostboot, one for each range of memory 92 * that has a different "affinity". In practice, it means one range 93 * per chip. 94 */ 95 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 96 { 97 char *mem_name; 98 uint64_t mem_reg_property[2]; 99 int off; 100 101 mem_reg_property[0] = cpu_to_be64(start); 102 mem_reg_property[1] = cpu_to_be64(size); 103 104 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 105 off = fdt_add_subnode(fdt, 0, mem_name); 106 g_free(mem_name); 107 108 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 109 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 110 sizeof(mem_reg_property)))); 111 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 112 } 113 114 static int get_cpus_node(void *fdt) 115 { 116 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 117 118 if (cpus_offset < 0) { 119 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 120 if (cpus_offset) { 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 123 } 124 } 125 _FDT(cpus_offset); 126 return cpus_offset; 127 } 128 129 /* 130 * The PowerNV cores (and threads) need to use real HW ids and not an 131 * incremental index like it has been done on other platforms. This HW 132 * id is stored in the CPU PIR, it is used to create cpu nodes in the 133 * device tree, used in XSCOM to address cores and in interrupt 134 * servers. 135 */ 136 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 137 { 138 PowerPCCPU *cpu = pc->threads[0]; 139 CPUState *cs = CPU(cpu); 140 DeviceClass *dc = DEVICE_GET_CLASS(cs); 141 int smt_threads = CPU_CORE(pc)->nr_threads; 142 CPUPPCState *env = &cpu->env; 143 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 145 int i; 146 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 147 0xffffffff, 0xffffffff}; 148 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 149 uint32_t cpufreq = 1000000000; 150 uint32_t page_sizes_prop[64]; 151 size_t page_sizes_prop_size; 152 const uint8_t pa_features[] = { 24, 0, 153 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 154 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 155 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 156 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 157 int offset; 158 char *nodename; 159 int cpus_offset = get_cpus_node(fdt); 160 161 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 162 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 163 _FDT(offset); 164 g_free(nodename); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 170 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 171 172 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 176 env->dcache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 178 env->icache_line_size))); 179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 180 env->icache_line_size))); 181 182 if (pcc->l1_dcache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 184 pcc->l1_dcache_size))); 185 } else { 186 warn_report("Unknown L1 dcache size for cpu"); 187 } 188 if (pcc->l1_icache_size) { 189 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 190 pcc->l1_icache_size))); 191 } else { 192 warn_report("Unknown L1 icache size for cpu"); 193 } 194 195 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 196 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 198 cpu->hash64_opts->slb_size))); 199 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 200 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 201 202 if (ppc_has_spr(cpu, SPR_PURR)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 204 } 205 206 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 207 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 208 segs, sizeof(segs)))); 209 } 210 211 /* 212 * Advertise VMX/VSX (vector extensions) if available 213 * 0 / no property == no vector extensions 214 * 1 == VMX / Altivec available 215 * 2 == VSX available 216 */ 217 if (env->insns_flags & PPC_ALTIVEC) { 218 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 219 220 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 221 } 222 223 /* 224 * Advertise DFP (Decimal Floating Point) if available 225 * 0 / no property == no DFP 226 * 1 == DFP available 227 */ 228 if (env->insns_flags2 & PPC2_DFP) { 229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 230 } 231 232 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 233 sizeof(page_sizes_prop)); 234 if (page_sizes_prop_size) { 235 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 236 page_sizes_prop, page_sizes_prop_size))); 237 } 238 239 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 240 pa_features, sizeof(pa_features)))); 241 242 /* Build interrupt servers properties */ 243 for (i = 0; i < smt_threads; i++) { 244 servers_prop[i] = cpu_to_be32(pc->pir + i); 245 } 246 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 247 servers_prop, sizeof(*servers_prop) * smt_threads))); 248 } 249 250 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 251 uint32_t nr_threads) 252 { 253 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 254 char *name; 255 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 256 uint32_t irange[2], i, rsize; 257 uint64_t *reg; 258 int offset; 259 260 irange[0] = cpu_to_be32(pir); 261 irange[1] = cpu_to_be32(nr_threads); 262 263 rsize = sizeof(uint64_t) * 2 * nr_threads; 264 reg = g_malloc(rsize); 265 for (i = 0; i < nr_threads; i++) { 266 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 267 reg[i * 2 + 1] = cpu_to_be64(0x1000); 268 } 269 270 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 271 offset = fdt_add_subnode(fdt, 0, name); 272 _FDT(offset); 273 g_free(name); 274 275 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 276 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 277 _FDT((fdt_setprop_string(fdt, offset, "device_type", 278 "PowerPC-External-Interrupt-Presentation"))); 279 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 280 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 281 irange, sizeof(irange)))); 282 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 283 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 284 g_free(reg); 285 } 286 287 /* 288 * Adds a PnvPHB to the chip on P8. 289 * Implemented here, like for defaults PHBs 290 */ 291 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 292 { 293 Pnv8Chip *chip8 = PNV8_CHIP(chip); 294 295 phb->chip = chip; 296 297 chip8->phbs[chip8->num_phbs] = phb; 298 chip8->num_phbs++; 299 return chip; 300 } 301 302 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 303 { 304 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 305 int i; 306 307 pnv_dt_xscom(chip, fdt, 0, 308 cpu_to_be64(PNV_XSCOM_BASE(chip)), 309 cpu_to_be64(PNV_XSCOM_SIZE), 310 compat, sizeof(compat)); 311 312 for (i = 0; i < chip->nr_cores; i++) { 313 PnvCore *pnv_core = chip->cores[i]; 314 315 pnv_dt_core(chip, pnv_core, fdt); 316 317 /* Interrupt Control Presenters (ICP). One per core. */ 318 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 319 } 320 321 if (chip->ram_size) { 322 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 323 } 324 } 325 326 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 327 { 328 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 329 int i; 330 331 pnv_dt_xscom(chip, fdt, 0, 332 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 333 cpu_to_be64(PNV9_XSCOM_SIZE), 334 compat, sizeof(compat)); 335 336 for (i = 0; i < chip->nr_cores; i++) { 337 PnvCore *pnv_core = chip->cores[i]; 338 339 pnv_dt_core(chip, pnv_core, fdt); 340 } 341 342 if (chip->ram_size) { 343 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 344 } 345 346 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 347 } 348 349 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 350 { 351 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 352 int i; 353 354 pnv_dt_xscom(chip, fdt, 0, 355 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 356 cpu_to_be64(PNV10_XSCOM_SIZE), 357 compat, sizeof(compat)); 358 359 for (i = 0; i < chip->nr_cores; i++) { 360 PnvCore *pnv_core = chip->cores[i]; 361 362 pnv_dt_core(chip, pnv_core, fdt); 363 } 364 365 if (chip->ram_size) { 366 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 367 } 368 369 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 370 } 371 372 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 373 { 374 uint32_t io_base = d->ioport_id; 375 uint32_t io_regs[] = { 376 cpu_to_be32(1), 377 cpu_to_be32(io_base), 378 cpu_to_be32(2) 379 }; 380 char *name; 381 int node; 382 383 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 384 node = fdt_add_subnode(fdt, lpc_off, name); 385 _FDT(node); 386 g_free(name); 387 388 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 389 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 390 } 391 392 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 393 { 394 const char compatible[] = "ns16550\0pnpPNP,501"; 395 uint32_t io_base = d->ioport_id; 396 uint32_t io_regs[] = { 397 cpu_to_be32(1), 398 cpu_to_be32(io_base), 399 cpu_to_be32(8) 400 }; 401 uint32_t irq; 402 char *name; 403 int node; 404 405 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 406 407 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 408 node = fdt_add_subnode(fdt, lpc_off, name); 409 _FDT(node); 410 g_free(name); 411 412 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 413 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 414 sizeof(compatible)))); 415 416 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 417 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 418 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 419 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 420 fdt_get_phandle(fdt, lpc_off)))); 421 422 /* This is needed by Linux */ 423 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 424 } 425 426 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 427 { 428 const char compatible[] = "bt\0ipmi-bt"; 429 uint32_t io_base; 430 uint32_t io_regs[] = { 431 cpu_to_be32(1), 432 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 433 cpu_to_be32(3) 434 }; 435 uint32_t irq; 436 char *name; 437 int node; 438 439 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 440 io_regs[1] = cpu_to_be32(io_base); 441 442 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 443 444 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 445 node = fdt_add_subnode(fdt, lpc_off, name); 446 _FDT(node); 447 g_free(name); 448 449 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 450 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 451 sizeof(compatible)))); 452 453 /* Mark it as reserved to avoid Linux trying to claim it */ 454 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 455 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 456 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 457 fdt_get_phandle(fdt, lpc_off)))); 458 } 459 460 typedef struct ForeachPopulateArgs { 461 void *fdt; 462 int offset; 463 } ForeachPopulateArgs; 464 465 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 466 { 467 ForeachPopulateArgs *args = opaque; 468 ISADevice *d = ISA_DEVICE(dev); 469 470 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 471 pnv_dt_rtc(d, args->fdt, args->offset); 472 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 473 pnv_dt_serial(d, args->fdt, args->offset); 474 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 475 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 476 } else { 477 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 478 d->ioport_id); 479 } 480 481 return 0; 482 } 483 484 /* 485 * The default LPC bus of a multichip system is on chip 0. It's 486 * recognized by the firmware (skiboot) using a "primary" property. 487 */ 488 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 489 { 490 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 491 ForeachPopulateArgs args = { 492 .fdt = fdt, 493 .offset = isa_offset, 494 }; 495 uint32_t phandle; 496 497 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 498 499 phandle = qemu_fdt_alloc_phandle(fdt); 500 assert(phandle > 0); 501 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 502 503 /* 504 * ISA devices are not necessarily parented to the ISA bus so we 505 * can not use object_child_foreach() 506 */ 507 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 508 &args); 509 } 510 511 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 512 { 513 int off; 514 515 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 516 off = fdt_add_subnode(fdt, off, "power-mgt"); 517 518 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 519 } 520 521 static void *pnv_dt_create(MachineState *machine) 522 { 523 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 524 PnvMachineState *pnv = PNV_MACHINE(machine); 525 void *fdt; 526 char *buf; 527 int off; 528 int i; 529 530 fdt = g_malloc0(FDT_MAX_SIZE); 531 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 532 533 /* /qemu node */ 534 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 535 536 /* Root node */ 537 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 538 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 539 _FDT((fdt_setprop_string(fdt, 0, "model", 540 "IBM PowerNV (emulated by qemu)"))); 541 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 542 543 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 544 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 545 if (qemu_uuid_set) { 546 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 547 } 548 g_free(buf); 549 550 off = fdt_add_subnode(fdt, 0, "chosen"); 551 if (machine->kernel_cmdline) { 552 _FDT((fdt_setprop_string(fdt, off, "bootargs", 553 machine->kernel_cmdline))); 554 } 555 556 if (pnv->initrd_size) { 557 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 558 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 559 560 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 561 &start_prop, sizeof(start_prop)))); 562 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 563 &end_prop, sizeof(end_prop)))); 564 } 565 566 /* Populate device tree for each chip */ 567 for (i = 0; i < pnv->num_chips; i++) { 568 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 569 } 570 571 /* Populate ISA devices on chip 0 */ 572 pnv_dt_isa(pnv, fdt); 573 574 if (pnv->bmc) { 575 pnv_dt_bmc_sensors(pnv->bmc, fdt); 576 } 577 578 /* Create an extra node for power management on machines that support it */ 579 if (pmc->dt_power_mgt) { 580 pmc->dt_power_mgt(pnv, fdt); 581 } 582 583 return fdt; 584 } 585 586 static void pnv_powerdown_notify(Notifier *n, void *opaque) 587 { 588 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 589 590 if (pnv->bmc) { 591 pnv_bmc_powerdown(pnv->bmc); 592 } 593 } 594 595 static void pnv_reset(MachineState *machine, ShutdownCause reason) 596 { 597 PnvMachineState *pnv = PNV_MACHINE(machine); 598 IPMIBmc *bmc; 599 void *fdt; 600 601 qemu_devices_reset(reason); 602 603 /* 604 * The machine should provide by default an internal BMC simulator. 605 * If not, try to use the BMC device that was provided on the command 606 * line. 607 */ 608 bmc = pnv_bmc_find(&error_fatal); 609 if (!pnv->bmc) { 610 if (!bmc) { 611 if (!qtest_enabled()) { 612 warn_report("machine has no BMC device. Use '-device " 613 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 614 "to define one"); 615 } 616 } else { 617 pnv_bmc_set_pnor(bmc, pnv->pnor); 618 pnv->bmc = bmc; 619 } 620 } 621 622 fdt = pnv_dt_create(machine); 623 624 /* Pack resulting tree */ 625 _FDT((fdt_pack(fdt))); 626 627 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 628 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 629 630 /* 631 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 632 * the existing machine->fdt to avoid leaking it during 633 * a reset. 634 */ 635 g_free(machine->fdt); 636 machine->fdt = fdt; 637 } 638 639 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 640 { 641 Pnv8Chip *chip8 = PNV8_CHIP(chip); 642 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 643 644 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 645 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 646 } 647 648 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 649 { 650 Pnv8Chip *chip8 = PNV8_CHIP(chip); 651 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 652 653 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 654 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 655 } 656 657 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 658 { 659 Pnv9Chip *chip9 = PNV9_CHIP(chip); 660 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 661 662 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 663 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 664 } 665 666 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 667 { 668 Pnv10Chip *chip10 = PNV10_CHIP(chip); 669 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 670 671 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 672 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 673 } 674 675 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 676 { 677 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 678 } 679 680 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 681 { 682 Pnv8Chip *chip8 = PNV8_CHIP(chip); 683 int i; 684 685 ics_pic_print_info(&chip8->psi.ics, mon); 686 687 for (i = 0; i < chip8->num_phbs; i++) { 688 PnvPHB *phb = chip8->phbs[i]; 689 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 690 691 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 692 ics_pic_print_info(&phb3->lsis, mon); 693 } 694 } 695 696 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 697 { 698 Monitor *mon = opaque; 699 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 700 701 if (!phb) { 702 return 0; 703 } 704 705 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon); 706 707 return 0; 708 } 709 710 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 711 { 712 Pnv9Chip *chip9 = PNV9_CHIP(chip); 713 714 pnv_xive_pic_print_info(&chip9->xive, mon); 715 pnv_psi_pic_print_info(&chip9->psi, mon); 716 717 object_child_foreach_recursive(OBJECT(chip), 718 pnv_chip_power9_pic_print_info_child, mon); 719 } 720 721 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 722 uint32_t core_id) 723 { 724 return PNV_XSCOM_EX_BASE(core_id); 725 } 726 727 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 728 uint32_t core_id) 729 { 730 return PNV9_XSCOM_EC_BASE(core_id); 731 } 732 733 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 734 uint32_t core_id) 735 { 736 return PNV10_XSCOM_EC_BASE(core_id); 737 } 738 739 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 740 { 741 PowerPCCPUClass *ppc_default = 742 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 743 PowerPCCPUClass *ppc = 744 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 745 746 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 747 } 748 749 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 750 { 751 ISADevice *dev = isa_new("isa-ipmi-bt"); 752 753 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 754 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 755 isa_realize_and_unref(dev, bus, &error_fatal); 756 } 757 758 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 759 { 760 Pnv10Chip *chip10 = PNV10_CHIP(chip); 761 762 pnv_xive2_pic_print_info(&chip10->xive, mon); 763 pnv_psi_pic_print_info(&chip10->psi, mon); 764 765 object_child_foreach_recursive(OBJECT(chip), 766 pnv_chip_power9_pic_print_info_child, mon); 767 } 768 769 /* Always give the first 1GB to chip 0 else we won't boot */ 770 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 771 { 772 MachineState *machine = MACHINE(pnv); 773 uint64_t ram_per_chip; 774 775 assert(machine->ram_size >= 1 * GiB); 776 777 ram_per_chip = machine->ram_size / pnv->num_chips; 778 if (ram_per_chip >= 1 * GiB) { 779 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 780 } 781 782 assert(pnv->num_chips > 1); 783 784 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 785 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 786 } 787 788 static void pnv_init(MachineState *machine) 789 { 790 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 791 PnvMachineState *pnv = PNV_MACHINE(machine); 792 MachineClass *mc = MACHINE_GET_CLASS(machine); 793 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 794 char *fw_filename; 795 long fw_size; 796 uint64_t chip_ram_start = 0; 797 int i; 798 char *chip_typename; 799 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 800 DeviceState *dev; 801 802 if (kvm_enabled()) { 803 error_report("machine %s does not support the KVM accelerator", 804 mc->name); 805 exit(EXIT_FAILURE); 806 } 807 808 /* allocate RAM */ 809 if (machine->ram_size < mc->default_ram_size) { 810 char *sz = size_to_str(mc->default_ram_size); 811 error_report("Invalid RAM size, should be bigger than %s", sz); 812 g_free(sz); 813 exit(EXIT_FAILURE); 814 } 815 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 816 817 /* 818 * Create our simple PNOR device 819 */ 820 dev = qdev_new(TYPE_PNV_PNOR); 821 if (pnor) { 822 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 823 } 824 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 825 pnv->pnor = PNV_PNOR(dev); 826 827 /* load skiboot firmware */ 828 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 829 if (!fw_filename) { 830 error_report("Could not find OPAL firmware '%s'", bios_name); 831 exit(1); 832 } 833 834 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 835 if (fw_size < 0) { 836 error_report("Could not load OPAL firmware '%s'", fw_filename); 837 exit(1); 838 } 839 g_free(fw_filename); 840 841 /* load kernel */ 842 if (machine->kernel_filename) { 843 long kernel_size; 844 845 kernel_size = load_image_targphys(machine->kernel_filename, 846 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 847 if (kernel_size < 0) { 848 error_report("Could not load kernel '%s'", 849 machine->kernel_filename); 850 exit(1); 851 } 852 } 853 854 /* load initrd */ 855 if (machine->initrd_filename) { 856 pnv->initrd_base = INITRD_LOAD_ADDR; 857 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 858 pnv->initrd_base, INITRD_MAX_SIZE); 859 if (pnv->initrd_size < 0) { 860 error_report("Could not load initial ram disk '%s'", 861 machine->initrd_filename); 862 exit(1); 863 } 864 } 865 866 /* MSIs are supported on this platform */ 867 msi_nonbroken = true; 868 869 /* 870 * Check compatibility of the specified CPU with the machine 871 * default. 872 */ 873 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 874 error_report("invalid CPU model '%s' for %s machine", 875 machine->cpu_type, mc->name); 876 exit(1); 877 } 878 879 /* Create the processor chips */ 880 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 881 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 882 i, machine->cpu_type); 883 if (!object_class_by_name(chip_typename)) { 884 error_report("invalid chip model '%.*s' for %s machine", 885 i, machine->cpu_type, mc->name); 886 exit(1); 887 } 888 889 pnv->num_chips = 890 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 891 892 if (machine->smp.threads > 8) { 893 error_report("Cannot support more than 8 threads/core " 894 "on a powernv machine"); 895 exit(1); 896 } 897 if (!is_power_of_2(machine->smp.threads)) { 898 error_report("Cannot support %d threads/core on a powernv" 899 "machine because it must be a power of 2", 900 machine->smp.threads); 901 exit(1); 902 } 903 /* 904 * TODO: should we decide on how many chips we can create based 905 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 906 */ 907 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 908 error_report("invalid number of chips: '%d'", pnv->num_chips); 909 error_printf( 910 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 911 exit(1); 912 } 913 914 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 915 for (i = 0; i < pnv->num_chips; i++) { 916 char chip_name[32]; 917 Object *chip = OBJECT(qdev_new(chip_typename)); 918 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 919 920 pnv->chips[i] = PNV_CHIP(chip); 921 922 /* Distribute RAM among the chips */ 923 object_property_set_int(chip, "ram-start", chip_ram_start, 924 &error_fatal); 925 object_property_set_int(chip, "ram-size", chip_ram_size, 926 &error_fatal); 927 chip_ram_start += chip_ram_size; 928 929 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 930 object_property_add_child(OBJECT(pnv), chip_name, chip); 931 object_property_set_int(chip, "chip-id", i, &error_fatal); 932 object_property_set_int(chip, "nr-cores", machine->smp.cores, 933 &error_fatal); 934 object_property_set_int(chip, "nr-threads", machine->smp.threads, 935 &error_fatal); 936 /* 937 * The POWER8 machine use the XICS interrupt interface. 938 * Propagate the XICS fabric to the chip and its controllers. 939 */ 940 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 941 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 942 } 943 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 944 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 945 &error_abort); 946 } 947 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 948 } 949 g_free(chip_typename); 950 951 /* Instantiate ISA bus on chip 0 */ 952 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 953 954 /* Create serial port */ 955 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 956 957 /* Create an RTC ISA device too */ 958 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 959 960 /* 961 * Create the machine BMC simulator and the IPMI BT device for 962 * communication with the BMC 963 */ 964 if (defaults_enabled()) { 965 pnv->bmc = pnv_bmc_create(pnv->pnor); 966 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 967 } 968 969 /* 970 * The PNOR is mapped on the LPC FW address space by the BMC. 971 * Since we can not reach the remote BMC machine with LPC memops, 972 * map it always for now. 973 */ 974 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 975 &pnv->pnor->mmio); 976 977 /* 978 * OpenPOWER systems use a IPMI SEL Event message to notify the 979 * host to powerdown 980 */ 981 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 982 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 983 984 /* 985 * Create/Connect any machine-specific I2C devices 986 */ 987 if (pmc->i2c_init) { 988 pmc->i2c_init(pnv); 989 } 990 } 991 992 /* 993 * 0:21 Reserved - Read as zeros 994 * 22:24 Chip ID 995 * 25:28 Core number 996 * 29:31 Thread ID 997 */ 998 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 999 { 1000 return (chip->chip_id << 7) | (core_id << 3); 1001 } 1002 1003 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1004 Error **errp) 1005 { 1006 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1007 Error *local_err = NULL; 1008 Object *obj; 1009 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1010 1011 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1012 if (local_err) { 1013 error_propagate(errp, local_err); 1014 return; 1015 } 1016 1017 pnv_cpu->intc = obj; 1018 } 1019 1020 1021 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1022 { 1023 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1024 1025 icp_reset(ICP(pnv_cpu->intc)); 1026 } 1027 1028 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1029 { 1030 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1031 1032 icp_destroy(ICP(pnv_cpu->intc)); 1033 pnv_cpu->intc = NULL; 1034 } 1035 1036 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1037 Monitor *mon) 1038 { 1039 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1040 } 1041 1042 /* 1043 * 0:48 Reserved - Read as zeroes 1044 * 49:52 Node ID 1045 * 53:55 Chip ID 1046 * 56 Reserved - Read as zero 1047 * 57:61 Core number 1048 * 62:63 Thread ID 1049 * 1050 * We only care about the lower bits. uint32_t is fine for the moment. 1051 */ 1052 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 1053 { 1054 return (chip->chip_id << 8) | (core_id << 2); 1055 } 1056 1057 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1058 { 1059 return (chip->chip_id << 8) | (core_id << 2); 1060 } 1061 1062 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1063 Error **errp) 1064 { 1065 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1066 Error *local_err = NULL; 1067 Object *obj; 1068 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1069 1070 /* 1071 * The core creates its interrupt presenter but the XIVE interrupt 1072 * controller object is initialized afterwards. Hopefully, it's 1073 * only used at runtime. 1074 */ 1075 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1076 &local_err); 1077 if (local_err) { 1078 error_propagate(errp, local_err); 1079 return; 1080 } 1081 1082 pnv_cpu->intc = obj; 1083 } 1084 1085 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1086 { 1087 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1088 1089 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1090 } 1091 1092 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1093 { 1094 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1095 1096 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1097 pnv_cpu->intc = NULL; 1098 } 1099 1100 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1101 Monitor *mon) 1102 { 1103 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1104 } 1105 1106 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1107 Error **errp) 1108 { 1109 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1110 Error *local_err = NULL; 1111 Object *obj; 1112 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1113 1114 /* 1115 * The core creates its interrupt presenter but the XIVE2 interrupt 1116 * controller object is initialized afterwards. Hopefully, it's 1117 * only used at runtime. 1118 */ 1119 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1120 &local_err); 1121 if (local_err) { 1122 error_propagate(errp, local_err); 1123 return; 1124 } 1125 1126 pnv_cpu->intc = obj; 1127 } 1128 1129 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1130 { 1131 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1132 1133 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1134 } 1135 1136 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1137 { 1138 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1139 1140 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1141 pnv_cpu->intc = NULL; 1142 } 1143 1144 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1145 Monitor *mon) 1146 { 1147 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1148 } 1149 1150 /* 1151 * Allowed core identifiers on a POWER8 Processor Chip : 1152 * 1153 * <EX0 reserved> 1154 * EX1 - Venice only 1155 * EX2 - Venice only 1156 * EX3 - Venice only 1157 * EX4 1158 * EX5 1159 * EX6 1160 * <EX7,8 reserved> <reserved> 1161 * EX9 - Venice only 1162 * EX10 - Venice only 1163 * EX11 - Venice only 1164 * EX12 1165 * EX13 1166 * EX14 1167 * <EX15 reserved> 1168 */ 1169 #define POWER8E_CORE_MASK (0x7070ull) 1170 #define POWER8_CORE_MASK (0x7e7eull) 1171 1172 /* 1173 * POWER9 has 24 cores, ids starting at 0x0 1174 */ 1175 #define POWER9_CORE_MASK (0xffffffffffffffull) 1176 1177 1178 #define POWER10_CORE_MASK (0xffffffffffffffull) 1179 1180 static void pnv_chip_power8_instance_init(Object *obj) 1181 { 1182 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1183 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1184 int i; 1185 1186 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1187 (Object **)&chip8->xics, 1188 object_property_allow_set_link, 1189 OBJ_PROP_LINK_STRONG); 1190 1191 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1192 1193 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1194 1195 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1196 1197 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1198 1199 if (defaults_enabled()) { 1200 chip8->num_phbs = pcc->num_phbs; 1201 1202 for (i = 0; i < chip8->num_phbs; i++) { 1203 Object *phb = object_new(TYPE_PNV_PHB); 1204 1205 /* 1206 * We need the chip to parent the PHB to allow the DT 1207 * to build correctly (via pnv_xscom_dt()). 1208 * 1209 * TODO: the PHB should be parented by a PEC device that, at 1210 * this moment, is not modelled powernv8/phb3. 1211 */ 1212 object_property_add_child(obj, "phb[*]", phb); 1213 chip8->phbs[i] = PNV_PHB(phb); 1214 } 1215 } 1216 1217 } 1218 1219 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1220 { 1221 PnvChip *chip = PNV_CHIP(chip8); 1222 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1223 int i, j; 1224 char *name; 1225 1226 name = g_strdup_printf("icp-%x", chip->chip_id); 1227 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1228 g_free(name); 1229 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1230 &chip8->icp_mmio); 1231 1232 /* Map the ICP registers for each thread */ 1233 for (i = 0; i < chip->nr_cores; i++) { 1234 PnvCore *pnv_core = chip->cores[i]; 1235 int core_hwid = CPU_CORE(pnv_core)->core_id; 1236 1237 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1238 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1239 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1240 1241 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1242 &icp->mmio); 1243 } 1244 } 1245 } 1246 1247 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1248 { 1249 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1250 PnvChip *chip = PNV_CHIP(dev); 1251 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1252 Pnv8Psi *psi8 = &chip8->psi; 1253 Error *local_err = NULL; 1254 int i; 1255 1256 assert(chip8->xics); 1257 1258 /* XSCOM bridge is first */ 1259 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1260 1261 pcc->parent_realize(dev, &local_err); 1262 if (local_err) { 1263 error_propagate(errp, local_err); 1264 return; 1265 } 1266 1267 /* Processor Service Interface (PSI) Host Bridge */ 1268 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1269 &error_fatal); 1270 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1271 OBJECT(chip8->xics), &error_abort); 1272 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1273 return; 1274 } 1275 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1276 &PNV_PSI(psi8)->xscom_regs); 1277 1278 /* Create LPC controller */ 1279 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1280 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1281 1282 chip->fw_mr = &chip8->lpc.isa_fw; 1283 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1284 (uint64_t) PNV_XSCOM_BASE(chip), 1285 PNV_XSCOM_LPC_BASE); 1286 1287 /* 1288 * Interrupt Management Area. This is the memory region holding 1289 * all the Interrupt Control Presenter (ICP) registers 1290 */ 1291 pnv_chip_icp_realize(chip8, &local_err); 1292 if (local_err) { 1293 error_propagate(errp, local_err); 1294 return; 1295 } 1296 1297 /* Create the simplified OCC model */ 1298 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1299 return; 1300 } 1301 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1302 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1303 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); 1304 1305 /* OCC SRAM model */ 1306 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1307 &chip8->occ.sram_regs); 1308 1309 /* HOMER */ 1310 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1311 &error_abort); 1312 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1313 return; 1314 } 1315 /* Homer Xscom region */ 1316 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1317 1318 /* Homer mmio region */ 1319 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1320 &chip8->homer.regs); 1321 1322 /* PHB controllers */ 1323 for (i = 0; i < chip8->num_phbs; i++) { 1324 PnvPHB *phb = chip8->phbs[i]; 1325 1326 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1327 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1328 &error_fatal); 1329 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1330 &error_fatal); 1331 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1332 return; 1333 } 1334 } 1335 } 1336 1337 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1338 { 1339 addr &= (PNV_XSCOM_SIZE - 1); 1340 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1341 } 1342 1343 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1344 { 1345 DeviceClass *dc = DEVICE_CLASS(klass); 1346 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1347 1348 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1349 k->cores_mask = POWER8E_CORE_MASK; 1350 k->num_phbs = 3; 1351 k->core_pir = pnv_chip_core_pir_p8; 1352 k->intc_create = pnv_chip_power8_intc_create; 1353 k->intc_reset = pnv_chip_power8_intc_reset; 1354 k->intc_destroy = pnv_chip_power8_intc_destroy; 1355 k->intc_print_info = pnv_chip_power8_intc_print_info; 1356 k->isa_create = pnv_chip_power8_isa_create; 1357 k->dt_populate = pnv_chip_power8_dt_populate; 1358 k->pic_print_info = pnv_chip_power8_pic_print_info; 1359 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1360 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1361 dc->desc = "PowerNV Chip POWER8E"; 1362 1363 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1364 &k->parent_realize); 1365 } 1366 1367 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1368 { 1369 DeviceClass *dc = DEVICE_CLASS(klass); 1370 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1371 1372 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1373 k->cores_mask = POWER8_CORE_MASK; 1374 k->num_phbs = 3; 1375 k->core_pir = pnv_chip_core_pir_p8; 1376 k->intc_create = pnv_chip_power8_intc_create; 1377 k->intc_reset = pnv_chip_power8_intc_reset; 1378 k->intc_destroy = pnv_chip_power8_intc_destroy; 1379 k->intc_print_info = pnv_chip_power8_intc_print_info; 1380 k->isa_create = pnv_chip_power8_isa_create; 1381 k->dt_populate = pnv_chip_power8_dt_populate; 1382 k->pic_print_info = pnv_chip_power8_pic_print_info; 1383 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1384 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1385 dc->desc = "PowerNV Chip POWER8"; 1386 1387 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1388 &k->parent_realize); 1389 } 1390 1391 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1392 { 1393 DeviceClass *dc = DEVICE_CLASS(klass); 1394 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1395 1396 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1397 k->cores_mask = POWER8_CORE_MASK; 1398 k->num_phbs = 4; 1399 k->core_pir = pnv_chip_core_pir_p8; 1400 k->intc_create = pnv_chip_power8_intc_create; 1401 k->intc_reset = pnv_chip_power8_intc_reset; 1402 k->intc_destroy = pnv_chip_power8_intc_destroy; 1403 k->intc_print_info = pnv_chip_power8_intc_print_info; 1404 k->isa_create = pnv_chip_power8nvl_isa_create; 1405 k->dt_populate = pnv_chip_power8_dt_populate; 1406 k->pic_print_info = pnv_chip_power8_pic_print_info; 1407 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1408 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1409 dc->desc = "PowerNV Chip POWER8NVL"; 1410 1411 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1412 &k->parent_realize); 1413 } 1414 1415 static void pnv_chip_power9_instance_init(Object *obj) 1416 { 1417 PnvChip *chip = PNV_CHIP(obj); 1418 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1419 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1420 int i; 1421 1422 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1423 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1424 "xive-fabric"); 1425 1426 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1427 1428 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1429 1430 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1431 1432 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1433 1434 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1435 1436 /* Number of PECs is the chip default */ 1437 chip->num_pecs = pcc->num_pecs; 1438 1439 for (i = 0; i < chip->num_pecs; i++) { 1440 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1441 TYPE_PNV_PHB4_PEC); 1442 } 1443 1444 for (i = 0; i < pcc->i2c_num_engines; i++) { 1445 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1446 } 1447 } 1448 1449 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1450 PnvCore *pnv_core, 1451 const char *type) 1452 { 1453 char eq_name[32]; 1454 int core_id = CPU_CORE(pnv_core)->core_id; 1455 1456 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1457 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1458 sizeof(*eq), type, 1459 &error_fatal, NULL); 1460 1461 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1462 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1463 } 1464 1465 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1466 { 1467 PnvChip *chip = PNV_CHIP(chip9); 1468 int i; 1469 1470 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1471 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1472 1473 for (i = 0; i < chip9->nr_quads; i++) { 1474 PnvQuad *eq = &chip9->quads[i]; 1475 1476 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1477 PNV_QUAD_TYPE_NAME("power9")); 1478 1479 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1480 &eq->xscom_regs); 1481 } 1482 } 1483 1484 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1485 { 1486 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1487 int i; 1488 1489 for (i = 0; i < chip->num_pecs; i++) { 1490 PnvPhb4PecState *pec = &chip9->pecs[i]; 1491 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1492 uint32_t pec_nest_base; 1493 uint32_t pec_pci_base; 1494 1495 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1496 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1497 &error_fatal); 1498 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1499 &error_fatal); 1500 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1501 return; 1502 } 1503 1504 pec_nest_base = pecc->xscom_nest_base(pec); 1505 pec_pci_base = pecc->xscom_pci_base(pec); 1506 1507 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1508 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1509 } 1510 } 1511 1512 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1513 { 1514 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1515 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1516 PnvChip *chip = PNV_CHIP(dev); 1517 Pnv9Psi *psi9 = &chip9->psi; 1518 Error *local_err = NULL; 1519 int i; 1520 1521 /* XSCOM bridge is first */ 1522 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1523 1524 pcc->parent_realize(dev, &local_err); 1525 if (local_err) { 1526 error_propagate(errp, local_err); 1527 return; 1528 } 1529 1530 pnv_chip_quad_realize(chip9, &local_err); 1531 if (local_err) { 1532 error_propagate(errp, local_err); 1533 return; 1534 } 1535 1536 /* XIVE interrupt controller (POWER9) */ 1537 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1538 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1539 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1540 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1541 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1542 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1543 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1544 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1545 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1546 &error_abort); 1547 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1548 return; 1549 } 1550 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1551 &chip9->xive.xscom_regs); 1552 1553 /* Processor Service Interface (PSI) Host Bridge */ 1554 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1555 &error_fatal); 1556 /* This is the only device with 4k ESB pages */ 1557 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1558 &error_fatal); 1559 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1560 return; 1561 } 1562 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1563 &PNV_PSI(psi9)->xscom_regs); 1564 1565 /* LPC */ 1566 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1567 return; 1568 } 1569 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1570 &chip9->lpc.xscom_regs); 1571 1572 chip->fw_mr = &chip9->lpc.isa_fw; 1573 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1574 (uint64_t) PNV9_LPCM_BASE(chip)); 1575 1576 /* Create the simplified OCC model */ 1577 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1578 return; 1579 } 1580 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1581 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1582 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); 1583 1584 /* OCC SRAM model */ 1585 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1586 &chip9->occ.sram_regs); 1587 1588 /* SBE */ 1589 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1590 return; 1591 } 1592 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1593 &chip9->sbe.xscom_ctrl_regs); 1594 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1595 &chip9->sbe.xscom_mbox_regs); 1596 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1597 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU)); 1598 1599 /* HOMER */ 1600 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1601 &error_abort); 1602 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1603 return; 1604 } 1605 /* Homer Xscom region */ 1606 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1607 1608 /* Homer mmio region */ 1609 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1610 &chip9->homer.regs); 1611 1612 /* PEC PHBs */ 1613 pnv_chip_power9_pec_realize(chip, &local_err); 1614 if (local_err) { 1615 error_propagate(errp, local_err); 1616 return; 1617 } 1618 1619 /* 1620 * I2C 1621 */ 1622 for (i = 0; i < pcc->i2c_num_engines; i++) { 1623 Object *obj = OBJECT(&chip9->i2c[i]); 1624 1625 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1626 object_property_set_int(obj, "num-busses", 1627 pcc->i2c_ports_per_engine[i], 1628 &error_fatal); 1629 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1630 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1631 return; 1632 } 1633 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1634 (chip9->i2c[i].engine - 1) * 1635 PNV9_XSCOM_I2CM_SIZE, 1636 &chip9->i2c[i].xscom_regs); 1637 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1638 qdev_get_gpio_in(DEVICE(&chip9->psi), 1639 PSIHB9_IRQ_SBE_I2C)); 1640 } 1641 } 1642 1643 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1644 { 1645 addr &= (PNV9_XSCOM_SIZE - 1); 1646 return addr >> 3; 1647 } 1648 1649 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1650 { 1651 DeviceClass *dc = DEVICE_CLASS(klass); 1652 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1653 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1654 1655 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1656 k->cores_mask = POWER9_CORE_MASK; 1657 k->core_pir = pnv_chip_core_pir_p9; 1658 k->intc_create = pnv_chip_power9_intc_create; 1659 k->intc_reset = pnv_chip_power9_intc_reset; 1660 k->intc_destroy = pnv_chip_power9_intc_destroy; 1661 k->intc_print_info = pnv_chip_power9_intc_print_info; 1662 k->isa_create = pnv_chip_power9_isa_create; 1663 k->dt_populate = pnv_chip_power9_dt_populate; 1664 k->pic_print_info = pnv_chip_power9_pic_print_info; 1665 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1666 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1667 dc->desc = "PowerNV Chip POWER9"; 1668 k->num_pecs = PNV9_CHIP_MAX_PEC; 1669 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1670 k->i2c_ports_per_engine = i2c_ports_per_engine; 1671 1672 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1673 &k->parent_realize); 1674 } 1675 1676 static void pnv_chip_power10_instance_init(Object *obj) 1677 { 1678 PnvChip *chip = PNV_CHIP(obj); 1679 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1680 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1681 int i; 1682 1683 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1684 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1685 "xive-fabric"); 1686 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1687 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1688 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1689 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1690 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1691 1692 chip->num_pecs = pcc->num_pecs; 1693 1694 for (i = 0; i < chip->num_pecs; i++) { 1695 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1696 TYPE_PNV_PHB5_PEC); 1697 } 1698 1699 for (i = 0; i < pcc->i2c_num_engines; i++) { 1700 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1701 } 1702 } 1703 1704 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1705 { 1706 PnvChip *chip = PNV_CHIP(chip10); 1707 int i; 1708 1709 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1710 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1711 1712 for (i = 0; i < chip10->nr_quads; i++) { 1713 PnvQuad *eq = &chip10->quads[i]; 1714 1715 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1716 PNV_QUAD_TYPE_NAME("power10")); 1717 1718 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1719 &eq->xscom_regs); 1720 1721 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1722 &eq->xscom_qme_regs); 1723 } 1724 } 1725 1726 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1727 { 1728 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1729 int i; 1730 1731 for (i = 0; i < chip->num_pecs; i++) { 1732 PnvPhb4PecState *pec = &chip10->pecs[i]; 1733 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1734 uint32_t pec_nest_base; 1735 uint32_t pec_pci_base; 1736 1737 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1738 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1739 &error_fatal); 1740 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1741 &error_fatal); 1742 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1743 return; 1744 } 1745 1746 pec_nest_base = pecc->xscom_nest_base(pec); 1747 pec_pci_base = pecc->xscom_pci_base(pec); 1748 1749 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1750 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1751 } 1752 } 1753 1754 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1755 { 1756 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1757 PnvChip *chip = PNV_CHIP(dev); 1758 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1759 Error *local_err = NULL; 1760 int i; 1761 1762 /* XSCOM bridge is first */ 1763 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 1764 1765 pcc->parent_realize(dev, &local_err); 1766 if (local_err) { 1767 error_propagate(errp, local_err); 1768 return; 1769 } 1770 1771 pnv_chip_power10_quad_realize(chip10, &local_err); 1772 if (local_err) { 1773 error_propagate(errp, local_err); 1774 return; 1775 } 1776 1777 /* XIVE2 interrupt controller (POWER10) */ 1778 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1779 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1780 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1781 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1782 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1783 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1784 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1785 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1786 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1787 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1788 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1789 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1790 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1791 &error_abort); 1792 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1793 return; 1794 } 1795 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1796 &chip10->xive.xscom_regs); 1797 1798 /* Processor Service Interface (PSI) Host Bridge */ 1799 object_property_set_int(OBJECT(&chip10->psi), "bar", 1800 PNV10_PSIHB_BASE(chip), &error_fatal); 1801 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1802 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1803 &error_fatal); 1804 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1805 return; 1806 } 1807 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1808 &PNV_PSI(&chip10->psi)->xscom_regs); 1809 1810 /* LPC */ 1811 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1812 return; 1813 } 1814 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1815 &chip10->lpc.xscom_regs); 1816 1817 chip->fw_mr = &chip10->lpc.isa_fw; 1818 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1819 (uint64_t) PNV10_LPCM_BASE(chip)); 1820 1821 /* Create the simplified OCC model */ 1822 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1823 return; 1824 } 1825 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1826 &chip10->occ.xscom_regs); 1827 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1828 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1829 1830 /* OCC SRAM model */ 1831 memory_region_add_subregion(get_system_memory(), 1832 PNV10_OCC_SENSOR_BASE(chip), 1833 &chip10->occ.sram_regs); 1834 1835 /* SBE */ 1836 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1837 return; 1838 } 1839 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1840 &chip10->sbe.xscom_ctrl_regs); 1841 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 1842 &chip10->sbe.xscom_mbox_regs); 1843 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 1844 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 1845 1846 /* HOMER */ 1847 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1848 &error_abort); 1849 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1850 return; 1851 } 1852 /* Homer Xscom region */ 1853 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1854 &chip10->homer.pba_regs); 1855 1856 /* Homer mmio region */ 1857 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1858 &chip10->homer.regs); 1859 1860 /* PHBs */ 1861 pnv_chip_power10_phb_realize(chip, &local_err); 1862 if (local_err) { 1863 error_propagate(errp, local_err); 1864 return; 1865 } 1866 1867 1868 /* 1869 * I2C 1870 */ 1871 for (i = 0; i < pcc->i2c_num_engines; i++) { 1872 Object *obj = OBJECT(&chip10->i2c[i]); 1873 1874 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1875 object_property_set_int(obj, "num-busses", 1876 pcc->i2c_ports_per_engine[i], 1877 &error_fatal); 1878 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1879 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1880 return; 1881 } 1882 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 1883 (chip10->i2c[i].engine - 1) * 1884 PNV10_XSCOM_I2CM_SIZE, 1885 &chip10->i2c[i].xscom_regs); 1886 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 1887 qdev_get_gpio_in(DEVICE(&chip10->psi), 1888 PSIHB9_IRQ_SBE_I2C)); 1889 } 1890 1891 } 1892 1893 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 1894 { 1895 int i; 1896 for (i = 0; i < pnv->num_chips; i++) { 1897 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 1898 1899 /* 1900 * Add a PCA9552 I2C device for PCIe hotplug control 1901 * to engine 2, bus 1, address 0x63 1902 */ 1903 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 1904 "pca9552", 0x63); 1905 1906 /* 1907 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 1908 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 1909 * after hypervisor code sets a SLOTx_EN pin high. 1910 */ 1911 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 1912 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 1913 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 1914 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 1915 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 1916 1917 /* 1918 * Add a PCA9554 I2C device for cable card presence detection 1919 * to engine 2, bus 1, address 0x25 1920 */ 1921 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 1922 } 1923 } 1924 1925 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1926 { 1927 addr &= (PNV10_XSCOM_SIZE - 1); 1928 return addr >> 3; 1929 } 1930 1931 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1932 { 1933 DeviceClass *dc = DEVICE_CLASS(klass); 1934 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1935 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 1936 1937 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1938 k->cores_mask = POWER10_CORE_MASK; 1939 k->core_pir = pnv_chip_core_pir_p10; 1940 k->intc_create = pnv_chip_power10_intc_create; 1941 k->intc_reset = pnv_chip_power10_intc_reset; 1942 k->intc_destroy = pnv_chip_power10_intc_destroy; 1943 k->intc_print_info = pnv_chip_power10_intc_print_info; 1944 k->isa_create = pnv_chip_power10_isa_create; 1945 k->dt_populate = pnv_chip_power10_dt_populate; 1946 k->pic_print_info = pnv_chip_power10_pic_print_info; 1947 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1948 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1949 dc->desc = "PowerNV Chip POWER10"; 1950 k->num_pecs = PNV10_CHIP_MAX_PEC; 1951 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 1952 k->i2c_ports_per_engine = i2c_ports_per_engine; 1953 1954 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1955 &k->parent_realize); 1956 } 1957 1958 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1959 { 1960 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1961 int cores_max; 1962 1963 /* 1964 * No custom mask for this chip, let's use the default one from * 1965 * the chip class 1966 */ 1967 if (!chip->cores_mask) { 1968 chip->cores_mask = pcc->cores_mask; 1969 } 1970 1971 /* filter alien core ids ! some are reserved */ 1972 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1973 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1974 chip->cores_mask); 1975 return; 1976 } 1977 chip->cores_mask &= pcc->cores_mask; 1978 1979 /* now that we have a sane layout, let check the number of cores */ 1980 cores_max = ctpop64(chip->cores_mask); 1981 if (chip->nr_cores > cores_max) { 1982 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1983 cores_max); 1984 return; 1985 } 1986 } 1987 1988 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1989 { 1990 Error *error = NULL; 1991 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1992 const char *typename = pnv_chip_core_typename(chip); 1993 int i, core_hwid; 1994 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1995 1996 if (!object_class_by_name(typename)) { 1997 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1998 return; 1999 } 2000 2001 /* Cores */ 2002 pnv_chip_core_sanitize(chip, &error); 2003 if (error) { 2004 error_propagate(errp, error); 2005 return; 2006 } 2007 2008 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2009 2010 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2011 && (i < chip->nr_cores); core_hwid++) { 2012 char core_name[32]; 2013 PnvCore *pnv_core; 2014 uint64_t xscom_core_base; 2015 2016 if (!(chip->cores_mask & (1ull << core_hwid))) { 2017 continue; 2018 } 2019 2020 pnv_core = PNV_CORE(object_new(typename)); 2021 2022 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2023 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2024 chip->cores[i] = pnv_core; 2025 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2026 chip->nr_threads, &error_fatal); 2027 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2028 core_hwid, &error_fatal); 2029 object_property_set_int(OBJECT(pnv_core), "pir", 2030 pcc->core_pir(chip, core_hwid), &error_fatal); 2031 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2032 &error_fatal); 2033 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2034 &error_abort); 2035 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2036 2037 /* Each core has an XSCOM MMIO region */ 2038 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2039 2040 pnv_xscom_add_subregion(chip, xscom_core_base, 2041 &pnv_core->xscom_regs); 2042 i++; 2043 } 2044 } 2045 2046 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2047 { 2048 PnvChip *chip = PNV_CHIP(dev); 2049 Error *error = NULL; 2050 2051 /* Cores */ 2052 pnv_chip_core_realize(chip, &error); 2053 if (error) { 2054 error_propagate(errp, error); 2055 return; 2056 } 2057 } 2058 2059 static Property pnv_chip_properties[] = { 2060 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2061 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2062 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2063 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2064 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2065 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2066 DEFINE_PROP_END_OF_LIST(), 2067 }; 2068 2069 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2070 { 2071 DeviceClass *dc = DEVICE_CLASS(klass); 2072 2073 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2074 dc->realize = pnv_chip_realize; 2075 device_class_set_props(dc, pnv_chip_properties); 2076 dc->desc = "PowerNV Chip"; 2077 } 2078 2079 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2080 { 2081 int i, j; 2082 2083 for (i = 0; i < chip->nr_cores; i++) { 2084 PnvCore *pc = chip->cores[i]; 2085 CPUCore *cc = CPU_CORE(pc); 2086 2087 for (j = 0; j < cc->nr_threads; j++) { 2088 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2089 return pc->threads[j]; 2090 } 2091 } 2092 } 2093 return NULL; 2094 } 2095 2096 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2097 { 2098 PnvMachineState *pnv = PNV_MACHINE(xi); 2099 int i, j; 2100 2101 for (i = 0; i < pnv->num_chips; i++) { 2102 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2103 2104 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2105 return &chip8->psi.ics; 2106 } 2107 2108 for (j = 0; j < chip8->num_phbs; j++) { 2109 PnvPHB *phb = chip8->phbs[j]; 2110 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2111 2112 if (ics_valid_irq(&phb3->lsis, irq)) { 2113 return &phb3->lsis; 2114 } 2115 2116 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2117 return ICS(&phb3->msis); 2118 } 2119 } 2120 } 2121 return NULL; 2122 } 2123 2124 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2125 { 2126 int i; 2127 2128 for (i = 0; i < pnv->num_chips; i++) { 2129 PnvChip *chip = pnv->chips[i]; 2130 if (chip->chip_id == chip_id) { 2131 return chip; 2132 } 2133 } 2134 return NULL; 2135 } 2136 2137 static void pnv_ics_resend(XICSFabric *xi) 2138 { 2139 PnvMachineState *pnv = PNV_MACHINE(xi); 2140 int i, j; 2141 2142 for (i = 0; i < pnv->num_chips; i++) { 2143 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2144 2145 ics_resend(&chip8->psi.ics); 2146 2147 for (j = 0; j < chip8->num_phbs; j++) { 2148 PnvPHB *phb = chip8->phbs[j]; 2149 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2150 2151 ics_resend(&phb3->lsis); 2152 ics_resend(ICS(&phb3->msis)); 2153 } 2154 } 2155 } 2156 2157 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2158 { 2159 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2160 2161 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2162 } 2163 2164 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2165 Monitor *mon) 2166 { 2167 PnvMachineState *pnv = PNV_MACHINE(obj); 2168 int i; 2169 CPUState *cs; 2170 2171 CPU_FOREACH(cs) { 2172 PowerPCCPU *cpu = POWERPC_CPU(cs); 2173 2174 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2175 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2176 mon); 2177 } 2178 2179 for (i = 0; i < pnv->num_chips; i++) { 2180 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2181 } 2182 } 2183 2184 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2185 uint8_t nvt_blk, uint32_t nvt_idx, 2186 bool cam_ignore, uint8_t priority, 2187 uint32_t logic_serv, 2188 XiveTCTXMatch *match) 2189 { 2190 PnvMachineState *pnv = PNV_MACHINE(xfb); 2191 int total_count = 0; 2192 int i; 2193 2194 for (i = 0; i < pnv->num_chips; i++) { 2195 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2196 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2197 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2198 int count; 2199 2200 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2201 priority, logic_serv, match); 2202 2203 if (count < 0) { 2204 return count; 2205 } 2206 2207 total_count += count; 2208 } 2209 2210 return total_count; 2211 } 2212 2213 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2214 uint8_t nvt_blk, uint32_t nvt_idx, 2215 bool cam_ignore, uint8_t priority, 2216 uint32_t logic_serv, 2217 XiveTCTXMatch *match) 2218 { 2219 PnvMachineState *pnv = PNV_MACHINE(xfb); 2220 int total_count = 0; 2221 int i; 2222 2223 for (i = 0; i < pnv->num_chips; i++) { 2224 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2225 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2226 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2227 int count; 2228 2229 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2230 priority, logic_serv, match); 2231 2232 if (count < 0) { 2233 return count; 2234 } 2235 2236 total_count += count; 2237 } 2238 2239 return total_count; 2240 } 2241 2242 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2243 { 2244 MachineClass *mc = MACHINE_CLASS(oc); 2245 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2246 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2247 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2248 2249 static GlobalProperty phb_compat[] = { 2250 { TYPE_PNV_PHB, "version", "3" }, 2251 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2252 }; 2253 2254 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2255 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2256 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2257 2258 xic->icp_get = pnv_icp_get; 2259 xic->ics_get = pnv_ics_get; 2260 xic->ics_resend = pnv_ics_resend; 2261 2262 pmc->compat = compat; 2263 pmc->compat_size = sizeof(compat); 2264 2265 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2266 } 2267 2268 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2269 { 2270 MachineClass *mc = MACHINE_CLASS(oc); 2271 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2272 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2273 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2274 2275 static GlobalProperty phb_compat[] = { 2276 { TYPE_PNV_PHB, "version", "4" }, 2277 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2278 }; 2279 2280 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2281 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2282 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2283 2284 xfc->match_nvt = pnv_match_nvt; 2285 2286 pmc->compat = compat; 2287 pmc->compat_size = sizeof(compat); 2288 pmc->dt_power_mgt = pnv_dt_power_mgt; 2289 2290 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2291 } 2292 2293 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2294 { 2295 MachineClass *mc = MACHINE_CLASS(oc); 2296 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2297 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2298 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2299 2300 static GlobalProperty phb_compat[] = { 2301 { TYPE_PNV_PHB, "version", "5" }, 2302 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2303 }; 2304 2305 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2306 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2307 2308 mc->alias = "powernv"; 2309 2310 pmc->compat = compat; 2311 pmc->compat_size = sizeof(compat); 2312 pmc->dt_power_mgt = pnv_dt_power_mgt; 2313 2314 xfc->match_nvt = pnv10_xive_match_nvt; 2315 2316 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2317 } 2318 2319 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2320 { 2321 MachineClass *mc = MACHINE_CLASS(oc); 2322 2323 pnv_machine_p10_common_class_init(oc, data); 2324 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2325 } 2326 2327 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2328 { 2329 MachineClass *mc = MACHINE_CLASS(oc); 2330 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2331 2332 pnv_machine_p10_common_class_init(oc, data); 2333 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2334 pmc->i2c_init = pnv_rainier_i2c_init; 2335 } 2336 2337 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2338 { 2339 PnvMachineState *pnv = PNV_MACHINE(obj); 2340 2341 return !!pnv->fw_load_addr; 2342 } 2343 2344 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2345 { 2346 PnvMachineState *pnv = PNV_MACHINE(obj); 2347 2348 if (value) { 2349 pnv->fw_load_addr = 0x8000000; 2350 } 2351 } 2352 2353 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2354 { 2355 PowerPCCPU *cpu = POWERPC_CPU(cs); 2356 CPUPPCState *env = &cpu->env; 2357 2358 cpu_synchronize_state(cs); 2359 ppc_cpu_do_system_reset(cs); 2360 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2361 /* 2362 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2363 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2364 * (PPC_BIT(43)). 2365 */ 2366 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2367 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2368 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2369 } 2370 } else { 2371 /* 2372 * For non-powersave system resets, SRR1[42:45] are defined to be 2373 * implementation-dependent. The POWER9 User Manual specifies that 2374 * an external (SCOM driven, which may come from a BMC nmi command or 2375 * another CPU requesting a NMI IPI) system reset exception should be 2376 * 0b0010 (PPC_BIT(44)). 2377 */ 2378 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2379 } 2380 } 2381 2382 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2383 { 2384 CPUState *cs; 2385 2386 CPU_FOREACH(cs) { 2387 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2388 } 2389 } 2390 2391 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2392 { 2393 MachineClass *mc = MACHINE_CLASS(oc); 2394 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2395 NMIClass *nc = NMI_CLASS(oc); 2396 2397 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2398 mc->init = pnv_init; 2399 mc->reset = pnv_reset; 2400 mc->max_cpus = MAX_CPUS; 2401 /* Pnv provides a AHCI device for storage */ 2402 mc->block_default_type = IF_IDE; 2403 mc->no_parallel = 1; 2404 mc->default_boot_order = NULL; 2405 /* 2406 * RAM defaults to less than 2048 for 32-bit hosts, and large 2407 * enough to fit the maximum initrd size at it's load address 2408 */ 2409 mc->default_ram_size = 1 * GiB; 2410 mc->default_ram_id = "pnv.ram"; 2411 ispc->print_info = pnv_pic_print_info; 2412 nc->nmi_monitor_handler = pnv_nmi; 2413 2414 object_class_property_add_bool(oc, "hb-mode", 2415 pnv_machine_get_hb, pnv_machine_set_hb); 2416 object_class_property_set_description(oc, "hb-mode", 2417 "Use a hostboot like boot loader"); 2418 } 2419 2420 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2421 { \ 2422 .name = type, \ 2423 .class_init = class_initfn, \ 2424 .parent = TYPE_PNV8_CHIP, \ 2425 } 2426 2427 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2428 { \ 2429 .name = type, \ 2430 .class_init = class_initfn, \ 2431 .parent = TYPE_PNV9_CHIP, \ 2432 } 2433 2434 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2435 { \ 2436 .name = type, \ 2437 .class_init = class_initfn, \ 2438 .parent = TYPE_PNV10_CHIP, \ 2439 } 2440 2441 static const TypeInfo types[] = { 2442 { 2443 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2444 .parent = MACHINE_TYPE_NAME("powernv10"), 2445 .class_init = pnv_machine_p10_rainier_class_init, 2446 }, 2447 { 2448 .name = MACHINE_TYPE_NAME("powernv10"), 2449 .parent = TYPE_PNV_MACHINE, 2450 .class_init = pnv_machine_power10_class_init, 2451 .interfaces = (InterfaceInfo[]) { 2452 { TYPE_XIVE_FABRIC }, 2453 { }, 2454 }, 2455 }, 2456 { 2457 .name = MACHINE_TYPE_NAME("powernv9"), 2458 .parent = TYPE_PNV_MACHINE, 2459 .class_init = pnv_machine_power9_class_init, 2460 .interfaces = (InterfaceInfo[]) { 2461 { TYPE_XIVE_FABRIC }, 2462 { }, 2463 }, 2464 }, 2465 { 2466 .name = MACHINE_TYPE_NAME("powernv8"), 2467 .parent = TYPE_PNV_MACHINE, 2468 .class_init = pnv_machine_power8_class_init, 2469 .interfaces = (InterfaceInfo[]) { 2470 { TYPE_XICS_FABRIC }, 2471 { }, 2472 }, 2473 }, 2474 { 2475 .name = TYPE_PNV_MACHINE, 2476 .parent = TYPE_MACHINE, 2477 .abstract = true, 2478 .instance_size = sizeof(PnvMachineState), 2479 .class_init = pnv_machine_class_init, 2480 .class_size = sizeof(PnvMachineClass), 2481 .interfaces = (InterfaceInfo[]) { 2482 { TYPE_INTERRUPT_STATS_PROVIDER }, 2483 { TYPE_NMI }, 2484 { }, 2485 }, 2486 }, 2487 { 2488 .name = TYPE_PNV_CHIP, 2489 .parent = TYPE_SYS_BUS_DEVICE, 2490 .class_init = pnv_chip_class_init, 2491 .instance_size = sizeof(PnvChip), 2492 .class_size = sizeof(PnvChipClass), 2493 .abstract = true, 2494 }, 2495 2496 /* 2497 * P10 chip and variants 2498 */ 2499 { 2500 .name = TYPE_PNV10_CHIP, 2501 .parent = TYPE_PNV_CHIP, 2502 .instance_init = pnv_chip_power10_instance_init, 2503 .instance_size = sizeof(Pnv10Chip), 2504 }, 2505 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2506 2507 /* 2508 * P9 chip and variants 2509 */ 2510 { 2511 .name = TYPE_PNV9_CHIP, 2512 .parent = TYPE_PNV_CHIP, 2513 .instance_init = pnv_chip_power9_instance_init, 2514 .instance_size = sizeof(Pnv9Chip), 2515 }, 2516 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2517 2518 /* 2519 * P8 chip and variants 2520 */ 2521 { 2522 .name = TYPE_PNV8_CHIP, 2523 .parent = TYPE_PNV_CHIP, 2524 .instance_init = pnv_chip_power8_instance_init, 2525 .instance_size = sizeof(Pnv8Chip), 2526 }, 2527 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2528 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2529 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2530 pnv_chip_power8nvl_class_init), 2531 }; 2532 2533 DEFINE_TYPES(types) 2534