1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "system/qtest.h" 26 #include "system/system.h" 27 #include "system/numa.h" 28 #include "system/reset.h" 29 #include "system/runstate.h" 30 #include "system/cpus.h" 31 #include "system/device_tree.h" 32 #include "system/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "hw/intc/intc.h" 42 #include "hw/ipmi/ipmi.h" 43 #include "target/ppc/mmu-hash64.h" 44 #include "hw/pci/msi.h" 45 #include "hw/pci-host/pnv_phb.h" 46 #include "hw/pci-host/pnv_phb3.h" 47 #include "hw/pci-host/pnv_phb4.h" 48 49 #include "hw/ppc/xics.h" 50 #include "hw/qdev-properties.h" 51 #include "hw/ppc/pnv_chip.h" 52 #include "hw/ppc/pnv_xscom.h" 53 #include "hw/ppc/pnv_pnor.h" 54 55 #include "hw/isa/isa.h" 56 #include "hw/char/serial-isa.h" 57 #include "hw/rtc/mc146818rtc.h" 58 59 #include <libfdt.h> 60 61 #define FDT_MAX_SIZE (1 * MiB) 62 63 #define FW_FILE_NAME "skiboot.lid" 64 #define FW_LOAD_ADDR 0x0 65 #define FW_MAX_SIZE (16 * MiB) 66 67 #define PNOR_FILE_NAME "pnv-pnor.bin" 68 69 #define KERNEL_LOAD_ADDR 0x20000000 70 #define KERNEL_MAX_SIZE (128 * MiB) 71 #define INITRD_LOAD_ADDR 0x28000000 72 #define INITRD_MAX_SIZE (128 * MiB) 73 74 static const char *pnv_chip_core_typename(const PnvChip *o) 75 { 76 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 77 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 78 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 79 const char *core_type = object_class_get_name(object_class_by_name(s)); 80 g_free(s); 81 return core_type; 82 } 83 84 /* 85 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 86 * 4 * 4 sockets * 12 cores * 8 threads = 1536 87 * Let's make it 2^11 88 */ 89 #define MAX_CPUS 2048 90 91 /* 92 * Memory nodes are created by hostboot, one for each range of memory 93 * that has a different "affinity". In practice, it means one range 94 * per chip. 95 */ 96 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 97 { 98 char *mem_name; 99 uint64_t mem_reg_property[2]; 100 int off; 101 102 mem_reg_property[0] = cpu_to_be64(start); 103 mem_reg_property[1] = cpu_to_be64(size); 104 105 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 106 off = fdt_add_subnode(fdt, 0, mem_name); 107 g_free(mem_name); 108 109 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 110 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 111 sizeof(mem_reg_property)))); 112 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 113 } 114 115 static int get_cpus_node(void *fdt) 116 { 117 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 118 119 if (cpus_offset < 0) { 120 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 121 if (cpus_offset) { 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 123 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 124 } 125 } 126 _FDT(cpus_offset); 127 return cpus_offset; 128 } 129 130 /* 131 * The PowerNV cores (and threads) need to use real HW ids and not an 132 * incremental index like it has been done on other platforms. This HW 133 * id is stored in the CPU PIR, it is used to create cpu nodes in the 134 * device tree, used in XSCOM to address cores and in interrupt 135 * servers. 136 */ 137 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 138 { 139 PowerPCCPU *cpu = pc->threads[0]; 140 CPUState *cs = CPU(cpu); 141 DeviceClass *dc = DEVICE_GET_CLASS(cs); 142 int smt_threads = CPU_CORE(pc)->nr_threads; 143 CPUPPCState *env = &cpu->env; 144 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 145 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 146 uint32_t *servers_prop; 147 int i; 148 uint32_t pir, tir; 149 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 150 0xffffffff, 0xffffffff}; 151 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 152 uint32_t cpufreq = 1000000000; 153 uint32_t page_sizes_prop[64]; 154 size_t page_sizes_prop_size; 155 int offset; 156 char *nodename; 157 int cpus_offset = get_cpus_node(fdt); 158 159 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir); 160 161 /* Only one DT node per (big) core */ 162 g_assert(tir == 0); 163 164 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 165 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 166 _FDT(offset); 167 g_free(nodename); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 170 171 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 172 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 173 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 174 175 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 176 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 177 env->dcache_line_size))); 178 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 179 env->dcache_line_size))); 180 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 181 env->icache_line_size))); 182 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 183 env->icache_line_size))); 184 185 if (pcc->l1_dcache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 187 pcc->l1_dcache_size))); 188 } else { 189 warn_report("Unknown L1 dcache size for cpu"); 190 } 191 if (pcc->l1_icache_size) { 192 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 193 pcc->l1_icache_size))); 194 } else { 195 warn_report("Unknown L1 icache size for cpu"); 196 } 197 198 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 199 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 200 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 201 cpu->hash64_opts->slb_size))); 202 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 203 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 204 205 if (ppc_has_spr(cpu, SPR_PURR)) { 206 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 207 } 208 209 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 210 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 211 segs, sizeof(segs)))); 212 } 213 214 /* 215 * Advertise VMX/VSX (vector extensions) if available 216 * 0 / no property == no vector extensions 217 * 1 == VMX / Altivec available 218 * 2 == VSX available 219 */ 220 if (env->insns_flags & PPC_ALTIVEC) { 221 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 222 223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 224 } 225 226 /* 227 * Advertise DFP (Decimal Floating Point) if available 228 * 0 / no property == no DFP 229 * 1 == DFP available 230 */ 231 if (env->insns_flags2 & PPC2_DFP) { 232 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 233 } 234 235 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 236 sizeof(page_sizes_prop)); 237 if (page_sizes_prop_size) { 238 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 239 page_sizes_prop, page_sizes_prop_size))); 240 } 241 242 /* Build interrupt servers properties */ 243 if (pc->big_core) { 244 servers_prop = g_new(uint32_t, smt_threads * 2); 245 for (i = 0; i < smt_threads; i++) { 246 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 247 servers_prop[i * 2] = cpu_to_be32(pir); 248 249 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL); 250 servers_prop[i * 2 + 1] = cpu_to_be32(pir); 251 } 252 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 253 servers_prop, sizeof(*servers_prop) * smt_threads 254 * 2))); 255 } else { 256 servers_prop = g_new(uint32_t, smt_threads); 257 for (i = 0; i < smt_threads; i++) { 258 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 259 servers_prop[i] = cpu_to_be32(pir); 260 } 261 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 262 servers_prop, sizeof(*servers_prop) * smt_threads))); 263 } 264 g_free(servers_prop); 265 266 return offset; 267 } 268 269 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 270 uint32_t nr_threads) 271 { 272 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 273 uint32_t pir; 274 uint64_t addr; 275 char *name; 276 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 277 uint32_t irange[2], i, rsize; 278 uint64_t *reg; 279 int offset; 280 281 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); 282 addr = PNV_ICP_BASE(chip) | (pir << 12); 283 284 irange[0] = cpu_to_be32(pir); 285 irange[1] = cpu_to_be32(nr_threads); 286 287 rsize = sizeof(uint64_t) * 2 * nr_threads; 288 reg = g_malloc(rsize); 289 for (i = 0; i < nr_threads; i++) { 290 /* We know P8 PIR is linear with thread id */ 291 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 292 reg[i * 2 + 1] = cpu_to_be64(0x1000); 293 } 294 295 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 296 offset = fdt_add_subnode(fdt, 0, name); 297 _FDT(offset); 298 g_free(name); 299 300 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 301 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 302 _FDT((fdt_setprop_string(fdt, offset, "device_type", 303 "PowerPC-External-Interrupt-Presentation"))); 304 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 305 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 306 irange, sizeof(irange)))); 307 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 308 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 309 g_free(reg); 310 } 311 312 /* 313 * Adds a PnvPHB to the chip on P8. 314 * Implemented here, like for defaults PHBs 315 */ 316 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 317 { 318 Pnv8Chip *chip8 = PNV8_CHIP(chip); 319 320 phb->chip = chip; 321 322 chip8->phbs[chip8->num_phbs] = phb; 323 chip8->num_phbs++; 324 return chip; 325 } 326 327 /* 328 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 329 * HTM is always enabled because TCG does implement HTM, it's just a 330 * degenerate implementation. 331 */ 332 static const uint8_t pa_features_207[] = { 24, 0, 333 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 334 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 335 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 336 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 337 338 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 339 { 340 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 341 int i; 342 343 pnv_dt_xscom(chip, fdt, 0, 344 cpu_to_be64(PNV_XSCOM_BASE(chip)), 345 cpu_to_be64(PNV_XSCOM_SIZE), 346 compat, sizeof(compat)); 347 348 for (i = 0; i < chip->nr_cores; i++) { 349 PnvCore *pnv_core = chip->cores[i]; 350 int offset; 351 352 offset = pnv_dt_core(chip, pnv_core, fdt); 353 354 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 355 pa_features_207, sizeof(pa_features_207)))); 356 357 /* Interrupt Control Presenters (ICP). One per core. */ 358 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 359 } 360 361 if (chip->ram_size) { 362 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 363 } 364 } 365 366 /* 367 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 368 */ 369 static const uint8_t pa_features_300[] = { 66, 0, 370 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 371 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 372 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 373 /* 6: DS207 */ 374 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 375 /* 16: Vector */ 376 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 377 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 378 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 379 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 380 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 381 /* 32: LE atomic, 34: EBB + ext EBB */ 382 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 383 /* 40: Radix MMU */ 384 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 385 /* 42: PM, 44: PC RA, 46: SC vec'd */ 386 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 387 /* 48: SIMD, 50: QP BFP, 52: String */ 388 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 389 /* 54: DecFP, 56: DecI, 58: SHA */ 390 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 391 /* 60: NM atomic, 62: RNG */ 392 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 393 }; 394 395 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 396 { 397 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 398 int i; 399 400 pnv_dt_xscom(chip, fdt, 0, 401 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 402 cpu_to_be64(PNV9_XSCOM_SIZE), 403 compat, sizeof(compat)); 404 405 for (i = 0; i < chip->nr_cores; i++) { 406 PnvCore *pnv_core = chip->cores[i]; 407 int offset; 408 409 offset = pnv_dt_core(chip, pnv_core, fdt); 410 411 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 412 pa_features_300, sizeof(pa_features_300)))); 413 414 if (pnv_core->big_core) { 415 i++; /* Big-core groups two QEMU cores */ 416 } 417 } 418 419 if (chip->ram_size) { 420 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 421 } 422 423 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 424 } 425 426 /* 427 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 428 * always disables copy/paste. 429 */ 430 static const uint8_t pa_features_31[] = { 74, 0, 431 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 432 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 433 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 434 /* 6: DS207 */ 435 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 436 /* 16: Vector */ 437 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 438 /* 18: Vec. Scalar, 20: Vec. XOR */ 439 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 440 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 441 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 442 /* 32: LE atomic, 34: EBB + ext EBB */ 443 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 444 /* 40: Radix MMU */ 445 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 446 /* 42: PM, 44: PC RA, 46: SC vec'd */ 447 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 448 /* 48: SIMD, 50: QP BFP, 52: String */ 449 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 450 /* 54: DecFP, 56: DecI, 58: SHA */ 451 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 452 /* 60: NM atomic, 62: RNG */ 453 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 454 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 455 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 456 /* 72: [P]HASHST/[P]HASHCHK */ 457 0x80, 0x00, /* 72 - 73 */ 458 }; 459 460 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 461 { 462 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 463 int i; 464 465 pnv_dt_xscom(chip, fdt, 0, 466 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 467 cpu_to_be64(PNV10_XSCOM_SIZE), 468 compat, sizeof(compat)); 469 470 for (i = 0; i < chip->nr_cores; i++) { 471 PnvCore *pnv_core = chip->cores[i]; 472 int offset; 473 474 offset = pnv_dt_core(chip, pnv_core, fdt); 475 476 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 477 pa_features_31, sizeof(pa_features_31)))); 478 479 if (pnv_core->big_core) { 480 i++; /* Big-core groups two QEMU cores */ 481 } 482 } 483 484 if (chip->ram_size) { 485 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 486 } 487 488 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 489 } 490 491 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 492 { 493 uint32_t io_base = d->ioport_id; 494 uint32_t io_regs[] = { 495 cpu_to_be32(1), 496 cpu_to_be32(io_base), 497 cpu_to_be32(2) 498 }; 499 char *name; 500 int node; 501 502 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 503 node = fdt_add_subnode(fdt, lpc_off, name); 504 _FDT(node); 505 g_free(name); 506 507 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 508 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 509 } 510 511 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 512 { 513 const char compatible[] = "ns16550\0pnpPNP,501"; 514 uint32_t io_base = d->ioport_id; 515 uint32_t io_regs[] = { 516 cpu_to_be32(1), 517 cpu_to_be32(io_base), 518 cpu_to_be32(8) 519 }; 520 uint32_t irq; 521 char *name; 522 int node; 523 524 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 525 526 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 527 node = fdt_add_subnode(fdt, lpc_off, name); 528 _FDT(node); 529 g_free(name); 530 531 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 532 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 533 sizeof(compatible)))); 534 535 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 536 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 537 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 538 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 539 fdt_get_phandle(fdt, lpc_off)))); 540 541 /* This is needed by Linux */ 542 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 543 } 544 545 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 546 { 547 const char compatible[] = "bt\0ipmi-bt"; 548 uint32_t io_base; 549 uint32_t io_regs[] = { 550 cpu_to_be32(1), 551 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 552 cpu_to_be32(3) 553 }; 554 uint32_t irq; 555 char *name; 556 int node; 557 558 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 559 io_regs[1] = cpu_to_be32(io_base); 560 561 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 562 563 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 564 node = fdt_add_subnode(fdt, lpc_off, name); 565 _FDT(node); 566 g_free(name); 567 568 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 569 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 570 sizeof(compatible)))); 571 572 /* Mark it as reserved to avoid Linux trying to claim it */ 573 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 574 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 575 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 576 fdt_get_phandle(fdt, lpc_off)))); 577 } 578 579 typedef struct ForeachPopulateArgs { 580 void *fdt; 581 int offset; 582 } ForeachPopulateArgs; 583 584 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 585 { 586 ForeachPopulateArgs *args = opaque; 587 ISADevice *d = ISA_DEVICE(dev); 588 589 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 590 pnv_dt_rtc(d, args->fdt, args->offset); 591 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 592 pnv_dt_serial(d, args->fdt, args->offset); 593 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 594 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 595 } else { 596 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 597 d->ioport_id); 598 } 599 600 return 0; 601 } 602 603 /* 604 * The default LPC bus of a multichip system is on chip 0. It's 605 * recognized by the firmware (skiboot) using a "primary" property. 606 */ 607 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 608 { 609 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 610 ForeachPopulateArgs args = { 611 .fdt = fdt, 612 .offset = isa_offset, 613 }; 614 uint32_t phandle; 615 616 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 617 618 phandle = qemu_fdt_alloc_phandle(fdt); 619 assert(phandle > 0); 620 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 621 622 /* 623 * ISA devices are not necessarily parented to the ISA bus so we 624 * can not use object_child_foreach() 625 */ 626 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 627 &args); 628 } 629 630 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 631 { 632 int off; 633 634 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 635 off = fdt_add_subnode(fdt, off, "power-mgt"); 636 637 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 638 } 639 640 static void *pnv_dt_create(MachineState *machine) 641 { 642 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 643 PnvMachineState *pnv = PNV_MACHINE(machine); 644 void *fdt; 645 char *buf; 646 int off; 647 int i; 648 649 fdt = g_malloc0(FDT_MAX_SIZE); 650 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 651 652 /* /qemu node */ 653 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 654 655 /* Root node */ 656 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 657 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 658 _FDT((fdt_setprop_string(fdt, 0, "model", 659 "IBM PowerNV (emulated by qemu)"))); 660 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 661 662 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 663 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 664 if (qemu_uuid_set) { 665 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 666 } 667 g_free(buf); 668 669 off = fdt_add_subnode(fdt, 0, "chosen"); 670 if (machine->kernel_cmdline) { 671 _FDT((fdt_setprop_string(fdt, off, "bootargs", 672 machine->kernel_cmdline))); 673 } 674 675 if (pnv->initrd_size) { 676 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 677 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 678 679 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 680 &start_prop, sizeof(start_prop)))); 681 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 682 &end_prop, sizeof(end_prop)))); 683 } 684 685 /* Populate device tree for each chip */ 686 for (i = 0; i < pnv->num_chips; i++) { 687 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 688 } 689 690 /* Populate ISA devices on chip 0 */ 691 pnv_dt_isa(pnv, fdt); 692 693 if (pnv->bmc) { 694 pnv_dt_bmc_sensors(pnv->bmc, fdt); 695 } 696 697 /* Create an extra node for power management on machines that support it */ 698 if (pmc->dt_power_mgt) { 699 pmc->dt_power_mgt(pnv, fdt); 700 } 701 702 return fdt; 703 } 704 705 static void pnv_powerdown_notify(Notifier *n, void *opaque) 706 { 707 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 708 709 if (pnv->bmc) { 710 pnv_bmc_powerdown(pnv->bmc); 711 } 712 } 713 714 static void pnv_reset(MachineState *machine, ResetType type) 715 { 716 PnvMachineState *pnv = PNV_MACHINE(machine); 717 IPMIBmc *bmc; 718 void *fdt; 719 720 qemu_devices_reset(type); 721 722 /* 723 * The machine should provide by default an internal BMC simulator. 724 * If not, try to use the BMC device that was provided on the command 725 * line. 726 */ 727 bmc = pnv_bmc_find(&error_fatal); 728 if (!pnv->bmc) { 729 if (!bmc) { 730 if (!qtest_enabled()) { 731 warn_report("machine has no BMC device. Use '-device " 732 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 733 "to define one"); 734 } 735 } else { 736 pnv_bmc_set_pnor(bmc, pnv->pnor); 737 pnv->bmc = bmc; 738 } 739 } 740 741 if (machine->fdt) { 742 fdt = machine->fdt; 743 } else { 744 fdt = pnv_dt_create(machine); 745 /* Pack resulting tree */ 746 _FDT((fdt_pack(fdt))); 747 } 748 749 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 750 751 /* Update machine->fdt with latest fdt */ 752 if (machine->fdt != fdt) { 753 /* 754 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 755 * the existing machine->fdt to avoid leaking it during 756 * a reset. 757 */ 758 g_free(machine->fdt); 759 machine->fdt = fdt; 760 } 761 } 762 763 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 764 { 765 Pnv8Chip *chip8 = PNV8_CHIP(chip); 766 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 767 768 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 769 770 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 771 } 772 773 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 774 { 775 Pnv8Chip *chip8 = PNV8_CHIP(chip); 776 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 777 778 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 779 780 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 781 } 782 783 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 784 { 785 Pnv9Chip *chip9 = PNV9_CHIP(chip); 786 qemu_irq irq; 787 788 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 789 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq); 790 791 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0); 792 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); 793 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1); 794 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); 795 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2); 796 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); 797 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3); 798 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); 799 800 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 801 } 802 803 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 804 { 805 Pnv10Chip *chip10 = PNV10_CHIP(chip); 806 qemu_irq irq; 807 808 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 809 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq); 810 811 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0); 812 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); 813 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1); 814 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); 815 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2); 816 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); 817 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3); 818 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); 819 820 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 821 } 822 823 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 824 { 825 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 826 } 827 828 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf) 829 { 830 Pnv8Chip *chip8 = PNV8_CHIP(chip); 831 int i; 832 833 ics_pic_print_info(&chip8->psi.ics, buf); 834 835 for (i = 0; i < chip8->num_phbs; i++) { 836 PnvPHB *phb = chip8->phbs[i]; 837 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 838 839 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 840 ics_pic_print_info(&phb3->lsis, buf); 841 } 842 } 843 844 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 845 { 846 GString *buf = opaque; 847 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 848 849 if (!phb) { 850 return 0; 851 } 852 853 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 854 855 return 0; 856 } 857 858 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf) 859 { 860 Pnv9Chip *chip9 = PNV9_CHIP(chip); 861 862 pnv_xive_pic_print_info(&chip9->xive, buf); 863 pnv_psi_pic_print_info(&chip9->psi, buf); 864 object_child_foreach_recursive(OBJECT(chip), 865 pnv_chip_power9_pic_print_info_child, buf); 866 } 867 868 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 869 uint32_t core_id) 870 { 871 return PNV_XSCOM_EX_BASE(core_id); 872 } 873 874 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 875 uint32_t core_id) 876 { 877 return PNV9_XSCOM_EC_BASE(core_id); 878 } 879 880 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 881 uint32_t core_id) 882 { 883 return PNV10_XSCOM_EC_BASE(core_id); 884 } 885 886 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 887 { 888 PowerPCCPUClass *ppc_default = 889 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 890 PowerPCCPUClass *ppc = 891 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 892 893 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 894 } 895 896 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 897 { 898 ISADevice *dev = isa_new("isa-ipmi-bt"); 899 900 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 901 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 902 isa_realize_and_unref(dev, bus, &error_fatal); 903 } 904 905 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf) 906 { 907 Pnv10Chip *chip10 = PNV10_CHIP(chip); 908 909 pnv_xive2_pic_print_info(&chip10->xive, buf); 910 pnv_psi_pic_print_info(&chip10->psi, buf); 911 object_child_foreach_recursive(OBJECT(chip), 912 pnv_chip_power9_pic_print_info_child, buf); 913 } 914 915 /* Always give the first 1GB to chip 0 else we won't boot */ 916 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 917 { 918 MachineState *machine = MACHINE(pnv); 919 uint64_t ram_per_chip; 920 921 assert(machine->ram_size >= 1 * GiB); 922 923 ram_per_chip = machine->ram_size / pnv->num_chips; 924 if (ram_per_chip >= 1 * GiB) { 925 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 926 } 927 928 assert(pnv->num_chips > 1); 929 930 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 931 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 932 } 933 934 static void pnv_init(MachineState *machine) 935 { 936 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 937 PnvMachineState *pnv = PNV_MACHINE(machine); 938 MachineClass *mc = MACHINE_GET_CLASS(machine); 939 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 940 int max_smt_threads = pmc->max_smt_threads; 941 char *fw_filename; 942 long fw_size; 943 uint64_t chip_ram_start = 0; 944 int i; 945 char *chip_typename; 946 DriveInfo *pnor; 947 DeviceState *dev; 948 949 if (kvm_enabled()) { 950 error_report("machine %s does not support the KVM accelerator", 951 mc->name); 952 exit(EXIT_FAILURE); 953 } 954 955 /* allocate RAM */ 956 if (machine->ram_size < mc->default_ram_size) { 957 char *sz = size_to_str(mc->default_ram_size); 958 error_report("Invalid RAM size, should be bigger than %s", sz); 959 g_free(sz); 960 exit(EXIT_FAILURE); 961 } 962 963 /* checks for invalid option combinations */ 964 if (machine->dtb && (strlen(machine->kernel_cmdline) != 0)) { 965 error_report("-append and -dtb cannot be used together, as passed" 966 " command line is ignored in case of custom dtb"); 967 exit(EXIT_FAILURE); 968 } 969 970 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 971 972 /* 973 * Create our simple PNOR device 974 */ 975 dev = qdev_new(TYPE_PNV_PNOR); 976 pnor = drive_get(IF_MTD, 0, 0); 977 if (!pnor && defaults_enabled()) { 978 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, PNOR_FILE_NAME); 979 if (!fw_filename) { 980 warn_report("Could not find PNOR '%s'", PNOR_FILE_NAME); 981 } else { 982 QemuOpts *opts; 983 opts = drive_add(IF_MTD, -1, fw_filename, "format=raw,readonly=on"); 984 pnor = drive_new(opts, IF_MTD, &error_fatal); 985 g_free(fw_filename); 986 } 987 } 988 if (pnor) { 989 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 990 } 991 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 992 pnv->pnor = PNV_PNOR(dev); 993 994 /* load skiboot firmware */ 995 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 996 if (!fw_filename) { 997 error_report("Could not find OPAL firmware '%s'", bios_name); 998 exit(1); 999 } 1000 1001 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 1002 if (fw_size < 0) { 1003 error_report("Could not load OPAL firmware '%s'", fw_filename); 1004 exit(1); 1005 } 1006 g_free(fw_filename); 1007 1008 /* load kernel */ 1009 if (machine->kernel_filename) { 1010 long kernel_size; 1011 1012 kernel_size = load_image_targphys(machine->kernel_filename, 1013 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 1014 if (kernel_size < 0) { 1015 error_report("Could not load kernel '%s'", 1016 machine->kernel_filename); 1017 exit(1); 1018 } 1019 } 1020 1021 /* load initrd */ 1022 if (machine->initrd_filename) { 1023 pnv->initrd_base = INITRD_LOAD_ADDR; 1024 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 1025 pnv->initrd_base, INITRD_MAX_SIZE); 1026 if (pnv->initrd_size < 0) { 1027 error_report("Could not load initial ram disk '%s'", 1028 machine->initrd_filename); 1029 exit(1); 1030 } 1031 } 1032 1033 /* load dtb if passed */ 1034 if (machine->dtb) { 1035 int fdt_size; 1036 1037 warn_report("with manually passed dtb, some options like '-append'" 1038 " will get ignored and the dtb passed will be used as-is"); 1039 1040 /* read the file 'machine->dtb', and load it into 'fdt' buffer */ 1041 machine->fdt = load_device_tree(machine->dtb, &fdt_size); 1042 if (!machine->fdt) { 1043 error_report("Could not load dtb '%s'", machine->dtb); 1044 exit(1); 1045 } 1046 } 1047 1048 /* MSIs are supported on this platform */ 1049 msi_nonbroken = true; 1050 1051 /* 1052 * Check compatibility of the specified CPU with the machine 1053 * default. 1054 */ 1055 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 1056 error_report("invalid CPU model '%s' for %s machine", 1057 machine->cpu_type, mc->name); 1058 exit(1); 1059 } 1060 1061 /* Create the processor chips */ 1062 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 1063 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 1064 i, machine->cpu_type); 1065 if (!object_class_by_name(chip_typename)) { 1066 error_report("invalid chip model '%.*s' for %s machine", 1067 i, machine->cpu_type, mc->name); 1068 exit(1); 1069 } 1070 1071 /* Set lpar-per-core mode if lpar-per-thread is not supported */ 1072 if (!pmc->has_lpar_per_thread) { 1073 pnv->lpar_per_core = true; 1074 } 1075 1076 pnv->num_chips = 1077 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 1078 1079 if (pnv->big_core) { 1080 if (machine->smp.threads % 2 == 1) { 1081 error_report("Cannot support %d threads with big-core option " 1082 "because it must be an even number", 1083 machine->smp.threads); 1084 exit(1); 1085 } 1086 max_smt_threads *= 2; 1087 } 1088 1089 if (machine->smp.threads > max_smt_threads) { 1090 error_report("Cannot support more than %d threads/core " 1091 "on %s machine", max_smt_threads, mc->desc); 1092 if (pmc->max_smt_threads == 4) { 1093 error_report("(use big-core=on for 8 threads per core)"); 1094 } 1095 exit(1); 1096 } 1097 1098 if (pnv->big_core) { 1099 /* 1100 * powernv models PnvCore as a SMT4 core. Big-core requires 2xPnvCore 1101 * per core, so adjust topology here. pnv_dt_core() processor 1102 * device-tree and TCG SMT code make the 2 cores appear as one big core 1103 * from software point of view. pnv pervasive models and xscoms tend to 1104 * see the big core as 2 small core halves. 1105 */ 1106 machine->smp.cores *= 2; 1107 machine->smp.threads /= 2; 1108 } 1109 1110 if (!is_power_of_2(machine->smp.threads)) { 1111 error_report("Cannot support %d threads/core on a powernv " 1112 "machine because it must be a power of 2", 1113 machine->smp.threads); 1114 exit(1); 1115 } 1116 1117 /* 1118 * TODO: should we decide on how many chips we can create based 1119 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1120 */ 1121 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1122 error_report("invalid number of chips: '%d'", pnv->num_chips); 1123 error_printf( 1124 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1125 exit(1); 1126 } 1127 1128 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1129 for (i = 0; i < pnv->num_chips; i++) { 1130 char chip_name[32]; 1131 Object *chip = OBJECT(qdev_new(chip_typename)); 1132 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1133 1134 pnv->chips[i] = PNV_CHIP(chip); 1135 1136 /* Distribute RAM among the chips */ 1137 object_property_set_int(chip, "ram-start", chip_ram_start, 1138 &error_fatal); 1139 object_property_set_int(chip, "ram-size", chip_ram_size, 1140 &error_fatal); 1141 chip_ram_start += chip_ram_size; 1142 1143 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1144 object_property_add_child(OBJECT(pnv), chip_name, chip); 1145 object_property_set_int(chip, "chip-id", i, &error_fatal); 1146 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1147 &error_fatal); 1148 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1149 &error_fatal); 1150 object_property_set_bool(chip, "big-core", pnv->big_core, 1151 &error_fatal); 1152 object_property_set_bool(chip, "lpar-per-core", pnv->lpar_per_core, 1153 &error_fatal); 1154 /* 1155 * The POWER8 machine use the XICS interrupt interface. 1156 * Propagate the XICS fabric to the chip and its controllers. 1157 */ 1158 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1159 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1160 } 1161 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1162 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1163 &error_abort); 1164 } 1165 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1166 } 1167 g_free(chip_typename); 1168 1169 /* Instantiate ISA bus on chip 0 */ 1170 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1171 1172 /* Create serial port */ 1173 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1174 1175 /* Create an RTC ISA device too */ 1176 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1177 1178 /* 1179 * Create the machine BMC simulator and the IPMI BT device for 1180 * communication with the BMC 1181 */ 1182 if (defaults_enabled()) { 1183 pnv->bmc = pnv_bmc_create(pnv->pnor); 1184 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1185 } 1186 1187 /* 1188 * The PNOR is mapped on the LPC FW address space by the BMC. 1189 * Since we can not reach the remote BMC machine with LPC memops, 1190 * map it always for now. 1191 */ 1192 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1193 &pnv->pnor->mmio); 1194 1195 /* 1196 * OpenPOWER systems use a IPMI SEL Event message to notify the 1197 * host to powerdown 1198 */ 1199 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1200 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1201 1202 /* 1203 * Create/Connect any machine-specific I2C devices 1204 */ 1205 if (pmc->i2c_init) { 1206 pmc->i2c_init(pnv); 1207 } 1208 } 1209 1210 /* 1211 * 0:21 Reserved - Read as zeros 1212 * 22:24 Chip ID 1213 * 25:28 Core number 1214 * 29:31 Thread ID 1215 */ 1216 static void pnv_get_pir_tir_p8(PnvChip *chip, 1217 uint32_t core_id, uint32_t thread_id, 1218 uint32_t *pir, uint32_t *tir) 1219 { 1220 if (pir) { 1221 *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id; 1222 } 1223 if (tir) { 1224 *tir = thread_id; 1225 } 1226 } 1227 1228 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1229 Error **errp) 1230 { 1231 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1232 Error *local_err = NULL; 1233 Object *obj; 1234 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1235 1236 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1237 if (local_err) { 1238 error_propagate(errp, local_err); 1239 return; 1240 } 1241 1242 pnv_cpu->intc = obj; 1243 } 1244 1245 1246 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1247 { 1248 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1249 1250 icp_reset(ICP(pnv_cpu->intc)); 1251 } 1252 1253 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1254 { 1255 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1256 1257 icp_destroy(ICP(pnv_cpu->intc)); 1258 pnv_cpu->intc = NULL; 1259 } 1260 1261 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1262 GString *buf) 1263 { 1264 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1265 } 1266 1267 /* 1268 * 0:48 Reserved - Read as zeroes 1269 * 49:52 Node ID 1270 * 53:55 Chip ID 1271 * 56 Reserved - Read as zero 1272 * 57:61 Core number 1273 * 62:63 Thread ID 1274 * 1275 * We only care about the lower bits. uint32_t is fine for the moment. 1276 */ 1277 static void pnv_get_pir_tir_p9(PnvChip *chip, 1278 uint32_t core_id, uint32_t thread_id, 1279 uint32_t *pir, uint32_t *tir) 1280 { 1281 if (chip->big_core) { 1282 /* Big-core interleaves thread ID between small-cores */ 1283 thread_id <<= 1; 1284 thread_id |= core_id & 1; 1285 core_id >>= 1; 1286 1287 if (pir) { 1288 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1289 } 1290 } else { 1291 if (pir) { 1292 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1293 } 1294 } 1295 if (tir) { 1296 *tir = thread_id; 1297 } 1298 } 1299 1300 /* 1301 * 0:48 Reserved - Read as zeroes 1302 * 49:52 Node ID 1303 * 53:55 Chip ID 1304 * 56 Reserved - Read as zero 1305 * 57:59 Quad ID 1306 * 60 Core Chiplet Pair ID 1307 * 61:63 Thread/Core Chiplet ID t0-t2 1308 * 1309 * We only care about the lower bits. uint32_t is fine for the moment. 1310 */ 1311 static void pnv_get_pir_tir_p10(PnvChip *chip, 1312 uint32_t core_id, uint32_t thread_id, 1313 uint32_t *pir, uint32_t *tir) 1314 { 1315 if (chip->big_core) { 1316 /* Big-core interleaves thread ID between small-cores */ 1317 thread_id <<= 1; 1318 thread_id |= core_id & 1; 1319 core_id >>= 1; 1320 1321 if (pir) { 1322 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1323 } 1324 } else { 1325 if (pir) { 1326 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1327 } 1328 } 1329 if (tir) { 1330 *tir = thread_id; 1331 } 1332 } 1333 1334 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1335 Error **errp) 1336 { 1337 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1338 Error *local_err = NULL; 1339 Object *obj; 1340 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1341 1342 /* 1343 * The core creates its interrupt presenter but the XIVE interrupt 1344 * controller object is initialized afterwards. Hopefully, it's 1345 * only used at runtime. 1346 */ 1347 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1348 &local_err); 1349 if (local_err) { 1350 error_propagate(errp, local_err); 1351 return; 1352 } 1353 1354 pnv_cpu->intc = obj; 1355 } 1356 1357 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1358 { 1359 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1360 1361 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1362 } 1363 1364 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1365 { 1366 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1367 1368 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1369 pnv_cpu->intc = NULL; 1370 } 1371 1372 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1373 GString *buf) 1374 { 1375 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1376 } 1377 1378 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1379 Error **errp) 1380 { 1381 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1382 Error *local_err = NULL; 1383 Object *obj; 1384 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1385 1386 /* 1387 * The core creates its interrupt presenter but the XIVE2 interrupt 1388 * controller object is initialized afterwards. Hopefully, it's 1389 * only used at runtime. 1390 */ 1391 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1392 &local_err); 1393 if (local_err) { 1394 error_propagate(errp, local_err); 1395 return; 1396 } 1397 1398 pnv_cpu->intc = obj; 1399 } 1400 1401 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1402 { 1403 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1404 1405 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1406 } 1407 1408 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1409 { 1410 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1411 1412 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1413 pnv_cpu->intc = NULL; 1414 } 1415 1416 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1417 GString *buf) 1418 { 1419 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1420 } 1421 1422 /* 1423 * Allowed core identifiers on a POWER8 Processor Chip : 1424 * 1425 * <EX0 reserved> 1426 * EX1 - Venice only 1427 * EX2 - Venice only 1428 * EX3 - Venice only 1429 * EX4 1430 * EX5 1431 * EX6 1432 * <EX7,8 reserved> <reserved> 1433 * EX9 - Venice only 1434 * EX10 - Venice only 1435 * EX11 - Venice only 1436 * EX12 1437 * EX13 1438 * EX14 1439 * <EX15 reserved> 1440 */ 1441 #define POWER8E_CORE_MASK (0x7070ull) 1442 #define POWER8_CORE_MASK (0x7e7eull) 1443 1444 /* 1445 * POWER9 has 24 cores, ids starting at 0x0 1446 */ 1447 #define POWER9_CORE_MASK (0xffffffffffffffull) 1448 1449 1450 #define POWER10_CORE_MASK (0xffffffffffffffull) 1451 1452 static void pnv_chip_power8_instance_init(Object *obj) 1453 { 1454 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1455 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1456 int i; 1457 1458 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1459 (Object **)&chip8->xics, 1460 object_property_allow_set_link, 1461 OBJ_PROP_LINK_STRONG); 1462 1463 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1464 1465 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1466 1467 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1468 1469 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1470 1471 if (defaults_enabled()) { 1472 chip8->num_phbs = pcc->num_phbs; 1473 1474 for (i = 0; i < chip8->num_phbs; i++) { 1475 Object *phb = object_new(TYPE_PNV_PHB); 1476 1477 /* 1478 * We need the chip to parent the PHB to allow the DT 1479 * to build correctly (via pnv_xscom_dt()). 1480 * 1481 * TODO: the PHB should be parented by a PEC device that, at 1482 * this moment, is not modelled powernv8/phb3. 1483 */ 1484 object_property_add_child(obj, "phb[*]", phb); 1485 chip8->phbs[i] = PNV_PHB(phb); 1486 } 1487 } 1488 1489 } 1490 1491 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1492 { 1493 PnvChip *chip = PNV_CHIP(chip8); 1494 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1495 int i, j; 1496 char *name; 1497 1498 name = g_strdup_printf("icp-%x", chip->chip_id); 1499 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1500 g_free(name); 1501 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1502 &chip8->icp_mmio); 1503 1504 /* Map the ICP registers for each thread */ 1505 for (i = 0; i < chip->nr_cores; i++) { 1506 PnvCore *pnv_core = chip->cores[i]; 1507 int core_hwid = CPU_CORE(pnv_core)->core_id; 1508 1509 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1510 uint32_t pir; 1511 PnvICPState *icp; 1512 1513 pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL); 1514 icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1515 1516 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1517 &icp->mmio); 1518 } 1519 } 1520 } 1521 1522 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1523 { 1524 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1525 PnvChip *chip = PNV_CHIP(dev); 1526 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1527 Pnv8Psi *psi8 = &chip8->psi; 1528 Error *local_err = NULL; 1529 int i; 1530 1531 assert(chip8->xics); 1532 1533 /* XSCOM bridge is first */ 1534 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1535 1536 pcc->parent_realize(dev, &local_err); 1537 if (local_err) { 1538 error_propagate(errp, local_err); 1539 return; 1540 } 1541 1542 /* Processor Service Interface (PSI) Host Bridge */ 1543 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1544 &error_fatal); 1545 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1546 OBJECT(chip8->xics), &error_abort); 1547 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1548 return; 1549 } 1550 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1551 &PNV_PSI(psi8)->xscom_regs); 1552 1553 /* Create LPC controller */ 1554 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1555 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1556 1557 chip->fw_mr = &chip8->lpc.isa_fw; 1558 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1559 (uint64_t) PNV_XSCOM_BASE(chip), 1560 PNV_XSCOM_LPC_BASE); 1561 1562 /* 1563 * Interrupt Management Area. This is the memory region holding 1564 * all the Interrupt Control Presenter (ICP) registers 1565 */ 1566 pnv_chip_icp_realize(chip8, &local_err); 1567 if (local_err) { 1568 error_propagate(errp, local_err); 1569 return; 1570 } 1571 1572 /* HOMER (must be created before OCC) */ 1573 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1574 &error_abort); 1575 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1576 return; 1577 } 1578 /* Homer Xscom region */ 1579 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1580 /* Homer RAM region */ 1581 memory_region_add_subregion(get_system_memory(), chip8->homer.base, 1582 &chip8->homer.mem); 1583 1584 /* Create the simplified OCC model */ 1585 object_property_set_link(OBJECT(&chip8->occ), "homer", 1586 OBJECT(&chip8->homer), &error_abort); 1587 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1588 return; 1589 } 1590 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1591 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1592 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1593 1594 /* OCC SRAM model */ 1595 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1596 &chip8->occ.sram_regs); 1597 1598 /* PHB controllers */ 1599 for (i = 0; i < chip8->num_phbs; i++) { 1600 PnvPHB *phb = chip8->phbs[i]; 1601 1602 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1603 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1604 &error_fatal); 1605 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1606 &error_fatal); 1607 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1608 return; 1609 } 1610 } 1611 } 1612 1613 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1614 { 1615 addr &= (PNV_XSCOM_SIZE - 1); 1616 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1617 } 1618 1619 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1620 { 1621 DeviceClass *dc = DEVICE_CLASS(klass); 1622 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1623 1624 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1625 k->cores_mask = POWER8E_CORE_MASK; 1626 k->num_phbs = 3; 1627 k->get_pir_tir = pnv_get_pir_tir_p8; 1628 k->intc_create = pnv_chip_power8_intc_create; 1629 k->intc_reset = pnv_chip_power8_intc_reset; 1630 k->intc_destroy = pnv_chip_power8_intc_destroy; 1631 k->intc_print_info = pnv_chip_power8_intc_print_info; 1632 k->isa_create = pnv_chip_power8_isa_create; 1633 k->dt_populate = pnv_chip_power8_dt_populate; 1634 k->pic_print_info = pnv_chip_power8_pic_print_info; 1635 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1636 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1637 dc->desc = "PowerNV Chip POWER8E"; 1638 1639 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1640 &k->parent_realize); 1641 } 1642 1643 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1644 { 1645 DeviceClass *dc = DEVICE_CLASS(klass); 1646 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1647 1648 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1649 k->cores_mask = POWER8_CORE_MASK; 1650 k->num_phbs = 3; 1651 k->get_pir_tir = pnv_get_pir_tir_p8; 1652 k->intc_create = pnv_chip_power8_intc_create; 1653 k->intc_reset = pnv_chip_power8_intc_reset; 1654 k->intc_destroy = pnv_chip_power8_intc_destroy; 1655 k->intc_print_info = pnv_chip_power8_intc_print_info; 1656 k->isa_create = pnv_chip_power8_isa_create; 1657 k->dt_populate = pnv_chip_power8_dt_populate; 1658 k->pic_print_info = pnv_chip_power8_pic_print_info; 1659 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1660 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1661 dc->desc = "PowerNV Chip POWER8"; 1662 1663 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1664 &k->parent_realize); 1665 } 1666 1667 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1668 { 1669 DeviceClass *dc = DEVICE_CLASS(klass); 1670 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1671 1672 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1673 k->cores_mask = POWER8_CORE_MASK; 1674 k->num_phbs = 4; 1675 k->get_pir_tir = pnv_get_pir_tir_p8; 1676 k->intc_create = pnv_chip_power8_intc_create; 1677 k->intc_reset = pnv_chip_power8_intc_reset; 1678 k->intc_destroy = pnv_chip_power8_intc_destroy; 1679 k->intc_print_info = pnv_chip_power8_intc_print_info; 1680 k->isa_create = pnv_chip_power8nvl_isa_create; 1681 k->dt_populate = pnv_chip_power8_dt_populate; 1682 k->pic_print_info = pnv_chip_power8_pic_print_info; 1683 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1684 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1685 dc->desc = "PowerNV Chip POWER8NVL"; 1686 1687 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1688 &k->parent_realize); 1689 } 1690 1691 static void pnv_chip_power9_instance_init(Object *obj) 1692 { 1693 PnvChip *chip = PNV_CHIP(obj); 1694 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1695 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1696 int i; 1697 1698 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU); 1699 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1700 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1701 "xive-fabric"); 1702 1703 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1704 1705 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1706 1707 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1708 1709 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1710 1711 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1712 1713 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1714 1715 /* Number of PECs is the chip default */ 1716 chip->num_pecs = pcc->num_pecs; 1717 1718 for (i = 0; i < chip->num_pecs; i++) { 1719 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1720 TYPE_PNV_PHB4_PEC); 1721 } 1722 1723 for (i = 0; i < pcc->i2c_num_engines; i++) { 1724 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1725 } 1726 } 1727 1728 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1729 PnvCore *pnv_core, 1730 const char *type) 1731 { 1732 char eq_name[32]; 1733 int core_id = CPU_CORE(pnv_core)->core_id; 1734 1735 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1736 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1737 sizeof(*eq), type, 1738 &error_fatal, NULL); 1739 1740 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1741 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1742 } 1743 1744 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1745 { 1746 PnvChip *chip = PNV_CHIP(chip9); 1747 int i; 1748 1749 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1750 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1751 1752 for (i = 0; i < chip9->nr_quads; i++) { 1753 PnvQuad *eq = &chip9->quads[i]; 1754 1755 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1756 PNV_QUAD_TYPE_NAME("power9")); 1757 1758 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1759 &eq->xscom_regs); 1760 } 1761 } 1762 1763 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1764 { 1765 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1766 int i; 1767 1768 for (i = 0; i < chip->num_pecs; i++) { 1769 PnvPhb4PecState *pec = &chip9->pecs[i]; 1770 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1771 uint32_t pec_cplt_base; 1772 uint32_t pec_nest_base; 1773 uint32_t pec_pci_base; 1774 1775 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1776 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1777 &error_fatal); 1778 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1779 &error_fatal); 1780 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1781 return; 1782 } 1783 1784 pec_cplt_base = pecc->xscom_cplt_base(pec); 1785 pec_nest_base = pecc->xscom_nest_base(pec); 1786 pec_pci_base = pecc->xscom_pci_base(pec); 1787 1788 pnv_xscom_add_subregion(chip, pec_cplt_base, 1789 &pec->nest_pervasive.xscom_ctrl_regs_mr); 1790 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1791 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1792 } 1793 } 1794 1795 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1796 { 1797 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1798 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1799 PnvChip *chip = PNV_CHIP(dev); 1800 Pnv9Psi *psi9 = &chip9->psi; 1801 Error *local_err = NULL; 1802 int i; 1803 1804 /* XSCOM bridge is first */ 1805 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1806 1807 pcc->parent_realize(dev, &local_err); 1808 if (local_err) { 1809 error_propagate(errp, local_err); 1810 return; 1811 } 1812 1813 /* ADU */ 1814 object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc), 1815 &error_abort); 1816 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { 1817 return; 1818 } 1819 pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE, 1820 &chip9->adu.xscom_regs); 1821 1822 pnv_chip_quad_realize(chip9, &local_err); 1823 if (local_err) { 1824 error_propagate(errp, local_err); 1825 return; 1826 } 1827 1828 /* XIVE interrupt controller (POWER9) */ 1829 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1830 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1831 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1832 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1833 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1834 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1835 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1836 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1837 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1838 &error_abort); 1839 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1840 return; 1841 } 1842 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1843 &chip9->xive.xscom_regs); 1844 1845 /* Processor Service Interface (PSI) Host Bridge */ 1846 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1847 &error_fatal); 1848 /* This is the only device with 4k ESB pages */ 1849 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1850 &error_fatal); 1851 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1852 return; 1853 } 1854 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1855 &PNV_PSI(psi9)->xscom_regs); 1856 1857 /* LPC */ 1858 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1859 return; 1860 } 1861 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1862 &chip9->lpc.xscom_regs); 1863 1864 chip->fw_mr = &chip9->lpc.isa_fw; 1865 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1866 (uint64_t) PNV9_LPCM_BASE(chip)); 1867 1868 /* ChipTOD */ 1869 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1870 chip->chip_id == 0, &error_abort); 1871 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1872 chip->chip_id == 1, &error_abort); 1873 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1874 &error_abort); 1875 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1876 return; 1877 } 1878 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1879 &chip9->chiptod.xscom_regs); 1880 1881 /* SBE */ 1882 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1883 return; 1884 } 1885 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1886 &chip9->sbe.xscom_ctrl_regs); 1887 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1888 &chip9->sbe.xscom_mbox_regs); 1889 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1890 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1891 1892 /* HOMER (must be created before OCC) */ 1893 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1894 &error_abort); 1895 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1896 return; 1897 } 1898 /* Homer Xscom region */ 1899 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1900 /* Homer RAM region */ 1901 memory_region_add_subregion(get_system_memory(), chip9->homer.base, 1902 &chip9->homer.mem); 1903 1904 /* Create the simplified OCC model */ 1905 object_property_set_link(OBJECT(&chip9->occ), "homer", 1906 OBJECT(&chip9->homer), &error_abort); 1907 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1908 return; 1909 } 1910 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1911 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1912 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1913 1914 /* OCC SRAM model */ 1915 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1916 &chip9->occ.sram_regs); 1917 1918 /* PEC PHBs */ 1919 pnv_chip_power9_pec_realize(chip, &local_err); 1920 if (local_err) { 1921 error_propagate(errp, local_err); 1922 return; 1923 } 1924 1925 /* 1926 * I2C 1927 */ 1928 for (i = 0; i < pcc->i2c_num_engines; i++) { 1929 Object *obj = OBJECT(&chip9->i2c[i]); 1930 1931 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1932 object_property_set_int(obj, "num-busses", 1933 pcc->i2c_ports_per_engine[i], 1934 &error_fatal); 1935 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1936 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1937 return; 1938 } 1939 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1940 (chip9->i2c[i].engine - 1) * 1941 PNV9_XSCOM_I2CM_SIZE, 1942 &chip9->i2c[i].xscom_regs); 1943 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1944 qdev_get_gpio_in(DEVICE(psi9), 1945 PSIHB9_IRQ_SBE_I2C)); 1946 } 1947 } 1948 1949 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1950 { 1951 addr &= (PNV9_XSCOM_SIZE - 1); 1952 return addr >> 3; 1953 } 1954 1955 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1956 { 1957 DeviceClass *dc = DEVICE_CLASS(klass); 1958 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1959 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1960 1961 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1962 k->cores_mask = POWER9_CORE_MASK; 1963 k->get_pir_tir = pnv_get_pir_tir_p9; 1964 k->intc_create = pnv_chip_power9_intc_create; 1965 k->intc_reset = pnv_chip_power9_intc_reset; 1966 k->intc_destroy = pnv_chip_power9_intc_destroy; 1967 k->intc_print_info = pnv_chip_power9_intc_print_info; 1968 k->isa_create = pnv_chip_power9_isa_create; 1969 k->dt_populate = pnv_chip_power9_dt_populate; 1970 k->pic_print_info = pnv_chip_power9_pic_print_info; 1971 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1972 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1973 dc->desc = "PowerNV Chip POWER9"; 1974 k->num_pecs = PNV9_CHIP_MAX_PEC; 1975 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1976 k->i2c_ports_per_engine = i2c_ports_per_engine; 1977 1978 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1979 &k->parent_realize); 1980 } 1981 1982 static void pnv_chip_power10_instance_init(Object *obj) 1983 { 1984 PnvChip *chip = PNV_CHIP(obj); 1985 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1986 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1987 int i; 1988 1989 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); 1990 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1991 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1992 "xive-fabric"); 1993 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1994 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1995 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1996 TYPE_PNV10_CHIPTOD); 1997 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1998 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1999 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 2000 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 2001 TYPE_PNV_N1_CHIPLET); 2002 2003 chip->num_pecs = pcc->num_pecs; 2004 2005 for (i = 0; i < chip->num_pecs; i++) { 2006 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 2007 TYPE_PNV_PHB5_PEC); 2008 } 2009 2010 for (i = 0; i < pcc->i2c_num_engines; i++) { 2011 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 2012 } 2013 2014 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 2015 object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i], 2016 TYPE_PNV_SPI); 2017 } 2018 } 2019 2020 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 2021 { 2022 PnvChip *chip = PNV_CHIP(chip10); 2023 int i; 2024 2025 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 2026 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 2027 2028 for (i = 0; i < chip10->nr_quads; i++) { 2029 PnvQuad *eq = &chip10->quads[i]; 2030 2031 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 2032 PNV_QUAD_TYPE_NAME("power10")); 2033 2034 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 2035 &eq->xscom_regs); 2036 2037 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 2038 &eq->xscom_qme_regs); 2039 } 2040 } 2041 2042 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 2043 { 2044 Pnv10Chip *chip10 = PNV10_CHIP(chip); 2045 int i; 2046 2047 for (i = 0; i < chip->num_pecs; i++) { 2048 PnvPhb4PecState *pec = &chip10->pecs[i]; 2049 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 2050 uint32_t pec_cplt_base; 2051 uint32_t pec_nest_base; 2052 uint32_t pec_pci_base; 2053 2054 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 2055 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 2056 &error_fatal); 2057 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 2058 &error_fatal); 2059 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 2060 return; 2061 } 2062 2063 pec_cplt_base = pecc->xscom_cplt_base(pec); 2064 pec_nest_base = pecc->xscom_nest_base(pec); 2065 pec_pci_base = pecc->xscom_pci_base(pec); 2066 2067 pnv_xscom_add_subregion(chip, pec_cplt_base, 2068 &pec->nest_pervasive.xscom_ctrl_regs_mr); 2069 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 2070 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 2071 } 2072 } 2073 2074 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 2075 { 2076 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 2077 PnvChip *chip = PNV_CHIP(dev); 2078 Pnv10Chip *chip10 = PNV10_CHIP(dev); 2079 Error *local_err = NULL; 2080 int i; 2081 2082 /* XSCOM bridge is first */ 2083 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 2084 2085 pcc->parent_realize(dev, &local_err); 2086 if (local_err) { 2087 error_propagate(errp, local_err); 2088 return; 2089 } 2090 2091 /* ADU */ 2092 object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc), 2093 &error_abort); 2094 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { 2095 return; 2096 } 2097 pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE, 2098 &chip10->adu.xscom_regs); 2099 2100 pnv_chip_power10_quad_realize(chip10, &local_err); 2101 if (local_err) { 2102 error_propagate(errp, local_err); 2103 return; 2104 } 2105 2106 /* XIVE2 interrupt controller (POWER10) */ 2107 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 2108 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 2109 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 2110 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 2111 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 2112 PNV10_XIVE2_END_BASE(chip), &error_fatal); 2113 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 2114 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 2115 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 2116 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 2117 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 2118 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 2119 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 2120 &error_abort); 2121 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 2122 return; 2123 } 2124 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 2125 &chip10->xive.xscom_regs); 2126 2127 /* Processor Service Interface (PSI) Host Bridge */ 2128 object_property_set_int(OBJECT(&chip10->psi), "bar", 2129 PNV10_PSIHB_BASE(chip), &error_fatal); 2130 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 2131 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 2132 &error_fatal); 2133 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 2134 return; 2135 } 2136 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 2137 &PNV_PSI(&chip10->psi)->xscom_regs); 2138 2139 /* LPC */ 2140 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 2141 return; 2142 } 2143 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 2144 &chip10->lpc.xscom_regs); 2145 2146 chip->fw_mr = &chip10->lpc.isa_fw; 2147 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 2148 (uint64_t) PNV10_LPCM_BASE(chip)); 2149 2150 /* ChipTOD */ 2151 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 2152 chip->chip_id == 0, &error_abort); 2153 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 2154 chip->chip_id == 1, &error_abort); 2155 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 2156 &error_abort); 2157 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 2158 return; 2159 } 2160 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 2161 &chip10->chiptod.xscom_regs); 2162 2163 /* HOMER (must be created before OCC) */ 2164 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2165 &error_abort); 2166 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2167 return; 2168 } 2169 /* Homer Xscom region */ 2170 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2171 &chip10->homer.pba_regs); 2172 /* Homer RAM region */ 2173 memory_region_add_subregion(get_system_memory(), chip10->homer.base, 2174 &chip10->homer.mem); 2175 2176 /* Create the simplified OCC model */ 2177 object_property_set_link(OBJECT(&chip10->occ), "homer", 2178 OBJECT(&chip10->homer), &error_abort); 2179 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 2180 return; 2181 } 2182 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 2183 &chip10->occ.xscom_regs); 2184 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 2185 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 2186 2187 /* OCC SRAM model */ 2188 memory_region_add_subregion(get_system_memory(), 2189 PNV10_OCC_SENSOR_BASE(chip), 2190 &chip10->occ.sram_regs); 2191 2192 /* SBE */ 2193 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 2194 return; 2195 } 2196 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2197 &chip10->sbe.xscom_ctrl_regs); 2198 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2199 &chip10->sbe.xscom_mbox_regs); 2200 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2201 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2202 2203 /* N1 chiplet */ 2204 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2205 return; 2206 } 2207 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2208 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2209 2210 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2211 &chip10->n1_chiplet.xscom_pb_eq_mr); 2212 2213 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2214 &chip10->n1_chiplet.xscom_pb_es_mr); 2215 2216 /* PHBs */ 2217 pnv_chip_power10_phb_realize(chip, &local_err); 2218 if (local_err) { 2219 error_propagate(errp, local_err); 2220 return; 2221 } 2222 2223 2224 /* 2225 * I2C 2226 */ 2227 for (i = 0; i < pcc->i2c_num_engines; i++) { 2228 Object *obj = OBJECT(&chip10->i2c[i]); 2229 2230 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2231 object_property_set_int(obj, "num-busses", 2232 pcc->i2c_ports_per_engine[i], 2233 &error_fatal); 2234 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2235 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2236 return; 2237 } 2238 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2239 (chip10->i2c[i].engine - 1) * 2240 PNV10_XSCOM_I2CM_SIZE, 2241 &chip10->i2c[i].xscom_regs); 2242 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2243 qdev_get_gpio_in(DEVICE(&chip10->psi), 2244 PSIHB9_IRQ_SBE_I2C)); 2245 } 2246 /* PIB SPI Controller */ 2247 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 2248 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num", 2249 i, &error_fatal); 2250 /* pib_spic[2] connected to 25csm04 which implements 1 byte transfer */ 2251 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "transfer_len", 2252 (i == 2) ? 1 : 4, &error_fatal); 2253 if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT 2254 (&chip10->pib_spic[i])), errp)) { 2255 return; 2256 } 2257 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE + 2258 i * PNV10_XSCOM_PIB_SPIC_SIZE, 2259 &chip10->pib_spic[i].xscom_spic_regs); 2260 } 2261 } 2262 2263 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2264 { 2265 int i; 2266 for (i = 0; i < pnv->num_chips; i++) { 2267 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2268 2269 /* 2270 * Add a PCA9552 I2C device for PCIe hotplug control 2271 * to engine 2, bus 1, address 0x63 2272 */ 2273 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2274 "pca9552", 0x63); 2275 2276 /* 2277 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2278 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2279 * after hypervisor code sets a SLOTx_EN pin high. 2280 */ 2281 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2282 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2283 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2284 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2285 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2286 2287 /* 2288 * Add a PCA9554 I2C device for cable card presence detection 2289 * to engine 2, bus 1, address 0x25 2290 */ 2291 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2292 } 2293 } 2294 2295 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2296 { 2297 addr &= (PNV10_XSCOM_SIZE - 1); 2298 return addr >> 3; 2299 } 2300 2301 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2302 { 2303 DeviceClass *dc = DEVICE_CLASS(klass); 2304 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2305 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2306 2307 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */ 2308 k->cores_mask = POWER10_CORE_MASK; 2309 k->get_pir_tir = pnv_get_pir_tir_p10; 2310 k->intc_create = pnv_chip_power10_intc_create; 2311 k->intc_reset = pnv_chip_power10_intc_reset; 2312 k->intc_destroy = pnv_chip_power10_intc_destroy; 2313 k->intc_print_info = pnv_chip_power10_intc_print_info; 2314 k->isa_create = pnv_chip_power10_isa_create; 2315 k->dt_populate = pnv_chip_power10_dt_populate; 2316 k->pic_print_info = pnv_chip_power10_pic_print_info; 2317 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2318 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2319 dc->desc = "PowerNV Chip POWER10"; 2320 k->num_pecs = PNV10_CHIP_MAX_PEC; 2321 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2322 k->i2c_ports_per_engine = i2c_ports_per_engine; 2323 2324 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2325 &k->parent_realize); 2326 } 2327 2328 static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip, 2329 Error **errp) 2330 { 2331 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2332 int cores_max; 2333 2334 /* 2335 * No custom mask for this chip, let's use the default one from * 2336 * the chip class 2337 */ 2338 if (!chip->cores_mask) { 2339 chip->cores_mask = pcc->cores_mask; 2340 } 2341 2342 /* filter alien core ids ! some are reserved */ 2343 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2344 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2345 chip->cores_mask); 2346 return; 2347 } 2348 chip->cores_mask &= pcc->cores_mask; 2349 2350 /* Ensure small-cores a paired up in big-core mode */ 2351 if (pnv->big_core) { 2352 uint64_t even_cores = chip->cores_mask & 0x5555555555555555ULL; 2353 uint64_t odd_cores = chip->cores_mask & 0xaaaaaaaaaaaaaaaaULL; 2354 2355 if (even_cores ^ (odd_cores >> 1)) { 2356 error_setg(errp, "warning: unpaired cores in big-core mode !"); 2357 return; 2358 } 2359 } 2360 2361 /* now that we have a sane layout, let check the number of cores */ 2362 cores_max = ctpop64(chip->cores_mask); 2363 if (chip->nr_cores > cores_max) { 2364 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2365 cores_max); 2366 return; 2367 } 2368 } 2369 2370 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2371 { 2372 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2373 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(pnv); 2374 Error *error = NULL; 2375 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2376 const char *typename = pnv_chip_core_typename(chip); 2377 int i, core_hwid; 2378 2379 if (!object_class_by_name(typename)) { 2380 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2381 return; 2382 } 2383 2384 /* Cores */ 2385 pnv_chip_core_sanitize(pnv, chip, &error); 2386 if (error) { 2387 error_propagate(errp, error); 2388 return; 2389 } 2390 2391 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2392 2393 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2394 && (i < chip->nr_cores); core_hwid++) { 2395 char core_name[32]; 2396 PnvCore *pnv_core; 2397 uint64_t xscom_core_base; 2398 2399 if (!(chip->cores_mask & (1ull << core_hwid))) { 2400 continue; 2401 } 2402 2403 pnv_core = PNV_CORE(object_new(typename)); 2404 2405 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2406 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2407 chip->cores[i] = pnv_core; 2408 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2409 chip->nr_threads, &error_fatal); 2410 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2411 core_hwid, &error_fatal); 2412 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2413 &error_fatal); 2414 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2415 &error_fatal); 2416 object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core, 2417 &error_fatal); 2418 object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core", 2419 pmc->quirk_tb_big_core, &error_fatal); 2420 object_property_set_bool(OBJECT(pnv_core), "lpar-per-core", 2421 chip->lpar_per_core, &error_fatal); 2422 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2423 &error_abort); 2424 2425 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2426 2427 /* Each core has an XSCOM MMIO region */ 2428 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2429 2430 pnv_xscom_add_subregion(chip, xscom_core_base, 2431 &pnv_core->xscom_regs); 2432 i++; 2433 } 2434 } 2435 2436 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2437 { 2438 PnvChip *chip = PNV_CHIP(dev); 2439 Error *error = NULL; 2440 2441 /* Cores */ 2442 pnv_chip_core_realize(chip, &error); 2443 if (error) { 2444 error_propagate(errp, error); 2445 return; 2446 } 2447 } 2448 2449 static const Property pnv_chip_properties[] = { 2450 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2451 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2452 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2453 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2454 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2455 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2456 DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false), 2457 DEFINE_PROP_BOOL("lpar-per-core", PnvChip, lpar_per_core, false), 2458 }; 2459 2460 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2461 { 2462 DeviceClass *dc = DEVICE_CLASS(klass); 2463 2464 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2465 dc->realize = pnv_chip_realize; 2466 device_class_set_props(dc, pnv_chip_properties); 2467 dc->desc = "PowerNV Chip"; 2468 } 2469 2470 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2471 { 2472 int i; 2473 2474 for (i = 0; i < chip->nr_cores; i++) { 2475 PnvCore *pc = chip->cores[i]; 2476 CPUCore *cc = CPU_CORE(pc); 2477 2478 if (cc->core_id == core_id) { 2479 return pc; 2480 } 2481 } 2482 return NULL; 2483 } 2484 2485 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2486 { 2487 int i, j; 2488 2489 for (i = 0; i < chip->nr_cores; i++) { 2490 PnvCore *pc = chip->cores[i]; 2491 CPUCore *cc = CPU_CORE(pc); 2492 2493 for (j = 0; j < cc->nr_threads; j++) { 2494 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2495 return pc->threads[j]; 2496 } 2497 } 2498 } 2499 return NULL; 2500 } 2501 2502 static void pnv_chip_foreach_cpu(PnvChip *chip, 2503 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque), 2504 void *opaque) 2505 { 2506 int i, j; 2507 2508 for (i = 0; i < chip->nr_cores; i++) { 2509 PnvCore *pc = chip->cores[i]; 2510 2511 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) { 2512 fn(chip, pc->threads[j], opaque); 2513 } 2514 } 2515 } 2516 2517 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2518 { 2519 PnvMachineState *pnv = PNV_MACHINE(xi); 2520 int i, j; 2521 2522 for (i = 0; i < pnv->num_chips; i++) { 2523 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2524 2525 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2526 return &chip8->psi.ics; 2527 } 2528 2529 for (j = 0; j < chip8->num_phbs; j++) { 2530 PnvPHB *phb = chip8->phbs[j]; 2531 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2532 2533 if (ics_valid_irq(&phb3->lsis, irq)) { 2534 return &phb3->lsis; 2535 } 2536 2537 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2538 return ICS(&phb3->msis); 2539 } 2540 } 2541 } 2542 return NULL; 2543 } 2544 2545 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2546 { 2547 int i; 2548 2549 for (i = 0; i < pnv->num_chips; i++) { 2550 PnvChip *chip = pnv->chips[i]; 2551 if (chip->chip_id == chip_id) { 2552 return chip; 2553 } 2554 } 2555 return NULL; 2556 } 2557 2558 static void pnv_ics_resend(XICSFabric *xi) 2559 { 2560 PnvMachineState *pnv = PNV_MACHINE(xi); 2561 int i, j; 2562 2563 for (i = 0; i < pnv->num_chips; i++) { 2564 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2565 2566 ics_resend(&chip8->psi.ics); 2567 2568 for (j = 0; j < chip8->num_phbs; j++) { 2569 PnvPHB *phb = chip8->phbs[j]; 2570 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2571 2572 ics_resend(&phb3->lsis); 2573 ics_resend(ICS(&phb3->msis)); 2574 } 2575 } 2576 } 2577 2578 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2579 { 2580 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2581 2582 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2583 } 2584 2585 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 2586 void *opaque) 2587 { 2588 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); 2589 } 2590 2591 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf) 2592 { 2593 PnvMachineState *pnv = PNV_MACHINE(obj); 2594 int i; 2595 2596 for (i = 0; i < pnv->num_chips; i++) { 2597 PnvChip *chip = pnv->chips[i]; 2598 2599 /* First CPU presenters */ 2600 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf); 2601 2602 /* Then other devices, PHB, PSI, XIVE */ 2603 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); 2604 } 2605 } 2606 2607 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2608 uint8_t nvt_blk, uint32_t nvt_idx, 2609 bool cam_ignore, uint8_t priority, 2610 uint32_t logic_serv, 2611 XiveTCTXMatch *match) 2612 { 2613 PnvMachineState *pnv = PNV_MACHINE(xfb); 2614 int total_count = 0; 2615 int i; 2616 2617 for (i = 0; i < pnv->num_chips; i++) { 2618 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2619 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2620 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2621 int count; 2622 2623 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2624 priority, logic_serv, match); 2625 2626 if (count < 0) { 2627 return count; 2628 } 2629 2630 total_count += count; 2631 } 2632 2633 return total_count; 2634 } 2635 2636 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2637 uint8_t nvt_blk, uint32_t nvt_idx, 2638 bool cam_ignore, uint8_t priority, 2639 uint32_t logic_serv, 2640 XiveTCTXMatch *match) 2641 { 2642 PnvMachineState *pnv = PNV_MACHINE(xfb); 2643 int total_count = 0; 2644 int i; 2645 2646 for (i = 0; i < pnv->num_chips; i++) { 2647 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2648 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2649 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2650 int count; 2651 2652 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2653 priority, logic_serv, match); 2654 2655 if (count < 0) { 2656 return count; 2657 } 2658 2659 total_count += count; 2660 } 2661 2662 return total_count; 2663 } 2664 2665 static bool pnv_machine_get_big_core(Object *obj, Error **errp) 2666 { 2667 PnvMachineState *pnv = PNV_MACHINE(obj); 2668 return pnv->big_core; 2669 } 2670 2671 static void pnv_machine_set_big_core(Object *obj, bool value, Error **errp) 2672 { 2673 PnvMachineState *pnv = PNV_MACHINE(obj); 2674 pnv->big_core = value; 2675 } 2676 2677 static bool pnv_machine_get_lpar_per_core(Object *obj, Error **errp) 2678 { 2679 PnvMachineState *pnv = PNV_MACHINE(obj); 2680 return pnv->lpar_per_core; 2681 } 2682 2683 static void pnv_machine_set_lpar_per_core(Object *obj, bool value, Error **errp) 2684 { 2685 PnvMachineState *pnv = PNV_MACHINE(obj); 2686 pnv->lpar_per_core = value; 2687 } 2688 2689 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2690 { 2691 PnvMachineState *pnv = PNV_MACHINE(obj); 2692 2693 return !!pnv->fw_load_addr; 2694 } 2695 2696 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2697 { 2698 PnvMachineState *pnv = PNV_MACHINE(obj); 2699 2700 if (value) { 2701 pnv->fw_load_addr = 0x8000000; 2702 } 2703 } 2704 2705 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2706 { 2707 MachineClass *mc = MACHINE_CLASS(oc); 2708 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2709 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2710 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2711 2712 static GlobalProperty phb_compat[] = { 2713 { TYPE_PNV_PHB, "version", "3" }, 2714 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2715 }; 2716 2717 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2718 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2719 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2720 2721 xic->icp_get = pnv_icp_get; 2722 xic->ics_get = pnv_ics_get; 2723 xic->ics_resend = pnv_ics_resend; 2724 2725 pmc->compat = compat; 2726 pmc->compat_size = sizeof(compat); 2727 pmc->max_smt_threads = 8; 2728 /* POWER8 is always lpar-per-core mode */ 2729 pmc->has_lpar_per_thread = false; 2730 2731 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2732 } 2733 2734 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2735 { 2736 MachineClass *mc = MACHINE_CLASS(oc); 2737 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2738 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2739 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2740 2741 static GlobalProperty phb_compat[] = { 2742 { TYPE_PNV_PHB, "version", "4" }, 2743 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2744 }; 2745 2746 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2747 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2748 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2749 2750 xfc->match_nvt = pnv_match_nvt; 2751 2752 pmc->compat = compat; 2753 pmc->compat_size = sizeof(compat); 2754 pmc->max_smt_threads = 4; 2755 pmc->has_lpar_per_thread = true; 2756 pmc->dt_power_mgt = pnv_dt_power_mgt; 2757 2758 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2759 2760 object_class_property_add_bool(oc, "big-core", 2761 pnv_machine_get_big_core, 2762 pnv_machine_set_big_core); 2763 object_class_property_set_description(oc, "big-core", 2764 "Use big-core (aka fused-core) mode"); 2765 2766 object_class_property_add_bool(oc, "lpar-per-core", 2767 pnv_machine_get_lpar_per_core, 2768 pnv_machine_set_lpar_per_core); 2769 object_class_property_set_description(oc, "lpar-per-core", 2770 "Use 1 LPAR per core mode"); 2771 } 2772 2773 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2774 { 2775 MachineClass *mc = MACHINE_CLASS(oc); 2776 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2777 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2778 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2779 2780 static GlobalProperty phb_compat[] = { 2781 { TYPE_PNV_PHB, "version", "5" }, 2782 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2783 }; 2784 2785 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2786 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2787 2788 mc->alias = "powernv"; 2789 2790 pmc->compat = compat; 2791 pmc->compat_size = sizeof(compat); 2792 pmc->max_smt_threads = 4; 2793 pmc->has_lpar_per_thread = true; 2794 pmc->quirk_tb_big_core = true; 2795 pmc->dt_power_mgt = pnv_dt_power_mgt; 2796 2797 xfc->match_nvt = pnv10_xive_match_nvt; 2798 2799 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2800 } 2801 2802 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2803 { 2804 MachineClass *mc = MACHINE_CLASS(oc); 2805 2806 pnv_machine_p10_common_class_init(oc, data); 2807 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2808 2809 /* 2810 * This is the parent of POWER10 Rainier class, so properies go here 2811 * rather than common init (which would add them to both parent and 2812 * child which is invalid). 2813 */ 2814 object_class_property_add_bool(oc, "big-core", 2815 pnv_machine_get_big_core, 2816 pnv_machine_set_big_core); 2817 object_class_property_set_description(oc, "big-core", 2818 "Use big-core (aka fused-core) mode"); 2819 2820 object_class_property_add_bool(oc, "lpar-per-core", 2821 pnv_machine_get_lpar_per_core, 2822 pnv_machine_set_lpar_per_core); 2823 object_class_property_set_description(oc, "lpar-per-core", 2824 "Use 1 LPAR per core mode"); 2825 } 2826 2827 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2828 { 2829 MachineClass *mc = MACHINE_CLASS(oc); 2830 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2831 2832 pnv_machine_p10_common_class_init(oc, data); 2833 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2834 pmc->i2c_init = pnv_rainier_i2c_init; 2835 } 2836 2837 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2838 { 2839 CPUPPCState *env = cpu_env(cs); 2840 2841 cpu_synchronize_state(cs); 2842 ppc_cpu_do_system_reset(cs); 2843 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2844 /* 2845 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2846 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2847 * (PPC_BIT(43)). 2848 */ 2849 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2850 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2851 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2852 } 2853 } else { 2854 /* 2855 * For non-powersave system resets, SRR1[42:45] are defined to be 2856 * implementation-dependent. The POWER9 User Manual specifies that 2857 * an external (SCOM driven, which may come from a BMC nmi command or 2858 * another CPU requesting a NMI IPI) system reset exception should be 2859 * 0b0010 (PPC_BIT(44)). 2860 */ 2861 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2862 } 2863 if (arg.host_int == 1) { 2864 cpu_resume(cs); 2865 } 2866 } 2867 2868 /* 2869 * Send a SRESET (NMI) interrupt to the CPU, and resume execution if it was 2870 * paused. 2871 */ 2872 void pnv_cpu_do_nmi_resume(CPUState *cs) 2873 { 2874 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(1)); 2875 } 2876 2877 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque) 2878 { 2879 async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(0)); 2880 } 2881 2882 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2883 { 2884 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2885 int i; 2886 2887 for (i = 0; i < pnv->num_chips; i++) { 2888 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL); 2889 } 2890 } 2891 2892 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2893 { 2894 MachineClass *mc = MACHINE_CLASS(oc); 2895 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2896 NMIClass *nc = NMI_CLASS(oc); 2897 2898 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2899 mc->init = pnv_init; 2900 mc->reset = pnv_reset; 2901 mc->max_cpus = MAX_CPUS; 2902 /* Pnv provides a AHCI device for storage */ 2903 mc->block_default_type = IF_IDE; 2904 mc->no_parallel = 1; 2905 mc->default_boot_order = NULL; 2906 /* 2907 * RAM defaults to less than 2048 for 32-bit hosts, and large 2908 * enough to fit the maximum initrd size at it's load address 2909 */ 2910 mc->default_ram_size = 1 * GiB; 2911 mc->default_ram_id = "pnv.ram"; 2912 ispc->print_info = pnv_pic_print_info; 2913 nc->nmi_monitor_handler = pnv_nmi; 2914 2915 object_class_property_add_bool(oc, "hb-mode", 2916 pnv_machine_get_hb, pnv_machine_set_hb); 2917 object_class_property_set_description(oc, "hb-mode", 2918 "Use a hostboot like boot loader"); 2919 } 2920 2921 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2922 { \ 2923 .name = type, \ 2924 .class_init = class_initfn, \ 2925 .parent = TYPE_PNV8_CHIP, \ 2926 } 2927 2928 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2929 { \ 2930 .name = type, \ 2931 .class_init = class_initfn, \ 2932 .parent = TYPE_PNV9_CHIP, \ 2933 } 2934 2935 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2936 { \ 2937 .name = type, \ 2938 .class_init = class_initfn, \ 2939 .parent = TYPE_PNV10_CHIP, \ 2940 } 2941 2942 static const TypeInfo types[] = { 2943 { 2944 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2945 .parent = MACHINE_TYPE_NAME("powernv10"), 2946 .class_init = pnv_machine_p10_rainier_class_init, 2947 }, 2948 { 2949 .name = MACHINE_TYPE_NAME("powernv10"), 2950 .parent = TYPE_PNV_MACHINE, 2951 .class_init = pnv_machine_power10_class_init, 2952 .interfaces = (InterfaceInfo[]) { 2953 { TYPE_XIVE_FABRIC }, 2954 { }, 2955 }, 2956 }, 2957 { 2958 .name = MACHINE_TYPE_NAME("powernv9"), 2959 .parent = TYPE_PNV_MACHINE, 2960 .class_init = pnv_machine_power9_class_init, 2961 .interfaces = (InterfaceInfo[]) { 2962 { TYPE_XIVE_FABRIC }, 2963 { }, 2964 }, 2965 }, 2966 { 2967 .name = MACHINE_TYPE_NAME("powernv8"), 2968 .parent = TYPE_PNV_MACHINE, 2969 .class_init = pnv_machine_power8_class_init, 2970 .interfaces = (InterfaceInfo[]) { 2971 { TYPE_XICS_FABRIC }, 2972 { }, 2973 }, 2974 }, 2975 { 2976 .name = TYPE_PNV_MACHINE, 2977 .parent = TYPE_MACHINE, 2978 .abstract = true, 2979 .instance_size = sizeof(PnvMachineState), 2980 .class_init = pnv_machine_class_init, 2981 .class_size = sizeof(PnvMachineClass), 2982 .interfaces = (InterfaceInfo[]) { 2983 { TYPE_INTERRUPT_STATS_PROVIDER }, 2984 { TYPE_NMI }, 2985 { }, 2986 }, 2987 }, 2988 { 2989 .name = TYPE_PNV_CHIP, 2990 .parent = TYPE_SYS_BUS_DEVICE, 2991 .class_init = pnv_chip_class_init, 2992 .instance_size = sizeof(PnvChip), 2993 .class_size = sizeof(PnvChipClass), 2994 .abstract = true, 2995 }, 2996 2997 /* 2998 * P10 chip and variants 2999 */ 3000 { 3001 .name = TYPE_PNV10_CHIP, 3002 .parent = TYPE_PNV_CHIP, 3003 .instance_init = pnv_chip_power10_instance_init, 3004 .instance_size = sizeof(Pnv10Chip), 3005 }, 3006 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 3007 3008 /* 3009 * P9 chip and variants 3010 */ 3011 { 3012 .name = TYPE_PNV9_CHIP, 3013 .parent = TYPE_PNV_CHIP, 3014 .instance_init = pnv_chip_power9_instance_init, 3015 .instance_size = sizeof(Pnv9Chip), 3016 }, 3017 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 3018 3019 /* 3020 * P8 chip and variants 3021 */ 3022 { 3023 .name = TYPE_PNV8_CHIP, 3024 .parent = TYPE_PNV_CHIP, 3025 .instance_init = pnv_chip_power8_instance_init, 3026 .instance_size = sizeof(Pnv8Chip), 3027 }, 3028 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 3029 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 3030 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 3031 pnv_chip_power8nvl_class_init), 3032 }; 3033 3034 DEFINE_TYPES(types) 3035