1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci-host/pnv_phb.h" 47 48 #include "hw/ppc/xics.h" 49 #include "hw/qdev-properties.h" 50 #include "hw/ppc/pnv_xscom.h" 51 #include "hw/ppc/pnv_pnor.h" 52 53 #include "hw/isa/isa.h" 54 #include "hw/char/serial.h" 55 #include "hw/rtc/mc146818rtc.h" 56 57 #include <libfdt.h> 58 59 #define FDT_MAX_SIZE (1 * MiB) 60 61 #define FW_FILE_NAME "skiboot.lid" 62 #define FW_LOAD_ADDR 0x0 63 #define FW_MAX_SIZE (16 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x20000000 66 #define KERNEL_MAX_SIZE (128 * MiB) 67 #define INITRD_LOAD_ADDR 0x28000000 68 #define INITRD_MAX_SIZE (128 * MiB) 69 70 static const char *pnv_chip_core_typename(const PnvChip *o) 71 { 72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 75 const char *core_type = object_class_get_name(object_class_by_name(s)); 76 g_free(s); 77 return core_type; 78 } 79 80 /* 81 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 82 * 4 * 4 sockets * 12 cores * 8 threads = 1536 83 * Let's make it 2^11 84 */ 85 #define MAX_CPUS 2048 86 87 /* 88 * Memory nodes are created by hostboot, one for each range of memory 89 * that has a different "affinity". In practice, it means one range 90 * per chip. 91 */ 92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 93 { 94 char *mem_name; 95 uint64_t mem_reg_property[2]; 96 int off; 97 98 mem_reg_property[0] = cpu_to_be64(start); 99 mem_reg_property[1] = cpu_to_be64(size); 100 101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 102 off = fdt_add_subnode(fdt, 0, mem_name); 103 g_free(mem_name); 104 105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 107 sizeof(mem_reg_property)))); 108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 109 } 110 111 static int get_cpus_node(void *fdt) 112 { 113 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 114 115 if (cpus_offset < 0) { 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 117 if (cpus_offset) { 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 120 } 121 } 122 _FDT(cpus_offset); 123 return cpus_offset; 124 } 125 126 /* 127 * The PowerNV cores (and threads) need to use real HW ids and not an 128 * incremental index like it has been done on other platforms. This HW 129 * id is stored in the CPU PIR, it is used to create cpu nodes in the 130 * device tree, used in XSCOM to address cores and in interrupt 131 * servers. 132 */ 133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 134 { 135 PowerPCCPU *cpu = pc->threads[0]; 136 CPUState *cs = CPU(cpu); 137 DeviceClass *dc = DEVICE_GET_CLASS(cs); 138 int smt_threads = CPU_CORE(pc)->nr_threads; 139 CPUPPCState *env = &cpu->env; 140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 141 uint32_t servers_prop[smt_threads]; 142 int i; 143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 144 0xffffffff, 0xffffffff}; 145 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 146 uint32_t cpufreq = 1000000000; 147 uint32_t page_sizes_prop[64]; 148 size_t page_sizes_prop_size; 149 const uint8_t pa_features[] = { 24, 0, 150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 154 int offset; 155 char *nodename; 156 int cpus_offset = get_cpus_node(fdt); 157 158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 159 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 160 _FDT(offset); 161 g_free(nodename); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 175 env->icache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 177 env->icache_line_size))); 178 179 if (pcc->l1_dcache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 181 pcc->l1_dcache_size))); 182 } else { 183 warn_report("Unknown L1 dcache size for cpu"); 184 } 185 if (pcc->l1_icache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 187 pcc->l1_icache_size))); 188 } else { 189 warn_report("Unknown L1 icache size for cpu"); 190 } 191 192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 195 cpu->hash64_opts->slb_size))); 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 198 199 if (ppc_has_spr(cpu, SPR_PURR)) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 201 } 202 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 205 segs, sizeof(segs)))); 206 } 207 208 /* 209 * Advertise VMX/VSX (vector extensions) if available 210 * 0 / no property == no vector extensions 211 * 1 == VMX / Altivec available 212 * 2 == VSX available 213 */ 214 if (env->insns_flags & PPC_ALTIVEC) { 215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 216 217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 218 } 219 220 /* 221 * Advertise DFP (Decimal Floating Point) if available 222 * 0 / no property == no DFP 223 * 1 == DFP available 224 */ 225 if (env->insns_flags2 & PPC2_DFP) { 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 227 } 228 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 230 sizeof(page_sizes_prop)); 231 if (page_sizes_prop_size) { 232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 233 page_sizes_prop, page_sizes_prop_size))); 234 } 235 236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 237 pa_features, sizeof(pa_features)))); 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pc->pir + i); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(servers_prop)))); 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 248 uint32_t nr_threads) 249 { 250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 251 char *name; 252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 253 uint32_t irange[2], i, rsize; 254 uint64_t *reg; 255 int offset; 256 257 irange[0] = cpu_to_be32(pir); 258 irange[1] = cpu_to_be32(nr_threads); 259 260 rsize = sizeof(uint64_t) * 2 * nr_threads; 261 reg = g_malloc(rsize); 262 for (i = 0; i < nr_threads; i++) { 263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 264 reg[i * 2 + 1] = cpu_to_be64(0x1000); 265 } 266 267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 268 offset = fdt_add_subnode(fdt, 0, name); 269 _FDT(offset); 270 g_free(name); 271 272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 274 _FDT((fdt_setprop_string(fdt, offset, "device_type", 275 "PowerPC-External-Interrupt-Presentation"))); 276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 278 irange, sizeof(irange)))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 281 g_free(reg); 282 } 283 284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 285 { 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 287 int i; 288 289 pnv_dt_xscom(chip, fdt, 0, 290 cpu_to_be64(PNV_XSCOM_BASE(chip)), 291 cpu_to_be64(PNV_XSCOM_SIZE), 292 compat, sizeof(compat)); 293 294 for (i = 0; i < chip->nr_cores; i++) { 295 PnvCore *pnv_core = chip->cores[i]; 296 297 pnv_dt_core(chip, pnv_core, fdt); 298 299 /* Interrupt Control Presenters (ICP). One per core. */ 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 301 } 302 303 if (chip->ram_size) { 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 305 } 306 } 307 308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 309 { 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 311 int i; 312 313 pnv_dt_xscom(chip, fdt, 0, 314 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 315 cpu_to_be64(PNV9_XSCOM_SIZE), 316 compat, sizeof(compat)); 317 318 for (i = 0; i < chip->nr_cores; i++) { 319 PnvCore *pnv_core = chip->cores[i]; 320 321 pnv_dt_core(chip, pnv_core, fdt); 322 } 323 324 if (chip->ram_size) { 325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 326 } 327 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 329 } 330 331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 332 { 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 334 int i; 335 336 pnv_dt_xscom(chip, fdt, 0, 337 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 338 cpu_to_be64(PNV10_XSCOM_SIZE), 339 compat, sizeof(compat)); 340 341 for (i = 0; i < chip->nr_cores; i++) { 342 PnvCore *pnv_core = chip->cores[i]; 343 344 pnv_dt_core(chip, pnv_core, fdt); 345 } 346 347 if (chip->ram_size) { 348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 349 } 350 351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 352 } 353 354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 355 { 356 uint32_t io_base = d->ioport_id; 357 uint32_t io_regs[] = { 358 cpu_to_be32(1), 359 cpu_to_be32(io_base), 360 cpu_to_be32(2) 361 }; 362 char *name; 363 int node; 364 365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 366 node = fdt_add_subnode(fdt, lpc_off, name); 367 _FDT(node); 368 g_free(name); 369 370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 372 } 373 374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 375 { 376 const char compatible[] = "ns16550\0pnpPNP,501"; 377 uint32_t io_base = d->ioport_id; 378 uint32_t io_regs[] = { 379 cpu_to_be32(1), 380 cpu_to_be32(io_base), 381 cpu_to_be32(8) 382 }; 383 uint32_t irq; 384 char *name; 385 int node; 386 387 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 388 389 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 390 node = fdt_add_subnode(fdt, lpc_off, name); 391 _FDT(node); 392 g_free(name); 393 394 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 395 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 396 sizeof(compatible)))); 397 398 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 399 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 400 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 401 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 402 fdt_get_phandle(fdt, lpc_off)))); 403 404 /* This is needed by Linux */ 405 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 406 } 407 408 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 409 { 410 const char compatible[] = "bt\0ipmi-bt"; 411 uint32_t io_base; 412 uint32_t io_regs[] = { 413 cpu_to_be32(1), 414 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 415 cpu_to_be32(3) 416 }; 417 uint32_t irq; 418 char *name; 419 int node; 420 421 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 422 io_regs[1] = cpu_to_be32(io_base); 423 424 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 425 426 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 427 node = fdt_add_subnode(fdt, lpc_off, name); 428 _FDT(node); 429 g_free(name); 430 431 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 432 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 433 sizeof(compatible)))); 434 435 /* Mark it as reserved to avoid Linux trying to claim it */ 436 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 437 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 438 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 439 fdt_get_phandle(fdt, lpc_off)))); 440 } 441 442 typedef struct ForeachPopulateArgs { 443 void *fdt; 444 int offset; 445 } ForeachPopulateArgs; 446 447 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 448 { 449 ForeachPopulateArgs *args = opaque; 450 ISADevice *d = ISA_DEVICE(dev); 451 452 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 453 pnv_dt_rtc(d, args->fdt, args->offset); 454 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 455 pnv_dt_serial(d, args->fdt, args->offset); 456 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 457 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 458 } else { 459 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 460 d->ioport_id); 461 } 462 463 return 0; 464 } 465 466 /* 467 * The default LPC bus of a multichip system is on chip 0. It's 468 * recognized by the firmware (skiboot) using a "primary" property. 469 */ 470 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 471 { 472 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 473 ForeachPopulateArgs args = { 474 .fdt = fdt, 475 .offset = isa_offset, 476 }; 477 uint32_t phandle; 478 479 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 480 481 phandle = qemu_fdt_alloc_phandle(fdt); 482 assert(phandle > 0); 483 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 484 485 /* 486 * ISA devices are not necessarily parented to the ISA bus so we 487 * can not use object_child_foreach() 488 */ 489 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 490 &args); 491 } 492 493 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 494 { 495 int off; 496 497 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 498 off = fdt_add_subnode(fdt, off, "power-mgt"); 499 500 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 501 } 502 503 static void *pnv_dt_create(MachineState *machine) 504 { 505 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 506 PnvMachineState *pnv = PNV_MACHINE(machine); 507 void *fdt; 508 char *buf; 509 int off; 510 int i; 511 512 fdt = g_malloc0(FDT_MAX_SIZE); 513 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 514 515 /* /qemu node */ 516 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 517 518 /* Root node */ 519 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 520 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 521 _FDT((fdt_setprop_string(fdt, 0, "model", 522 "IBM PowerNV (emulated by qemu)"))); 523 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 524 525 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 526 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 527 if (qemu_uuid_set) { 528 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 529 } 530 g_free(buf); 531 532 off = fdt_add_subnode(fdt, 0, "chosen"); 533 if (machine->kernel_cmdline) { 534 _FDT((fdt_setprop_string(fdt, off, "bootargs", 535 machine->kernel_cmdline))); 536 } 537 538 if (pnv->initrd_size) { 539 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 540 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 541 542 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 543 &start_prop, sizeof(start_prop)))); 544 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 545 &end_prop, sizeof(end_prop)))); 546 } 547 548 /* Populate device tree for each chip */ 549 for (i = 0; i < pnv->num_chips; i++) { 550 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 551 } 552 553 /* Populate ISA devices on chip 0 */ 554 pnv_dt_isa(pnv, fdt); 555 556 if (pnv->bmc) { 557 pnv_dt_bmc_sensors(pnv->bmc, fdt); 558 } 559 560 /* Create an extra node for power management on machines that support it */ 561 if (pmc->dt_power_mgt) { 562 pmc->dt_power_mgt(pnv, fdt); 563 } 564 565 return fdt; 566 } 567 568 static void pnv_powerdown_notify(Notifier *n, void *opaque) 569 { 570 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 571 572 if (pnv->bmc) { 573 pnv_bmc_powerdown(pnv->bmc); 574 } 575 } 576 577 static void pnv_reset(MachineState *machine) 578 { 579 PnvMachineState *pnv = PNV_MACHINE(machine); 580 IPMIBmc *bmc; 581 void *fdt; 582 583 qemu_devices_reset(); 584 585 /* 586 * The machine should provide by default an internal BMC simulator. 587 * If not, try to use the BMC device that was provided on the command 588 * line. 589 */ 590 bmc = pnv_bmc_find(&error_fatal); 591 if (!pnv->bmc) { 592 if (!bmc) { 593 if (!qtest_enabled()) { 594 warn_report("machine has no BMC device. Use '-device " 595 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 596 "to define one"); 597 } 598 } else { 599 pnv_bmc_set_pnor(bmc, pnv->pnor); 600 pnv->bmc = bmc; 601 } 602 } 603 604 fdt = pnv_dt_create(machine); 605 606 /* Pack resulting tree */ 607 _FDT((fdt_pack(fdt))); 608 609 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 610 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 611 612 g_free(fdt); 613 } 614 615 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 616 { 617 Pnv8Chip *chip8 = PNV8_CHIP(chip); 618 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 619 620 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 621 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 622 } 623 624 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 625 { 626 Pnv8Chip *chip8 = PNV8_CHIP(chip); 627 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 628 629 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 630 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 631 } 632 633 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 634 { 635 Pnv9Chip *chip9 = PNV9_CHIP(chip); 636 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 637 638 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 639 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 640 } 641 642 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 643 { 644 Pnv10Chip *chip10 = PNV10_CHIP(chip); 645 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 646 647 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 648 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 649 } 650 651 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 652 { 653 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 654 } 655 656 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 657 { 658 Pnv8Chip *chip8 = PNV8_CHIP(chip); 659 int i; 660 661 ics_pic_print_info(&chip8->psi.ics, mon); 662 663 for (i = 0; i < chip8->num_phbs; i++) { 664 PnvPHB *phb = &chip8->phbs[i]; 665 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 666 667 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 668 ics_pic_print_info(&phb3->lsis, mon); 669 } 670 } 671 672 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 673 { 674 Monitor *mon = opaque; 675 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 676 677 if (!phb) { 678 return 0; 679 } 680 681 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon); 682 683 return 0; 684 } 685 686 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 687 { 688 Pnv9Chip *chip9 = PNV9_CHIP(chip); 689 690 pnv_xive_pic_print_info(&chip9->xive, mon); 691 pnv_psi_pic_print_info(&chip9->psi, mon); 692 693 object_child_foreach_recursive(OBJECT(chip), 694 pnv_chip_power9_pic_print_info_child, mon); 695 } 696 697 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 698 uint32_t core_id) 699 { 700 return PNV_XSCOM_EX_BASE(core_id); 701 } 702 703 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 704 uint32_t core_id) 705 { 706 return PNV9_XSCOM_EC_BASE(core_id); 707 } 708 709 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 710 uint32_t core_id) 711 { 712 return PNV10_XSCOM_EC_BASE(core_id); 713 } 714 715 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 716 { 717 PowerPCCPUClass *ppc_default = 718 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 719 PowerPCCPUClass *ppc = 720 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 721 722 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 723 } 724 725 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 726 { 727 ISADevice *dev = isa_new("isa-ipmi-bt"); 728 729 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 730 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 731 isa_realize_and_unref(dev, bus, &error_fatal); 732 } 733 734 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 735 { 736 Pnv10Chip *chip10 = PNV10_CHIP(chip); 737 738 pnv_xive2_pic_print_info(&chip10->xive, mon); 739 pnv_psi_pic_print_info(&chip10->psi, mon); 740 741 object_child_foreach_recursive(OBJECT(chip), 742 pnv_chip_power9_pic_print_info_child, mon); 743 } 744 745 /* Always give the first 1GB to chip 0 else we won't boot */ 746 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 747 { 748 MachineState *machine = MACHINE(pnv); 749 uint64_t ram_per_chip; 750 751 assert(machine->ram_size >= 1 * GiB); 752 753 ram_per_chip = machine->ram_size / pnv->num_chips; 754 if (ram_per_chip >= 1 * GiB) { 755 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 756 } 757 758 assert(pnv->num_chips > 1); 759 760 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 761 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 762 } 763 764 static void pnv_init(MachineState *machine) 765 { 766 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 767 PnvMachineState *pnv = PNV_MACHINE(machine); 768 MachineClass *mc = MACHINE_GET_CLASS(machine); 769 char *fw_filename; 770 long fw_size; 771 uint64_t chip_ram_start = 0; 772 int i; 773 char *chip_typename; 774 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 775 DeviceState *dev; 776 777 if (kvm_enabled()) { 778 error_report("The powernv machine does not work with KVM acceleration"); 779 exit(EXIT_FAILURE); 780 } 781 782 /* allocate RAM */ 783 if (machine->ram_size < mc->default_ram_size) { 784 char *sz = size_to_str(mc->default_ram_size); 785 error_report("Invalid RAM size, should be bigger than %s", sz); 786 g_free(sz); 787 exit(EXIT_FAILURE); 788 } 789 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 790 791 /* 792 * Create our simple PNOR device 793 */ 794 dev = qdev_new(TYPE_PNV_PNOR); 795 if (pnor) { 796 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 797 } 798 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 799 pnv->pnor = PNV_PNOR(dev); 800 801 /* load skiboot firmware */ 802 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 803 if (!fw_filename) { 804 error_report("Could not find OPAL firmware '%s'", bios_name); 805 exit(1); 806 } 807 808 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 809 if (fw_size < 0) { 810 error_report("Could not load OPAL firmware '%s'", fw_filename); 811 exit(1); 812 } 813 g_free(fw_filename); 814 815 /* load kernel */ 816 if (machine->kernel_filename) { 817 long kernel_size; 818 819 kernel_size = load_image_targphys(machine->kernel_filename, 820 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 821 if (kernel_size < 0) { 822 error_report("Could not load kernel '%s'", 823 machine->kernel_filename); 824 exit(1); 825 } 826 } 827 828 /* load initrd */ 829 if (machine->initrd_filename) { 830 pnv->initrd_base = INITRD_LOAD_ADDR; 831 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 832 pnv->initrd_base, INITRD_MAX_SIZE); 833 if (pnv->initrd_size < 0) { 834 error_report("Could not load initial ram disk '%s'", 835 machine->initrd_filename); 836 exit(1); 837 } 838 } 839 840 /* MSIs are supported on this platform */ 841 msi_nonbroken = true; 842 843 /* 844 * Check compatibility of the specified CPU with the machine 845 * default. 846 */ 847 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 848 error_report("invalid CPU model '%s' for %s machine", 849 machine->cpu_type, mc->name); 850 exit(1); 851 } 852 853 /* Create the processor chips */ 854 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 855 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 856 i, machine->cpu_type); 857 if (!object_class_by_name(chip_typename)) { 858 error_report("invalid chip model '%.*s' for %s machine", 859 i, machine->cpu_type, mc->name); 860 exit(1); 861 } 862 863 pnv->num_chips = 864 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 865 /* 866 * TODO: should we decide on how many chips we can create based 867 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 868 */ 869 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 870 error_report("invalid number of chips: '%d'", pnv->num_chips); 871 error_printf( 872 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 873 exit(1); 874 } 875 876 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 877 for (i = 0; i < pnv->num_chips; i++) { 878 char chip_name[32]; 879 Object *chip = OBJECT(qdev_new(chip_typename)); 880 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 881 882 pnv->chips[i] = PNV_CHIP(chip); 883 884 /* Distribute RAM among the chips */ 885 object_property_set_int(chip, "ram-start", chip_ram_start, 886 &error_fatal); 887 object_property_set_int(chip, "ram-size", chip_ram_size, 888 &error_fatal); 889 chip_ram_start += chip_ram_size; 890 891 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 892 object_property_add_child(OBJECT(pnv), chip_name, chip); 893 object_property_set_int(chip, "chip-id", i, &error_fatal); 894 object_property_set_int(chip, "nr-cores", machine->smp.cores, 895 &error_fatal); 896 object_property_set_int(chip, "nr-threads", machine->smp.threads, 897 &error_fatal); 898 /* 899 * The POWER8 machine use the XICS interrupt interface. 900 * Propagate the XICS fabric to the chip and its controllers. 901 */ 902 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 903 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 904 } 905 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 906 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 907 &error_abort); 908 } 909 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 910 } 911 g_free(chip_typename); 912 913 /* Instantiate ISA bus on chip 0 */ 914 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 915 916 /* Create serial port */ 917 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 918 919 /* Create an RTC ISA device too */ 920 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 921 922 /* 923 * Create the machine BMC simulator and the IPMI BT device for 924 * communication with the BMC 925 */ 926 if (defaults_enabled()) { 927 pnv->bmc = pnv_bmc_create(pnv->pnor); 928 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 929 } 930 931 /* 932 * The PNOR is mapped on the LPC FW address space by the BMC. 933 * Since we can not reach the remote BMC machine with LPC memops, 934 * map it always for now. 935 */ 936 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 937 &pnv->pnor->mmio); 938 939 /* 940 * OpenPOWER systems use a IPMI SEL Event message to notify the 941 * host to powerdown 942 */ 943 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 944 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 945 } 946 947 /* 948 * 0:21 Reserved - Read as zeros 949 * 22:24 Chip ID 950 * 25:28 Core number 951 * 29:31 Thread ID 952 */ 953 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 954 { 955 return (chip->chip_id << 7) | (core_id << 3); 956 } 957 958 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 959 Error **errp) 960 { 961 Pnv8Chip *chip8 = PNV8_CHIP(chip); 962 Error *local_err = NULL; 963 Object *obj; 964 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 965 966 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 967 if (local_err) { 968 error_propagate(errp, local_err); 969 return; 970 } 971 972 pnv_cpu->intc = obj; 973 } 974 975 976 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 977 { 978 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 979 980 icp_reset(ICP(pnv_cpu->intc)); 981 } 982 983 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 984 { 985 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 986 987 icp_destroy(ICP(pnv_cpu->intc)); 988 pnv_cpu->intc = NULL; 989 } 990 991 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 992 Monitor *mon) 993 { 994 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 995 } 996 997 /* 998 * 0:48 Reserved - Read as zeroes 999 * 49:52 Node ID 1000 * 53:55 Chip ID 1001 * 56 Reserved - Read as zero 1002 * 57:61 Core number 1003 * 62:63 Thread ID 1004 * 1005 * We only care about the lower bits. uint32_t is fine for the moment. 1006 */ 1007 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 1008 { 1009 return (chip->chip_id << 8) | (core_id << 2); 1010 } 1011 1012 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1013 { 1014 return (chip->chip_id << 8) | (core_id << 2); 1015 } 1016 1017 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1018 Error **errp) 1019 { 1020 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1021 Error *local_err = NULL; 1022 Object *obj; 1023 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1024 1025 /* 1026 * The core creates its interrupt presenter but the XIVE interrupt 1027 * controller object is initialized afterwards. Hopefully, it's 1028 * only used at runtime. 1029 */ 1030 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1031 &local_err); 1032 if (local_err) { 1033 error_propagate(errp, local_err); 1034 return; 1035 } 1036 1037 pnv_cpu->intc = obj; 1038 } 1039 1040 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1041 { 1042 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1043 1044 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1045 } 1046 1047 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1048 { 1049 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1050 1051 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1052 pnv_cpu->intc = NULL; 1053 } 1054 1055 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1056 Monitor *mon) 1057 { 1058 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1059 } 1060 1061 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1062 Error **errp) 1063 { 1064 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1065 Error *local_err = NULL; 1066 Object *obj; 1067 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1068 1069 /* 1070 * The core creates its interrupt presenter but the XIVE2 interrupt 1071 * controller object is initialized afterwards. Hopefully, it's 1072 * only used at runtime. 1073 */ 1074 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1075 &local_err); 1076 if (local_err) { 1077 error_propagate(errp, local_err); 1078 return; 1079 } 1080 1081 pnv_cpu->intc = obj; 1082 } 1083 1084 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1085 { 1086 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1087 1088 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1089 } 1090 1091 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1092 { 1093 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1094 1095 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1096 pnv_cpu->intc = NULL; 1097 } 1098 1099 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1100 Monitor *mon) 1101 { 1102 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1103 } 1104 1105 /* 1106 * Allowed core identifiers on a POWER8 Processor Chip : 1107 * 1108 * <EX0 reserved> 1109 * EX1 - Venice only 1110 * EX2 - Venice only 1111 * EX3 - Venice only 1112 * EX4 1113 * EX5 1114 * EX6 1115 * <EX7,8 reserved> <reserved> 1116 * EX9 - Venice only 1117 * EX10 - Venice only 1118 * EX11 - Venice only 1119 * EX12 1120 * EX13 1121 * EX14 1122 * <EX15 reserved> 1123 */ 1124 #define POWER8E_CORE_MASK (0x7070ull) 1125 #define POWER8_CORE_MASK (0x7e7eull) 1126 1127 /* 1128 * POWER9 has 24 cores, ids starting at 0x0 1129 */ 1130 #define POWER9_CORE_MASK (0xffffffffffffffull) 1131 1132 1133 #define POWER10_CORE_MASK (0xffffffffffffffull) 1134 1135 static void pnv_chip_power8_instance_init(Object *obj) 1136 { 1137 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1138 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1139 int i; 1140 1141 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1142 (Object **)&chip8->xics, 1143 object_property_allow_set_link, 1144 OBJ_PROP_LINK_STRONG); 1145 1146 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1147 1148 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1149 1150 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1151 1152 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1153 1154 chip8->num_phbs = pcc->num_phbs; 1155 1156 for (i = 0; i < chip8->num_phbs; i++) { 1157 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB); 1158 } 1159 1160 } 1161 1162 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1163 { 1164 PnvChip *chip = PNV_CHIP(chip8); 1165 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1166 int i, j; 1167 char *name; 1168 1169 name = g_strdup_printf("icp-%x", chip->chip_id); 1170 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1171 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1172 g_free(name); 1173 1174 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1175 1176 /* Map the ICP registers for each thread */ 1177 for (i = 0; i < chip->nr_cores; i++) { 1178 PnvCore *pnv_core = chip->cores[i]; 1179 int core_hwid = CPU_CORE(pnv_core)->core_id; 1180 1181 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1182 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1183 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1184 1185 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1186 &icp->mmio); 1187 } 1188 } 1189 } 1190 1191 /* 1192 * Attach a root port device. 1193 * 1194 * 'index' will be used both as a PCIE slot value and to calculate 1195 * QOM id. 'chip_id' is going to be used as PCIE chassis for the 1196 * root port. 1197 */ 1198 void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id) 1199 { 1200 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT); 1201 g_autofree char *default_id = g_strdup_printf("%s[%d]", 1202 TYPE_PNV_PHB_ROOT_PORT, 1203 index); 1204 const char *dev_id = DEVICE(root)->id; 1205 1206 object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id, 1207 OBJECT(root)); 1208 1209 /* Set unique chassis/slot values for the root port */ 1210 qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id); 1211 qdev_prop_set_uint16(DEVICE(root), "slot", index); 1212 1213 pci_realize_and_unref(root, pci->bus, &error_fatal); 1214 } 1215 1216 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1217 { 1218 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1219 PnvChip *chip = PNV_CHIP(dev); 1220 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1221 Pnv8Psi *psi8 = &chip8->psi; 1222 Error *local_err = NULL; 1223 int i; 1224 1225 assert(chip8->xics); 1226 1227 /* XSCOM bridge is first */ 1228 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1229 if (local_err) { 1230 error_propagate(errp, local_err); 1231 return; 1232 } 1233 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1234 1235 pcc->parent_realize(dev, &local_err); 1236 if (local_err) { 1237 error_propagate(errp, local_err); 1238 return; 1239 } 1240 1241 /* Processor Service Interface (PSI) Host Bridge */ 1242 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1243 &error_fatal); 1244 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1245 OBJECT(chip8->xics), &error_abort); 1246 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1247 return; 1248 } 1249 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1250 &PNV_PSI(psi8)->xscom_regs); 1251 1252 /* Create LPC controller */ 1253 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1254 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1255 1256 chip->fw_mr = &chip8->lpc.isa_fw; 1257 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1258 (uint64_t) PNV_XSCOM_BASE(chip), 1259 PNV_XSCOM_LPC_BASE); 1260 1261 /* 1262 * Interrupt Management Area. This is the memory region holding 1263 * all the Interrupt Control Presenter (ICP) registers 1264 */ 1265 pnv_chip_icp_realize(chip8, &local_err); 1266 if (local_err) { 1267 error_propagate(errp, local_err); 1268 return; 1269 } 1270 1271 /* Create the simplified OCC model */ 1272 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1273 return; 1274 } 1275 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1276 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1277 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); 1278 1279 /* OCC SRAM model */ 1280 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1281 &chip8->occ.sram_regs); 1282 1283 /* HOMER */ 1284 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1285 &error_abort); 1286 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1287 return; 1288 } 1289 /* Homer Xscom region */ 1290 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1291 1292 /* Homer mmio region */ 1293 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1294 &chip8->homer.regs); 1295 1296 /* PHB controllers */ 1297 for (i = 0; i < chip8->num_phbs; i++) { 1298 PnvPHB *phb = &chip8->phbs[i]; 1299 1300 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1301 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1302 &error_fatal); 1303 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1304 &error_fatal); 1305 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1306 return; 1307 } 1308 } 1309 } 1310 1311 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1312 { 1313 addr &= (PNV_XSCOM_SIZE - 1); 1314 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1315 } 1316 1317 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1318 { 1319 DeviceClass *dc = DEVICE_CLASS(klass); 1320 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1321 1322 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1323 k->cores_mask = POWER8E_CORE_MASK; 1324 k->num_phbs = 3; 1325 k->core_pir = pnv_chip_core_pir_p8; 1326 k->intc_create = pnv_chip_power8_intc_create; 1327 k->intc_reset = pnv_chip_power8_intc_reset; 1328 k->intc_destroy = pnv_chip_power8_intc_destroy; 1329 k->intc_print_info = pnv_chip_power8_intc_print_info; 1330 k->isa_create = pnv_chip_power8_isa_create; 1331 k->dt_populate = pnv_chip_power8_dt_populate; 1332 k->pic_print_info = pnv_chip_power8_pic_print_info; 1333 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1334 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1335 dc->desc = "PowerNV Chip POWER8E"; 1336 1337 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1338 &k->parent_realize); 1339 } 1340 1341 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1342 { 1343 DeviceClass *dc = DEVICE_CLASS(klass); 1344 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1345 1346 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1347 k->cores_mask = POWER8_CORE_MASK; 1348 k->num_phbs = 3; 1349 k->core_pir = pnv_chip_core_pir_p8; 1350 k->intc_create = pnv_chip_power8_intc_create; 1351 k->intc_reset = pnv_chip_power8_intc_reset; 1352 k->intc_destroy = pnv_chip_power8_intc_destroy; 1353 k->intc_print_info = pnv_chip_power8_intc_print_info; 1354 k->isa_create = pnv_chip_power8_isa_create; 1355 k->dt_populate = pnv_chip_power8_dt_populate; 1356 k->pic_print_info = pnv_chip_power8_pic_print_info; 1357 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1358 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1359 dc->desc = "PowerNV Chip POWER8"; 1360 1361 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1362 &k->parent_realize); 1363 } 1364 1365 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1366 { 1367 DeviceClass *dc = DEVICE_CLASS(klass); 1368 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1369 1370 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1371 k->cores_mask = POWER8_CORE_MASK; 1372 k->num_phbs = 4; 1373 k->core_pir = pnv_chip_core_pir_p8; 1374 k->intc_create = pnv_chip_power8_intc_create; 1375 k->intc_reset = pnv_chip_power8_intc_reset; 1376 k->intc_destroy = pnv_chip_power8_intc_destroy; 1377 k->intc_print_info = pnv_chip_power8_intc_print_info; 1378 k->isa_create = pnv_chip_power8nvl_isa_create; 1379 k->dt_populate = pnv_chip_power8_dt_populate; 1380 k->pic_print_info = pnv_chip_power8_pic_print_info; 1381 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1382 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1383 dc->desc = "PowerNV Chip POWER8NVL"; 1384 1385 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1386 &k->parent_realize); 1387 } 1388 1389 static void pnv_chip_power9_instance_init(Object *obj) 1390 { 1391 PnvChip *chip = PNV_CHIP(obj); 1392 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1393 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1394 int i; 1395 1396 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1397 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1398 "xive-fabric"); 1399 1400 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1401 1402 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1403 1404 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1405 1406 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1407 1408 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1409 1410 /* Number of PECs is the chip default */ 1411 chip->num_pecs = pcc->num_pecs; 1412 1413 for (i = 0; i < chip->num_pecs; i++) { 1414 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1415 TYPE_PNV_PHB4_PEC); 1416 } 1417 } 1418 1419 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1420 PnvCore *pnv_core) 1421 { 1422 char eq_name[32]; 1423 int core_id = CPU_CORE(pnv_core)->core_id; 1424 1425 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1426 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1427 sizeof(*eq), TYPE_PNV_QUAD, 1428 &error_fatal, NULL); 1429 1430 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1431 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1432 } 1433 1434 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1435 { 1436 PnvChip *chip = PNV_CHIP(chip9); 1437 int i; 1438 1439 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1440 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1441 1442 for (i = 0; i < chip9->nr_quads; i++) { 1443 PnvQuad *eq = &chip9->quads[i]; 1444 1445 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1446 1447 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1448 &eq->xscom_regs); 1449 } 1450 } 1451 1452 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1453 { 1454 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1455 int i; 1456 1457 for (i = 0; i < chip->num_pecs; i++) { 1458 PnvPhb4PecState *pec = &chip9->pecs[i]; 1459 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1460 uint32_t pec_nest_base; 1461 uint32_t pec_pci_base; 1462 1463 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1464 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1465 &error_fatal); 1466 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1467 &error_fatal); 1468 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1469 return; 1470 } 1471 1472 pec_nest_base = pecc->xscom_nest_base(pec); 1473 pec_pci_base = pecc->xscom_pci_base(pec); 1474 1475 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1476 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1477 } 1478 } 1479 1480 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1481 { 1482 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1483 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1484 PnvChip *chip = PNV_CHIP(dev); 1485 Pnv9Psi *psi9 = &chip9->psi; 1486 Error *local_err = NULL; 1487 1488 /* XSCOM bridge is first */ 1489 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1490 if (local_err) { 1491 error_propagate(errp, local_err); 1492 return; 1493 } 1494 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1495 1496 pcc->parent_realize(dev, &local_err); 1497 if (local_err) { 1498 error_propagate(errp, local_err); 1499 return; 1500 } 1501 1502 pnv_chip_quad_realize(chip9, &local_err); 1503 if (local_err) { 1504 error_propagate(errp, local_err); 1505 return; 1506 } 1507 1508 /* XIVE interrupt controller (POWER9) */ 1509 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1510 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1511 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1512 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1513 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1514 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1515 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1516 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1517 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1518 &error_abort); 1519 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1520 return; 1521 } 1522 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1523 &chip9->xive.xscom_regs); 1524 1525 /* Processor Service Interface (PSI) Host Bridge */ 1526 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1527 &error_fatal); 1528 /* This is the only device with 4k ESB pages */ 1529 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1530 &error_fatal); 1531 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1532 return; 1533 } 1534 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1535 &PNV_PSI(psi9)->xscom_regs); 1536 1537 /* LPC */ 1538 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1539 return; 1540 } 1541 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1542 &chip9->lpc.xscom_regs); 1543 1544 chip->fw_mr = &chip9->lpc.isa_fw; 1545 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1546 (uint64_t) PNV9_LPCM_BASE(chip)); 1547 1548 /* Create the simplified OCC model */ 1549 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1550 return; 1551 } 1552 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1553 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1554 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); 1555 1556 /* OCC SRAM model */ 1557 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1558 &chip9->occ.sram_regs); 1559 1560 /* SBE */ 1561 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1562 return; 1563 } 1564 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1565 &chip9->sbe.xscom_ctrl_regs); 1566 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1567 &chip9->sbe.xscom_mbox_regs); 1568 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1569 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU)); 1570 1571 /* HOMER */ 1572 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1573 &error_abort); 1574 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1575 return; 1576 } 1577 /* Homer Xscom region */ 1578 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1579 1580 /* Homer mmio region */ 1581 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1582 &chip9->homer.regs); 1583 1584 /* PEC PHBs */ 1585 pnv_chip_power9_pec_realize(chip, &local_err); 1586 if (local_err) { 1587 error_propagate(errp, local_err); 1588 return; 1589 } 1590 } 1591 1592 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1593 { 1594 addr &= (PNV9_XSCOM_SIZE - 1); 1595 return addr >> 3; 1596 } 1597 1598 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1599 { 1600 DeviceClass *dc = DEVICE_CLASS(klass); 1601 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1602 1603 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1604 k->cores_mask = POWER9_CORE_MASK; 1605 k->core_pir = pnv_chip_core_pir_p9; 1606 k->intc_create = pnv_chip_power9_intc_create; 1607 k->intc_reset = pnv_chip_power9_intc_reset; 1608 k->intc_destroy = pnv_chip_power9_intc_destroy; 1609 k->intc_print_info = pnv_chip_power9_intc_print_info; 1610 k->isa_create = pnv_chip_power9_isa_create; 1611 k->dt_populate = pnv_chip_power9_dt_populate; 1612 k->pic_print_info = pnv_chip_power9_pic_print_info; 1613 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1614 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1615 dc->desc = "PowerNV Chip POWER9"; 1616 k->num_pecs = PNV9_CHIP_MAX_PEC; 1617 1618 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1619 &k->parent_realize); 1620 } 1621 1622 static void pnv_chip_power10_instance_init(Object *obj) 1623 { 1624 PnvChip *chip = PNV_CHIP(obj); 1625 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1626 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1627 int i; 1628 1629 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1630 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1631 "xive-fabric"); 1632 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1633 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1634 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1635 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1636 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1637 1638 chip->num_pecs = pcc->num_pecs; 1639 1640 for (i = 0; i < chip->num_pecs; i++) { 1641 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1642 TYPE_PNV_PHB5_PEC); 1643 } 1644 } 1645 1646 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1647 { 1648 PnvChip *chip = PNV_CHIP(chip10); 1649 int i; 1650 1651 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1652 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1653 1654 for (i = 0; i < chip10->nr_quads; i++) { 1655 PnvQuad *eq = &chip10->quads[i]; 1656 1657 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1658 1659 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1660 &eq->xscom_regs); 1661 } 1662 } 1663 1664 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1665 { 1666 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1667 int i; 1668 1669 for (i = 0; i < chip->num_pecs; i++) { 1670 PnvPhb4PecState *pec = &chip10->pecs[i]; 1671 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1672 uint32_t pec_nest_base; 1673 uint32_t pec_pci_base; 1674 1675 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1676 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1677 &error_fatal); 1678 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1679 &error_fatal); 1680 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1681 return; 1682 } 1683 1684 pec_nest_base = pecc->xscom_nest_base(pec); 1685 pec_pci_base = pecc->xscom_pci_base(pec); 1686 1687 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1688 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1689 } 1690 } 1691 1692 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1693 { 1694 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1695 PnvChip *chip = PNV_CHIP(dev); 1696 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1697 Error *local_err = NULL; 1698 1699 /* XSCOM bridge is first */ 1700 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1701 if (local_err) { 1702 error_propagate(errp, local_err); 1703 return; 1704 } 1705 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1706 1707 pcc->parent_realize(dev, &local_err); 1708 if (local_err) { 1709 error_propagate(errp, local_err); 1710 return; 1711 } 1712 1713 pnv_chip_power10_quad_realize(chip10, &local_err); 1714 if (local_err) { 1715 error_propagate(errp, local_err); 1716 return; 1717 } 1718 1719 /* XIVE2 interrupt controller (POWER10) */ 1720 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1721 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1722 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1723 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1724 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1725 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1726 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1727 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1728 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1729 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1730 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1731 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1732 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1733 &error_abort); 1734 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1735 return; 1736 } 1737 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1738 &chip10->xive.xscom_regs); 1739 1740 /* Processor Service Interface (PSI) Host Bridge */ 1741 object_property_set_int(OBJECT(&chip10->psi), "bar", 1742 PNV10_PSIHB_BASE(chip), &error_fatal); 1743 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1744 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1745 &error_fatal); 1746 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1747 return; 1748 } 1749 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1750 &PNV_PSI(&chip10->psi)->xscom_regs); 1751 1752 /* LPC */ 1753 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1754 return; 1755 } 1756 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1757 &chip10->lpc.xscom_regs); 1758 1759 chip->fw_mr = &chip10->lpc.isa_fw; 1760 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1761 (uint64_t) PNV10_LPCM_BASE(chip)); 1762 1763 /* Create the simplified OCC model */ 1764 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1765 return; 1766 } 1767 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1768 &chip10->occ.xscom_regs); 1769 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1770 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1771 1772 /* OCC SRAM model */ 1773 memory_region_add_subregion(get_system_memory(), 1774 PNV10_OCC_SENSOR_BASE(chip), 1775 &chip10->occ.sram_regs); 1776 1777 /* SBE */ 1778 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1779 return; 1780 } 1781 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1782 &chip10->sbe.xscom_ctrl_regs); 1783 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 1784 &chip10->sbe.xscom_mbox_regs); 1785 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 1786 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 1787 1788 /* HOMER */ 1789 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1790 &error_abort); 1791 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1792 return; 1793 } 1794 /* Homer Xscom region */ 1795 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1796 &chip10->homer.pba_regs); 1797 1798 /* Homer mmio region */ 1799 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1800 &chip10->homer.regs); 1801 1802 /* PHBs */ 1803 pnv_chip_power10_phb_realize(chip, &local_err); 1804 if (local_err) { 1805 error_propagate(errp, local_err); 1806 return; 1807 } 1808 } 1809 1810 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1811 { 1812 addr &= (PNV10_XSCOM_SIZE - 1); 1813 return addr >> 3; 1814 } 1815 1816 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1817 { 1818 DeviceClass *dc = DEVICE_CLASS(klass); 1819 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1820 1821 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1822 k->cores_mask = POWER10_CORE_MASK; 1823 k->core_pir = pnv_chip_core_pir_p10; 1824 k->intc_create = pnv_chip_power10_intc_create; 1825 k->intc_reset = pnv_chip_power10_intc_reset; 1826 k->intc_destroy = pnv_chip_power10_intc_destroy; 1827 k->intc_print_info = pnv_chip_power10_intc_print_info; 1828 k->isa_create = pnv_chip_power10_isa_create; 1829 k->dt_populate = pnv_chip_power10_dt_populate; 1830 k->pic_print_info = pnv_chip_power10_pic_print_info; 1831 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1832 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1833 dc->desc = "PowerNV Chip POWER10"; 1834 k->num_pecs = PNV10_CHIP_MAX_PEC; 1835 1836 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1837 &k->parent_realize); 1838 } 1839 1840 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1841 { 1842 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1843 int cores_max; 1844 1845 /* 1846 * No custom mask for this chip, let's use the default one from * 1847 * the chip class 1848 */ 1849 if (!chip->cores_mask) { 1850 chip->cores_mask = pcc->cores_mask; 1851 } 1852 1853 /* filter alien core ids ! some are reserved */ 1854 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1855 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1856 chip->cores_mask); 1857 return; 1858 } 1859 chip->cores_mask &= pcc->cores_mask; 1860 1861 /* now that we have a sane layout, let check the number of cores */ 1862 cores_max = ctpop64(chip->cores_mask); 1863 if (chip->nr_cores > cores_max) { 1864 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1865 cores_max); 1866 return; 1867 } 1868 } 1869 1870 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1871 { 1872 Error *error = NULL; 1873 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1874 const char *typename = pnv_chip_core_typename(chip); 1875 int i, core_hwid; 1876 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1877 1878 if (!object_class_by_name(typename)) { 1879 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1880 return; 1881 } 1882 1883 /* Cores */ 1884 pnv_chip_core_sanitize(chip, &error); 1885 if (error) { 1886 error_propagate(errp, error); 1887 return; 1888 } 1889 1890 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1891 1892 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1893 && (i < chip->nr_cores); core_hwid++) { 1894 char core_name[32]; 1895 PnvCore *pnv_core; 1896 uint64_t xscom_core_base; 1897 1898 if (!(chip->cores_mask & (1ull << core_hwid))) { 1899 continue; 1900 } 1901 1902 pnv_core = PNV_CORE(object_new(typename)); 1903 1904 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1905 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1906 chip->cores[i] = pnv_core; 1907 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1908 chip->nr_threads, &error_fatal); 1909 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1910 core_hwid, &error_fatal); 1911 object_property_set_int(OBJECT(pnv_core), "pir", 1912 pcc->core_pir(chip, core_hwid), &error_fatal); 1913 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1914 &error_fatal); 1915 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1916 &error_abort); 1917 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1918 1919 /* Each core has an XSCOM MMIO region */ 1920 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1921 1922 pnv_xscom_add_subregion(chip, xscom_core_base, 1923 &pnv_core->xscom_regs); 1924 i++; 1925 } 1926 } 1927 1928 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1929 { 1930 PnvChip *chip = PNV_CHIP(dev); 1931 Error *error = NULL; 1932 1933 /* Cores */ 1934 pnv_chip_core_realize(chip, &error); 1935 if (error) { 1936 error_propagate(errp, error); 1937 return; 1938 } 1939 } 1940 1941 static Property pnv_chip_properties[] = { 1942 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1943 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1944 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1945 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1946 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1947 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1948 DEFINE_PROP_END_OF_LIST(), 1949 }; 1950 1951 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1952 { 1953 DeviceClass *dc = DEVICE_CLASS(klass); 1954 1955 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1956 dc->realize = pnv_chip_realize; 1957 device_class_set_props(dc, pnv_chip_properties); 1958 dc->desc = "PowerNV Chip"; 1959 } 1960 1961 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1962 { 1963 int i, j; 1964 1965 for (i = 0; i < chip->nr_cores; i++) { 1966 PnvCore *pc = chip->cores[i]; 1967 CPUCore *cc = CPU_CORE(pc); 1968 1969 for (j = 0; j < cc->nr_threads; j++) { 1970 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1971 return pc->threads[j]; 1972 } 1973 } 1974 } 1975 return NULL; 1976 } 1977 1978 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1979 { 1980 PnvMachineState *pnv = PNV_MACHINE(xi); 1981 int i, j; 1982 1983 for (i = 0; i < pnv->num_chips; i++) { 1984 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1985 1986 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1987 return &chip8->psi.ics; 1988 } 1989 1990 for (j = 0; j < chip8->num_phbs; j++) { 1991 PnvPHB *phb = &chip8->phbs[j]; 1992 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 1993 1994 if (ics_valid_irq(&phb3->lsis, irq)) { 1995 return &phb3->lsis; 1996 } 1997 1998 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 1999 return ICS(&phb3->msis); 2000 } 2001 } 2002 } 2003 return NULL; 2004 } 2005 2006 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2007 { 2008 int i; 2009 2010 for (i = 0; i < pnv->num_chips; i++) { 2011 PnvChip *chip = pnv->chips[i]; 2012 if (chip->chip_id == chip_id) { 2013 return chip; 2014 } 2015 } 2016 return NULL; 2017 } 2018 2019 static void pnv_ics_resend(XICSFabric *xi) 2020 { 2021 PnvMachineState *pnv = PNV_MACHINE(xi); 2022 int i, j; 2023 2024 for (i = 0; i < pnv->num_chips; i++) { 2025 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2026 2027 ics_resend(&chip8->psi.ics); 2028 2029 for (j = 0; j < chip8->num_phbs; j++) { 2030 PnvPHB *phb = &chip8->phbs[j]; 2031 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2032 2033 ics_resend(&phb3->lsis); 2034 ics_resend(ICS(&phb3->msis)); 2035 } 2036 } 2037 } 2038 2039 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2040 { 2041 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2042 2043 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2044 } 2045 2046 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2047 Monitor *mon) 2048 { 2049 PnvMachineState *pnv = PNV_MACHINE(obj); 2050 int i; 2051 CPUState *cs; 2052 2053 CPU_FOREACH(cs) { 2054 PowerPCCPU *cpu = POWERPC_CPU(cs); 2055 2056 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2057 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2058 mon); 2059 } 2060 2061 for (i = 0; i < pnv->num_chips; i++) { 2062 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2063 } 2064 } 2065 2066 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2067 uint8_t nvt_blk, uint32_t nvt_idx, 2068 bool cam_ignore, uint8_t priority, 2069 uint32_t logic_serv, 2070 XiveTCTXMatch *match) 2071 { 2072 PnvMachineState *pnv = PNV_MACHINE(xfb); 2073 int total_count = 0; 2074 int i; 2075 2076 for (i = 0; i < pnv->num_chips; i++) { 2077 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2078 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2079 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2080 int count; 2081 2082 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2083 priority, logic_serv, match); 2084 2085 if (count < 0) { 2086 return count; 2087 } 2088 2089 total_count += count; 2090 } 2091 2092 return total_count; 2093 } 2094 2095 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2096 uint8_t nvt_blk, uint32_t nvt_idx, 2097 bool cam_ignore, uint8_t priority, 2098 uint32_t logic_serv, 2099 XiveTCTXMatch *match) 2100 { 2101 PnvMachineState *pnv = PNV_MACHINE(xfb); 2102 int total_count = 0; 2103 int i; 2104 2105 for (i = 0; i < pnv->num_chips; i++) { 2106 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2107 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2108 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2109 int count; 2110 2111 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2112 priority, logic_serv, match); 2113 2114 if (count < 0) { 2115 return count; 2116 } 2117 2118 total_count += count; 2119 } 2120 2121 return total_count; 2122 } 2123 2124 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2125 { 2126 MachineClass *mc = MACHINE_CLASS(oc); 2127 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2128 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2129 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2130 2131 static GlobalProperty phb_compat[] = { 2132 { TYPE_PNV_PHB, "version", "3" }, 2133 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2134 }; 2135 2136 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2137 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2138 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2139 2140 xic->icp_get = pnv_icp_get; 2141 xic->ics_get = pnv_ics_get; 2142 xic->ics_resend = pnv_ics_resend; 2143 2144 pmc->compat = compat; 2145 pmc->compat_size = sizeof(compat); 2146 } 2147 2148 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2149 { 2150 MachineClass *mc = MACHINE_CLASS(oc); 2151 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2152 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2153 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2154 2155 static GlobalProperty phb_compat[] = { 2156 { TYPE_PNV_PHB, "version", "4" }, 2157 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2158 }; 2159 2160 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2161 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 2162 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2163 2164 xfc->match_nvt = pnv_match_nvt; 2165 2166 mc->alias = "powernv"; 2167 2168 pmc->compat = compat; 2169 pmc->compat_size = sizeof(compat); 2170 pmc->dt_power_mgt = pnv_dt_power_mgt; 2171 } 2172 2173 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2174 { 2175 MachineClass *mc = MACHINE_CLASS(oc); 2176 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2177 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2178 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2179 2180 static GlobalProperty phb_compat[] = { 2181 { TYPE_PNV_PHB, "version", "5" }, 2182 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2183 }; 2184 2185 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2186 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2187 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2188 2189 pmc->compat = compat; 2190 pmc->compat_size = sizeof(compat); 2191 pmc->dt_power_mgt = pnv_dt_power_mgt; 2192 2193 xfc->match_nvt = pnv10_xive_match_nvt; 2194 } 2195 2196 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2197 { 2198 PnvMachineState *pnv = PNV_MACHINE(obj); 2199 2200 return !!pnv->fw_load_addr; 2201 } 2202 2203 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2204 { 2205 PnvMachineState *pnv = PNV_MACHINE(obj); 2206 2207 if (value) { 2208 pnv->fw_load_addr = 0x8000000; 2209 } 2210 } 2211 2212 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2213 { 2214 PowerPCCPU *cpu = POWERPC_CPU(cs); 2215 CPUPPCState *env = &cpu->env; 2216 2217 cpu_synchronize_state(cs); 2218 ppc_cpu_do_system_reset(cs); 2219 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2220 /* 2221 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2222 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2223 * (PPC_BIT(43)). 2224 */ 2225 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2226 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2227 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2228 } 2229 } else { 2230 /* 2231 * For non-powersave system resets, SRR1[42:45] are defined to be 2232 * implementation-dependent. The POWER9 User Manual specifies that 2233 * an external (SCOM driven, which may come from a BMC nmi command or 2234 * another CPU requesting a NMI IPI) system reset exception should be 2235 * 0b0010 (PPC_BIT(44)). 2236 */ 2237 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2238 } 2239 } 2240 2241 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2242 { 2243 CPUState *cs; 2244 2245 CPU_FOREACH(cs) { 2246 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2247 } 2248 } 2249 2250 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2251 { 2252 MachineClass *mc = MACHINE_CLASS(oc); 2253 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2254 NMIClass *nc = NMI_CLASS(oc); 2255 2256 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2257 mc->init = pnv_init; 2258 mc->reset = pnv_reset; 2259 mc->max_cpus = MAX_CPUS; 2260 /* Pnv provides a AHCI device for storage */ 2261 mc->block_default_type = IF_IDE; 2262 mc->no_parallel = 1; 2263 mc->default_boot_order = NULL; 2264 /* 2265 * RAM defaults to less than 2048 for 32-bit hosts, and large 2266 * enough to fit the maximum initrd size at it's load address 2267 */ 2268 mc->default_ram_size = 1 * GiB; 2269 mc->default_ram_id = "pnv.ram"; 2270 ispc->print_info = pnv_pic_print_info; 2271 nc->nmi_monitor_handler = pnv_nmi; 2272 2273 object_class_property_add_bool(oc, "hb-mode", 2274 pnv_machine_get_hb, pnv_machine_set_hb); 2275 object_class_property_set_description(oc, "hb-mode", 2276 "Use a hostboot like boot loader"); 2277 } 2278 2279 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2280 { \ 2281 .name = type, \ 2282 .class_init = class_initfn, \ 2283 .parent = TYPE_PNV8_CHIP, \ 2284 } 2285 2286 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2287 { \ 2288 .name = type, \ 2289 .class_init = class_initfn, \ 2290 .parent = TYPE_PNV9_CHIP, \ 2291 } 2292 2293 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2294 { \ 2295 .name = type, \ 2296 .class_init = class_initfn, \ 2297 .parent = TYPE_PNV10_CHIP, \ 2298 } 2299 2300 static const TypeInfo types[] = { 2301 { 2302 .name = MACHINE_TYPE_NAME("powernv10"), 2303 .parent = TYPE_PNV_MACHINE, 2304 .class_init = pnv_machine_power10_class_init, 2305 .interfaces = (InterfaceInfo[]) { 2306 { TYPE_XIVE_FABRIC }, 2307 { }, 2308 }, 2309 }, 2310 { 2311 .name = MACHINE_TYPE_NAME("powernv9"), 2312 .parent = TYPE_PNV_MACHINE, 2313 .class_init = pnv_machine_power9_class_init, 2314 .interfaces = (InterfaceInfo[]) { 2315 { TYPE_XIVE_FABRIC }, 2316 { }, 2317 }, 2318 }, 2319 { 2320 .name = MACHINE_TYPE_NAME("powernv8"), 2321 .parent = TYPE_PNV_MACHINE, 2322 .class_init = pnv_machine_power8_class_init, 2323 .interfaces = (InterfaceInfo[]) { 2324 { TYPE_XICS_FABRIC }, 2325 { }, 2326 }, 2327 }, 2328 { 2329 .name = TYPE_PNV_MACHINE, 2330 .parent = TYPE_MACHINE, 2331 .abstract = true, 2332 .instance_size = sizeof(PnvMachineState), 2333 .class_init = pnv_machine_class_init, 2334 .class_size = sizeof(PnvMachineClass), 2335 .interfaces = (InterfaceInfo[]) { 2336 { TYPE_INTERRUPT_STATS_PROVIDER }, 2337 { TYPE_NMI }, 2338 { }, 2339 }, 2340 }, 2341 { 2342 .name = TYPE_PNV_CHIP, 2343 .parent = TYPE_SYS_BUS_DEVICE, 2344 .class_init = pnv_chip_class_init, 2345 .instance_size = sizeof(PnvChip), 2346 .class_size = sizeof(PnvChipClass), 2347 .abstract = true, 2348 }, 2349 2350 /* 2351 * P10 chip and variants 2352 */ 2353 { 2354 .name = TYPE_PNV10_CHIP, 2355 .parent = TYPE_PNV_CHIP, 2356 .instance_init = pnv_chip_power10_instance_init, 2357 .instance_size = sizeof(Pnv10Chip), 2358 }, 2359 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2360 2361 /* 2362 * P9 chip and variants 2363 */ 2364 { 2365 .name = TYPE_PNV9_CHIP, 2366 .parent = TYPE_PNV_CHIP, 2367 .instance_init = pnv_chip_power9_instance_init, 2368 .instance_size = sizeof(Pnv9Chip), 2369 }, 2370 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2371 2372 /* 2373 * P8 chip and variants 2374 */ 2375 { 2376 .name = TYPE_PNV8_CHIP, 2377 .parent = TYPE_PNV_CHIP, 2378 .instance_init = pnv_chip_power8_instance_init, 2379 .instance_size = sizeof(Pnv8Chip), 2380 }, 2381 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2382 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2383 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2384 pnv_chip_power8nvl_class_init), 2385 }; 2386 2387 DEFINE_TYPES(types) 2388