1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/qtest.h" 25 #include "sysemu/sysemu.h" 26 #include "sysemu/numa.h" 27 #include "sysemu/reset.h" 28 #include "sysemu/runstate.h" 29 #include "sysemu/cpus.h" 30 #include "sysemu/device_tree.h" 31 #include "sysemu/hw_accel.h" 32 #include "target/ppc/cpu.h" 33 #include "qemu/log.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "exec/address-spaces.h" 41 #include "qapi/visitor.h" 42 #include "monitor/monitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 48 #include "hw/ppc/xics.h" 49 #include "hw/qdev-properties.h" 50 #include "hw/ppc/pnv_xscom.h" 51 #include "hw/ppc/pnv_pnor.h" 52 53 #include "hw/isa/isa.h" 54 #include "hw/boards.h" 55 #include "hw/char/serial.h" 56 #include "hw/rtc/mc146818rtc.h" 57 58 #include <libfdt.h> 59 60 #define FDT_MAX_SIZE (1 * MiB) 61 62 #define FW_FILE_NAME "skiboot.lid" 63 #define FW_LOAD_ADDR 0x0 64 #define FW_MAX_SIZE (16 * MiB) 65 66 #define KERNEL_LOAD_ADDR 0x20000000 67 #define KERNEL_MAX_SIZE (256 * MiB) 68 #define INITRD_LOAD_ADDR 0x60000000 69 #define INITRD_MAX_SIZE (256 * MiB) 70 71 static const char *pnv_chip_core_typename(const PnvChip *o) 72 { 73 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 74 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 75 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 76 const char *core_type = object_class_get_name(object_class_by_name(s)); 77 g_free(s); 78 return core_type; 79 } 80 81 /* 82 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 83 * 4 * 4 sockets * 12 cores * 8 threads = 1536 84 * Let's make it 2^11 85 */ 86 #define MAX_CPUS 2048 87 88 /* 89 * Memory nodes are created by hostboot, one for each range of memory 90 * that has a different "affinity". In practice, it means one range 91 * per chip. 92 */ 93 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 94 { 95 char *mem_name; 96 uint64_t mem_reg_property[2]; 97 int off; 98 99 mem_reg_property[0] = cpu_to_be64(start); 100 mem_reg_property[1] = cpu_to_be64(size); 101 102 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 103 off = fdt_add_subnode(fdt, 0, mem_name); 104 g_free(mem_name); 105 106 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 107 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 108 sizeof(mem_reg_property)))); 109 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 110 } 111 112 static int get_cpus_node(void *fdt) 113 { 114 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 115 116 if (cpus_offset < 0) { 117 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 118 if (cpus_offset) { 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 121 } 122 } 123 _FDT(cpus_offset); 124 return cpus_offset; 125 } 126 127 /* 128 * The PowerNV cores (and threads) need to use real HW ids and not an 129 * incremental index like it has been done on other platforms. This HW 130 * id is stored in the CPU PIR, it is used to create cpu nodes in the 131 * device tree, used in XSCOM to address cores and in interrupt 132 * servers. 133 */ 134 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 135 { 136 PowerPCCPU *cpu = pc->threads[0]; 137 CPUState *cs = CPU(cpu); 138 DeviceClass *dc = DEVICE_GET_CLASS(cs); 139 int smt_threads = CPU_CORE(pc)->nr_threads; 140 CPUPPCState *env = &cpu->env; 141 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 142 uint32_t servers_prop[smt_threads]; 143 int i; 144 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 145 0xffffffff, 0xffffffff}; 146 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 147 uint32_t cpufreq = 1000000000; 148 uint32_t page_sizes_prop[64]; 149 size_t page_sizes_prop_size; 150 const uint8_t pa_features[] = { 24, 0, 151 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 152 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 153 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 154 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 155 int offset; 156 char *nodename; 157 int cpus_offset = get_cpus_node(fdt); 158 159 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 160 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 161 _FDT(offset); 162 g_free(nodename); 163 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 167 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 168 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 169 170 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 172 env->dcache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 176 env->icache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 178 env->icache_line_size))); 179 180 if (pcc->l1_dcache_size) { 181 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 182 pcc->l1_dcache_size))); 183 } else { 184 warn_report("Unknown L1 dcache size for cpu"); 185 } 186 if (pcc->l1_icache_size) { 187 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 188 pcc->l1_icache_size))); 189 } else { 190 warn_report("Unknown L1 icache size for cpu"); 191 } 192 193 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 195 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 196 cpu->hash64_opts->slb_size))); 197 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 198 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 199 200 if (env->spr_cb[SPR_PURR].oea_read) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 202 } 203 204 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 205 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 206 segs, sizeof(segs)))); 207 } 208 209 /* 210 * Advertise VMX/VSX (vector extensions) if available 211 * 0 / no property == no vector extensions 212 * 1 == VMX / Altivec available 213 * 2 == VSX available 214 */ 215 if (env->insns_flags & PPC_ALTIVEC) { 216 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 217 218 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 219 } 220 221 /* 222 * Advertise DFP (Decimal Floating Point) if available 223 * 0 / no property == no DFP 224 * 1 == DFP available 225 */ 226 if (env->insns_flags2 & PPC2_DFP) { 227 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 228 } 229 230 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 231 sizeof(page_sizes_prop)); 232 if (page_sizes_prop_size) { 233 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 234 page_sizes_prop, page_sizes_prop_size))); 235 } 236 237 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 238 pa_features, sizeof(pa_features)))); 239 240 /* Build interrupt servers properties */ 241 for (i = 0; i < smt_threads; i++) { 242 servers_prop[i] = cpu_to_be32(pc->pir + i); 243 } 244 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 245 servers_prop, sizeof(servers_prop)))); 246 } 247 248 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 249 uint32_t nr_threads) 250 { 251 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 252 char *name; 253 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 254 uint32_t irange[2], i, rsize; 255 uint64_t *reg; 256 int offset; 257 258 irange[0] = cpu_to_be32(pir); 259 irange[1] = cpu_to_be32(nr_threads); 260 261 rsize = sizeof(uint64_t) * 2 * nr_threads; 262 reg = g_malloc(rsize); 263 for (i = 0; i < nr_threads; i++) { 264 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 265 reg[i * 2 + 1] = cpu_to_be64(0x1000); 266 } 267 268 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 269 offset = fdt_add_subnode(fdt, 0, name); 270 _FDT(offset); 271 g_free(name); 272 273 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 274 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 275 _FDT((fdt_setprop_string(fdt, offset, "device_type", 276 "PowerPC-External-Interrupt-Presentation"))); 277 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 278 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 279 irange, sizeof(irange)))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 281 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 282 g_free(reg); 283 } 284 285 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 286 { 287 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 288 int i; 289 290 pnv_dt_xscom(chip, fdt, 0, 291 cpu_to_be64(PNV_XSCOM_BASE(chip)), 292 cpu_to_be64(PNV_XSCOM_SIZE), 293 compat, sizeof(compat)); 294 295 for (i = 0; i < chip->nr_cores; i++) { 296 PnvCore *pnv_core = chip->cores[i]; 297 298 pnv_dt_core(chip, pnv_core, fdt); 299 300 /* Interrupt Control Presenters (ICP). One per core. */ 301 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 302 } 303 304 if (chip->ram_size) { 305 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 306 } 307 } 308 309 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 310 { 311 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 312 int i; 313 314 pnv_dt_xscom(chip, fdt, 0, 315 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 316 cpu_to_be64(PNV9_XSCOM_SIZE), 317 compat, sizeof(compat)); 318 319 for (i = 0; i < chip->nr_cores; i++) { 320 PnvCore *pnv_core = chip->cores[i]; 321 322 pnv_dt_core(chip, pnv_core, fdt); 323 } 324 325 if (chip->ram_size) { 326 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 327 } 328 329 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 330 } 331 332 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 333 { 334 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 335 int i; 336 337 pnv_dt_xscom(chip, fdt, 0, 338 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 339 cpu_to_be64(PNV10_XSCOM_SIZE), 340 compat, sizeof(compat)); 341 342 for (i = 0; i < chip->nr_cores; i++) { 343 PnvCore *pnv_core = chip->cores[i]; 344 345 pnv_dt_core(chip, pnv_core, fdt); 346 } 347 348 if (chip->ram_size) { 349 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 350 } 351 352 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 353 } 354 355 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 356 { 357 uint32_t io_base = d->ioport_id; 358 uint32_t io_regs[] = { 359 cpu_to_be32(1), 360 cpu_to_be32(io_base), 361 cpu_to_be32(2) 362 }; 363 char *name; 364 int node; 365 366 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 367 node = fdt_add_subnode(fdt, lpc_off, name); 368 _FDT(node); 369 g_free(name); 370 371 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 372 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 373 } 374 375 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 376 { 377 const char compatible[] = "ns16550\0pnpPNP,501"; 378 uint32_t io_base = d->ioport_id; 379 uint32_t io_regs[] = { 380 cpu_to_be32(1), 381 cpu_to_be32(io_base), 382 cpu_to_be32(8) 383 }; 384 char *name; 385 int node; 386 387 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 388 node = fdt_add_subnode(fdt, lpc_off, name); 389 _FDT(node); 390 g_free(name); 391 392 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 393 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 394 sizeof(compatible)))); 395 396 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 397 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 398 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 399 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 400 fdt_get_phandle(fdt, lpc_off)))); 401 402 /* This is needed by Linux */ 403 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 404 } 405 406 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 407 { 408 const char compatible[] = "bt\0ipmi-bt"; 409 uint32_t io_base; 410 uint32_t io_regs[] = { 411 cpu_to_be32(1), 412 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 413 cpu_to_be32(3) 414 }; 415 uint32_t irq; 416 char *name; 417 int node; 418 419 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 420 io_regs[1] = cpu_to_be32(io_base); 421 422 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 423 424 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 425 node = fdt_add_subnode(fdt, lpc_off, name); 426 _FDT(node); 427 g_free(name); 428 429 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 430 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 431 sizeof(compatible)))); 432 433 /* Mark it as reserved to avoid Linux trying to claim it */ 434 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 435 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 436 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 437 fdt_get_phandle(fdt, lpc_off)))); 438 } 439 440 typedef struct ForeachPopulateArgs { 441 void *fdt; 442 int offset; 443 } ForeachPopulateArgs; 444 445 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 446 { 447 ForeachPopulateArgs *args = opaque; 448 ISADevice *d = ISA_DEVICE(dev); 449 450 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 451 pnv_dt_rtc(d, args->fdt, args->offset); 452 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 453 pnv_dt_serial(d, args->fdt, args->offset); 454 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 455 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 456 } else { 457 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 458 d->ioport_id); 459 } 460 461 return 0; 462 } 463 464 /* 465 * The default LPC bus of a multichip system is on chip 0. It's 466 * recognized by the firmware (skiboot) using a "primary" property. 467 */ 468 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 469 { 470 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 471 ForeachPopulateArgs args = { 472 .fdt = fdt, 473 .offset = isa_offset, 474 }; 475 uint32_t phandle; 476 477 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 478 479 phandle = qemu_fdt_alloc_phandle(fdt); 480 assert(phandle > 0); 481 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 482 483 /* 484 * ISA devices are not necessarily parented to the ISA bus so we 485 * can not use object_child_foreach() 486 */ 487 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 488 &args); 489 } 490 491 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 492 { 493 int off; 494 495 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 496 off = fdt_add_subnode(fdt, off, "power-mgt"); 497 498 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 499 } 500 501 static void *pnv_dt_create(MachineState *machine) 502 { 503 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 504 PnvMachineState *pnv = PNV_MACHINE(machine); 505 void *fdt; 506 char *buf; 507 int off; 508 int i; 509 510 fdt = g_malloc0(FDT_MAX_SIZE); 511 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 512 513 /* /qemu node */ 514 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 515 516 /* Root node */ 517 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 518 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 519 _FDT((fdt_setprop_string(fdt, 0, "model", 520 "IBM PowerNV (emulated by qemu)"))); 521 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 522 523 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 524 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 525 if (qemu_uuid_set) { 526 _FDT((fdt_property_string(fdt, "system-id", buf))); 527 } 528 g_free(buf); 529 530 off = fdt_add_subnode(fdt, 0, "chosen"); 531 if (machine->kernel_cmdline) { 532 _FDT((fdt_setprop_string(fdt, off, "bootargs", 533 machine->kernel_cmdline))); 534 } 535 536 if (pnv->initrd_size) { 537 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 538 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 539 540 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 541 &start_prop, sizeof(start_prop)))); 542 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 543 &end_prop, sizeof(end_prop)))); 544 } 545 546 /* Populate device tree for each chip */ 547 for (i = 0; i < pnv->num_chips; i++) { 548 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 549 } 550 551 /* Populate ISA devices on chip 0 */ 552 pnv_dt_isa(pnv, fdt); 553 554 if (pnv->bmc) { 555 pnv_dt_bmc_sensors(pnv->bmc, fdt); 556 } 557 558 /* Create an extra node for power management on machines that support it */ 559 if (pmc->dt_power_mgt) { 560 pmc->dt_power_mgt(pnv, fdt); 561 } 562 563 return fdt; 564 } 565 566 static void pnv_powerdown_notify(Notifier *n, void *opaque) 567 { 568 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 569 570 if (pnv->bmc) { 571 pnv_bmc_powerdown(pnv->bmc); 572 } 573 } 574 575 static void pnv_reset(MachineState *machine) 576 { 577 PnvMachineState *pnv = PNV_MACHINE(machine); 578 IPMIBmc *bmc; 579 void *fdt; 580 581 qemu_devices_reset(); 582 583 /* 584 * The machine should provide by default an internal BMC simulator. 585 * If not, try to use the BMC device that was provided on the command 586 * line. 587 */ 588 bmc = pnv_bmc_find(&error_fatal); 589 if (!pnv->bmc) { 590 if (!bmc) { 591 if (!qtest_enabled()) { 592 warn_report("machine has no BMC device. Use '-device " 593 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 594 "to define one"); 595 } 596 } else { 597 pnv_bmc_set_pnor(bmc, pnv->pnor); 598 pnv->bmc = bmc; 599 } 600 } 601 602 fdt = pnv_dt_create(machine); 603 604 /* Pack resulting tree */ 605 _FDT((fdt_pack(fdt))); 606 607 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 608 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 609 610 g_free(fdt); 611 } 612 613 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 614 { 615 Pnv8Chip *chip8 = PNV8_CHIP(chip); 616 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 617 } 618 619 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 620 { 621 Pnv8Chip *chip8 = PNV8_CHIP(chip); 622 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 623 } 624 625 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 626 { 627 Pnv9Chip *chip9 = PNV9_CHIP(chip); 628 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 629 } 630 631 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 632 { 633 Pnv10Chip *chip10 = PNV10_CHIP(chip); 634 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 635 } 636 637 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 638 { 639 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 640 } 641 642 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 643 { 644 Pnv8Chip *chip8 = PNV8_CHIP(chip); 645 int i; 646 647 ics_pic_print_info(&chip8->psi.ics, mon); 648 for (i = 0; i < chip->num_phbs; i++) { 649 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 650 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 651 } 652 } 653 654 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 655 { 656 Pnv9Chip *chip9 = PNV9_CHIP(chip); 657 int i, j; 658 659 pnv_xive_pic_print_info(&chip9->xive, mon); 660 pnv_psi_pic_print_info(&chip9->psi, mon); 661 662 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 663 PnvPhb4PecState *pec = &chip9->pecs[i]; 664 for (j = 0; j < pec->num_stacks; j++) { 665 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 666 } 667 } 668 } 669 670 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 671 uint32_t core_id) 672 { 673 return PNV_XSCOM_EX_BASE(core_id); 674 } 675 676 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 677 uint32_t core_id) 678 { 679 return PNV9_XSCOM_EC_BASE(core_id); 680 } 681 682 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 683 uint32_t core_id) 684 { 685 return PNV10_XSCOM_EC_BASE(core_id); 686 } 687 688 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 689 { 690 PowerPCCPUClass *ppc_default = 691 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 692 PowerPCCPUClass *ppc = 693 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 694 695 return ppc_default->pvr_match(ppc_default, ppc->pvr); 696 } 697 698 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 699 { 700 ISADevice *dev = isa_new("isa-ipmi-bt"); 701 702 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 703 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 704 isa_realize_and_unref(dev, bus, &error_fatal); 705 } 706 707 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 708 { 709 Pnv10Chip *chip10 = PNV10_CHIP(chip); 710 711 pnv_psi_pic_print_info(&chip10->psi, mon); 712 } 713 714 static void pnv_init(MachineState *machine) 715 { 716 PnvMachineState *pnv = PNV_MACHINE(machine); 717 MachineClass *mc = MACHINE_GET_CLASS(machine); 718 char *fw_filename; 719 long fw_size; 720 int i; 721 char *chip_typename; 722 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 723 DeviceState *dev; 724 725 /* allocate RAM */ 726 if (machine->ram_size < (1 * GiB)) { 727 warn_report("skiboot may not work with < 1GB of RAM"); 728 } 729 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 730 731 /* 732 * Create our simple PNOR device 733 */ 734 dev = qdev_new(TYPE_PNV_PNOR); 735 if (pnor) { 736 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 737 } 738 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 739 pnv->pnor = PNV_PNOR(dev); 740 741 /* load skiboot firmware */ 742 if (bios_name == NULL) { 743 bios_name = FW_FILE_NAME; 744 } 745 746 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 747 if (!fw_filename) { 748 error_report("Could not find OPAL firmware '%s'", bios_name); 749 exit(1); 750 } 751 752 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 753 if (fw_size < 0) { 754 error_report("Could not load OPAL firmware '%s'", fw_filename); 755 exit(1); 756 } 757 g_free(fw_filename); 758 759 /* load kernel */ 760 if (machine->kernel_filename) { 761 long kernel_size; 762 763 kernel_size = load_image_targphys(machine->kernel_filename, 764 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 765 if (kernel_size < 0) { 766 error_report("Could not load kernel '%s'", 767 machine->kernel_filename); 768 exit(1); 769 } 770 } 771 772 /* load initrd */ 773 if (machine->initrd_filename) { 774 pnv->initrd_base = INITRD_LOAD_ADDR; 775 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 776 pnv->initrd_base, INITRD_MAX_SIZE); 777 if (pnv->initrd_size < 0) { 778 error_report("Could not load initial ram disk '%s'", 779 machine->initrd_filename); 780 exit(1); 781 } 782 } 783 784 /* MSIs are supported on this platform */ 785 msi_nonbroken = true; 786 787 /* 788 * Check compatibility of the specified CPU with the machine 789 * default. 790 */ 791 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 792 error_report("invalid CPU model '%s' for %s machine", 793 machine->cpu_type, mc->name); 794 exit(1); 795 } 796 797 /* Create the processor chips */ 798 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 799 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 800 i, machine->cpu_type); 801 if (!object_class_by_name(chip_typename)) { 802 error_report("invalid chip model '%.*s' for %s machine", 803 i, machine->cpu_type, mc->name); 804 exit(1); 805 } 806 807 pnv->num_chips = 808 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 809 /* 810 * TODO: should we decide on how many chips we can create based 811 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 812 */ 813 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 814 error_report("invalid number of chips: '%d'", pnv->num_chips); 815 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 816 exit(1); 817 } 818 819 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 820 for (i = 0; i < pnv->num_chips; i++) { 821 char chip_name[32]; 822 Object *chip = OBJECT(qdev_new(chip_typename)); 823 824 pnv->chips[i] = PNV_CHIP(chip); 825 826 /* 827 * TODO: put all the memory in one node on chip 0 until we find a 828 * way to specify different ranges for each chip 829 */ 830 if (i == 0) { 831 object_property_set_int(chip, "ram-size", machine->ram_size, 832 &error_fatal); 833 } 834 835 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 836 object_property_add_child(OBJECT(pnv), chip_name, chip); 837 object_property_set_int(chip, "chip-id", PNV_CHIP_HWID(i), 838 &error_fatal); 839 object_property_set_int(chip, "nr-cores", machine->smp.cores, 840 &error_fatal); 841 object_property_set_int(chip, "nr-threads", machine->smp.threads, 842 &error_fatal); 843 /* 844 * The POWER8 machine use the XICS interrupt interface. 845 * Propagate the XICS fabric to the chip and its controllers. 846 */ 847 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 848 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 849 } 850 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 851 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 852 &error_abort); 853 } 854 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 855 } 856 g_free(chip_typename); 857 858 /* Instantiate ISA bus on chip 0 */ 859 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 860 861 /* Create serial port */ 862 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 863 864 /* Create an RTC ISA device too */ 865 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 866 867 /* 868 * Create the machine BMC simulator and the IPMI BT device for 869 * communication with the BMC 870 */ 871 if (defaults_enabled()) { 872 pnv->bmc = pnv_bmc_create(pnv->pnor); 873 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 874 } 875 876 /* 877 * OpenPOWER systems use a IPMI SEL Event message to notify the 878 * host to powerdown 879 */ 880 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 881 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 882 } 883 884 /* 885 * 0:21 Reserved - Read as zeros 886 * 22:24 Chip ID 887 * 25:28 Core number 888 * 29:31 Thread ID 889 */ 890 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 891 { 892 return (chip->chip_id << 7) | (core_id << 3); 893 } 894 895 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 896 Error **errp) 897 { 898 Pnv8Chip *chip8 = PNV8_CHIP(chip); 899 Error *local_err = NULL; 900 Object *obj; 901 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 902 903 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 904 if (local_err) { 905 error_propagate(errp, local_err); 906 return; 907 } 908 909 pnv_cpu->intc = obj; 910 } 911 912 913 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 914 { 915 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 916 917 icp_reset(ICP(pnv_cpu->intc)); 918 } 919 920 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 921 { 922 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 923 924 icp_destroy(ICP(pnv_cpu->intc)); 925 pnv_cpu->intc = NULL; 926 } 927 928 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 929 Monitor *mon) 930 { 931 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 932 } 933 934 /* 935 * 0:48 Reserved - Read as zeroes 936 * 49:52 Node ID 937 * 53:55 Chip ID 938 * 56 Reserved - Read as zero 939 * 57:61 Core number 940 * 62:63 Thread ID 941 * 942 * We only care about the lower bits. uint32_t is fine for the moment. 943 */ 944 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 945 { 946 return (chip->chip_id << 8) | (core_id << 2); 947 } 948 949 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 950 { 951 return (chip->chip_id << 8) | (core_id << 2); 952 } 953 954 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 955 Error **errp) 956 { 957 Pnv9Chip *chip9 = PNV9_CHIP(chip); 958 Error *local_err = NULL; 959 Object *obj; 960 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 961 962 /* 963 * The core creates its interrupt presenter but the XIVE interrupt 964 * controller object is initialized afterwards. Hopefully, it's 965 * only used at runtime. 966 */ 967 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 968 &local_err); 969 if (local_err) { 970 error_propagate(errp, local_err); 971 return; 972 } 973 974 pnv_cpu->intc = obj; 975 } 976 977 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 978 { 979 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 980 981 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 982 } 983 984 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 985 { 986 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 987 988 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 989 pnv_cpu->intc = NULL; 990 } 991 992 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 993 Monitor *mon) 994 { 995 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 996 } 997 998 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 999 Error **errp) 1000 { 1001 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1002 1003 /* Will be defined when the interrupt controller is */ 1004 pnv_cpu->intc = NULL; 1005 } 1006 1007 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1008 { 1009 ; 1010 } 1011 1012 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1013 { 1014 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1015 1016 pnv_cpu->intc = NULL; 1017 } 1018 1019 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1020 Monitor *mon) 1021 { 1022 } 1023 1024 /* 1025 * Allowed core identifiers on a POWER8 Processor Chip : 1026 * 1027 * <EX0 reserved> 1028 * EX1 - Venice only 1029 * EX2 - Venice only 1030 * EX3 - Venice only 1031 * EX4 1032 * EX5 1033 * EX6 1034 * <EX7,8 reserved> <reserved> 1035 * EX9 - Venice only 1036 * EX10 - Venice only 1037 * EX11 - Venice only 1038 * EX12 1039 * EX13 1040 * EX14 1041 * <EX15 reserved> 1042 */ 1043 #define POWER8E_CORE_MASK (0x7070ull) 1044 #define POWER8_CORE_MASK (0x7e7eull) 1045 1046 /* 1047 * POWER9 has 24 cores, ids starting at 0x0 1048 */ 1049 #define POWER9_CORE_MASK (0xffffffffffffffull) 1050 1051 1052 #define POWER10_CORE_MASK (0xffffffffffffffull) 1053 1054 static void pnv_chip_power8_instance_init(Object *obj) 1055 { 1056 PnvChip *chip = PNV_CHIP(obj); 1057 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1058 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1059 int i; 1060 1061 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1062 (Object **)&chip8->xics, 1063 object_property_allow_set_link, 1064 OBJ_PROP_LINK_STRONG); 1065 1066 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1067 1068 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1069 1070 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1071 1072 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1073 1074 for (i = 0; i < pcc->num_phbs; i++) { 1075 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1076 } 1077 1078 /* 1079 * Number of PHBs is the chip default 1080 */ 1081 chip->num_phbs = pcc->num_phbs; 1082 } 1083 1084 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1085 { 1086 PnvChip *chip = PNV_CHIP(chip8); 1087 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1088 int i, j; 1089 char *name; 1090 1091 name = g_strdup_printf("icp-%x", chip->chip_id); 1092 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1093 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1094 g_free(name); 1095 1096 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1097 1098 /* Map the ICP registers for each thread */ 1099 for (i = 0; i < chip->nr_cores; i++) { 1100 PnvCore *pnv_core = chip->cores[i]; 1101 int core_hwid = CPU_CORE(pnv_core)->core_id; 1102 1103 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1104 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1105 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1106 1107 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1108 &icp->mmio); 1109 } 1110 } 1111 } 1112 1113 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1114 { 1115 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1116 PnvChip *chip = PNV_CHIP(dev); 1117 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1118 Pnv8Psi *psi8 = &chip8->psi; 1119 Error *local_err = NULL; 1120 int i; 1121 1122 assert(chip8->xics); 1123 1124 /* XSCOM bridge is first */ 1125 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1126 if (local_err) { 1127 error_propagate(errp, local_err); 1128 return; 1129 } 1130 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1131 1132 pcc->parent_realize(dev, &local_err); 1133 if (local_err) { 1134 error_propagate(errp, local_err); 1135 return; 1136 } 1137 1138 /* Processor Service Interface (PSI) Host Bridge */ 1139 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1140 &error_fatal); 1141 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1142 OBJECT(chip8->xics), &error_abort); 1143 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1144 return; 1145 } 1146 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1147 &PNV_PSI(psi8)->xscom_regs); 1148 1149 /* Create LPC controller */ 1150 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi), 1151 &error_abort); 1152 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1153 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1154 1155 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1156 (uint64_t) PNV_XSCOM_BASE(chip), 1157 PNV_XSCOM_LPC_BASE); 1158 1159 /* 1160 * Interrupt Management Area. This is the memory region holding 1161 * all the Interrupt Control Presenter (ICP) registers 1162 */ 1163 pnv_chip_icp_realize(chip8, &local_err); 1164 if (local_err) { 1165 error_propagate(errp, local_err); 1166 return; 1167 } 1168 1169 /* Create the simplified OCC model */ 1170 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi), 1171 &error_abort); 1172 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1173 return; 1174 } 1175 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1176 1177 /* OCC SRAM model */ 1178 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1179 &chip8->occ.sram_regs); 1180 1181 /* HOMER */ 1182 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1183 &error_abort); 1184 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1185 return; 1186 } 1187 /* Homer Xscom region */ 1188 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1189 1190 /* Homer mmio region */ 1191 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1192 &chip8->homer.regs); 1193 1194 /* PHB3 controllers */ 1195 for (i = 0; i < chip->num_phbs; i++) { 1196 PnvPHB3 *phb = &chip8->phbs[i]; 1197 PnvPBCQState *pbcq = &phb->pbcq; 1198 1199 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1200 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1201 &error_fatal); 1202 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1203 return; 1204 } 1205 1206 /* Populate the XSCOM address space. */ 1207 pnv_xscom_add_subregion(chip, 1208 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1209 &pbcq->xscom_nest_regs); 1210 pnv_xscom_add_subregion(chip, 1211 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1212 &pbcq->xscom_pci_regs); 1213 pnv_xscom_add_subregion(chip, 1214 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1215 &pbcq->xscom_spci_regs); 1216 } 1217 } 1218 1219 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1220 { 1221 addr &= (PNV_XSCOM_SIZE - 1); 1222 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1223 } 1224 1225 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1226 { 1227 DeviceClass *dc = DEVICE_CLASS(klass); 1228 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1229 1230 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1231 k->cores_mask = POWER8E_CORE_MASK; 1232 k->num_phbs = 3; 1233 k->core_pir = pnv_chip_core_pir_p8; 1234 k->intc_create = pnv_chip_power8_intc_create; 1235 k->intc_reset = pnv_chip_power8_intc_reset; 1236 k->intc_destroy = pnv_chip_power8_intc_destroy; 1237 k->intc_print_info = pnv_chip_power8_intc_print_info; 1238 k->isa_create = pnv_chip_power8_isa_create; 1239 k->dt_populate = pnv_chip_power8_dt_populate; 1240 k->pic_print_info = pnv_chip_power8_pic_print_info; 1241 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1242 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1243 dc->desc = "PowerNV Chip POWER8E"; 1244 1245 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1246 &k->parent_realize); 1247 } 1248 1249 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1250 { 1251 DeviceClass *dc = DEVICE_CLASS(klass); 1252 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1253 1254 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1255 k->cores_mask = POWER8_CORE_MASK; 1256 k->num_phbs = 3; 1257 k->core_pir = pnv_chip_core_pir_p8; 1258 k->intc_create = pnv_chip_power8_intc_create; 1259 k->intc_reset = pnv_chip_power8_intc_reset; 1260 k->intc_destroy = pnv_chip_power8_intc_destroy; 1261 k->intc_print_info = pnv_chip_power8_intc_print_info; 1262 k->isa_create = pnv_chip_power8_isa_create; 1263 k->dt_populate = pnv_chip_power8_dt_populate; 1264 k->pic_print_info = pnv_chip_power8_pic_print_info; 1265 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1266 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1267 dc->desc = "PowerNV Chip POWER8"; 1268 1269 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1270 &k->parent_realize); 1271 } 1272 1273 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1274 { 1275 DeviceClass *dc = DEVICE_CLASS(klass); 1276 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1277 1278 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1279 k->cores_mask = POWER8_CORE_MASK; 1280 k->num_phbs = 3; 1281 k->core_pir = pnv_chip_core_pir_p8; 1282 k->intc_create = pnv_chip_power8_intc_create; 1283 k->intc_reset = pnv_chip_power8_intc_reset; 1284 k->intc_destroy = pnv_chip_power8_intc_destroy; 1285 k->intc_print_info = pnv_chip_power8_intc_print_info; 1286 k->isa_create = pnv_chip_power8nvl_isa_create; 1287 k->dt_populate = pnv_chip_power8_dt_populate; 1288 k->pic_print_info = pnv_chip_power8_pic_print_info; 1289 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1290 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1291 dc->desc = "PowerNV Chip POWER8NVL"; 1292 1293 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1294 &k->parent_realize); 1295 } 1296 1297 static void pnv_chip_power9_instance_init(Object *obj) 1298 { 1299 PnvChip *chip = PNV_CHIP(obj); 1300 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1301 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1302 int i; 1303 1304 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1305 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1306 "xive-fabric"); 1307 1308 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1309 1310 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1311 1312 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1313 1314 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1315 1316 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1317 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1318 TYPE_PNV_PHB4_PEC); 1319 } 1320 1321 /* 1322 * Number of PHBs is the chip default 1323 */ 1324 chip->num_phbs = pcc->num_phbs; 1325 } 1326 1327 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1328 { 1329 PnvChip *chip = PNV_CHIP(chip9); 1330 int i; 1331 1332 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1333 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1334 1335 for (i = 0; i < chip9->nr_quads; i++) { 1336 char eq_name[32]; 1337 PnvQuad *eq = &chip9->quads[i]; 1338 PnvCore *pnv_core = chip->cores[i * 4]; 1339 int core_id = CPU_CORE(pnv_core)->core_id; 1340 1341 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1342 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1343 sizeof(*eq), TYPE_PNV_QUAD, 1344 &error_fatal, NULL); 1345 1346 object_property_set_int(OBJECT(eq), "id", core_id, &error_fatal); 1347 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1348 1349 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1350 &eq->xscom_regs); 1351 } 1352 } 1353 1354 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1355 { 1356 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1357 int i, j; 1358 int phb_id = 0; 1359 1360 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1361 PnvPhb4PecState *pec = &chip9->pecs[i]; 1362 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1363 uint32_t pec_nest_base; 1364 uint32_t pec_pci_base; 1365 1366 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1367 /* 1368 * PEC0 -> 1 stack 1369 * PEC1 -> 2 stacks 1370 * PEC2 -> 3 stacks 1371 */ 1372 object_property_set_int(OBJECT(pec), "num-stacks", i + 1, 1373 &error_fatal); 1374 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1375 &error_fatal); 1376 object_property_set_link(OBJECT(pec), "system-memory", 1377 OBJECT(get_system_memory()), &error_abort); 1378 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1379 return; 1380 } 1381 1382 pec_nest_base = pecc->xscom_nest_base(pec); 1383 pec_pci_base = pecc->xscom_pci_base(pec); 1384 1385 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1386 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1387 1388 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1389 j++, phb_id++) { 1390 PnvPhb4PecStack *stack = &pec->stacks[j]; 1391 Object *obj = OBJECT(&stack->phb); 1392 1393 object_property_set_int(obj, "index", phb_id, &error_fatal); 1394 object_property_set_int(obj, "chip-id", chip->chip_id, 1395 &error_fatal); 1396 object_property_set_int(obj, "version", PNV_PHB4_VERSION, 1397 &error_fatal); 1398 object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID, 1399 &error_fatal); 1400 object_property_set_link(obj, "stack", OBJECT(stack), 1401 &error_abort); 1402 if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) { 1403 return; 1404 } 1405 1406 /* Populate the XSCOM address space. */ 1407 pnv_xscom_add_subregion(chip, 1408 pec_nest_base + 0x40 * (stack->stack_no + 1), 1409 &stack->nest_regs_mr); 1410 pnv_xscom_add_subregion(chip, 1411 pec_pci_base + 0x40 * (stack->stack_no + 1), 1412 &stack->pci_regs_mr); 1413 pnv_xscom_add_subregion(chip, 1414 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1415 0x40 * stack->stack_no, 1416 &stack->phb_regs_mr); 1417 } 1418 } 1419 } 1420 1421 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1422 { 1423 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1424 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1425 PnvChip *chip = PNV_CHIP(dev); 1426 Pnv9Psi *psi9 = &chip9->psi; 1427 Error *local_err = NULL; 1428 1429 /* XSCOM bridge is first */ 1430 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1431 if (local_err) { 1432 error_propagate(errp, local_err); 1433 return; 1434 } 1435 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1436 1437 pcc->parent_realize(dev, &local_err); 1438 if (local_err) { 1439 error_propagate(errp, local_err); 1440 return; 1441 } 1442 1443 pnv_chip_quad_realize(chip9, &local_err); 1444 if (local_err) { 1445 error_propagate(errp, local_err); 1446 return; 1447 } 1448 1449 /* XIVE interrupt controller (POWER9) */ 1450 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1451 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1452 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1453 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1454 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1455 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1456 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1457 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1458 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1459 &error_abort); 1460 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1461 return; 1462 } 1463 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1464 &chip9->xive.xscom_regs); 1465 1466 /* Processor Service Interface (PSI) Host Bridge */ 1467 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1468 &error_fatal); 1469 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1470 return; 1471 } 1472 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1473 &PNV_PSI(psi9)->xscom_regs); 1474 1475 /* LPC */ 1476 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi), 1477 &error_abort); 1478 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1479 return; 1480 } 1481 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1482 &chip9->lpc.xscom_regs); 1483 1484 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1485 (uint64_t) PNV9_LPCM_BASE(chip)); 1486 1487 /* Create the simplified OCC model */ 1488 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi), 1489 &error_abort); 1490 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1491 return; 1492 } 1493 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1494 1495 /* OCC SRAM model */ 1496 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1497 &chip9->occ.sram_regs); 1498 1499 /* HOMER */ 1500 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1501 &error_abort); 1502 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1503 return; 1504 } 1505 /* Homer Xscom region */ 1506 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1507 1508 /* Homer mmio region */ 1509 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1510 &chip9->homer.regs); 1511 1512 /* PHBs */ 1513 pnv_chip_power9_phb_realize(chip, &local_err); 1514 if (local_err) { 1515 error_propagate(errp, local_err); 1516 return; 1517 } 1518 } 1519 1520 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1521 { 1522 addr &= (PNV9_XSCOM_SIZE - 1); 1523 return addr >> 3; 1524 } 1525 1526 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1527 { 1528 DeviceClass *dc = DEVICE_CLASS(klass); 1529 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1530 1531 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1532 k->cores_mask = POWER9_CORE_MASK; 1533 k->core_pir = pnv_chip_core_pir_p9; 1534 k->intc_create = pnv_chip_power9_intc_create; 1535 k->intc_reset = pnv_chip_power9_intc_reset; 1536 k->intc_destroy = pnv_chip_power9_intc_destroy; 1537 k->intc_print_info = pnv_chip_power9_intc_print_info; 1538 k->isa_create = pnv_chip_power9_isa_create; 1539 k->dt_populate = pnv_chip_power9_dt_populate; 1540 k->pic_print_info = pnv_chip_power9_pic_print_info; 1541 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1542 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1543 dc->desc = "PowerNV Chip POWER9"; 1544 k->num_phbs = 6; 1545 1546 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1547 &k->parent_realize); 1548 } 1549 1550 static void pnv_chip_power10_instance_init(Object *obj) 1551 { 1552 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1553 1554 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1555 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1556 } 1557 1558 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1559 { 1560 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1561 PnvChip *chip = PNV_CHIP(dev); 1562 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1563 Error *local_err = NULL; 1564 1565 /* XSCOM bridge is first */ 1566 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1567 if (local_err) { 1568 error_propagate(errp, local_err); 1569 return; 1570 } 1571 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1572 1573 pcc->parent_realize(dev, &local_err); 1574 if (local_err) { 1575 error_propagate(errp, local_err); 1576 return; 1577 } 1578 1579 /* Processor Service Interface (PSI) Host Bridge */ 1580 object_property_set_int(OBJECT(&chip10->psi), "bar", 1581 PNV10_PSIHB_BASE(chip), &error_fatal); 1582 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1583 return; 1584 } 1585 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1586 &PNV_PSI(&chip10->psi)->xscom_regs); 1587 1588 /* LPC */ 1589 object_property_set_link(OBJECT(&chip10->lpc), "psi", 1590 OBJECT(&chip10->psi), &error_abort); 1591 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1592 return; 1593 } 1594 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1595 &chip10->lpc.xscom_regs); 1596 1597 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1598 (uint64_t) PNV10_LPCM_BASE(chip)); 1599 } 1600 1601 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1602 { 1603 addr &= (PNV10_XSCOM_SIZE - 1); 1604 return addr >> 3; 1605 } 1606 1607 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1608 { 1609 DeviceClass *dc = DEVICE_CLASS(klass); 1610 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1611 1612 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1613 k->cores_mask = POWER10_CORE_MASK; 1614 k->core_pir = pnv_chip_core_pir_p10; 1615 k->intc_create = pnv_chip_power10_intc_create; 1616 k->intc_reset = pnv_chip_power10_intc_reset; 1617 k->intc_destroy = pnv_chip_power10_intc_destroy; 1618 k->intc_print_info = pnv_chip_power10_intc_print_info; 1619 k->isa_create = pnv_chip_power10_isa_create; 1620 k->dt_populate = pnv_chip_power10_dt_populate; 1621 k->pic_print_info = pnv_chip_power10_pic_print_info; 1622 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1623 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1624 dc->desc = "PowerNV Chip POWER10"; 1625 1626 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1627 &k->parent_realize); 1628 } 1629 1630 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1631 { 1632 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1633 int cores_max; 1634 1635 /* 1636 * No custom mask for this chip, let's use the default one from * 1637 * the chip class 1638 */ 1639 if (!chip->cores_mask) { 1640 chip->cores_mask = pcc->cores_mask; 1641 } 1642 1643 /* filter alien core ids ! some are reserved */ 1644 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1645 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1646 chip->cores_mask); 1647 return; 1648 } 1649 chip->cores_mask &= pcc->cores_mask; 1650 1651 /* now that we have a sane layout, let check the number of cores */ 1652 cores_max = ctpop64(chip->cores_mask); 1653 if (chip->nr_cores > cores_max) { 1654 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1655 cores_max); 1656 return; 1657 } 1658 } 1659 1660 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1661 { 1662 Error *error = NULL; 1663 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1664 const char *typename = pnv_chip_core_typename(chip); 1665 int i, core_hwid; 1666 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1667 1668 if (!object_class_by_name(typename)) { 1669 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1670 return; 1671 } 1672 1673 /* Cores */ 1674 pnv_chip_core_sanitize(chip, &error); 1675 if (error) { 1676 error_propagate(errp, error); 1677 return; 1678 } 1679 1680 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1681 1682 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1683 && (i < chip->nr_cores); core_hwid++) { 1684 char core_name[32]; 1685 PnvCore *pnv_core; 1686 uint64_t xscom_core_base; 1687 1688 if (!(chip->cores_mask & (1ull << core_hwid))) { 1689 continue; 1690 } 1691 1692 pnv_core = PNV_CORE(object_new(typename)); 1693 1694 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1695 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1696 chip->cores[i] = pnv_core; 1697 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1698 chip->nr_threads, &error_fatal); 1699 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1700 core_hwid, &error_fatal); 1701 object_property_set_int(OBJECT(pnv_core), "pir", 1702 pcc->core_pir(chip, core_hwid), &error_fatal); 1703 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1704 &error_fatal); 1705 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1706 &error_abort); 1707 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1708 1709 /* Each core has an XSCOM MMIO region */ 1710 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1711 1712 pnv_xscom_add_subregion(chip, xscom_core_base, 1713 &pnv_core->xscom_regs); 1714 i++; 1715 } 1716 } 1717 1718 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1719 { 1720 PnvChip *chip = PNV_CHIP(dev); 1721 Error *error = NULL; 1722 1723 /* Cores */ 1724 pnv_chip_core_realize(chip, &error); 1725 if (error) { 1726 error_propagate(errp, error); 1727 return; 1728 } 1729 } 1730 1731 static Property pnv_chip_properties[] = { 1732 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1733 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1734 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1735 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1736 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1737 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1738 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1739 DEFINE_PROP_END_OF_LIST(), 1740 }; 1741 1742 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1743 { 1744 DeviceClass *dc = DEVICE_CLASS(klass); 1745 1746 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1747 dc->realize = pnv_chip_realize; 1748 device_class_set_props(dc, pnv_chip_properties); 1749 dc->desc = "PowerNV Chip"; 1750 } 1751 1752 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1753 { 1754 int i, j; 1755 1756 for (i = 0; i < chip->nr_cores; i++) { 1757 PnvCore *pc = chip->cores[i]; 1758 CPUCore *cc = CPU_CORE(pc); 1759 1760 for (j = 0; j < cc->nr_threads; j++) { 1761 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1762 return pc->threads[j]; 1763 } 1764 } 1765 } 1766 return NULL; 1767 } 1768 1769 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1770 { 1771 PnvMachineState *pnv = PNV_MACHINE(xi); 1772 int i, j; 1773 1774 for (i = 0; i < pnv->num_chips; i++) { 1775 PnvChip *chip = pnv->chips[i]; 1776 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1777 1778 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1779 return &chip8->psi.ics; 1780 } 1781 for (j = 0; j < chip->num_phbs; j++) { 1782 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1783 return &chip8->phbs[j].lsis; 1784 } 1785 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1786 return ICS(&chip8->phbs[j].msis); 1787 } 1788 } 1789 } 1790 return NULL; 1791 } 1792 1793 static void pnv_ics_resend(XICSFabric *xi) 1794 { 1795 PnvMachineState *pnv = PNV_MACHINE(xi); 1796 int i, j; 1797 1798 for (i = 0; i < pnv->num_chips; i++) { 1799 PnvChip *chip = pnv->chips[i]; 1800 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1801 1802 ics_resend(&chip8->psi.ics); 1803 for (j = 0; j < chip->num_phbs; j++) { 1804 ics_resend(&chip8->phbs[j].lsis); 1805 ics_resend(ICS(&chip8->phbs[j].msis)); 1806 } 1807 } 1808 } 1809 1810 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1811 { 1812 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1813 1814 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1815 } 1816 1817 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1818 Monitor *mon) 1819 { 1820 PnvMachineState *pnv = PNV_MACHINE(obj); 1821 int i; 1822 CPUState *cs; 1823 1824 CPU_FOREACH(cs) { 1825 PowerPCCPU *cpu = POWERPC_CPU(cs); 1826 1827 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1828 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1829 mon); 1830 } 1831 1832 for (i = 0; i < pnv->num_chips; i++) { 1833 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1834 } 1835 } 1836 1837 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1838 uint8_t nvt_blk, uint32_t nvt_idx, 1839 bool cam_ignore, uint8_t priority, 1840 uint32_t logic_serv, 1841 XiveTCTXMatch *match) 1842 { 1843 PnvMachineState *pnv = PNV_MACHINE(xfb); 1844 int total_count = 0; 1845 int i; 1846 1847 for (i = 0; i < pnv->num_chips; i++) { 1848 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1849 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1850 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1851 int count; 1852 1853 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1854 priority, logic_serv, match); 1855 1856 if (count < 0) { 1857 return count; 1858 } 1859 1860 total_count += count; 1861 } 1862 1863 return total_count; 1864 } 1865 1866 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1867 { 1868 MachineClass *mc = MACHINE_CLASS(oc); 1869 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1870 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1871 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1872 1873 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1874 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1875 1876 xic->icp_get = pnv_icp_get; 1877 xic->ics_get = pnv_ics_get; 1878 xic->ics_resend = pnv_ics_resend; 1879 1880 pmc->compat = compat; 1881 pmc->compat_size = sizeof(compat); 1882 } 1883 1884 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1885 { 1886 MachineClass *mc = MACHINE_CLASS(oc); 1887 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1888 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1889 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1890 1891 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1892 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1893 xfc->match_nvt = pnv_match_nvt; 1894 1895 mc->alias = "powernv"; 1896 1897 pmc->compat = compat; 1898 pmc->compat_size = sizeof(compat); 1899 pmc->dt_power_mgt = pnv_dt_power_mgt; 1900 } 1901 1902 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1903 { 1904 MachineClass *mc = MACHINE_CLASS(oc); 1905 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1906 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1907 1908 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1909 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1910 1911 pmc->compat = compat; 1912 pmc->compat_size = sizeof(compat); 1913 pmc->dt_power_mgt = pnv_dt_power_mgt; 1914 } 1915 1916 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1917 { 1918 PnvMachineState *pnv = PNV_MACHINE(obj); 1919 1920 return !!pnv->fw_load_addr; 1921 } 1922 1923 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1924 { 1925 PnvMachineState *pnv = PNV_MACHINE(obj); 1926 1927 if (value) { 1928 pnv->fw_load_addr = 0x8000000; 1929 } 1930 } 1931 1932 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 1933 { 1934 PowerPCCPU *cpu = POWERPC_CPU(cs); 1935 CPUPPCState *env = &cpu->env; 1936 1937 cpu_synchronize_state(cs); 1938 ppc_cpu_do_system_reset(cs); 1939 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 1940 /* 1941 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 1942 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 1943 * (PPC_BIT(43)). 1944 */ 1945 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 1946 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 1947 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 1948 } 1949 } else { 1950 /* 1951 * For non-powersave system resets, SRR1[42:45] are defined to be 1952 * implementation-dependent. The POWER9 User Manual specifies that 1953 * an external (SCOM driven, which may come from a BMC nmi command or 1954 * another CPU requesting a NMI IPI) system reset exception should be 1955 * 0b0010 (PPC_BIT(44)). 1956 */ 1957 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 1958 } 1959 } 1960 1961 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 1962 { 1963 CPUState *cs; 1964 1965 CPU_FOREACH(cs) { 1966 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 1967 } 1968 } 1969 1970 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1971 { 1972 MachineClass *mc = MACHINE_CLASS(oc); 1973 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1974 NMIClass *nc = NMI_CLASS(oc); 1975 1976 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1977 mc->init = pnv_init; 1978 mc->reset = pnv_reset; 1979 mc->max_cpus = MAX_CPUS; 1980 /* Pnv provides a AHCI device for storage */ 1981 mc->block_default_type = IF_IDE; 1982 mc->no_parallel = 1; 1983 mc->default_boot_order = NULL; 1984 /* 1985 * RAM defaults to less than 2048 for 32-bit hosts, and large 1986 * enough to fit the maximum initrd size at it's load address 1987 */ 1988 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1989 mc->default_ram_id = "pnv.ram"; 1990 ispc->print_info = pnv_pic_print_info; 1991 nc->nmi_monitor_handler = pnv_nmi; 1992 1993 object_class_property_add_bool(oc, "hb-mode", 1994 pnv_machine_get_hb, pnv_machine_set_hb); 1995 object_class_property_set_description(oc, "hb-mode", 1996 "Use a hostboot like boot loader"); 1997 } 1998 1999 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2000 { \ 2001 .name = type, \ 2002 .class_init = class_initfn, \ 2003 .parent = TYPE_PNV8_CHIP, \ 2004 } 2005 2006 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2007 { \ 2008 .name = type, \ 2009 .class_init = class_initfn, \ 2010 .parent = TYPE_PNV9_CHIP, \ 2011 } 2012 2013 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2014 { \ 2015 .name = type, \ 2016 .class_init = class_initfn, \ 2017 .parent = TYPE_PNV10_CHIP, \ 2018 } 2019 2020 static const TypeInfo types[] = { 2021 { 2022 .name = MACHINE_TYPE_NAME("powernv10"), 2023 .parent = TYPE_PNV_MACHINE, 2024 .class_init = pnv_machine_power10_class_init, 2025 }, 2026 { 2027 .name = MACHINE_TYPE_NAME("powernv9"), 2028 .parent = TYPE_PNV_MACHINE, 2029 .class_init = pnv_machine_power9_class_init, 2030 .interfaces = (InterfaceInfo[]) { 2031 { TYPE_XIVE_FABRIC }, 2032 { }, 2033 }, 2034 }, 2035 { 2036 .name = MACHINE_TYPE_NAME("powernv8"), 2037 .parent = TYPE_PNV_MACHINE, 2038 .class_init = pnv_machine_power8_class_init, 2039 .interfaces = (InterfaceInfo[]) { 2040 { TYPE_XICS_FABRIC }, 2041 { }, 2042 }, 2043 }, 2044 { 2045 .name = TYPE_PNV_MACHINE, 2046 .parent = TYPE_MACHINE, 2047 .abstract = true, 2048 .instance_size = sizeof(PnvMachineState), 2049 .class_init = pnv_machine_class_init, 2050 .class_size = sizeof(PnvMachineClass), 2051 .interfaces = (InterfaceInfo[]) { 2052 { TYPE_INTERRUPT_STATS_PROVIDER }, 2053 { TYPE_NMI }, 2054 { }, 2055 }, 2056 }, 2057 { 2058 .name = TYPE_PNV_CHIP, 2059 .parent = TYPE_SYS_BUS_DEVICE, 2060 .class_init = pnv_chip_class_init, 2061 .instance_size = sizeof(PnvChip), 2062 .class_size = sizeof(PnvChipClass), 2063 .abstract = true, 2064 }, 2065 2066 /* 2067 * P10 chip and variants 2068 */ 2069 { 2070 .name = TYPE_PNV10_CHIP, 2071 .parent = TYPE_PNV_CHIP, 2072 .instance_init = pnv_chip_power10_instance_init, 2073 .instance_size = sizeof(Pnv10Chip), 2074 }, 2075 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2076 2077 /* 2078 * P9 chip and variants 2079 */ 2080 { 2081 .name = TYPE_PNV9_CHIP, 2082 .parent = TYPE_PNV_CHIP, 2083 .instance_init = pnv_chip_power9_instance_init, 2084 .instance_size = sizeof(Pnv9Chip), 2085 }, 2086 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2087 2088 /* 2089 * P8 chip and variants 2090 */ 2091 { 2092 .name = TYPE_PNV8_CHIP, 2093 .parent = TYPE_PNV_CHIP, 2094 .instance_init = pnv_chip_power8_instance_init, 2095 .instance_size = sizeof(Pnv8Chip), 2096 }, 2097 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2098 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2099 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2100 pnv_chip_power8nvl_class_init), 2101 }; 2102 2103 DEFINE_TYPES(types) 2104