1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 44 #include "hw/ppc/xics.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/ppc/pnv_xscom.h" 47 #include "hw/ppc/pnv_pnor.h" 48 49 #include "hw/isa/isa.h" 50 #include "hw/boards.h" 51 #include "hw/char/serial.h" 52 #include "hw/rtc/mc146818rtc.h" 53 54 #include <libfdt.h> 55 56 #define FDT_MAX_SIZE (1 * MiB) 57 58 #define FW_FILE_NAME "skiboot.lid" 59 #define FW_LOAD_ADDR 0x0 60 #define FW_MAX_SIZE (4 * MiB) 61 62 #define KERNEL_LOAD_ADDR 0x20000000 63 #define KERNEL_MAX_SIZE (256 * MiB) 64 #define INITRD_LOAD_ADDR 0x60000000 65 #define INITRD_MAX_SIZE (256 * MiB) 66 67 static const char *pnv_chip_core_typename(const PnvChip *o) 68 { 69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 72 const char *core_type = object_class_get_name(object_class_by_name(s)); 73 g_free(s); 74 return core_type; 75 } 76 77 /* 78 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 79 * 4 * 4 sockets * 12 cores * 8 threads = 1536 80 * Let's make it 2^11 81 */ 82 #define MAX_CPUS 2048 83 84 /* 85 * Memory nodes are created by hostboot, one for each range of memory 86 * that has a different "affinity". In practice, it means one range 87 * per chip. 88 */ 89 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 90 { 91 char *mem_name; 92 uint64_t mem_reg_property[2]; 93 int off; 94 95 mem_reg_property[0] = cpu_to_be64(start); 96 mem_reg_property[1] = cpu_to_be64(size); 97 98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 99 off = fdt_add_subnode(fdt, 0, mem_name); 100 g_free(mem_name); 101 102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 104 sizeof(mem_reg_property)))); 105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 106 } 107 108 static int get_cpus_node(void *fdt) 109 { 110 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 111 112 if (cpus_offset < 0) { 113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 114 if (cpus_offset) { 115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 117 } 118 } 119 _FDT(cpus_offset); 120 return cpus_offset; 121 } 122 123 /* 124 * The PowerNV cores (and threads) need to use real HW ids and not an 125 * incremental index like it has been done on other platforms. This HW 126 * id is stored in the CPU PIR, it is used to create cpu nodes in the 127 * device tree, used in XSCOM to address cores and in interrupt 128 * servers. 129 */ 130 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 131 { 132 PowerPCCPU *cpu = pc->threads[0]; 133 CPUState *cs = CPU(cpu); 134 DeviceClass *dc = DEVICE_GET_CLASS(cs); 135 int smt_threads = CPU_CORE(pc)->nr_threads; 136 CPUPPCState *env = &cpu->env; 137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 138 uint32_t servers_prop[smt_threads]; 139 int i; 140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 141 0xffffffff, 0xffffffff}; 142 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 143 uint32_t cpufreq = 1000000000; 144 uint32_t page_sizes_prop[64]; 145 size_t page_sizes_prop_size; 146 const uint8_t pa_features[] = { 24, 0, 147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 151 int offset; 152 char *nodename; 153 int cpus_offset = get_cpus_node(fdt); 154 155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 156 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 157 _FDT(offset); 158 g_free(nodename); 159 160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 161 162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 168 env->dcache_line_size))); 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 170 env->dcache_line_size))); 171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 172 env->icache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 174 env->icache_line_size))); 175 176 if (pcc->l1_dcache_size) { 177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 178 pcc->l1_dcache_size))); 179 } else { 180 warn_report("Unknown L1 dcache size for cpu"); 181 } 182 if (pcc->l1_icache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 184 pcc->l1_icache_size))); 185 } else { 186 warn_report("Unknown L1 icache size for cpu"); 187 } 188 189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 192 cpu->hash64_opts->slb_size))); 193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 195 196 if (env->spr_cb[SPR_PURR].oea_read) { 197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 198 } 199 200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 202 segs, sizeof(segs)))); 203 } 204 205 /* 206 * Advertise VMX/VSX (vector extensions) if available 207 * 0 / no property == no vector extensions 208 * 1 == VMX / Altivec available 209 * 2 == VSX available 210 */ 211 if (env->insns_flags & PPC_ALTIVEC) { 212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 213 214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 215 } 216 217 /* 218 * Advertise DFP (Decimal Floating Point) if available 219 * 0 / no property == no DFP 220 * 1 == DFP available 221 */ 222 if (env->insns_flags2 & PPC2_DFP) { 223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 224 } 225 226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 227 sizeof(page_sizes_prop)); 228 if (page_sizes_prop_size) { 229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 230 page_sizes_prop, page_sizes_prop_size))); 231 } 232 233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 234 pa_features, sizeof(pa_features)))); 235 236 /* Build interrupt servers properties */ 237 for (i = 0; i < smt_threads; i++) { 238 servers_prop[i] = cpu_to_be32(pc->pir + i); 239 } 240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 241 servers_prop, sizeof(servers_prop)))); 242 } 243 244 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 245 uint32_t nr_threads) 246 { 247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 248 char *name; 249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 250 uint32_t irange[2], i, rsize; 251 uint64_t *reg; 252 int offset; 253 254 irange[0] = cpu_to_be32(pir); 255 irange[1] = cpu_to_be32(nr_threads); 256 257 rsize = sizeof(uint64_t) * 2 * nr_threads; 258 reg = g_malloc(rsize); 259 for (i = 0; i < nr_threads; i++) { 260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 261 reg[i * 2 + 1] = cpu_to_be64(0x1000); 262 } 263 264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 265 offset = fdt_add_subnode(fdt, 0, name); 266 _FDT(offset); 267 g_free(name); 268 269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 271 _FDT((fdt_setprop_string(fdt, offset, "device_type", 272 "PowerPC-External-Interrupt-Presentation"))); 273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 275 irange, sizeof(irange)))); 276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 278 g_free(reg); 279 } 280 281 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 282 { 283 const char *typename = pnv_chip_core_typename(chip); 284 size_t typesize = object_type_get_instance_size(typename); 285 int i; 286 287 pnv_dt_xscom(chip, fdt, 0); 288 289 for (i = 0; i < chip->nr_cores; i++) { 290 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 291 292 pnv_dt_core(chip, pnv_core, fdt); 293 294 /* Interrupt Control Presenters (ICP). One per core. */ 295 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 296 } 297 298 if (chip->ram_size) { 299 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 300 } 301 } 302 303 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 304 { 305 const char *typename = pnv_chip_core_typename(chip); 306 size_t typesize = object_type_get_instance_size(typename); 307 int i; 308 309 pnv_dt_xscom(chip, fdt, 0); 310 311 for (i = 0; i < chip->nr_cores; i++) { 312 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 313 314 pnv_dt_core(chip, pnv_core, fdt); 315 } 316 317 if (chip->ram_size) { 318 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 319 } 320 321 pnv_dt_lpc(chip, fdt, 0); 322 } 323 324 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 325 { 326 uint32_t io_base = d->ioport_id; 327 uint32_t io_regs[] = { 328 cpu_to_be32(1), 329 cpu_to_be32(io_base), 330 cpu_to_be32(2) 331 }; 332 char *name; 333 int node; 334 335 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 336 node = fdt_add_subnode(fdt, lpc_off, name); 337 _FDT(node); 338 g_free(name); 339 340 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 341 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 342 } 343 344 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 345 { 346 const char compatible[] = "ns16550\0pnpPNP,501"; 347 uint32_t io_base = d->ioport_id; 348 uint32_t io_regs[] = { 349 cpu_to_be32(1), 350 cpu_to_be32(io_base), 351 cpu_to_be32(8) 352 }; 353 char *name; 354 int node; 355 356 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 357 node = fdt_add_subnode(fdt, lpc_off, name); 358 _FDT(node); 359 g_free(name); 360 361 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 362 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 363 sizeof(compatible)))); 364 365 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 366 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 367 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 368 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 369 fdt_get_phandle(fdt, lpc_off)))); 370 371 /* This is needed by Linux */ 372 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 373 } 374 375 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 376 { 377 const char compatible[] = "bt\0ipmi-bt"; 378 uint32_t io_base; 379 uint32_t io_regs[] = { 380 cpu_to_be32(1), 381 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 382 cpu_to_be32(3) 383 }; 384 uint32_t irq; 385 char *name; 386 int node; 387 388 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 389 io_regs[1] = cpu_to_be32(io_base); 390 391 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 392 393 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 394 node = fdt_add_subnode(fdt, lpc_off, name); 395 _FDT(node); 396 g_free(name); 397 398 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 399 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 400 sizeof(compatible)))); 401 402 /* Mark it as reserved to avoid Linux trying to claim it */ 403 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 404 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 405 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 406 fdt_get_phandle(fdt, lpc_off)))); 407 } 408 409 typedef struct ForeachPopulateArgs { 410 void *fdt; 411 int offset; 412 } ForeachPopulateArgs; 413 414 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 415 { 416 ForeachPopulateArgs *args = opaque; 417 ISADevice *d = ISA_DEVICE(dev); 418 419 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 420 pnv_dt_rtc(d, args->fdt, args->offset); 421 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 422 pnv_dt_serial(d, args->fdt, args->offset); 423 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 424 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 425 } else { 426 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 427 d->ioport_id); 428 } 429 430 return 0; 431 } 432 433 /* 434 * The default LPC bus of a multichip system is on chip 0. It's 435 * recognized by the firmware (skiboot) using a "primary" property. 436 */ 437 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 438 { 439 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 440 ForeachPopulateArgs args = { 441 .fdt = fdt, 442 .offset = isa_offset, 443 }; 444 uint32_t phandle; 445 446 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 447 448 phandle = qemu_fdt_alloc_phandle(fdt); 449 assert(phandle > 0); 450 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 451 452 /* 453 * ISA devices are not necessarily parented to the ISA bus so we 454 * can not use object_child_foreach() 455 */ 456 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 457 &args); 458 } 459 460 static void pnv_dt_power_mgt(void *fdt) 461 { 462 int off; 463 464 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 465 off = fdt_add_subnode(fdt, off, "power-mgt"); 466 467 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 468 } 469 470 static void *pnv_dt_create(MachineState *machine) 471 { 472 const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 473 const char plat_compat9[] = "qemu,powernv9\0ibm,powernv"; 474 PnvMachineState *pnv = PNV_MACHINE(machine); 475 void *fdt; 476 char *buf; 477 int off; 478 int i; 479 480 fdt = g_malloc0(FDT_MAX_SIZE); 481 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 482 483 /* /qemu node */ 484 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 485 486 /* Root node */ 487 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 488 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 489 _FDT((fdt_setprop_string(fdt, 0, "model", 490 "IBM PowerNV (emulated by qemu)"))); 491 if (pnv_is_power9(pnv)) { 492 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, 493 sizeof(plat_compat9)))); 494 } else { 495 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8, 496 sizeof(plat_compat8)))); 497 } 498 499 500 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 501 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 502 if (qemu_uuid_set) { 503 _FDT((fdt_property_string(fdt, "system-id", buf))); 504 } 505 g_free(buf); 506 507 off = fdt_add_subnode(fdt, 0, "chosen"); 508 if (machine->kernel_cmdline) { 509 _FDT((fdt_setprop_string(fdt, off, "bootargs", 510 machine->kernel_cmdline))); 511 } 512 513 if (pnv->initrd_size) { 514 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 515 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 516 517 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 518 &start_prop, sizeof(start_prop)))); 519 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 520 &end_prop, sizeof(end_prop)))); 521 } 522 523 /* Populate device tree for each chip */ 524 for (i = 0; i < pnv->num_chips; i++) { 525 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 526 } 527 528 /* Populate ISA devices on chip 0 */ 529 pnv_dt_isa(pnv, fdt); 530 531 if (pnv->bmc) { 532 pnv_dt_bmc_sensors(pnv->bmc, fdt); 533 } 534 535 /* Create an extra node for power management on Power9 */ 536 if (pnv_is_power9(pnv)) { 537 pnv_dt_power_mgt(fdt); 538 } 539 540 return fdt; 541 } 542 543 static void pnv_powerdown_notify(Notifier *n, void *opaque) 544 { 545 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 546 547 if (pnv->bmc) { 548 pnv_bmc_powerdown(pnv->bmc); 549 } 550 } 551 552 static void pnv_reset(MachineState *machine) 553 { 554 void *fdt; 555 556 qemu_devices_reset(); 557 558 fdt = pnv_dt_create(machine); 559 560 /* Pack resulting tree */ 561 _FDT((fdt_pack(fdt))); 562 563 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 564 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 565 } 566 567 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 568 { 569 Pnv8Chip *chip8 = PNV8_CHIP(chip); 570 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 571 } 572 573 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 574 { 575 Pnv8Chip *chip8 = PNV8_CHIP(chip); 576 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 577 } 578 579 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 580 { 581 Pnv9Chip *chip9 = PNV9_CHIP(chip); 582 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 583 } 584 585 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 586 { 587 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 588 } 589 590 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 591 { 592 Pnv8Chip *chip8 = PNV8_CHIP(chip); 593 594 ics_pic_print_info(&chip8->psi.ics, mon); 595 } 596 597 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 598 { 599 Pnv9Chip *chip9 = PNV9_CHIP(chip); 600 601 pnv_xive_pic_print_info(&chip9->xive, mon); 602 pnv_psi_pic_print_info(&chip9->psi, mon); 603 } 604 605 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 606 { 607 PowerPCCPUClass *ppc_default = 608 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 609 PowerPCCPUClass *ppc = 610 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 611 612 return ppc_default->pvr_match(ppc_default, ppc->pvr); 613 } 614 615 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 616 { 617 Object *obj; 618 619 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 620 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 621 object_property_set_int(obj, irq, "irq", &error_fatal); 622 object_property_set_bool(obj, true, "realized", &error_fatal); 623 } 624 625 static void pnv_init(MachineState *machine) 626 { 627 PnvMachineState *pnv = PNV_MACHINE(machine); 628 MachineClass *mc = MACHINE_GET_CLASS(machine); 629 MemoryRegion *ram; 630 char *fw_filename; 631 long fw_size; 632 int i; 633 char *chip_typename; 634 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 635 DeviceState *dev; 636 637 /* allocate RAM */ 638 if (machine->ram_size < (1 * GiB)) { 639 warn_report("skiboot may not work with < 1GB of RAM"); 640 } 641 642 ram = g_new(MemoryRegion, 1); 643 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 644 machine->ram_size); 645 memory_region_add_subregion(get_system_memory(), 0, ram); 646 647 /* 648 * Create our simple PNOR device 649 */ 650 dev = qdev_create(NULL, TYPE_PNV_PNOR); 651 if (pnor) { 652 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 653 &error_abort); 654 } 655 qdev_init_nofail(dev); 656 pnv->pnor = PNV_PNOR(dev); 657 658 /* load skiboot firmware */ 659 if (bios_name == NULL) { 660 bios_name = FW_FILE_NAME; 661 } 662 663 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 664 if (!fw_filename) { 665 error_report("Could not find OPAL firmware '%s'", bios_name); 666 exit(1); 667 } 668 669 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 670 if (fw_size < 0) { 671 error_report("Could not load OPAL firmware '%s'", fw_filename); 672 exit(1); 673 } 674 g_free(fw_filename); 675 676 /* load kernel */ 677 if (machine->kernel_filename) { 678 long kernel_size; 679 680 kernel_size = load_image_targphys(machine->kernel_filename, 681 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 682 if (kernel_size < 0) { 683 error_report("Could not load kernel '%s'", 684 machine->kernel_filename); 685 exit(1); 686 } 687 } 688 689 /* load initrd */ 690 if (machine->initrd_filename) { 691 pnv->initrd_base = INITRD_LOAD_ADDR; 692 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 693 pnv->initrd_base, INITRD_MAX_SIZE); 694 if (pnv->initrd_size < 0) { 695 error_report("Could not load initial ram disk '%s'", 696 machine->initrd_filename); 697 exit(1); 698 } 699 } 700 701 /* 702 * Check compatibility of the specified CPU with the machine 703 * default. 704 */ 705 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 706 error_report("invalid CPU model '%s' for %s machine", 707 machine->cpu_type, mc->name); 708 exit(1); 709 } 710 711 /* Create the processor chips */ 712 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 713 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 714 i, machine->cpu_type); 715 if (!object_class_by_name(chip_typename)) { 716 error_report("invalid chip model '%.*s' for %s machine", 717 i, machine->cpu_type, mc->name); 718 exit(1); 719 } 720 721 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 722 for (i = 0; i < pnv->num_chips; i++) { 723 char chip_name[32]; 724 Object *chip = object_new(chip_typename); 725 726 pnv->chips[i] = PNV_CHIP(chip); 727 728 /* 729 * TODO: put all the memory in one node on chip 0 until we find a 730 * way to specify different ranges for each chip 731 */ 732 if (i == 0) { 733 object_property_set_int(chip, machine->ram_size, "ram-size", 734 &error_fatal); 735 } 736 737 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 738 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 739 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 740 &error_fatal); 741 object_property_set_int(chip, machine->smp.cores, 742 "nr-cores", &error_fatal); 743 object_property_set_bool(chip, true, "realized", &error_fatal); 744 } 745 g_free(chip_typename); 746 747 /* Create the machine BMC simulator */ 748 pnv->bmc = pnv_bmc_create(); 749 750 /* Instantiate ISA bus on chip 0 */ 751 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 752 753 /* Create serial port */ 754 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 755 756 /* Create an RTC ISA device too */ 757 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 758 759 /* Create the IPMI BT device for communication with the BMC */ 760 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 761 762 /* 763 * OpenPOWER systems use a IPMI SEL Event message to notify the 764 * host to powerdown 765 */ 766 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 767 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 768 } 769 770 /* 771 * 0:21 Reserved - Read as zeros 772 * 22:24 Chip ID 773 * 25:28 Core number 774 * 29:31 Thread ID 775 */ 776 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 777 { 778 return (chip->chip_id << 7) | (core_id << 3); 779 } 780 781 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 782 Error **errp) 783 { 784 Error *local_err = NULL; 785 Object *obj; 786 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 787 788 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 789 &local_err); 790 if (local_err) { 791 error_propagate(errp, local_err); 792 return; 793 } 794 795 pnv_cpu->intc = obj; 796 } 797 798 799 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 800 { 801 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 802 803 icp_reset(ICP(pnv_cpu->intc)); 804 } 805 806 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 807 { 808 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 809 810 icp_destroy(ICP(pnv_cpu->intc)); 811 pnv_cpu->intc = NULL; 812 } 813 814 /* 815 * 0:48 Reserved - Read as zeroes 816 * 49:52 Node ID 817 * 53:55 Chip ID 818 * 56 Reserved - Read as zero 819 * 57:61 Core number 820 * 62:63 Thread ID 821 * 822 * We only care about the lower bits. uint32_t is fine for the moment. 823 */ 824 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 825 { 826 return (chip->chip_id << 8) | (core_id << 2); 827 } 828 829 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 830 Error **errp) 831 { 832 Pnv9Chip *chip9 = PNV9_CHIP(chip); 833 Error *local_err = NULL; 834 Object *obj; 835 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 836 837 /* 838 * The core creates its interrupt presenter but the XIVE interrupt 839 * controller object is initialized afterwards. Hopefully, it's 840 * only used at runtime. 841 */ 842 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); 843 if (local_err) { 844 error_propagate(errp, local_err); 845 return; 846 } 847 848 pnv_cpu->intc = obj; 849 } 850 851 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 852 { 853 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 854 855 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 856 } 857 858 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 859 { 860 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 861 862 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 863 pnv_cpu->intc = NULL; 864 } 865 866 /* 867 * Allowed core identifiers on a POWER8 Processor Chip : 868 * 869 * <EX0 reserved> 870 * EX1 - Venice only 871 * EX2 - Venice only 872 * EX3 - Venice only 873 * EX4 874 * EX5 875 * EX6 876 * <EX7,8 reserved> <reserved> 877 * EX9 - Venice only 878 * EX10 - Venice only 879 * EX11 - Venice only 880 * EX12 881 * EX13 882 * EX14 883 * <EX15 reserved> 884 */ 885 #define POWER8E_CORE_MASK (0x7070ull) 886 #define POWER8_CORE_MASK (0x7e7eull) 887 888 /* 889 * POWER9 has 24 cores, ids starting at 0x0 890 */ 891 #define POWER9_CORE_MASK (0xffffffffffffffull) 892 893 static void pnv_chip_power8_instance_init(Object *obj) 894 { 895 Pnv8Chip *chip8 = PNV8_CHIP(obj); 896 897 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 898 TYPE_PNV8_PSI, &error_abort, NULL); 899 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 900 OBJECT(qdev_get_machine()), &error_abort); 901 902 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 903 TYPE_PNV8_LPC, &error_abort, NULL); 904 905 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 906 TYPE_PNV8_OCC, &error_abort, NULL); 907 908 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 909 TYPE_PNV8_HOMER, &error_abort, NULL); 910 } 911 912 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 913 { 914 PnvChip *chip = PNV_CHIP(chip8); 915 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 916 const char *typename = pnv_chip_core_typename(chip); 917 size_t typesize = object_type_get_instance_size(typename); 918 int i, j; 919 char *name; 920 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 921 922 name = g_strdup_printf("icp-%x", chip->chip_id); 923 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 924 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 925 g_free(name); 926 927 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 928 929 /* Map the ICP registers for each thread */ 930 for (i = 0; i < chip->nr_cores; i++) { 931 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 932 int core_hwid = CPU_CORE(pnv_core)->core_id; 933 934 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 935 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 936 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 937 938 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 939 &icp->mmio); 940 } 941 } 942 } 943 944 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 945 { 946 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 947 PnvChip *chip = PNV_CHIP(dev); 948 Pnv8Chip *chip8 = PNV8_CHIP(dev); 949 Pnv8Psi *psi8 = &chip8->psi; 950 Error *local_err = NULL; 951 952 /* XSCOM bridge is first */ 953 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 954 if (local_err) { 955 error_propagate(errp, local_err); 956 return; 957 } 958 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 959 960 pcc->parent_realize(dev, &local_err); 961 if (local_err) { 962 error_propagate(errp, local_err); 963 return; 964 } 965 966 /* Processor Service Interface (PSI) Host Bridge */ 967 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 968 "bar", &error_fatal); 969 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 970 if (local_err) { 971 error_propagate(errp, local_err); 972 return; 973 } 974 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 975 &PNV_PSI(psi8)->xscom_regs); 976 977 /* Create LPC controller */ 978 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 979 &error_abort); 980 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 981 &error_fatal); 982 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 983 984 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 985 (uint64_t) PNV_XSCOM_BASE(chip), 986 PNV_XSCOM_LPC_BASE); 987 988 /* 989 * Interrupt Management Area. This is the memory region holding 990 * all the Interrupt Control Presenter (ICP) registers 991 */ 992 pnv_chip_icp_realize(chip8, &local_err); 993 if (local_err) { 994 error_propagate(errp, local_err); 995 return; 996 } 997 998 /* Create the simplified OCC model */ 999 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1000 &error_abort); 1001 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1002 if (local_err) { 1003 error_propagate(errp, local_err); 1004 return; 1005 } 1006 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1007 1008 /* OCC SRAM model */ 1009 memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip), 1010 &chip8->occ.sram_regs); 1011 1012 /* HOMER */ 1013 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1014 &error_abort); 1015 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1016 &local_err); 1017 if (local_err) { 1018 error_propagate(errp, local_err); 1019 return; 1020 } 1021 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1022 &chip8->homer.regs); 1023 } 1024 1025 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1026 { 1027 DeviceClass *dc = DEVICE_CLASS(klass); 1028 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1029 1030 k->chip_type = PNV_CHIP_POWER8E; 1031 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1032 k->cores_mask = POWER8E_CORE_MASK; 1033 k->core_pir = pnv_chip_core_pir_p8; 1034 k->intc_create = pnv_chip_power8_intc_create; 1035 k->intc_reset = pnv_chip_power8_intc_reset; 1036 k->intc_destroy = pnv_chip_power8_intc_destroy; 1037 k->isa_create = pnv_chip_power8_isa_create; 1038 k->dt_populate = pnv_chip_power8_dt_populate; 1039 k->pic_print_info = pnv_chip_power8_pic_print_info; 1040 dc->desc = "PowerNV Chip POWER8E"; 1041 1042 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1043 &k->parent_realize); 1044 } 1045 1046 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1047 { 1048 DeviceClass *dc = DEVICE_CLASS(klass); 1049 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1050 1051 k->chip_type = PNV_CHIP_POWER8; 1052 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1053 k->cores_mask = POWER8_CORE_MASK; 1054 k->core_pir = pnv_chip_core_pir_p8; 1055 k->intc_create = pnv_chip_power8_intc_create; 1056 k->intc_reset = pnv_chip_power8_intc_reset; 1057 k->intc_destroy = pnv_chip_power8_intc_destroy; 1058 k->isa_create = pnv_chip_power8_isa_create; 1059 k->dt_populate = pnv_chip_power8_dt_populate; 1060 k->pic_print_info = pnv_chip_power8_pic_print_info; 1061 dc->desc = "PowerNV Chip POWER8"; 1062 1063 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1064 &k->parent_realize); 1065 } 1066 1067 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1068 { 1069 DeviceClass *dc = DEVICE_CLASS(klass); 1070 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1071 1072 k->chip_type = PNV_CHIP_POWER8NVL; 1073 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1074 k->cores_mask = POWER8_CORE_MASK; 1075 k->core_pir = pnv_chip_core_pir_p8; 1076 k->intc_create = pnv_chip_power8_intc_create; 1077 k->intc_reset = pnv_chip_power8_intc_reset; 1078 k->intc_destroy = pnv_chip_power8_intc_destroy; 1079 k->isa_create = pnv_chip_power8nvl_isa_create; 1080 k->dt_populate = pnv_chip_power8_dt_populate; 1081 k->pic_print_info = pnv_chip_power8_pic_print_info; 1082 dc->desc = "PowerNV Chip POWER8NVL"; 1083 1084 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1085 &k->parent_realize); 1086 } 1087 1088 static void pnv_chip_power9_instance_init(Object *obj) 1089 { 1090 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1091 1092 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1093 TYPE_PNV_XIVE, &error_abort, NULL); 1094 1095 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1096 TYPE_PNV9_PSI, &error_abort, NULL); 1097 1098 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1099 TYPE_PNV9_LPC, &error_abort, NULL); 1100 1101 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1102 TYPE_PNV9_OCC, &error_abort, NULL); 1103 1104 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1105 TYPE_PNV9_HOMER, &error_abort, NULL); 1106 } 1107 1108 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1109 { 1110 PnvChip *chip = PNV_CHIP(chip9); 1111 const char *typename = pnv_chip_core_typename(chip); 1112 size_t typesize = object_type_get_instance_size(typename); 1113 int i; 1114 1115 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1116 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1117 1118 for (i = 0; i < chip9->nr_quads; i++) { 1119 char eq_name[32]; 1120 PnvQuad *eq = &chip9->quads[i]; 1121 PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize); 1122 int core_id = CPU_CORE(pnv_core)->core_id; 1123 1124 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1125 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1126 TYPE_PNV_QUAD, &error_fatal, NULL); 1127 1128 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1129 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1130 1131 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1132 &eq->xscom_regs); 1133 } 1134 } 1135 1136 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1137 { 1138 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1139 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1140 PnvChip *chip = PNV_CHIP(dev); 1141 Pnv9Psi *psi9 = &chip9->psi; 1142 Error *local_err = NULL; 1143 1144 /* XSCOM bridge is first */ 1145 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1146 if (local_err) { 1147 error_propagate(errp, local_err); 1148 return; 1149 } 1150 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1151 1152 pcc->parent_realize(dev, &local_err); 1153 if (local_err) { 1154 error_propagate(errp, local_err); 1155 return; 1156 } 1157 1158 pnv_chip_quad_realize(chip9, &local_err); 1159 if (local_err) { 1160 error_propagate(errp, local_err); 1161 return; 1162 } 1163 1164 /* XIVE interrupt controller (POWER9) */ 1165 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1166 "ic-bar", &error_fatal); 1167 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1168 "vc-bar", &error_fatal); 1169 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1170 "pc-bar", &error_fatal); 1171 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1172 "tm-bar", &error_fatal); 1173 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1174 &error_abort); 1175 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1176 &local_err); 1177 if (local_err) { 1178 error_propagate(errp, local_err); 1179 return; 1180 } 1181 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1182 &chip9->xive.xscom_regs); 1183 1184 /* Processor Service Interface (PSI) Host Bridge */ 1185 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1186 "bar", &error_fatal); 1187 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1188 if (local_err) { 1189 error_propagate(errp, local_err); 1190 return; 1191 } 1192 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1193 &PNV_PSI(psi9)->xscom_regs); 1194 1195 /* LPC */ 1196 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1197 &error_abort); 1198 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1199 if (local_err) { 1200 error_propagate(errp, local_err); 1201 return; 1202 } 1203 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1204 &chip9->lpc.xscom_regs); 1205 1206 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1207 (uint64_t) PNV9_LPCM_BASE(chip)); 1208 1209 /* Create the simplified OCC model */ 1210 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1211 &error_abort); 1212 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1213 if (local_err) { 1214 error_propagate(errp, local_err); 1215 return; 1216 } 1217 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1218 1219 /* OCC SRAM model */ 1220 memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip), 1221 &chip9->occ.sram_regs); 1222 1223 /* HOMER */ 1224 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1225 &error_abort); 1226 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1227 &local_err); 1228 if (local_err) { 1229 error_propagate(errp, local_err); 1230 return; 1231 } 1232 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1233 &chip9->homer.regs); 1234 } 1235 1236 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1237 { 1238 DeviceClass *dc = DEVICE_CLASS(klass); 1239 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1240 1241 k->chip_type = PNV_CHIP_POWER9; 1242 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1243 k->cores_mask = POWER9_CORE_MASK; 1244 k->core_pir = pnv_chip_core_pir_p9; 1245 k->intc_create = pnv_chip_power9_intc_create; 1246 k->intc_reset = pnv_chip_power9_intc_reset; 1247 k->intc_destroy = pnv_chip_power9_intc_destroy; 1248 k->isa_create = pnv_chip_power9_isa_create; 1249 k->dt_populate = pnv_chip_power9_dt_populate; 1250 k->pic_print_info = pnv_chip_power9_pic_print_info; 1251 dc->desc = "PowerNV Chip POWER9"; 1252 1253 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1254 &k->parent_realize); 1255 } 1256 1257 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1258 { 1259 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1260 int cores_max; 1261 1262 /* 1263 * No custom mask for this chip, let's use the default one from * 1264 * the chip class 1265 */ 1266 if (!chip->cores_mask) { 1267 chip->cores_mask = pcc->cores_mask; 1268 } 1269 1270 /* filter alien core ids ! some are reserved */ 1271 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1272 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1273 chip->cores_mask); 1274 return; 1275 } 1276 chip->cores_mask &= pcc->cores_mask; 1277 1278 /* now that we have a sane layout, let check the number of cores */ 1279 cores_max = ctpop64(chip->cores_mask); 1280 if (chip->nr_cores > cores_max) { 1281 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1282 cores_max); 1283 return; 1284 } 1285 } 1286 1287 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1288 { 1289 MachineState *ms = MACHINE(qdev_get_machine()); 1290 Error *error = NULL; 1291 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1292 const char *typename = pnv_chip_core_typename(chip); 1293 size_t typesize = object_type_get_instance_size(typename); 1294 int i, core_hwid; 1295 1296 if (!object_class_by_name(typename)) { 1297 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1298 return; 1299 } 1300 1301 /* Cores */ 1302 pnv_chip_core_sanitize(chip, &error); 1303 if (error) { 1304 error_propagate(errp, error); 1305 return; 1306 } 1307 1308 chip->cores = g_malloc0(typesize * chip->nr_cores); 1309 1310 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1311 && (i < chip->nr_cores); core_hwid++) { 1312 char core_name[32]; 1313 void *pnv_core = chip->cores + i * typesize; 1314 uint64_t xscom_core_base; 1315 1316 if (!(chip->cores_mask & (1ull << core_hwid))) { 1317 continue; 1318 } 1319 1320 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1321 object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize, 1322 typename, &error_fatal, NULL); 1323 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", 1324 &error_fatal); 1325 object_property_set_int(OBJECT(pnv_core), core_hwid, 1326 CPU_CORE_PROP_CORE_ID, &error_fatal); 1327 object_property_set_int(OBJECT(pnv_core), 1328 pcc->core_pir(chip, core_hwid), 1329 "pir", &error_fatal); 1330 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1331 &error_abort); 1332 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1333 &error_fatal); 1334 1335 /* Each core has an XSCOM MMIO region */ 1336 if (!pnv_chip_is_power9(chip)) { 1337 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); 1338 } else { 1339 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); 1340 } 1341 1342 pnv_xscom_add_subregion(chip, xscom_core_base, 1343 &PNV_CORE(pnv_core)->xscom_regs); 1344 i++; 1345 } 1346 } 1347 1348 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1349 { 1350 PnvChip *chip = PNV_CHIP(dev); 1351 Error *error = NULL; 1352 1353 /* Cores */ 1354 pnv_chip_core_realize(chip, &error); 1355 if (error) { 1356 error_propagate(errp, error); 1357 return; 1358 } 1359 } 1360 1361 static Property pnv_chip_properties[] = { 1362 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1363 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1364 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1365 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1366 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1367 DEFINE_PROP_END_OF_LIST(), 1368 }; 1369 1370 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1371 { 1372 DeviceClass *dc = DEVICE_CLASS(klass); 1373 1374 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1375 dc->realize = pnv_chip_realize; 1376 dc->props = pnv_chip_properties; 1377 dc->desc = "PowerNV Chip"; 1378 } 1379 1380 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1381 { 1382 PnvMachineState *pnv = PNV_MACHINE(xi); 1383 int i; 1384 1385 for (i = 0; i < pnv->num_chips; i++) { 1386 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1387 1388 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1389 return &chip8->psi.ics; 1390 } 1391 } 1392 return NULL; 1393 } 1394 1395 static void pnv_ics_resend(XICSFabric *xi) 1396 { 1397 PnvMachineState *pnv = PNV_MACHINE(xi); 1398 int i; 1399 1400 for (i = 0; i < pnv->num_chips; i++) { 1401 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1402 ics_resend(&chip8->psi.ics); 1403 } 1404 } 1405 1406 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1407 { 1408 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1409 1410 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1411 } 1412 1413 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1414 Monitor *mon) 1415 { 1416 PnvMachineState *pnv = PNV_MACHINE(obj); 1417 int i; 1418 CPUState *cs; 1419 1420 CPU_FOREACH(cs) { 1421 PowerPCCPU *cpu = POWERPC_CPU(cs); 1422 1423 if (pnv_chip_is_power9(pnv->chips[0])) { 1424 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1425 } else { 1426 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1427 } 1428 } 1429 1430 for (i = 0; i < pnv->num_chips; i++) { 1431 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1432 } 1433 } 1434 1435 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1436 void *opaque, Error **errp) 1437 { 1438 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1439 } 1440 1441 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1442 void *opaque, Error **errp) 1443 { 1444 PnvMachineState *pnv = PNV_MACHINE(obj); 1445 uint32_t num_chips; 1446 Error *local_err = NULL; 1447 1448 visit_type_uint32(v, name, &num_chips, &local_err); 1449 if (local_err) { 1450 error_propagate(errp, local_err); 1451 return; 1452 } 1453 1454 /* 1455 * TODO: should we decide on how many chips we can create based 1456 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1457 */ 1458 if (!is_power_of_2(num_chips) || num_chips > 4) { 1459 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1460 return; 1461 } 1462 1463 pnv->num_chips = num_chips; 1464 } 1465 1466 static void pnv_machine_instance_init(Object *obj) 1467 { 1468 PnvMachineState *pnv = PNV_MACHINE(obj); 1469 pnv->num_chips = 1; 1470 } 1471 1472 static void pnv_machine_class_props_init(ObjectClass *oc) 1473 { 1474 object_class_property_add(oc, "num-chips", "uint32", 1475 pnv_get_num_chips, pnv_set_num_chips, 1476 NULL, NULL, NULL); 1477 object_class_property_set_description(oc, "num-chips", 1478 "Specifies the number of processor chips", 1479 NULL); 1480 } 1481 1482 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1483 { 1484 MachineClass *mc = MACHINE_CLASS(oc); 1485 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1486 1487 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1488 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1489 1490 xic->icp_get = pnv_icp_get; 1491 xic->ics_get = pnv_ics_get; 1492 xic->ics_resend = pnv_ics_resend; 1493 } 1494 1495 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1496 { 1497 MachineClass *mc = MACHINE_CLASS(oc); 1498 1499 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1500 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1501 1502 mc->alias = "powernv"; 1503 } 1504 1505 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1506 { 1507 MachineClass *mc = MACHINE_CLASS(oc); 1508 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1509 1510 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1511 mc->init = pnv_init; 1512 mc->reset = pnv_reset; 1513 mc->max_cpus = MAX_CPUS; 1514 /* Pnv provides a AHCI device for storage */ 1515 mc->block_default_type = IF_IDE; 1516 mc->no_parallel = 1; 1517 mc->default_boot_order = NULL; 1518 /* 1519 * RAM defaults to less than 2048 for 32-bit hosts, and large 1520 * enough to fit the maximum initrd size at it's load address 1521 */ 1522 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1523 ispc->print_info = pnv_pic_print_info; 1524 1525 pnv_machine_class_props_init(oc); 1526 } 1527 1528 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1529 { \ 1530 .name = type, \ 1531 .class_init = class_initfn, \ 1532 .parent = TYPE_PNV8_CHIP, \ 1533 } 1534 1535 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1536 { \ 1537 .name = type, \ 1538 .class_init = class_initfn, \ 1539 .parent = TYPE_PNV9_CHIP, \ 1540 } 1541 1542 static const TypeInfo types[] = { 1543 { 1544 .name = MACHINE_TYPE_NAME("powernv9"), 1545 .parent = TYPE_PNV_MACHINE, 1546 .class_init = pnv_machine_power9_class_init, 1547 }, 1548 { 1549 .name = MACHINE_TYPE_NAME("powernv8"), 1550 .parent = TYPE_PNV_MACHINE, 1551 .class_init = pnv_machine_power8_class_init, 1552 .interfaces = (InterfaceInfo[]) { 1553 { TYPE_XICS_FABRIC }, 1554 { }, 1555 }, 1556 }, 1557 { 1558 .name = TYPE_PNV_MACHINE, 1559 .parent = TYPE_MACHINE, 1560 .abstract = true, 1561 .instance_size = sizeof(PnvMachineState), 1562 .instance_init = pnv_machine_instance_init, 1563 .class_init = pnv_machine_class_init, 1564 .interfaces = (InterfaceInfo[]) { 1565 { TYPE_INTERRUPT_STATS_PROVIDER }, 1566 { }, 1567 }, 1568 }, 1569 { 1570 .name = TYPE_PNV_CHIP, 1571 .parent = TYPE_SYS_BUS_DEVICE, 1572 .class_init = pnv_chip_class_init, 1573 .instance_size = sizeof(PnvChip), 1574 .class_size = sizeof(PnvChipClass), 1575 .abstract = true, 1576 }, 1577 1578 /* 1579 * P9 chip and variants 1580 */ 1581 { 1582 .name = TYPE_PNV9_CHIP, 1583 .parent = TYPE_PNV_CHIP, 1584 .instance_init = pnv_chip_power9_instance_init, 1585 .instance_size = sizeof(Pnv9Chip), 1586 }, 1587 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1588 1589 /* 1590 * P8 chip and variants 1591 */ 1592 { 1593 .name = TYPE_PNV8_CHIP, 1594 .parent = TYPE_PNV_CHIP, 1595 .instance_init = pnv_chip_power8_instance_init, 1596 .instance_size = sizeof(Pnv8Chip), 1597 }, 1598 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1599 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1600 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1601 pnv_chip_power8nvl_class_init), 1602 }; 1603 1604 DEFINE_TYPES(types) 1605