1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci-host/pnv_phb.h" 47 #include "hw/pci-host/pnv_phb3.h" 48 #include "hw/pci-host/pnv_phb4.h" 49 50 #include "hw/ppc/xics.h" 51 #include "hw/qdev-properties.h" 52 #include "hw/ppc/pnv_chip.h" 53 #include "hw/ppc/pnv_xscom.h" 54 #include "hw/ppc/pnv_pnor.h" 55 56 #include "hw/isa/isa.h" 57 #include "hw/char/serial.h" 58 #include "hw/rtc/mc146818rtc.h" 59 60 #include <libfdt.h> 61 62 #define FDT_MAX_SIZE (1 * MiB) 63 64 #define FW_FILE_NAME "skiboot.lid" 65 #define FW_LOAD_ADDR 0x0 66 #define FW_MAX_SIZE (16 * MiB) 67 68 #define KERNEL_LOAD_ADDR 0x20000000 69 #define KERNEL_MAX_SIZE (128 * MiB) 70 #define INITRD_LOAD_ADDR 0x28000000 71 #define INITRD_MAX_SIZE (128 * MiB) 72 73 static const char *pnv_chip_core_typename(const PnvChip *o) 74 { 75 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 76 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 77 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 78 const char *core_type = object_class_get_name(object_class_by_name(s)); 79 g_free(s); 80 return core_type; 81 } 82 83 /* 84 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 85 * 4 * 4 sockets * 12 cores * 8 threads = 1536 86 * Let's make it 2^11 87 */ 88 #define MAX_CPUS 2048 89 90 /* 91 * Memory nodes are created by hostboot, one for each range of memory 92 * that has a different "affinity". In practice, it means one range 93 * per chip. 94 */ 95 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 96 { 97 char *mem_name; 98 uint64_t mem_reg_property[2]; 99 int off; 100 101 mem_reg_property[0] = cpu_to_be64(start); 102 mem_reg_property[1] = cpu_to_be64(size); 103 104 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 105 off = fdt_add_subnode(fdt, 0, mem_name); 106 g_free(mem_name); 107 108 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 109 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 110 sizeof(mem_reg_property)))); 111 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 112 } 113 114 static int get_cpus_node(void *fdt) 115 { 116 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 117 118 if (cpus_offset < 0) { 119 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 120 if (cpus_offset) { 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 123 } 124 } 125 _FDT(cpus_offset); 126 return cpus_offset; 127 } 128 129 /* 130 * The PowerNV cores (and threads) need to use real HW ids and not an 131 * incremental index like it has been done on other platforms. This HW 132 * id is stored in the CPU PIR, it is used to create cpu nodes in the 133 * device tree, used in XSCOM to address cores and in interrupt 134 * servers. 135 */ 136 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 137 { 138 PowerPCCPU *cpu = pc->threads[0]; 139 CPUState *cs = CPU(cpu); 140 DeviceClass *dc = DEVICE_GET_CLASS(cs); 141 int smt_threads = CPU_CORE(pc)->nr_threads; 142 CPUPPCState *env = &cpu->env; 143 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 145 int i; 146 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 147 0xffffffff, 0xffffffff}; 148 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 149 uint32_t cpufreq = 1000000000; 150 uint32_t page_sizes_prop[64]; 151 size_t page_sizes_prop_size; 152 const uint8_t pa_features[] = { 24, 0, 153 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 154 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 155 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 156 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 157 int offset; 158 char *nodename; 159 int cpus_offset = get_cpus_node(fdt); 160 161 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 162 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 163 _FDT(offset); 164 g_free(nodename); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 170 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 171 172 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 176 env->dcache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 178 env->icache_line_size))); 179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 180 env->icache_line_size))); 181 182 if (pcc->l1_dcache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 184 pcc->l1_dcache_size))); 185 } else { 186 warn_report("Unknown L1 dcache size for cpu"); 187 } 188 if (pcc->l1_icache_size) { 189 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 190 pcc->l1_icache_size))); 191 } else { 192 warn_report("Unknown L1 icache size for cpu"); 193 } 194 195 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 196 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 198 cpu->hash64_opts->slb_size))); 199 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 200 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 201 202 if (ppc_has_spr(cpu, SPR_PURR)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 204 } 205 206 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 207 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 208 segs, sizeof(segs)))); 209 } 210 211 /* 212 * Advertise VMX/VSX (vector extensions) if available 213 * 0 / no property == no vector extensions 214 * 1 == VMX / Altivec available 215 * 2 == VSX available 216 */ 217 if (env->insns_flags & PPC_ALTIVEC) { 218 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 219 220 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 221 } 222 223 /* 224 * Advertise DFP (Decimal Floating Point) if available 225 * 0 / no property == no DFP 226 * 1 == DFP available 227 */ 228 if (env->insns_flags2 & PPC2_DFP) { 229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 230 } 231 232 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 233 sizeof(page_sizes_prop)); 234 if (page_sizes_prop_size) { 235 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 236 page_sizes_prop, page_sizes_prop_size))); 237 } 238 239 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 240 pa_features, sizeof(pa_features)))); 241 242 /* Build interrupt servers properties */ 243 for (i = 0; i < smt_threads; i++) { 244 servers_prop[i] = cpu_to_be32(pc->pir + i); 245 } 246 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 247 servers_prop, sizeof(*servers_prop) * smt_threads))); 248 } 249 250 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 251 uint32_t nr_threads) 252 { 253 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 254 char *name; 255 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 256 uint32_t irange[2], i, rsize; 257 uint64_t *reg; 258 int offset; 259 260 irange[0] = cpu_to_be32(pir); 261 irange[1] = cpu_to_be32(nr_threads); 262 263 rsize = sizeof(uint64_t) * 2 * nr_threads; 264 reg = g_malloc(rsize); 265 for (i = 0; i < nr_threads; i++) { 266 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 267 reg[i * 2 + 1] = cpu_to_be64(0x1000); 268 } 269 270 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 271 offset = fdt_add_subnode(fdt, 0, name); 272 _FDT(offset); 273 g_free(name); 274 275 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 276 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 277 _FDT((fdt_setprop_string(fdt, offset, "device_type", 278 "PowerPC-External-Interrupt-Presentation"))); 279 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 280 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 281 irange, sizeof(irange)))); 282 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 283 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 284 g_free(reg); 285 } 286 287 static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb, 288 Error **errp) 289 { 290 PnvPHB *phb_base = phb->phb_base; 291 PnvPhb4PecState *pecs = NULL; 292 int chip_id = phb->chip_id; 293 int index = phb->phb_id; 294 int i, j; 295 296 if (phb_base->version == 4) { 297 Pnv9Chip *chip9 = PNV9_CHIP(chip); 298 299 pecs = chip9->pecs; 300 } else if (phb_base->version == 5) { 301 Pnv10Chip *chip10 = PNV10_CHIP(chip); 302 303 pecs = chip10->pecs; 304 } else { 305 g_assert_not_reached(); 306 } 307 308 for (i = 0; i < chip->num_pecs; i++) { 309 /* 310 * For each PEC, check the amount of phbs it supports 311 * and see if the given phb4 index matches an index. 312 */ 313 PnvPhb4PecState *pec = &pecs[i]; 314 315 for (j = 0; j < pec->num_phbs; j++) { 316 if (index == pnv_phb4_pec_get_phb_id(pec, j)) { 317 pec->phbs[j] = phb->phb_base; 318 return pec; 319 } 320 } 321 } 322 error_setg(errp, 323 "pnv-phb4 chip-id %d index %d didn't match any existing PEC", 324 chip_id, index); 325 326 return NULL; 327 } 328 329 /* 330 * Adds a PnvPHB to the chip. Returns the parent obj of the 331 * PHB which varies with each version (phb version 3 is parented 332 * by the chip, version 4 and 5 are parented by the PEC 333 * device). 334 * 335 * TODO: for version 3 we're still parenting the PHB with the 336 * chip. We should parent with a (so far not implemented) 337 * PHB3 PEC device. 338 */ 339 Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp) 340 { 341 if (phb->version == 3) { 342 Pnv8Chip *chip8 = PNV8_CHIP(chip); 343 344 phb->chip = chip; 345 346 chip8->phbs[chip8->num_phbs] = phb; 347 chip8->num_phbs++; 348 349 return OBJECT(chip); 350 } 351 352 phb->pec = pnv_phb4_get_pec(chip, PNV_PHB4(phb->backend), errp); 353 354 return OBJECT(phb->pec); 355 } 356 357 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 358 { 359 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 360 int i; 361 362 pnv_dt_xscom(chip, fdt, 0, 363 cpu_to_be64(PNV_XSCOM_BASE(chip)), 364 cpu_to_be64(PNV_XSCOM_SIZE), 365 compat, sizeof(compat)); 366 367 for (i = 0; i < chip->nr_cores; i++) { 368 PnvCore *pnv_core = chip->cores[i]; 369 370 pnv_dt_core(chip, pnv_core, fdt); 371 372 /* Interrupt Control Presenters (ICP). One per core. */ 373 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 374 } 375 376 if (chip->ram_size) { 377 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 378 } 379 } 380 381 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 382 { 383 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 384 int i; 385 386 pnv_dt_xscom(chip, fdt, 0, 387 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 388 cpu_to_be64(PNV9_XSCOM_SIZE), 389 compat, sizeof(compat)); 390 391 for (i = 0; i < chip->nr_cores; i++) { 392 PnvCore *pnv_core = chip->cores[i]; 393 394 pnv_dt_core(chip, pnv_core, fdt); 395 } 396 397 if (chip->ram_size) { 398 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 399 } 400 401 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 402 } 403 404 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 405 { 406 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 407 int i; 408 409 pnv_dt_xscom(chip, fdt, 0, 410 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 411 cpu_to_be64(PNV10_XSCOM_SIZE), 412 compat, sizeof(compat)); 413 414 for (i = 0; i < chip->nr_cores; i++) { 415 PnvCore *pnv_core = chip->cores[i]; 416 417 pnv_dt_core(chip, pnv_core, fdt); 418 } 419 420 if (chip->ram_size) { 421 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 422 } 423 424 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 425 } 426 427 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 428 { 429 uint32_t io_base = d->ioport_id; 430 uint32_t io_regs[] = { 431 cpu_to_be32(1), 432 cpu_to_be32(io_base), 433 cpu_to_be32(2) 434 }; 435 char *name; 436 int node; 437 438 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 439 node = fdt_add_subnode(fdt, lpc_off, name); 440 _FDT(node); 441 g_free(name); 442 443 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 444 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 445 } 446 447 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 448 { 449 const char compatible[] = "ns16550\0pnpPNP,501"; 450 uint32_t io_base = d->ioport_id; 451 uint32_t io_regs[] = { 452 cpu_to_be32(1), 453 cpu_to_be32(io_base), 454 cpu_to_be32(8) 455 }; 456 uint32_t irq; 457 char *name; 458 int node; 459 460 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 461 462 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 463 node = fdt_add_subnode(fdt, lpc_off, name); 464 _FDT(node); 465 g_free(name); 466 467 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 468 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 469 sizeof(compatible)))); 470 471 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 472 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 473 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 474 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 475 fdt_get_phandle(fdt, lpc_off)))); 476 477 /* This is needed by Linux */ 478 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 479 } 480 481 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 482 { 483 const char compatible[] = "bt\0ipmi-bt"; 484 uint32_t io_base; 485 uint32_t io_regs[] = { 486 cpu_to_be32(1), 487 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 488 cpu_to_be32(3) 489 }; 490 uint32_t irq; 491 char *name; 492 int node; 493 494 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 495 io_regs[1] = cpu_to_be32(io_base); 496 497 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 498 499 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 500 node = fdt_add_subnode(fdt, lpc_off, name); 501 _FDT(node); 502 g_free(name); 503 504 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 505 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 506 sizeof(compatible)))); 507 508 /* Mark it as reserved to avoid Linux trying to claim it */ 509 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 510 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 511 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 512 fdt_get_phandle(fdt, lpc_off)))); 513 } 514 515 typedef struct ForeachPopulateArgs { 516 void *fdt; 517 int offset; 518 } ForeachPopulateArgs; 519 520 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 521 { 522 ForeachPopulateArgs *args = opaque; 523 ISADevice *d = ISA_DEVICE(dev); 524 525 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 526 pnv_dt_rtc(d, args->fdt, args->offset); 527 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 528 pnv_dt_serial(d, args->fdt, args->offset); 529 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 530 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 531 } else { 532 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 533 d->ioport_id); 534 } 535 536 return 0; 537 } 538 539 /* 540 * The default LPC bus of a multichip system is on chip 0. It's 541 * recognized by the firmware (skiboot) using a "primary" property. 542 */ 543 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 544 { 545 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 546 ForeachPopulateArgs args = { 547 .fdt = fdt, 548 .offset = isa_offset, 549 }; 550 uint32_t phandle; 551 552 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 553 554 phandle = qemu_fdt_alloc_phandle(fdt); 555 assert(phandle > 0); 556 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 557 558 /* 559 * ISA devices are not necessarily parented to the ISA bus so we 560 * can not use object_child_foreach() 561 */ 562 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 563 &args); 564 } 565 566 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 567 { 568 int off; 569 570 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 571 off = fdt_add_subnode(fdt, off, "power-mgt"); 572 573 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 574 } 575 576 static void *pnv_dt_create(MachineState *machine) 577 { 578 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 579 PnvMachineState *pnv = PNV_MACHINE(machine); 580 void *fdt; 581 char *buf; 582 int off; 583 int i; 584 585 fdt = g_malloc0(FDT_MAX_SIZE); 586 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 587 588 /* /qemu node */ 589 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 590 591 /* Root node */ 592 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 593 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 594 _FDT((fdt_setprop_string(fdt, 0, "model", 595 "IBM PowerNV (emulated by qemu)"))); 596 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 597 598 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 599 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 600 if (qemu_uuid_set) { 601 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 602 } 603 g_free(buf); 604 605 off = fdt_add_subnode(fdt, 0, "chosen"); 606 if (machine->kernel_cmdline) { 607 _FDT((fdt_setprop_string(fdt, off, "bootargs", 608 machine->kernel_cmdline))); 609 } 610 611 if (pnv->initrd_size) { 612 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 613 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 614 615 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 616 &start_prop, sizeof(start_prop)))); 617 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 618 &end_prop, sizeof(end_prop)))); 619 } 620 621 /* Populate device tree for each chip */ 622 for (i = 0; i < pnv->num_chips; i++) { 623 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 624 } 625 626 /* Populate ISA devices on chip 0 */ 627 pnv_dt_isa(pnv, fdt); 628 629 if (pnv->bmc) { 630 pnv_dt_bmc_sensors(pnv->bmc, fdt); 631 } 632 633 /* Create an extra node for power management on machines that support it */ 634 if (pmc->dt_power_mgt) { 635 pmc->dt_power_mgt(pnv, fdt); 636 } 637 638 return fdt; 639 } 640 641 static void pnv_powerdown_notify(Notifier *n, void *opaque) 642 { 643 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 644 645 if (pnv->bmc) { 646 pnv_bmc_powerdown(pnv->bmc); 647 } 648 } 649 650 static void pnv_reset(MachineState *machine, ShutdownCause reason) 651 { 652 PnvMachineState *pnv = PNV_MACHINE(machine); 653 IPMIBmc *bmc; 654 void *fdt; 655 656 qemu_devices_reset(reason); 657 658 /* 659 * The machine should provide by default an internal BMC simulator. 660 * If not, try to use the BMC device that was provided on the command 661 * line. 662 */ 663 bmc = pnv_bmc_find(&error_fatal); 664 if (!pnv->bmc) { 665 if (!bmc) { 666 if (!qtest_enabled()) { 667 warn_report("machine has no BMC device. Use '-device " 668 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 669 "to define one"); 670 } 671 } else { 672 pnv_bmc_set_pnor(bmc, pnv->pnor); 673 pnv->bmc = bmc; 674 } 675 } 676 677 fdt = pnv_dt_create(machine); 678 679 /* Pack resulting tree */ 680 _FDT((fdt_pack(fdt))); 681 682 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 683 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 684 685 /* 686 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 687 * the existing machine->fdt to avoid leaking it during 688 * a reset. 689 */ 690 g_free(machine->fdt); 691 machine->fdt = fdt; 692 } 693 694 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 695 { 696 Pnv8Chip *chip8 = PNV8_CHIP(chip); 697 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 698 699 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 700 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 701 } 702 703 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 704 { 705 Pnv8Chip *chip8 = PNV8_CHIP(chip); 706 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 707 708 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 709 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 710 } 711 712 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 713 { 714 Pnv9Chip *chip9 = PNV9_CHIP(chip); 715 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 716 717 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 718 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 719 } 720 721 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 722 { 723 Pnv10Chip *chip10 = PNV10_CHIP(chip); 724 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 725 726 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 727 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 728 } 729 730 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 731 { 732 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 733 } 734 735 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 736 { 737 Pnv8Chip *chip8 = PNV8_CHIP(chip); 738 int i; 739 740 ics_pic_print_info(&chip8->psi.ics, mon); 741 742 for (i = 0; i < chip8->num_phbs; i++) { 743 PnvPHB *phb = chip8->phbs[i]; 744 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 745 746 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 747 ics_pic_print_info(&phb3->lsis, mon); 748 } 749 } 750 751 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 752 { 753 Monitor *mon = opaque; 754 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 755 756 if (!phb) { 757 return 0; 758 } 759 760 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon); 761 762 return 0; 763 } 764 765 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 766 { 767 Pnv9Chip *chip9 = PNV9_CHIP(chip); 768 769 pnv_xive_pic_print_info(&chip9->xive, mon); 770 pnv_psi_pic_print_info(&chip9->psi, mon); 771 772 object_child_foreach_recursive(OBJECT(chip), 773 pnv_chip_power9_pic_print_info_child, mon); 774 } 775 776 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 777 uint32_t core_id) 778 { 779 return PNV_XSCOM_EX_BASE(core_id); 780 } 781 782 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 783 uint32_t core_id) 784 { 785 return PNV9_XSCOM_EC_BASE(core_id); 786 } 787 788 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 789 uint32_t core_id) 790 { 791 return PNV10_XSCOM_EC_BASE(core_id); 792 } 793 794 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 795 { 796 PowerPCCPUClass *ppc_default = 797 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 798 PowerPCCPUClass *ppc = 799 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 800 801 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 802 } 803 804 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 805 { 806 ISADevice *dev = isa_new("isa-ipmi-bt"); 807 808 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 809 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 810 isa_realize_and_unref(dev, bus, &error_fatal); 811 } 812 813 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 814 { 815 Pnv10Chip *chip10 = PNV10_CHIP(chip); 816 817 pnv_xive2_pic_print_info(&chip10->xive, mon); 818 pnv_psi_pic_print_info(&chip10->psi, mon); 819 820 object_child_foreach_recursive(OBJECT(chip), 821 pnv_chip_power9_pic_print_info_child, mon); 822 } 823 824 /* Always give the first 1GB to chip 0 else we won't boot */ 825 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 826 { 827 MachineState *machine = MACHINE(pnv); 828 uint64_t ram_per_chip; 829 830 assert(machine->ram_size >= 1 * GiB); 831 832 ram_per_chip = machine->ram_size / pnv->num_chips; 833 if (ram_per_chip >= 1 * GiB) { 834 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 835 } 836 837 assert(pnv->num_chips > 1); 838 839 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 840 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 841 } 842 843 static void pnv_init(MachineState *machine) 844 { 845 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 846 PnvMachineState *pnv = PNV_MACHINE(machine); 847 MachineClass *mc = MACHINE_GET_CLASS(machine); 848 char *fw_filename; 849 long fw_size; 850 uint64_t chip_ram_start = 0; 851 int i; 852 char *chip_typename; 853 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 854 DeviceState *dev; 855 856 if (kvm_enabled()) { 857 error_report("The powernv machine does not work with KVM acceleration"); 858 exit(EXIT_FAILURE); 859 } 860 861 /* allocate RAM */ 862 if (machine->ram_size < mc->default_ram_size) { 863 char *sz = size_to_str(mc->default_ram_size); 864 error_report("Invalid RAM size, should be bigger than %s", sz); 865 g_free(sz); 866 exit(EXIT_FAILURE); 867 } 868 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 869 870 /* 871 * Create our simple PNOR device 872 */ 873 dev = qdev_new(TYPE_PNV_PNOR); 874 if (pnor) { 875 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 876 } 877 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 878 pnv->pnor = PNV_PNOR(dev); 879 880 /* load skiboot firmware */ 881 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 882 if (!fw_filename) { 883 error_report("Could not find OPAL firmware '%s'", bios_name); 884 exit(1); 885 } 886 887 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 888 if (fw_size < 0) { 889 error_report("Could not load OPAL firmware '%s'", fw_filename); 890 exit(1); 891 } 892 g_free(fw_filename); 893 894 /* load kernel */ 895 if (machine->kernel_filename) { 896 long kernel_size; 897 898 kernel_size = load_image_targphys(machine->kernel_filename, 899 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 900 if (kernel_size < 0) { 901 error_report("Could not load kernel '%s'", 902 machine->kernel_filename); 903 exit(1); 904 } 905 } 906 907 /* load initrd */ 908 if (machine->initrd_filename) { 909 pnv->initrd_base = INITRD_LOAD_ADDR; 910 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 911 pnv->initrd_base, INITRD_MAX_SIZE); 912 if (pnv->initrd_size < 0) { 913 error_report("Could not load initial ram disk '%s'", 914 machine->initrd_filename); 915 exit(1); 916 } 917 } 918 919 /* MSIs are supported on this platform */ 920 msi_nonbroken = true; 921 922 /* 923 * Check compatibility of the specified CPU with the machine 924 * default. 925 */ 926 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 927 error_report("invalid CPU model '%s' for %s machine", 928 machine->cpu_type, mc->name); 929 exit(1); 930 } 931 932 /* Create the processor chips */ 933 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 934 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 935 i, machine->cpu_type); 936 if (!object_class_by_name(chip_typename)) { 937 error_report("invalid chip model '%.*s' for %s machine", 938 i, machine->cpu_type, mc->name); 939 exit(1); 940 } 941 942 pnv->num_chips = 943 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 944 /* 945 * TODO: should we decide on how many chips we can create based 946 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 947 */ 948 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 949 error_report("invalid number of chips: '%d'", pnv->num_chips); 950 error_printf( 951 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 952 exit(1); 953 } 954 955 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 956 for (i = 0; i < pnv->num_chips; i++) { 957 char chip_name[32]; 958 Object *chip = OBJECT(qdev_new(chip_typename)); 959 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 960 961 pnv->chips[i] = PNV_CHIP(chip); 962 963 /* Distribute RAM among the chips */ 964 object_property_set_int(chip, "ram-start", chip_ram_start, 965 &error_fatal); 966 object_property_set_int(chip, "ram-size", chip_ram_size, 967 &error_fatal); 968 chip_ram_start += chip_ram_size; 969 970 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 971 object_property_add_child(OBJECT(pnv), chip_name, chip); 972 object_property_set_int(chip, "chip-id", i, &error_fatal); 973 object_property_set_int(chip, "nr-cores", machine->smp.cores, 974 &error_fatal); 975 object_property_set_int(chip, "nr-threads", machine->smp.threads, 976 &error_fatal); 977 /* 978 * The POWER8 machine use the XICS interrupt interface. 979 * Propagate the XICS fabric to the chip and its controllers. 980 */ 981 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 982 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 983 } 984 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 985 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 986 &error_abort); 987 } 988 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 989 } 990 g_free(chip_typename); 991 992 /* Instantiate ISA bus on chip 0 */ 993 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 994 995 /* Create serial port */ 996 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 997 998 /* Create an RTC ISA device too */ 999 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1000 1001 /* 1002 * Create the machine BMC simulator and the IPMI BT device for 1003 * communication with the BMC 1004 */ 1005 if (defaults_enabled()) { 1006 pnv->bmc = pnv_bmc_create(pnv->pnor); 1007 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1008 } 1009 1010 /* 1011 * The PNOR is mapped on the LPC FW address space by the BMC. 1012 * Since we can not reach the remote BMC machine with LPC memops, 1013 * map it always for now. 1014 */ 1015 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1016 &pnv->pnor->mmio); 1017 1018 /* 1019 * OpenPOWER systems use a IPMI SEL Event message to notify the 1020 * host to powerdown 1021 */ 1022 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1023 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1024 } 1025 1026 /* 1027 * 0:21 Reserved - Read as zeros 1028 * 22:24 Chip ID 1029 * 25:28 Core number 1030 * 29:31 Thread ID 1031 */ 1032 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 1033 { 1034 return (chip->chip_id << 7) | (core_id << 3); 1035 } 1036 1037 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1038 Error **errp) 1039 { 1040 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1041 Error *local_err = NULL; 1042 Object *obj; 1043 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1044 1045 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1046 if (local_err) { 1047 error_propagate(errp, local_err); 1048 return; 1049 } 1050 1051 pnv_cpu->intc = obj; 1052 } 1053 1054 1055 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1056 { 1057 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1058 1059 icp_reset(ICP(pnv_cpu->intc)); 1060 } 1061 1062 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1063 { 1064 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1065 1066 icp_destroy(ICP(pnv_cpu->intc)); 1067 pnv_cpu->intc = NULL; 1068 } 1069 1070 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1071 Monitor *mon) 1072 { 1073 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1074 } 1075 1076 /* 1077 * 0:48 Reserved - Read as zeroes 1078 * 49:52 Node ID 1079 * 53:55 Chip ID 1080 * 56 Reserved - Read as zero 1081 * 57:61 Core number 1082 * 62:63 Thread ID 1083 * 1084 * We only care about the lower bits. uint32_t is fine for the moment. 1085 */ 1086 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 1087 { 1088 return (chip->chip_id << 8) | (core_id << 2); 1089 } 1090 1091 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1092 { 1093 return (chip->chip_id << 8) | (core_id << 2); 1094 } 1095 1096 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1097 Error **errp) 1098 { 1099 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1100 Error *local_err = NULL; 1101 Object *obj; 1102 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1103 1104 /* 1105 * The core creates its interrupt presenter but the XIVE interrupt 1106 * controller object is initialized afterwards. Hopefully, it's 1107 * only used at runtime. 1108 */ 1109 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1110 &local_err); 1111 if (local_err) { 1112 error_propagate(errp, local_err); 1113 return; 1114 } 1115 1116 pnv_cpu->intc = obj; 1117 } 1118 1119 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1120 { 1121 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1122 1123 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1124 } 1125 1126 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1127 { 1128 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1129 1130 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1131 pnv_cpu->intc = NULL; 1132 } 1133 1134 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1135 Monitor *mon) 1136 { 1137 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1138 } 1139 1140 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1141 Error **errp) 1142 { 1143 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1144 Error *local_err = NULL; 1145 Object *obj; 1146 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1147 1148 /* 1149 * The core creates its interrupt presenter but the XIVE2 interrupt 1150 * controller object is initialized afterwards. Hopefully, it's 1151 * only used at runtime. 1152 */ 1153 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1154 &local_err); 1155 if (local_err) { 1156 error_propagate(errp, local_err); 1157 return; 1158 } 1159 1160 pnv_cpu->intc = obj; 1161 } 1162 1163 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1164 { 1165 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1166 1167 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1168 } 1169 1170 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1171 { 1172 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1173 1174 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1175 pnv_cpu->intc = NULL; 1176 } 1177 1178 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1179 Monitor *mon) 1180 { 1181 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1182 } 1183 1184 /* 1185 * Allowed core identifiers on a POWER8 Processor Chip : 1186 * 1187 * <EX0 reserved> 1188 * EX1 - Venice only 1189 * EX2 - Venice only 1190 * EX3 - Venice only 1191 * EX4 1192 * EX5 1193 * EX6 1194 * <EX7,8 reserved> <reserved> 1195 * EX9 - Venice only 1196 * EX10 - Venice only 1197 * EX11 - Venice only 1198 * EX12 1199 * EX13 1200 * EX14 1201 * <EX15 reserved> 1202 */ 1203 #define POWER8E_CORE_MASK (0x7070ull) 1204 #define POWER8_CORE_MASK (0x7e7eull) 1205 1206 /* 1207 * POWER9 has 24 cores, ids starting at 0x0 1208 */ 1209 #define POWER9_CORE_MASK (0xffffffffffffffull) 1210 1211 1212 #define POWER10_CORE_MASK (0xffffffffffffffull) 1213 1214 static void pnv_chip_power8_instance_init(Object *obj) 1215 { 1216 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1217 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1218 int i; 1219 1220 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1221 (Object **)&chip8->xics, 1222 object_property_allow_set_link, 1223 OBJ_PROP_LINK_STRONG); 1224 1225 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1226 1227 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1228 1229 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1230 1231 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1232 1233 if (defaults_enabled()) { 1234 chip8->num_phbs = pcc->num_phbs; 1235 1236 for (i = 0; i < chip8->num_phbs; i++) { 1237 Object *phb = object_new(TYPE_PNV_PHB); 1238 1239 /* 1240 * We need the chip to parent the PHB to allow the DT 1241 * to build correctly (via pnv_xscom_dt()). 1242 * 1243 * TODO: the PHB should be parented by a PEC device that, at 1244 * this moment, is not modelled powernv8/phb3. 1245 */ 1246 object_property_add_child(obj, "phb[*]", phb); 1247 chip8->phbs[i] = PNV_PHB(phb); 1248 } 1249 } 1250 1251 } 1252 1253 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1254 { 1255 PnvChip *chip = PNV_CHIP(chip8); 1256 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1257 int i, j; 1258 char *name; 1259 1260 name = g_strdup_printf("icp-%x", chip->chip_id); 1261 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1262 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1263 g_free(name); 1264 1265 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1266 1267 /* Map the ICP registers for each thread */ 1268 for (i = 0; i < chip->nr_cores; i++) { 1269 PnvCore *pnv_core = chip->cores[i]; 1270 int core_hwid = CPU_CORE(pnv_core)->core_id; 1271 1272 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1273 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1274 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1275 1276 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1277 &icp->mmio); 1278 } 1279 } 1280 } 1281 1282 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1283 { 1284 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1285 PnvChip *chip = PNV_CHIP(dev); 1286 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1287 Pnv8Psi *psi8 = &chip8->psi; 1288 Error *local_err = NULL; 1289 int i; 1290 1291 assert(chip8->xics); 1292 1293 /* XSCOM bridge is first */ 1294 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1295 if (local_err) { 1296 error_propagate(errp, local_err); 1297 return; 1298 } 1299 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1300 1301 pcc->parent_realize(dev, &local_err); 1302 if (local_err) { 1303 error_propagate(errp, local_err); 1304 return; 1305 } 1306 1307 /* Processor Service Interface (PSI) Host Bridge */ 1308 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1309 &error_fatal); 1310 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1311 OBJECT(chip8->xics), &error_abort); 1312 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1313 return; 1314 } 1315 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1316 &PNV_PSI(psi8)->xscom_regs); 1317 1318 /* Create LPC controller */ 1319 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1320 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1321 1322 chip->fw_mr = &chip8->lpc.isa_fw; 1323 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1324 (uint64_t) PNV_XSCOM_BASE(chip), 1325 PNV_XSCOM_LPC_BASE); 1326 1327 /* 1328 * Interrupt Management Area. This is the memory region holding 1329 * all the Interrupt Control Presenter (ICP) registers 1330 */ 1331 pnv_chip_icp_realize(chip8, &local_err); 1332 if (local_err) { 1333 error_propagate(errp, local_err); 1334 return; 1335 } 1336 1337 /* Create the simplified OCC model */ 1338 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1339 return; 1340 } 1341 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1342 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1343 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); 1344 1345 /* OCC SRAM model */ 1346 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1347 &chip8->occ.sram_regs); 1348 1349 /* HOMER */ 1350 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1351 &error_abort); 1352 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1353 return; 1354 } 1355 /* Homer Xscom region */ 1356 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1357 1358 /* Homer mmio region */ 1359 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1360 &chip8->homer.regs); 1361 1362 /* PHB controllers */ 1363 for (i = 0; i < chip8->num_phbs; i++) { 1364 PnvPHB *phb = chip8->phbs[i]; 1365 1366 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1367 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1368 &error_fatal); 1369 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1370 &error_fatal); 1371 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1372 return; 1373 } 1374 } 1375 } 1376 1377 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1378 { 1379 addr &= (PNV_XSCOM_SIZE - 1); 1380 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1381 } 1382 1383 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1384 { 1385 DeviceClass *dc = DEVICE_CLASS(klass); 1386 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1387 1388 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1389 k->cores_mask = POWER8E_CORE_MASK; 1390 k->num_phbs = 3; 1391 k->core_pir = pnv_chip_core_pir_p8; 1392 k->intc_create = pnv_chip_power8_intc_create; 1393 k->intc_reset = pnv_chip_power8_intc_reset; 1394 k->intc_destroy = pnv_chip_power8_intc_destroy; 1395 k->intc_print_info = pnv_chip_power8_intc_print_info; 1396 k->isa_create = pnv_chip_power8_isa_create; 1397 k->dt_populate = pnv_chip_power8_dt_populate; 1398 k->pic_print_info = pnv_chip_power8_pic_print_info; 1399 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1400 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1401 dc->desc = "PowerNV Chip POWER8E"; 1402 1403 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1404 &k->parent_realize); 1405 } 1406 1407 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1408 { 1409 DeviceClass *dc = DEVICE_CLASS(klass); 1410 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1411 1412 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1413 k->cores_mask = POWER8_CORE_MASK; 1414 k->num_phbs = 3; 1415 k->core_pir = pnv_chip_core_pir_p8; 1416 k->intc_create = pnv_chip_power8_intc_create; 1417 k->intc_reset = pnv_chip_power8_intc_reset; 1418 k->intc_destroy = pnv_chip_power8_intc_destroy; 1419 k->intc_print_info = pnv_chip_power8_intc_print_info; 1420 k->isa_create = pnv_chip_power8_isa_create; 1421 k->dt_populate = pnv_chip_power8_dt_populate; 1422 k->pic_print_info = pnv_chip_power8_pic_print_info; 1423 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1424 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1425 dc->desc = "PowerNV Chip POWER8"; 1426 1427 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1428 &k->parent_realize); 1429 } 1430 1431 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1432 { 1433 DeviceClass *dc = DEVICE_CLASS(klass); 1434 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1435 1436 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1437 k->cores_mask = POWER8_CORE_MASK; 1438 k->num_phbs = 4; 1439 k->core_pir = pnv_chip_core_pir_p8; 1440 k->intc_create = pnv_chip_power8_intc_create; 1441 k->intc_reset = pnv_chip_power8_intc_reset; 1442 k->intc_destroy = pnv_chip_power8_intc_destroy; 1443 k->intc_print_info = pnv_chip_power8_intc_print_info; 1444 k->isa_create = pnv_chip_power8nvl_isa_create; 1445 k->dt_populate = pnv_chip_power8_dt_populate; 1446 k->pic_print_info = pnv_chip_power8_pic_print_info; 1447 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1448 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1449 dc->desc = "PowerNV Chip POWER8NVL"; 1450 1451 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1452 &k->parent_realize); 1453 } 1454 1455 static void pnv_chip_power9_instance_init(Object *obj) 1456 { 1457 PnvChip *chip = PNV_CHIP(obj); 1458 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1459 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1460 int i; 1461 1462 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1463 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1464 "xive-fabric"); 1465 1466 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1467 1468 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1469 1470 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1471 1472 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1473 1474 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1475 1476 /* Number of PECs is the chip default */ 1477 chip->num_pecs = pcc->num_pecs; 1478 1479 for (i = 0; i < chip->num_pecs; i++) { 1480 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1481 TYPE_PNV_PHB4_PEC); 1482 } 1483 } 1484 1485 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1486 PnvCore *pnv_core) 1487 { 1488 char eq_name[32]; 1489 int core_id = CPU_CORE(pnv_core)->core_id; 1490 1491 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1492 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1493 sizeof(*eq), TYPE_PNV_QUAD, 1494 &error_fatal, NULL); 1495 1496 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1497 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1498 } 1499 1500 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1501 { 1502 PnvChip *chip = PNV_CHIP(chip9); 1503 int i; 1504 1505 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1506 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1507 1508 for (i = 0; i < chip9->nr_quads; i++) { 1509 PnvQuad *eq = &chip9->quads[i]; 1510 1511 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1512 1513 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1514 &eq->xscom_regs); 1515 } 1516 } 1517 1518 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1519 { 1520 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1521 int i; 1522 1523 for (i = 0; i < chip->num_pecs; i++) { 1524 PnvPhb4PecState *pec = &chip9->pecs[i]; 1525 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1526 uint32_t pec_nest_base; 1527 uint32_t pec_pci_base; 1528 1529 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1530 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1531 &error_fatal); 1532 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1533 &error_fatal); 1534 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1535 return; 1536 } 1537 1538 pec_nest_base = pecc->xscom_nest_base(pec); 1539 pec_pci_base = pecc->xscom_pci_base(pec); 1540 1541 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1542 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1543 } 1544 } 1545 1546 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1547 { 1548 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1549 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1550 PnvChip *chip = PNV_CHIP(dev); 1551 Pnv9Psi *psi9 = &chip9->psi; 1552 Error *local_err = NULL; 1553 1554 /* XSCOM bridge is first */ 1555 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1556 if (local_err) { 1557 error_propagate(errp, local_err); 1558 return; 1559 } 1560 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1561 1562 pcc->parent_realize(dev, &local_err); 1563 if (local_err) { 1564 error_propagate(errp, local_err); 1565 return; 1566 } 1567 1568 pnv_chip_quad_realize(chip9, &local_err); 1569 if (local_err) { 1570 error_propagate(errp, local_err); 1571 return; 1572 } 1573 1574 /* XIVE interrupt controller (POWER9) */ 1575 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1576 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1577 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1578 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1579 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1580 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1581 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1582 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1583 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1584 &error_abort); 1585 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1586 return; 1587 } 1588 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1589 &chip9->xive.xscom_regs); 1590 1591 /* Processor Service Interface (PSI) Host Bridge */ 1592 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1593 &error_fatal); 1594 /* This is the only device with 4k ESB pages */ 1595 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1596 &error_fatal); 1597 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1598 return; 1599 } 1600 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1601 &PNV_PSI(psi9)->xscom_regs); 1602 1603 /* LPC */ 1604 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1605 return; 1606 } 1607 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1608 &chip9->lpc.xscom_regs); 1609 1610 chip->fw_mr = &chip9->lpc.isa_fw; 1611 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1612 (uint64_t) PNV9_LPCM_BASE(chip)); 1613 1614 /* Create the simplified OCC model */ 1615 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1616 return; 1617 } 1618 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1619 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1620 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); 1621 1622 /* OCC SRAM model */ 1623 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1624 &chip9->occ.sram_regs); 1625 1626 /* SBE */ 1627 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1628 return; 1629 } 1630 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1631 &chip9->sbe.xscom_ctrl_regs); 1632 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1633 &chip9->sbe.xscom_mbox_regs); 1634 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1635 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU)); 1636 1637 /* HOMER */ 1638 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1639 &error_abort); 1640 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1641 return; 1642 } 1643 /* Homer Xscom region */ 1644 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1645 1646 /* Homer mmio region */ 1647 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1648 &chip9->homer.regs); 1649 1650 /* PEC PHBs */ 1651 pnv_chip_power9_pec_realize(chip, &local_err); 1652 if (local_err) { 1653 error_propagate(errp, local_err); 1654 return; 1655 } 1656 } 1657 1658 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1659 { 1660 addr &= (PNV9_XSCOM_SIZE - 1); 1661 return addr >> 3; 1662 } 1663 1664 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1665 { 1666 DeviceClass *dc = DEVICE_CLASS(klass); 1667 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1668 1669 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1670 k->cores_mask = POWER9_CORE_MASK; 1671 k->core_pir = pnv_chip_core_pir_p9; 1672 k->intc_create = pnv_chip_power9_intc_create; 1673 k->intc_reset = pnv_chip_power9_intc_reset; 1674 k->intc_destroy = pnv_chip_power9_intc_destroy; 1675 k->intc_print_info = pnv_chip_power9_intc_print_info; 1676 k->isa_create = pnv_chip_power9_isa_create; 1677 k->dt_populate = pnv_chip_power9_dt_populate; 1678 k->pic_print_info = pnv_chip_power9_pic_print_info; 1679 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1680 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1681 dc->desc = "PowerNV Chip POWER9"; 1682 k->num_pecs = PNV9_CHIP_MAX_PEC; 1683 1684 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1685 &k->parent_realize); 1686 } 1687 1688 static void pnv_chip_power10_instance_init(Object *obj) 1689 { 1690 PnvChip *chip = PNV_CHIP(obj); 1691 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1692 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1693 int i; 1694 1695 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1696 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1697 "xive-fabric"); 1698 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1699 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1700 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1701 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1702 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1703 1704 chip->num_pecs = pcc->num_pecs; 1705 1706 for (i = 0; i < chip->num_pecs; i++) { 1707 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1708 TYPE_PNV_PHB5_PEC); 1709 } 1710 } 1711 1712 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1713 { 1714 PnvChip *chip = PNV_CHIP(chip10); 1715 int i; 1716 1717 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1718 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1719 1720 for (i = 0; i < chip10->nr_quads; i++) { 1721 PnvQuad *eq = &chip10->quads[i]; 1722 1723 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1724 1725 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1726 &eq->xscom_regs); 1727 } 1728 } 1729 1730 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1731 { 1732 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1733 int i; 1734 1735 for (i = 0; i < chip->num_pecs; i++) { 1736 PnvPhb4PecState *pec = &chip10->pecs[i]; 1737 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1738 uint32_t pec_nest_base; 1739 uint32_t pec_pci_base; 1740 1741 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1742 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1743 &error_fatal); 1744 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1745 &error_fatal); 1746 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1747 return; 1748 } 1749 1750 pec_nest_base = pecc->xscom_nest_base(pec); 1751 pec_pci_base = pecc->xscom_pci_base(pec); 1752 1753 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1754 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1755 } 1756 } 1757 1758 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1759 { 1760 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1761 PnvChip *chip = PNV_CHIP(dev); 1762 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1763 Error *local_err = NULL; 1764 1765 /* XSCOM bridge is first */ 1766 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1767 if (local_err) { 1768 error_propagate(errp, local_err); 1769 return; 1770 } 1771 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1772 1773 pcc->parent_realize(dev, &local_err); 1774 if (local_err) { 1775 error_propagate(errp, local_err); 1776 return; 1777 } 1778 1779 pnv_chip_power10_quad_realize(chip10, &local_err); 1780 if (local_err) { 1781 error_propagate(errp, local_err); 1782 return; 1783 } 1784 1785 /* XIVE2 interrupt controller (POWER10) */ 1786 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1787 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1788 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1789 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1790 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1791 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1792 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1793 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1794 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1795 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1796 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1797 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1798 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1799 &error_abort); 1800 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1801 return; 1802 } 1803 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1804 &chip10->xive.xscom_regs); 1805 1806 /* Processor Service Interface (PSI) Host Bridge */ 1807 object_property_set_int(OBJECT(&chip10->psi), "bar", 1808 PNV10_PSIHB_BASE(chip), &error_fatal); 1809 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1810 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1811 &error_fatal); 1812 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1813 return; 1814 } 1815 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1816 &PNV_PSI(&chip10->psi)->xscom_regs); 1817 1818 /* LPC */ 1819 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1820 return; 1821 } 1822 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1823 &chip10->lpc.xscom_regs); 1824 1825 chip->fw_mr = &chip10->lpc.isa_fw; 1826 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1827 (uint64_t) PNV10_LPCM_BASE(chip)); 1828 1829 /* Create the simplified OCC model */ 1830 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1831 return; 1832 } 1833 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1834 &chip10->occ.xscom_regs); 1835 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1836 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1837 1838 /* OCC SRAM model */ 1839 memory_region_add_subregion(get_system_memory(), 1840 PNV10_OCC_SENSOR_BASE(chip), 1841 &chip10->occ.sram_regs); 1842 1843 /* SBE */ 1844 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1845 return; 1846 } 1847 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1848 &chip10->sbe.xscom_ctrl_regs); 1849 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 1850 &chip10->sbe.xscom_mbox_regs); 1851 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 1852 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 1853 1854 /* HOMER */ 1855 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1856 &error_abort); 1857 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1858 return; 1859 } 1860 /* Homer Xscom region */ 1861 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1862 &chip10->homer.pba_regs); 1863 1864 /* Homer mmio region */ 1865 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1866 &chip10->homer.regs); 1867 1868 /* PHBs */ 1869 pnv_chip_power10_phb_realize(chip, &local_err); 1870 if (local_err) { 1871 error_propagate(errp, local_err); 1872 return; 1873 } 1874 } 1875 1876 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1877 { 1878 addr &= (PNV10_XSCOM_SIZE - 1); 1879 return addr >> 3; 1880 } 1881 1882 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1883 { 1884 DeviceClass *dc = DEVICE_CLASS(klass); 1885 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1886 1887 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1888 k->cores_mask = POWER10_CORE_MASK; 1889 k->core_pir = pnv_chip_core_pir_p10; 1890 k->intc_create = pnv_chip_power10_intc_create; 1891 k->intc_reset = pnv_chip_power10_intc_reset; 1892 k->intc_destroy = pnv_chip_power10_intc_destroy; 1893 k->intc_print_info = pnv_chip_power10_intc_print_info; 1894 k->isa_create = pnv_chip_power10_isa_create; 1895 k->dt_populate = pnv_chip_power10_dt_populate; 1896 k->pic_print_info = pnv_chip_power10_pic_print_info; 1897 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1898 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1899 dc->desc = "PowerNV Chip POWER10"; 1900 k->num_pecs = PNV10_CHIP_MAX_PEC; 1901 1902 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1903 &k->parent_realize); 1904 } 1905 1906 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1907 { 1908 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1909 int cores_max; 1910 1911 /* 1912 * No custom mask for this chip, let's use the default one from * 1913 * the chip class 1914 */ 1915 if (!chip->cores_mask) { 1916 chip->cores_mask = pcc->cores_mask; 1917 } 1918 1919 /* filter alien core ids ! some are reserved */ 1920 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1921 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1922 chip->cores_mask); 1923 return; 1924 } 1925 chip->cores_mask &= pcc->cores_mask; 1926 1927 /* now that we have a sane layout, let check the number of cores */ 1928 cores_max = ctpop64(chip->cores_mask); 1929 if (chip->nr_cores > cores_max) { 1930 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1931 cores_max); 1932 return; 1933 } 1934 } 1935 1936 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1937 { 1938 Error *error = NULL; 1939 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1940 const char *typename = pnv_chip_core_typename(chip); 1941 int i, core_hwid; 1942 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1943 1944 if (!object_class_by_name(typename)) { 1945 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1946 return; 1947 } 1948 1949 /* Cores */ 1950 pnv_chip_core_sanitize(chip, &error); 1951 if (error) { 1952 error_propagate(errp, error); 1953 return; 1954 } 1955 1956 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1957 1958 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1959 && (i < chip->nr_cores); core_hwid++) { 1960 char core_name[32]; 1961 PnvCore *pnv_core; 1962 uint64_t xscom_core_base; 1963 1964 if (!(chip->cores_mask & (1ull << core_hwid))) { 1965 continue; 1966 } 1967 1968 pnv_core = PNV_CORE(object_new(typename)); 1969 1970 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1971 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1972 chip->cores[i] = pnv_core; 1973 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1974 chip->nr_threads, &error_fatal); 1975 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1976 core_hwid, &error_fatal); 1977 object_property_set_int(OBJECT(pnv_core), "pir", 1978 pcc->core_pir(chip, core_hwid), &error_fatal); 1979 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1980 &error_fatal); 1981 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1982 &error_abort); 1983 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1984 1985 /* Each core has an XSCOM MMIO region */ 1986 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1987 1988 pnv_xscom_add_subregion(chip, xscom_core_base, 1989 &pnv_core->xscom_regs); 1990 i++; 1991 } 1992 } 1993 1994 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1995 { 1996 PnvChip *chip = PNV_CHIP(dev); 1997 Error *error = NULL; 1998 1999 /* Cores */ 2000 pnv_chip_core_realize(chip, &error); 2001 if (error) { 2002 error_propagate(errp, error); 2003 return; 2004 } 2005 } 2006 2007 static Property pnv_chip_properties[] = { 2008 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2009 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2010 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2011 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2012 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2013 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2014 DEFINE_PROP_END_OF_LIST(), 2015 }; 2016 2017 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2018 { 2019 DeviceClass *dc = DEVICE_CLASS(klass); 2020 2021 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2022 dc->realize = pnv_chip_realize; 2023 device_class_set_props(dc, pnv_chip_properties); 2024 dc->desc = "PowerNV Chip"; 2025 } 2026 2027 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2028 { 2029 int i, j; 2030 2031 for (i = 0; i < chip->nr_cores; i++) { 2032 PnvCore *pc = chip->cores[i]; 2033 CPUCore *cc = CPU_CORE(pc); 2034 2035 for (j = 0; j < cc->nr_threads; j++) { 2036 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2037 return pc->threads[j]; 2038 } 2039 } 2040 } 2041 return NULL; 2042 } 2043 2044 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2045 { 2046 PnvMachineState *pnv = PNV_MACHINE(xi); 2047 int i, j; 2048 2049 for (i = 0; i < pnv->num_chips; i++) { 2050 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2051 2052 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2053 return &chip8->psi.ics; 2054 } 2055 2056 for (j = 0; j < chip8->num_phbs; j++) { 2057 PnvPHB *phb = chip8->phbs[j]; 2058 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2059 2060 if (ics_valid_irq(&phb3->lsis, irq)) { 2061 return &phb3->lsis; 2062 } 2063 2064 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2065 return ICS(&phb3->msis); 2066 } 2067 } 2068 } 2069 return NULL; 2070 } 2071 2072 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2073 { 2074 int i; 2075 2076 for (i = 0; i < pnv->num_chips; i++) { 2077 PnvChip *chip = pnv->chips[i]; 2078 if (chip->chip_id == chip_id) { 2079 return chip; 2080 } 2081 } 2082 return NULL; 2083 } 2084 2085 static void pnv_ics_resend(XICSFabric *xi) 2086 { 2087 PnvMachineState *pnv = PNV_MACHINE(xi); 2088 int i, j; 2089 2090 for (i = 0; i < pnv->num_chips; i++) { 2091 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2092 2093 ics_resend(&chip8->psi.ics); 2094 2095 for (j = 0; j < chip8->num_phbs; j++) { 2096 PnvPHB *phb = chip8->phbs[j]; 2097 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2098 2099 ics_resend(&phb3->lsis); 2100 ics_resend(ICS(&phb3->msis)); 2101 } 2102 } 2103 } 2104 2105 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2106 { 2107 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2108 2109 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2110 } 2111 2112 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2113 Monitor *mon) 2114 { 2115 PnvMachineState *pnv = PNV_MACHINE(obj); 2116 int i; 2117 CPUState *cs; 2118 2119 CPU_FOREACH(cs) { 2120 PowerPCCPU *cpu = POWERPC_CPU(cs); 2121 2122 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2123 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2124 mon); 2125 } 2126 2127 for (i = 0; i < pnv->num_chips; i++) { 2128 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2129 } 2130 } 2131 2132 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2133 uint8_t nvt_blk, uint32_t nvt_idx, 2134 bool cam_ignore, uint8_t priority, 2135 uint32_t logic_serv, 2136 XiveTCTXMatch *match) 2137 { 2138 PnvMachineState *pnv = PNV_MACHINE(xfb); 2139 int total_count = 0; 2140 int i; 2141 2142 for (i = 0; i < pnv->num_chips; i++) { 2143 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2144 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2145 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2146 int count; 2147 2148 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2149 priority, logic_serv, match); 2150 2151 if (count < 0) { 2152 return count; 2153 } 2154 2155 total_count += count; 2156 } 2157 2158 return total_count; 2159 } 2160 2161 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2162 uint8_t nvt_blk, uint32_t nvt_idx, 2163 bool cam_ignore, uint8_t priority, 2164 uint32_t logic_serv, 2165 XiveTCTXMatch *match) 2166 { 2167 PnvMachineState *pnv = PNV_MACHINE(xfb); 2168 int total_count = 0; 2169 int i; 2170 2171 for (i = 0; i < pnv->num_chips; i++) { 2172 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2173 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2174 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2175 int count; 2176 2177 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2178 priority, logic_serv, match); 2179 2180 if (count < 0) { 2181 return count; 2182 } 2183 2184 total_count += count; 2185 } 2186 2187 return total_count; 2188 } 2189 2190 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2191 { 2192 MachineClass *mc = MACHINE_CLASS(oc); 2193 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2194 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2195 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2196 2197 static GlobalProperty phb_compat[] = { 2198 { TYPE_PNV_PHB, "version", "3" }, 2199 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2200 }; 2201 2202 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2203 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2204 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2205 2206 xic->icp_get = pnv_icp_get; 2207 xic->ics_get = pnv_ics_get; 2208 xic->ics_resend = pnv_ics_resend; 2209 2210 pmc->compat = compat; 2211 pmc->compat_size = sizeof(compat); 2212 2213 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2214 } 2215 2216 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2217 { 2218 MachineClass *mc = MACHINE_CLASS(oc); 2219 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2220 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2221 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2222 2223 static GlobalProperty phb_compat[] = { 2224 { TYPE_PNV_PHB, "version", "4" }, 2225 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2226 }; 2227 2228 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2229 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 2230 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2231 2232 xfc->match_nvt = pnv_match_nvt; 2233 2234 mc->alias = "powernv"; 2235 2236 pmc->compat = compat; 2237 pmc->compat_size = sizeof(compat); 2238 pmc->dt_power_mgt = pnv_dt_power_mgt; 2239 2240 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2241 } 2242 2243 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2244 { 2245 MachineClass *mc = MACHINE_CLASS(oc); 2246 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2247 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2248 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2249 2250 static GlobalProperty phb_compat[] = { 2251 { TYPE_PNV_PHB, "version", "5" }, 2252 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2253 }; 2254 2255 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2256 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2257 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2258 2259 pmc->compat = compat; 2260 pmc->compat_size = sizeof(compat); 2261 pmc->dt_power_mgt = pnv_dt_power_mgt; 2262 2263 xfc->match_nvt = pnv10_xive_match_nvt; 2264 2265 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2266 } 2267 2268 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2269 { 2270 PnvMachineState *pnv = PNV_MACHINE(obj); 2271 2272 return !!pnv->fw_load_addr; 2273 } 2274 2275 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2276 { 2277 PnvMachineState *pnv = PNV_MACHINE(obj); 2278 2279 if (value) { 2280 pnv->fw_load_addr = 0x8000000; 2281 } 2282 } 2283 2284 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2285 { 2286 PowerPCCPU *cpu = POWERPC_CPU(cs); 2287 CPUPPCState *env = &cpu->env; 2288 2289 cpu_synchronize_state(cs); 2290 ppc_cpu_do_system_reset(cs); 2291 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2292 /* 2293 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2294 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2295 * (PPC_BIT(43)). 2296 */ 2297 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2298 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2299 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2300 } 2301 } else { 2302 /* 2303 * For non-powersave system resets, SRR1[42:45] are defined to be 2304 * implementation-dependent. The POWER9 User Manual specifies that 2305 * an external (SCOM driven, which may come from a BMC nmi command or 2306 * another CPU requesting a NMI IPI) system reset exception should be 2307 * 0b0010 (PPC_BIT(44)). 2308 */ 2309 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2310 } 2311 } 2312 2313 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2314 { 2315 CPUState *cs; 2316 2317 CPU_FOREACH(cs) { 2318 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2319 } 2320 } 2321 2322 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2323 { 2324 MachineClass *mc = MACHINE_CLASS(oc); 2325 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2326 NMIClass *nc = NMI_CLASS(oc); 2327 2328 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2329 mc->init = pnv_init; 2330 mc->reset = pnv_reset; 2331 mc->max_cpus = MAX_CPUS; 2332 /* Pnv provides a AHCI device for storage */ 2333 mc->block_default_type = IF_IDE; 2334 mc->no_parallel = 1; 2335 mc->default_boot_order = NULL; 2336 /* 2337 * RAM defaults to less than 2048 for 32-bit hosts, and large 2338 * enough to fit the maximum initrd size at it's load address 2339 */ 2340 mc->default_ram_size = 1 * GiB; 2341 mc->default_ram_id = "pnv.ram"; 2342 ispc->print_info = pnv_pic_print_info; 2343 nc->nmi_monitor_handler = pnv_nmi; 2344 2345 object_class_property_add_bool(oc, "hb-mode", 2346 pnv_machine_get_hb, pnv_machine_set_hb); 2347 object_class_property_set_description(oc, "hb-mode", 2348 "Use a hostboot like boot loader"); 2349 } 2350 2351 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2352 { \ 2353 .name = type, \ 2354 .class_init = class_initfn, \ 2355 .parent = TYPE_PNV8_CHIP, \ 2356 } 2357 2358 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2359 { \ 2360 .name = type, \ 2361 .class_init = class_initfn, \ 2362 .parent = TYPE_PNV9_CHIP, \ 2363 } 2364 2365 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2366 { \ 2367 .name = type, \ 2368 .class_init = class_initfn, \ 2369 .parent = TYPE_PNV10_CHIP, \ 2370 } 2371 2372 static const TypeInfo types[] = { 2373 { 2374 .name = MACHINE_TYPE_NAME("powernv10"), 2375 .parent = TYPE_PNV_MACHINE, 2376 .class_init = pnv_machine_power10_class_init, 2377 .interfaces = (InterfaceInfo[]) { 2378 { TYPE_XIVE_FABRIC }, 2379 { }, 2380 }, 2381 }, 2382 { 2383 .name = MACHINE_TYPE_NAME("powernv9"), 2384 .parent = TYPE_PNV_MACHINE, 2385 .class_init = pnv_machine_power9_class_init, 2386 .interfaces = (InterfaceInfo[]) { 2387 { TYPE_XIVE_FABRIC }, 2388 { }, 2389 }, 2390 }, 2391 { 2392 .name = MACHINE_TYPE_NAME("powernv8"), 2393 .parent = TYPE_PNV_MACHINE, 2394 .class_init = pnv_machine_power8_class_init, 2395 .interfaces = (InterfaceInfo[]) { 2396 { TYPE_XICS_FABRIC }, 2397 { }, 2398 }, 2399 }, 2400 { 2401 .name = TYPE_PNV_MACHINE, 2402 .parent = TYPE_MACHINE, 2403 .abstract = true, 2404 .instance_size = sizeof(PnvMachineState), 2405 .class_init = pnv_machine_class_init, 2406 .class_size = sizeof(PnvMachineClass), 2407 .interfaces = (InterfaceInfo[]) { 2408 { TYPE_INTERRUPT_STATS_PROVIDER }, 2409 { TYPE_NMI }, 2410 { }, 2411 }, 2412 }, 2413 { 2414 .name = TYPE_PNV_CHIP, 2415 .parent = TYPE_SYS_BUS_DEVICE, 2416 .class_init = pnv_chip_class_init, 2417 .instance_size = sizeof(PnvChip), 2418 .class_size = sizeof(PnvChipClass), 2419 .abstract = true, 2420 }, 2421 2422 /* 2423 * P10 chip and variants 2424 */ 2425 { 2426 .name = TYPE_PNV10_CHIP, 2427 .parent = TYPE_PNV_CHIP, 2428 .instance_init = pnv_chip_power10_instance_init, 2429 .instance_size = sizeof(Pnv10Chip), 2430 }, 2431 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2432 2433 /* 2434 * P9 chip and variants 2435 */ 2436 { 2437 .name = TYPE_PNV9_CHIP, 2438 .parent = TYPE_PNV_CHIP, 2439 .instance_init = pnv_chip_power9_instance_init, 2440 .instance_size = sizeof(Pnv9Chip), 2441 }, 2442 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2443 2444 /* 2445 * P8 chip and variants 2446 */ 2447 { 2448 .name = TYPE_PNV8_CHIP, 2449 .parent = TYPE_PNV_CHIP, 2450 .instance_init = pnv_chip_power8_instance_init, 2451 .instance_size = sizeof(Pnv8Chip), 2452 }, 2453 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2454 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2455 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2456 pnv_chip_power8nvl_class_init), 2457 }; 2458 2459 DEFINE_TYPES(types) 2460