xref: /openbmc/qemu/hw/ppc/pnv.c (revision 05caa062)
1 /*
2  * QEMU PowerPC PowerNV machine model
3  *
4  * Copyright (c) 2016, IBM Corporation.
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/datadir.h"
22 #include "qemu/units.h"
23 #include "qemu/cutils.h"
24 #include "qapi/error.h"
25 #include "sysemu/qtest.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/numa.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/cpus.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/hw_accel.h"
33 #include "target/ppc/cpu.h"
34 #include "hw/ppc/fdt.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/ppc/pnv.h"
37 #include "hw/ppc/pnv_core.h"
38 #include "hw/loader.h"
39 #include "hw/nmi.h"
40 #include "qapi/visitor.h"
41 #include "hw/intc/intc.h"
42 #include "hw/ipmi/ipmi.h"
43 #include "target/ppc/mmu-hash64.h"
44 #include "hw/pci/msi.h"
45 #include "hw/pci-host/pnv_phb.h"
46 #include "hw/pci-host/pnv_phb3.h"
47 #include "hw/pci-host/pnv_phb4.h"
48 
49 #include "hw/ppc/xics.h"
50 #include "hw/qdev-properties.h"
51 #include "hw/ppc/pnv_chip.h"
52 #include "hw/ppc/pnv_xscom.h"
53 #include "hw/ppc/pnv_pnor.h"
54 
55 #include "hw/isa/isa.h"
56 #include "hw/char/serial.h"
57 #include "hw/rtc/mc146818rtc.h"
58 
59 #include <libfdt.h>
60 
61 #define FDT_MAX_SIZE            (1 * MiB)
62 
63 #define FW_FILE_NAME            "skiboot.lid"
64 #define FW_LOAD_ADDR            0x0
65 #define FW_MAX_SIZE             (16 * MiB)
66 
67 #define KERNEL_LOAD_ADDR        0x20000000
68 #define KERNEL_MAX_SIZE         (128 * MiB)
69 #define INITRD_LOAD_ADDR        0x28000000
70 #define INITRD_MAX_SIZE         (128 * MiB)
71 
72 static const char *pnv_chip_core_typename(const PnvChip *o)
73 {
74     const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
75     int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
76     char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
77     const char *core_type = object_class_get_name(object_class_by_name(s));
78     g_free(s);
79     return core_type;
80 }
81 
82 /*
83  * On Power Systems E880 (POWER8), the max cpus (threads) should be :
84  *     4 * 4 sockets * 12 cores * 8 threads = 1536
85  * Let's make it 2^11
86  */
87 #define MAX_CPUS                2048
88 
89 /*
90  * Memory nodes are created by hostboot, one for each range of memory
91  * that has a different "affinity". In practice, it means one range
92  * per chip.
93  */
94 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
95 {
96     char *mem_name;
97     uint64_t mem_reg_property[2];
98     int off;
99 
100     mem_reg_property[0] = cpu_to_be64(start);
101     mem_reg_property[1] = cpu_to_be64(size);
102 
103     mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
104     off = fdt_add_subnode(fdt, 0, mem_name);
105     g_free(mem_name);
106 
107     _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
108     _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
109                        sizeof(mem_reg_property))));
110     _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
111 }
112 
113 static int get_cpus_node(void *fdt)
114 {
115     int cpus_offset = fdt_path_offset(fdt, "/cpus");
116 
117     if (cpus_offset < 0) {
118         cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
119         if (cpus_offset) {
120             _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
121             _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
122         }
123     }
124     _FDT(cpus_offset);
125     return cpus_offset;
126 }
127 
128 /*
129  * The PowerNV cores (and threads) need to use real HW ids and not an
130  * incremental index like it has been done on other platforms. This HW
131  * id is stored in the CPU PIR, it is used to create cpu nodes in the
132  * device tree, used in XSCOM to address cores and in interrupt
133  * servers.
134  */
135 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
136 {
137     PowerPCCPU *cpu = pc->threads[0];
138     CPUState *cs = CPU(cpu);
139     DeviceClass *dc = DEVICE_GET_CLASS(cs);
140     int smt_threads = CPU_CORE(pc)->nr_threads;
141     CPUPPCState *env = &cpu->env;
142     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
143     PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip);
144     uint32_t *servers_prop;
145     int i;
146     uint32_t pir, tir;
147     uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
148                        0xffffffff, 0xffffffff};
149     uint32_t tbfreq = PNV_TIMEBASE_FREQ;
150     uint32_t cpufreq = 1000000000;
151     uint32_t page_sizes_prop[64];
152     size_t page_sizes_prop_size;
153     int offset;
154     char *nodename;
155     int cpus_offset = get_cpus_node(fdt);
156 
157     pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir);
158 
159     /* Only one DT node per (big) core */
160     g_assert(tir == 0);
161 
162     nodename = g_strdup_printf("%s@%x", dc->fw_name, pir);
163     offset = fdt_add_subnode(fdt, cpus_offset, nodename);
164     _FDT(offset);
165     g_free(nodename);
166 
167     _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
168 
169     _FDT((fdt_setprop_cell(fdt, offset, "reg", pir)));
170     _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir)));
171     _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
172 
173     _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
174     _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
175                             env->dcache_line_size)));
176     _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
177                             env->dcache_line_size)));
178     _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
179                             env->icache_line_size)));
180     _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
181                             env->icache_line_size)));
182 
183     if (pcc->l1_dcache_size) {
184         _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
185                                pcc->l1_dcache_size)));
186     } else {
187         warn_report("Unknown L1 dcache size for cpu");
188     }
189     if (pcc->l1_icache_size) {
190         _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
191                                pcc->l1_icache_size)));
192     } else {
193         warn_report("Unknown L1 icache size for cpu");
194     }
195 
196     _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
197     _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
198     _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
199                            cpu->hash64_opts->slb_size)));
200     _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
201     _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
202 
203     if (ppc_has_spr(cpu, SPR_PURR)) {
204         _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
205     }
206 
207     if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
208         _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
209                            segs, sizeof(segs))));
210     }
211 
212     /*
213      * Advertise VMX/VSX (vector extensions) if available
214      *   0 / no property == no vector extensions
215      *   1               == VMX / Altivec available
216      *   2               == VSX available
217      */
218     if (env->insns_flags & PPC_ALTIVEC) {
219         uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
220 
221         _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
222     }
223 
224     /*
225      * Advertise DFP (Decimal Floating Point) if available
226      *   0 / no property == no DFP
227      *   1               == DFP available
228      */
229     if (env->insns_flags2 & PPC2_DFP) {
230         _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
231     }
232 
233     page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
234                                                       sizeof(page_sizes_prop));
235     if (page_sizes_prop_size) {
236         _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
237                            page_sizes_prop, page_sizes_prop_size)));
238     }
239 
240     /* Build interrupt servers properties */
241     if (pc->big_core) {
242         servers_prop = g_new(uint32_t, smt_threads * 2);
243         for (i = 0; i < smt_threads; i++) {
244             pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL);
245             servers_prop[i * 2] = cpu_to_be32(pir);
246 
247             pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL);
248             servers_prop[i * 2 + 1] = cpu_to_be32(pir);
249         }
250         _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
251                           servers_prop, sizeof(*servers_prop) * smt_threads
252                                         * 2)));
253     } else {
254         servers_prop = g_new(uint32_t, smt_threads);
255         for (i = 0; i < smt_threads; i++) {
256             pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL);
257             servers_prop[i] = cpu_to_be32(pir);
258         }
259         _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
260                           servers_prop, sizeof(*servers_prop) * smt_threads)));
261     }
262     g_free(servers_prop);
263 
264     return offset;
265 }
266 
267 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid,
268                        uint32_t nr_threads)
269 {
270     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
271     uint32_t pir;
272     uint64_t addr;
273     char *name;
274     const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
275     uint32_t irange[2], i, rsize;
276     uint64_t *reg;
277     int offset;
278 
279     pcc->get_pir_tir(chip, hwid, 0, &pir, NULL);
280     addr = PNV_ICP_BASE(chip) | (pir << 12);
281 
282     irange[0] = cpu_to_be32(pir);
283     irange[1] = cpu_to_be32(nr_threads);
284 
285     rsize = sizeof(uint64_t) * 2 * nr_threads;
286     reg = g_malloc(rsize);
287     for (i = 0; i < nr_threads; i++) {
288         /* We know P8 PIR is linear with thread id */
289         reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
290         reg[i * 2 + 1] = cpu_to_be64(0x1000);
291     }
292 
293     name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
294     offset = fdt_add_subnode(fdt, 0, name);
295     _FDT(offset);
296     g_free(name);
297 
298     _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
299     _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
300     _FDT((fdt_setprop_string(fdt, offset, "device_type",
301                               "PowerPC-External-Interrupt-Presentation")));
302     _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
303     _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
304                        irange, sizeof(irange))));
305     _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
306     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
307     g_free(reg);
308 }
309 
310 /*
311  * Adds a PnvPHB to the chip on P8.
312  * Implemented here, like for defaults PHBs
313  */
314 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb)
315 {
316     Pnv8Chip *chip8 = PNV8_CHIP(chip);
317 
318     phb->chip = chip;
319 
320     chip8->phbs[chip8->num_phbs] = phb;
321     chip8->num_phbs++;
322     return chip;
323 }
324 
325 /*
326  * Same as spapr pa_features_207 except pnv always enables CI largepages bit.
327  * HTM is always enabled because TCG does implement HTM, it's just a
328  * degenerate implementation.
329  */
330 static const uint8_t pa_features_207[] = { 24, 0,
331                  0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0,
332                  0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
333                  0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
334                  0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
335 
336 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
337 {
338     static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
339     int i;
340 
341     pnv_dt_xscom(chip, fdt, 0,
342                  cpu_to_be64(PNV_XSCOM_BASE(chip)),
343                  cpu_to_be64(PNV_XSCOM_SIZE),
344                  compat, sizeof(compat));
345 
346     for (i = 0; i < chip->nr_cores; i++) {
347         PnvCore *pnv_core = chip->cores[i];
348         int offset;
349 
350         offset = pnv_dt_core(chip, pnv_core, fdt);
351 
352         _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
353                            pa_features_207, sizeof(pa_features_207))));
354 
355         /* Interrupt Control Presenters (ICP). One per core. */
356         pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads);
357     }
358 
359     if (chip->ram_size) {
360         pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
361     }
362 }
363 
364 /*
365  * Same as spapr pa_features_300 except pnv always enables CI largepages bit.
366  */
367 static const uint8_t pa_features_300[] = { 66, 0,
368     /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
369     /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
370     0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
371     /* 6: DS207 */
372     0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
373     /* 16: Vector */
374     0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
375     /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
376     0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
377     /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
378     0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
379     /* 32: LE atomic, 34: EBB + ext EBB */
380     0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
381     /* 40: Radix MMU */
382     0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
383     /* 42: PM, 44: PC RA, 46: SC vec'd */
384     0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
385     /* 48: SIMD, 50: QP BFP, 52: String */
386     0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
387     /* 54: DecFP, 56: DecI, 58: SHA */
388     0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
389     /* 60: NM atomic, 62: RNG */
390     0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
391 };
392 
393 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
394 {
395     static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
396     int i;
397 
398     pnv_dt_xscom(chip, fdt, 0,
399                  cpu_to_be64(PNV9_XSCOM_BASE(chip)),
400                  cpu_to_be64(PNV9_XSCOM_SIZE),
401                  compat, sizeof(compat));
402 
403     for (i = 0; i < chip->nr_cores; i++) {
404         PnvCore *pnv_core = chip->cores[i];
405         int offset;
406 
407         offset = pnv_dt_core(chip, pnv_core, fdt);
408 
409         _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
410                            pa_features_300, sizeof(pa_features_300))));
411 
412         if (pnv_core->big_core) {
413             i++; /* Big-core groups two QEMU cores */
414         }
415     }
416 
417     if (chip->ram_size) {
418         pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
419     }
420 
421     pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
422 }
423 
424 /*
425  * Same as spapr pa_features_31 except pnv always enables CI largepages bit,
426  * always disables copy/paste.
427  */
428 static const uint8_t pa_features_31[] = { 74, 0,
429     /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
430     /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
431     0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
432     /* 6: DS207 */
433     0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
434     /* 16: Vector */
435     0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
436     /* 18: Vec. Scalar, 20: Vec. XOR */
437     0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
438     /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
439     0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
440     /* 32: LE atomic, 34: EBB + ext EBB */
441     0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
442     /* 40: Radix MMU */
443     0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
444     /* 42: PM, 44: PC RA, 46: SC vec'd */
445     0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
446     /* 48: SIMD, 50: QP BFP, 52: String */
447     0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
448     /* 54: DecFP, 56: DecI, 58: SHA */
449     0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
450     /* 60: NM atomic, 62: RNG */
451     0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
452     /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
453     0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
454     /* 72: [P]HASHST/[P]HASHCHK */
455     0x80, 0x00,                         /* 72 - 73 */
456 };
457 
458 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
459 {
460     static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
461     int i;
462 
463     pnv_dt_xscom(chip, fdt, 0,
464                  cpu_to_be64(PNV10_XSCOM_BASE(chip)),
465                  cpu_to_be64(PNV10_XSCOM_SIZE),
466                  compat, sizeof(compat));
467 
468     for (i = 0; i < chip->nr_cores; i++) {
469         PnvCore *pnv_core = chip->cores[i];
470         int offset;
471 
472         offset = pnv_dt_core(chip, pnv_core, fdt);
473 
474         _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
475                            pa_features_31, sizeof(pa_features_31))));
476 
477         if (pnv_core->big_core) {
478             i++; /* Big-core groups two QEMU cores */
479         }
480     }
481 
482     if (chip->ram_size) {
483         pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
484     }
485 
486     pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
487 }
488 
489 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
490 {
491     uint32_t io_base = d->ioport_id;
492     uint32_t io_regs[] = {
493         cpu_to_be32(1),
494         cpu_to_be32(io_base),
495         cpu_to_be32(2)
496     };
497     char *name;
498     int node;
499 
500     name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
501     node = fdt_add_subnode(fdt, lpc_off, name);
502     _FDT(node);
503     g_free(name);
504 
505     _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
506     _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
507 }
508 
509 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
510 {
511     const char compatible[] = "ns16550\0pnpPNP,501";
512     uint32_t io_base = d->ioport_id;
513     uint32_t io_regs[] = {
514         cpu_to_be32(1),
515         cpu_to_be32(io_base),
516         cpu_to_be32(8)
517     };
518     uint32_t irq;
519     char *name;
520     int node;
521 
522     irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal);
523 
524     name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
525     node = fdt_add_subnode(fdt, lpc_off, name);
526     _FDT(node);
527     g_free(name);
528 
529     _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
530     _FDT((fdt_setprop(fdt, node, "compatible", compatible,
531                       sizeof(compatible))));
532 
533     _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
534     _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
535     _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
536     _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
537                            fdt_get_phandle(fdt, lpc_off))));
538 
539     /* This is needed by Linux */
540     _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
541 }
542 
543 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
544 {
545     const char compatible[] = "bt\0ipmi-bt";
546     uint32_t io_base;
547     uint32_t io_regs[] = {
548         cpu_to_be32(1),
549         0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
550         cpu_to_be32(3)
551     };
552     uint32_t irq;
553     char *name;
554     int node;
555 
556     io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
557     io_regs[1] = cpu_to_be32(io_base);
558 
559     irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
560 
561     name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
562     node = fdt_add_subnode(fdt, lpc_off, name);
563     _FDT(node);
564     g_free(name);
565 
566     _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
567     _FDT((fdt_setprop(fdt, node, "compatible", compatible,
568                       sizeof(compatible))));
569 
570     /* Mark it as reserved to avoid Linux trying to claim it */
571     _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
572     _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
573     _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
574                            fdt_get_phandle(fdt, lpc_off))));
575 }
576 
577 typedef struct ForeachPopulateArgs {
578     void *fdt;
579     int offset;
580 } ForeachPopulateArgs;
581 
582 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
583 {
584     ForeachPopulateArgs *args = opaque;
585     ISADevice *d = ISA_DEVICE(dev);
586 
587     if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
588         pnv_dt_rtc(d, args->fdt, args->offset);
589     } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
590         pnv_dt_serial(d, args->fdt, args->offset);
591     } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
592         pnv_dt_ipmi_bt(d, args->fdt, args->offset);
593     } else {
594         error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
595                      d->ioport_id);
596     }
597 
598     return 0;
599 }
600 
601 /*
602  * The default LPC bus of a multichip system is on chip 0. It's
603  * recognized by the firmware (skiboot) using a "primary" property.
604  */
605 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
606 {
607     int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
608     ForeachPopulateArgs args = {
609         .fdt = fdt,
610         .offset = isa_offset,
611     };
612     uint32_t phandle;
613 
614     _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
615 
616     phandle = qemu_fdt_alloc_phandle(fdt);
617     assert(phandle > 0);
618     _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
619 
620     /*
621      * ISA devices are not necessarily parented to the ISA bus so we
622      * can not use object_child_foreach()
623      */
624     qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
625                        &args);
626 }
627 
628 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
629 {
630     int off;
631 
632     off = fdt_add_subnode(fdt, 0, "ibm,opal");
633     off = fdt_add_subnode(fdt, off, "power-mgt");
634 
635     _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
636 }
637 
638 static void *pnv_dt_create(MachineState *machine)
639 {
640     PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
641     PnvMachineState *pnv = PNV_MACHINE(machine);
642     void *fdt;
643     char *buf;
644     int off;
645     int i;
646 
647     fdt = g_malloc0(FDT_MAX_SIZE);
648     _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
649 
650     /* /qemu node */
651     _FDT((fdt_add_subnode(fdt, 0, "qemu")));
652 
653     /* Root node */
654     _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
655     _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
656     _FDT((fdt_setprop_string(fdt, 0, "model",
657                              "IBM PowerNV (emulated by qemu)")));
658     _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
659 
660     buf =  qemu_uuid_unparse_strdup(&qemu_uuid);
661     _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
662     if (qemu_uuid_set) {
663         _FDT((fdt_setprop_string(fdt, 0, "system-id", buf)));
664     }
665     g_free(buf);
666 
667     off = fdt_add_subnode(fdt, 0, "chosen");
668     if (machine->kernel_cmdline) {
669         _FDT((fdt_setprop_string(fdt, off, "bootargs",
670                                  machine->kernel_cmdline)));
671     }
672 
673     if (pnv->initrd_size) {
674         uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
675         uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
676 
677         _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
678                                &start_prop, sizeof(start_prop))));
679         _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
680                                &end_prop, sizeof(end_prop))));
681     }
682 
683     /* Populate device tree for each chip */
684     for (i = 0; i < pnv->num_chips; i++) {
685         PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
686     }
687 
688     /* Populate ISA devices on chip 0 */
689     pnv_dt_isa(pnv, fdt);
690 
691     if (pnv->bmc) {
692         pnv_dt_bmc_sensors(pnv->bmc, fdt);
693     }
694 
695     /* Create an extra node for power management on machines that support it */
696     if (pmc->dt_power_mgt) {
697         pmc->dt_power_mgt(pnv, fdt);
698     }
699 
700     return fdt;
701 }
702 
703 static void pnv_powerdown_notify(Notifier *n, void *opaque)
704 {
705     PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
706 
707     if (pnv->bmc) {
708         pnv_bmc_powerdown(pnv->bmc);
709     }
710 }
711 
712 static void pnv_reset(MachineState *machine, ShutdownCause reason)
713 {
714     PnvMachineState *pnv = PNV_MACHINE(machine);
715     IPMIBmc *bmc;
716     void *fdt;
717 
718     qemu_devices_reset(reason);
719 
720     /*
721      * The machine should provide by default an internal BMC simulator.
722      * If not, try to use the BMC device that was provided on the command
723      * line.
724      */
725     bmc = pnv_bmc_find(&error_fatal);
726     if (!pnv->bmc) {
727         if (!bmc) {
728             if (!qtest_enabled()) {
729                 warn_report("machine has no BMC device. Use '-device "
730                             "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
731                             "to define one");
732             }
733         } else {
734             pnv_bmc_set_pnor(bmc, pnv->pnor);
735             pnv->bmc = bmc;
736         }
737     }
738 
739     fdt = pnv_dt_create(machine);
740 
741     /* Pack resulting tree */
742     _FDT((fdt_pack(fdt)));
743 
744     qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
745     cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
746 
747     /*
748      * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free
749      * the existing machine->fdt to avoid leaking it during
750      * a reset.
751      */
752     g_free(machine->fdt);
753     machine->fdt = fdt;
754 }
755 
756 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
757 {
758     Pnv8Chip *chip8 = PNV8_CHIP(chip);
759     qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL);
760 
761     qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq);
762 
763     return pnv_lpc_isa_create(&chip8->lpc, true, errp);
764 }
765 
766 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
767 {
768     Pnv8Chip *chip8 = PNV8_CHIP(chip);
769     qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C);
770 
771     qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq);
772 
773     return pnv_lpc_isa_create(&chip8->lpc, false, errp);
774 }
775 
776 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
777 {
778     Pnv9Chip *chip9 = PNV9_CHIP(chip);
779     qemu_irq irq;
780 
781     irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC);
782     qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq);
783 
784     irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0);
785     qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq);
786     irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1);
787     qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq);
788     irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2);
789     qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq);
790     irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3);
791     qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq);
792 
793     return pnv_lpc_isa_create(&chip9->lpc, false, errp);
794 }
795 
796 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
797 {
798     Pnv10Chip *chip10 = PNV10_CHIP(chip);
799     qemu_irq irq;
800 
801     irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC);
802     qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq);
803 
804     irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0);
805     qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq);
806     irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1);
807     qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq);
808     irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2);
809     qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq);
810     irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3);
811     qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq);
812 
813     return pnv_lpc_isa_create(&chip10->lpc, false, errp);
814 }
815 
816 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
817 {
818     return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
819 }
820 
821 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf)
822 {
823     Pnv8Chip *chip8 = PNV8_CHIP(chip);
824     int i;
825 
826     ics_pic_print_info(&chip8->psi.ics, buf);
827 
828     for (i = 0; i < chip8->num_phbs; i++) {
829         PnvPHB *phb = chip8->phbs[i];
830         PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
831 
832         pnv_phb3_msi_pic_print_info(&phb3->msis, buf);
833         ics_pic_print_info(&phb3->lsis, buf);
834     }
835 }
836 
837 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
838 {
839     GString *buf = opaque;
840     PnvPHB *phb =  (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
841 
842     if (!phb) {
843         return 0;
844     }
845 
846     pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf);
847 
848     return 0;
849 }
850 
851 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf)
852 {
853     Pnv9Chip *chip9 = PNV9_CHIP(chip);
854 
855     pnv_xive_pic_print_info(&chip9->xive, buf);
856     pnv_psi_pic_print_info(&chip9->psi, buf);
857     object_child_foreach_recursive(OBJECT(chip),
858                          pnv_chip_power9_pic_print_info_child, buf);
859 }
860 
861 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
862                                                 uint32_t core_id)
863 {
864     return PNV_XSCOM_EX_BASE(core_id);
865 }
866 
867 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
868                                                 uint32_t core_id)
869 {
870     return PNV9_XSCOM_EC_BASE(core_id);
871 }
872 
873 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
874                                                  uint32_t core_id)
875 {
876     return PNV10_XSCOM_EC_BASE(core_id);
877 }
878 
879 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
880 {
881     PowerPCCPUClass *ppc_default =
882         POWERPC_CPU_CLASS(object_class_by_name(default_type));
883     PowerPCCPUClass *ppc =
884         POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
885 
886     return ppc_default->pvr_match(ppc_default, ppc->pvr, false);
887 }
888 
889 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
890 {
891     ISADevice *dev = isa_new("isa-ipmi-bt");
892 
893     object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
894     object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
895     isa_realize_and_unref(dev, bus, &error_fatal);
896 }
897 
898 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf)
899 {
900     Pnv10Chip *chip10 = PNV10_CHIP(chip);
901 
902     pnv_xive2_pic_print_info(&chip10->xive, buf);
903     pnv_psi_pic_print_info(&chip10->psi, buf);
904     object_child_foreach_recursive(OBJECT(chip),
905                          pnv_chip_power9_pic_print_info_child, buf);
906 }
907 
908 /* Always give the first 1GB to chip 0 else we won't boot */
909 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
910 {
911     MachineState *machine = MACHINE(pnv);
912     uint64_t ram_per_chip;
913 
914     assert(machine->ram_size >= 1 * GiB);
915 
916     ram_per_chip = machine->ram_size / pnv->num_chips;
917     if (ram_per_chip >= 1 * GiB) {
918         return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
919     }
920 
921     assert(pnv->num_chips > 1);
922 
923     ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);
924     return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
925 }
926 
927 static void pnv_init(MachineState *machine)
928 {
929     const char *bios_name = machine->firmware ?: FW_FILE_NAME;
930     PnvMachineState *pnv = PNV_MACHINE(machine);
931     MachineClass *mc = MACHINE_GET_CLASS(machine);
932     PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
933     int max_smt_threads = pmc->max_smt_threads;
934     char *fw_filename;
935     long fw_size;
936     uint64_t chip_ram_start = 0;
937     int i;
938     char *chip_typename;
939     DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
940     DeviceState *dev;
941 
942     if (kvm_enabled()) {
943         error_report("machine %s does not support the KVM accelerator",
944                      mc->name);
945         exit(EXIT_FAILURE);
946     }
947 
948     /* allocate RAM */
949     if (machine->ram_size < mc->default_ram_size) {
950         char *sz = size_to_str(mc->default_ram_size);
951         error_report("Invalid RAM size, should be bigger than %s", sz);
952         g_free(sz);
953         exit(EXIT_FAILURE);
954     }
955     memory_region_add_subregion(get_system_memory(), 0, machine->ram);
956 
957     /*
958      * Create our simple PNOR device
959      */
960     dev = qdev_new(TYPE_PNV_PNOR);
961     if (pnor) {
962         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
963     }
964     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
965     pnv->pnor = PNV_PNOR(dev);
966 
967     /* load skiboot firmware  */
968     fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
969     if (!fw_filename) {
970         error_report("Could not find OPAL firmware '%s'", bios_name);
971         exit(1);
972     }
973 
974     fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
975     if (fw_size < 0) {
976         error_report("Could not load OPAL firmware '%s'", fw_filename);
977         exit(1);
978     }
979     g_free(fw_filename);
980 
981     /* load kernel */
982     if (machine->kernel_filename) {
983         long kernel_size;
984 
985         kernel_size = load_image_targphys(machine->kernel_filename,
986                                           KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
987         if (kernel_size < 0) {
988             error_report("Could not load kernel '%s'",
989                          machine->kernel_filename);
990             exit(1);
991         }
992     }
993 
994     /* load initrd */
995     if (machine->initrd_filename) {
996         pnv->initrd_base = INITRD_LOAD_ADDR;
997         pnv->initrd_size = load_image_targphys(machine->initrd_filename,
998                                   pnv->initrd_base, INITRD_MAX_SIZE);
999         if (pnv->initrd_size < 0) {
1000             error_report("Could not load initial ram disk '%s'",
1001                          machine->initrd_filename);
1002             exit(1);
1003         }
1004     }
1005 
1006     /* MSIs are supported on this platform */
1007     msi_nonbroken = true;
1008 
1009     /*
1010      * Check compatibility of the specified CPU with the machine
1011      * default.
1012      */
1013     if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
1014         error_report("invalid CPU model '%s' for %s machine",
1015                      machine->cpu_type, mc->name);
1016         exit(1);
1017     }
1018 
1019     /* Create the processor chips */
1020     i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
1021     chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
1022                                     i, machine->cpu_type);
1023     if (!object_class_by_name(chip_typename)) {
1024         error_report("invalid chip model '%.*s' for %s machine",
1025                      i, machine->cpu_type, mc->name);
1026         exit(1);
1027     }
1028 
1029     /* Set lpar-per-core mode if lpar-per-thread is not supported */
1030     if (!pmc->has_lpar_per_thread) {
1031         pnv->lpar_per_core = true;
1032     }
1033 
1034     pnv->num_chips =
1035         machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
1036 
1037     if (pnv->big_core) {
1038         if (machine->smp.threads % 2 == 1) {
1039             error_report("Cannot support %d threads with big-core option "
1040                          "because it must be an even number",
1041                          machine->smp.threads);
1042             exit(1);
1043         }
1044         max_smt_threads *= 2;
1045     }
1046 
1047     if (machine->smp.threads > max_smt_threads) {
1048         error_report("Cannot support more than %d threads/core "
1049                      "on %s machine", max_smt_threads, mc->desc);
1050         if (pmc->max_smt_threads == 4) {
1051             error_report("(use big-core=on for 8 threads per core)");
1052         }
1053         exit(1);
1054     }
1055 
1056     if (pnv->big_core) {
1057         /*
1058          * powernv models PnvCore as a SMT4 core. Big-core requires 2xPnvCore
1059          * per core, so adjust topology here. pnv_dt_core() processor
1060          * device-tree and TCG SMT code make the 2 cores appear as one big core
1061          * from software point of view. pnv pervasive models and xscoms tend to
1062          * see the big core as 2 small core halves.
1063          */
1064         machine->smp.cores *= 2;
1065         machine->smp.threads /= 2;
1066     }
1067 
1068     if (!is_power_of_2(machine->smp.threads)) {
1069         error_report("Cannot support %d threads/core on a powernv "
1070                      "machine because it must be a power of 2",
1071                      machine->smp.threads);
1072         exit(1);
1073     }
1074 
1075     /*
1076      * TODO: should we decide on how many chips we can create based
1077      * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1078      */
1079     if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) {
1080         error_report("invalid number of chips: '%d'", pnv->num_chips);
1081         error_printf(
1082             "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
1083         exit(1);
1084     }
1085 
1086     pnv->chips = g_new0(PnvChip *, pnv->num_chips);
1087     for (i = 0; i < pnv->num_chips; i++) {
1088         char chip_name[32];
1089         Object *chip = OBJECT(qdev_new(chip_typename));
1090         uint64_t chip_ram_size =  pnv_chip_get_ram_size(pnv, i);
1091 
1092         pnv->chips[i] = PNV_CHIP(chip);
1093 
1094         /* Distribute RAM among the chips  */
1095         object_property_set_int(chip, "ram-start", chip_ram_start,
1096                                 &error_fatal);
1097         object_property_set_int(chip, "ram-size", chip_ram_size,
1098                                 &error_fatal);
1099         chip_ram_start += chip_ram_size;
1100 
1101         snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
1102         object_property_add_child(OBJECT(pnv), chip_name, chip);
1103         object_property_set_int(chip, "chip-id", i, &error_fatal);
1104         object_property_set_int(chip, "nr-cores", machine->smp.cores,
1105                                 &error_fatal);
1106         object_property_set_int(chip, "nr-threads", machine->smp.threads,
1107                                 &error_fatal);
1108         object_property_set_bool(chip, "big-core", pnv->big_core,
1109                                 &error_fatal);
1110         object_property_set_bool(chip, "lpar-per-core", pnv->lpar_per_core,
1111                                 &error_fatal);
1112         /*
1113          * The POWER8 machine use the XICS interrupt interface.
1114          * Propagate the XICS fabric to the chip and its controllers.
1115          */
1116         if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
1117             object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
1118         }
1119         if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
1120             object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
1121                                      &error_abort);
1122         }
1123         sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
1124     }
1125     g_free(chip_typename);
1126 
1127     /* Instantiate ISA bus on chip 0 */
1128     pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
1129 
1130     /* Create serial port */
1131     serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1132 
1133     /* Create an RTC ISA device too */
1134     mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
1135 
1136     /*
1137      * Create the machine BMC simulator and the IPMI BT device for
1138      * communication with the BMC
1139      */
1140     if (defaults_enabled()) {
1141         pnv->bmc = pnv_bmc_create(pnv->pnor);
1142         pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
1143     }
1144 
1145     /*
1146      * The PNOR is mapped on the LPC FW address space by the BMC.
1147      * Since we can not reach the remote BMC machine with LPC memops,
1148      * map it always for now.
1149      */
1150     memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
1151                                 &pnv->pnor->mmio);
1152 
1153     /*
1154      * OpenPOWER systems use a IPMI SEL Event message to notify the
1155      * host to powerdown
1156      */
1157     pnv->powerdown_notifier.notify = pnv_powerdown_notify;
1158     qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
1159 
1160     /*
1161      * Create/Connect any machine-specific I2C devices
1162      */
1163     if (pmc->i2c_init) {
1164         pmc->i2c_init(pnv);
1165     }
1166 }
1167 
1168 /*
1169  *    0:21  Reserved - Read as zeros
1170  *   22:24  Chip ID
1171  *   25:28  Core number
1172  *   29:31  Thread ID
1173  */
1174 static void pnv_get_pir_tir_p8(PnvChip *chip,
1175                                 uint32_t core_id, uint32_t thread_id,
1176                                 uint32_t *pir, uint32_t *tir)
1177 {
1178     if (pir) {
1179         *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id;
1180     }
1181     if (tir) {
1182         *tir = thread_id;
1183     }
1184 }
1185 
1186 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1187                                         Error **errp)
1188 {
1189     Pnv8Chip *chip8 = PNV8_CHIP(chip);
1190     Error *local_err = NULL;
1191     Object *obj;
1192     PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1193 
1194     obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
1195     if (local_err) {
1196         error_propagate(errp, local_err);
1197         return;
1198     }
1199 
1200     pnv_cpu->intc = obj;
1201 }
1202 
1203 
1204 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1205 {
1206     PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1207 
1208     icp_reset(ICP(pnv_cpu->intc));
1209 }
1210 
1211 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1212 {
1213     PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1214 
1215     icp_destroy(ICP(pnv_cpu->intc));
1216     pnv_cpu->intc = NULL;
1217 }
1218 
1219 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1220                                             GString *buf)
1221 {
1222     icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf);
1223 }
1224 
1225 /*
1226  *    0:48  Reserved - Read as zeroes
1227  *   49:52  Node ID
1228  *   53:55  Chip ID
1229  *   56     Reserved - Read as zero
1230  *   57:61  Core number
1231  *   62:63  Thread ID
1232  *
1233  * We only care about the lower bits. uint32_t is fine for the moment.
1234  */
1235 static void pnv_get_pir_tir_p9(PnvChip *chip,
1236                                 uint32_t core_id, uint32_t thread_id,
1237                                 uint32_t *pir, uint32_t *tir)
1238 {
1239     if (chip->big_core) {
1240         /* Big-core interleaves thread ID between small-cores */
1241         thread_id <<= 1;
1242         thread_id |= core_id & 1;
1243         core_id >>= 1;
1244 
1245         if (pir) {
1246             *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id;
1247         }
1248     } else {
1249         if (pir) {
1250             *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id;
1251         }
1252     }
1253     if (tir) {
1254         *tir = thread_id;
1255     }
1256 }
1257 
1258 /*
1259  *    0:48  Reserved - Read as zeroes
1260  *   49:52  Node ID
1261  *   53:55  Chip ID
1262  *   56     Reserved - Read as zero
1263  *   57:59  Quad ID
1264  *   60     Core Chiplet Pair ID
1265  *   61:63  Thread/Core Chiplet ID t0-t2
1266  *
1267  * We only care about the lower bits. uint32_t is fine for the moment.
1268  */
1269 static void pnv_get_pir_tir_p10(PnvChip *chip,
1270                                 uint32_t core_id, uint32_t thread_id,
1271                                 uint32_t *pir, uint32_t *tir)
1272 {
1273     if (chip->big_core) {
1274         /* Big-core interleaves thread ID between small-cores */
1275         thread_id <<= 1;
1276         thread_id |= core_id & 1;
1277         core_id >>= 1;
1278 
1279         if (pir) {
1280             *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id;
1281         }
1282     } else {
1283         if (pir) {
1284             *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id;
1285         }
1286     }
1287     if (tir) {
1288         *tir = thread_id;
1289     }
1290 }
1291 
1292 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1293                                         Error **errp)
1294 {
1295     Pnv9Chip *chip9 = PNV9_CHIP(chip);
1296     Error *local_err = NULL;
1297     Object *obj;
1298     PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1299 
1300     /*
1301      * The core creates its interrupt presenter but the XIVE interrupt
1302      * controller object is initialized afterwards. Hopefully, it's
1303      * only used at runtime.
1304      */
1305     obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
1306                            &local_err);
1307     if (local_err) {
1308         error_propagate(errp, local_err);
1309         return;
1310     }
1311 
1312     pnv_cpu->intc = obj;
1313 }
1314 
1315 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1316 {
1317     PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1318 
1319     xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1320 }
1321 
1322 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1323 {
1324     PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1325 
1326     xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1327     pnv_cpu->intc = NULL;
1328 }
1329 
1330 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1331                                             GString *buf)
1332 {
1333     xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
1334 }
1335 
1336 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1337                                         Error **errp)
1338 {
1339     Pnv10Chip *chip10 = PNV10_CHIP(chip);
1340     Error *local_err = NULL;
1341     Object *obj;
1342     PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1343 
1344     /*
1345      * The core creates its interrupt presenter but the XIVE2 interrupt
1346      * controller object is initialized afterwards. Hopefully, it's
1347      * only used at runtime.
1348      */
1349     obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive),
1350                            &local_err);
1351     if (local_err) {
1352         error_propagate(errp, local_err);
1353         return;
1354     }
1355 
1356     pnv_cpu->intc = obj;
1357 }
1358 
1359 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1360 {
1361     PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1362 
1363     xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1364 }
1365 
1366 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1367 {
1368     PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1369 
1370     xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1371     pnv_cpu->intc = NULL;
1372 }
1373 
1374 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1375                                              GString *buf)
1376 {
1377     xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
1378 }
1379 
1380 /*
1381  * Allowed core identifiers on a POWER8 Processor Chip :
1382  *
1383  * <EX0 reserved>
1384  *  EX1  - Venice only
1385  *  EX2  - Venice only
1386  *  EX3  - Venice only
1387  *  EX4
1388  *  EX5
1389  *  EX6
1390  * <EX7,8 reserved> <reserved>
1391  *  EX9  - Venice only
1392  *  EX10 - Venice only
1393  *  EX11 - Venice only
1394  *  EX12
1395  *  EX13
1396  *  EX14
1397  * <EX15 reserved>
1398  */
1399 #define POWER8E_CORE_MASK  (0x7070ull)
1400 #define POWER8_CORE_MASK   (0x7e7eull)
1401 
1402 /*
1403  * POWER9 has 24 cores, ids starting at 0x0
1404  */
1405 #define POWER9_CORE_MASK   (0xffffffffffffffull)
1406 
1407 
1408 #define POWER10_CORE_MASK  (0xffffffffffffffull)
1409 
1410 static void pnv_chip_power8_instance_init(Object *obj)
1411 {
1412     Pnv8Chip *chip8 = PNV8_CHIP(obj);
1413     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1414     int i;
1415 
1416     object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1417                              (Object **)&chip8->xics,
1418                              object_property_allow_set_link,
1419                              OBJ_PROP_LINK_STRONG);
1420 
1421     object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1422 
1423     object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1424 
1425     object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1426 
1427     object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1428 
1429     if (defaults_enabled()) {
1430         chip8->num_phbs = pcc->num_phbs;
1431 
1432         for (i = 0; i < chip8->num_phbs; i++) {
1433             Object *phb = object_new(TYPE_PNV_PHB);
1434 
1435             /*
1436              * We need the chip to parent the PHB to allow the DT
1437              * to build correctly (via pnv_xscom_dt()).
1438              *
1439              * TODO: the PHB should be parented by a PEC device that, at
1440              * this moment, is not modelled powernv8/phb3.
1441              */
1442             object_property_add_child(obj, "phb[*]", phb);
1443             chip8->phbs[i] = PNV_PHB(phb);
1444         }
1445     }
1446 
1447 }
1448 
1449 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1450  {
1451     PnvChip *chip = PNV_CHIP(chip8);
1452     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1453     int i, j;
1454     char *name;
1455 
1456     name = g_strdup_printf("icp-%x", chip->chip_id);
1457     memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1458     g_free(name);
1459     memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip),
1460                                 &chip8->icp_mmio);
1461 
1462     /* Map the ICP registers for each thread */
1463     for (i = 0; i < chip->nr_cores; i++) {
1464         PnvCore *pnv_core = chip->cores[i];
1465         int core_hwid = CPU_CORE(pnv_core)->core_id;
1466 
1467         for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1468             uint32_t pir;
1469             PnvICPState *icp;
1470 
1471             pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL);
1472             icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1473 
1474             memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1475                                         &icp->mmio);
1476         }
1477     }
1478 }
1479 
1480 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1481 {
1482     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1483     PnvChip *chip = PNV_CHIP(dev);
1484     Pnv8Chip *chip8 = PNV8_CHIP(dev);
1485     Pnv8Psi *psi8 = &chip8->psi;
1486     Error *local_err = NULL;
1487     int i;
1488 
1489     assert(chip8->xics);
1490 
1491     /* XSCOM bridge is first */
1492     pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip));
1493 
1494     pcc->parent_realize(dev, &local_err);
1495     if (local_err) {
1496         error_propagate(errp, local_err);
1497         return;
1498     }
1499 
1500     /* Processor Service Interface (PSI) Host Bridge */
1501     object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip),
1502                             &error_fatal);
1503     object_property_set_link(OBJECT(psi8), ICS_PROP_XICS,
1504                              OBJECT(chip8->xics), &error_abort);
1505     if (!qdev_realize(DEVICE(psi8), NULL, errp)) {
1506         return;
1507     }
1508     pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1509                             &PNV_PSI(psi8)->xscom_regs);
1510 
1511     /* Create LPC controller */
1512     qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1513     pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1514 
1515     chip->fw_mr = &chip8->lpc.isa_fw;
1516     chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1517                                             (uint64_t) PNV_XSCOM_BASE(chip),
1518                                             PNV_XSCOM_LPC_BASE);
1519 
1520     /*
1521      * Interrupt Management Area. This is the memory region holding
1522      * all the Interrupt Control Presenter (ICP) registers
1523      */
1524     pnv_chip_icp_realize(chip8, &local_err);
1525     if (local_err) {
1526         error_propagate(errp, local_err);
1527         return;
1528     }
1529 
1530     /* Create the simplified OCC model */
1531     if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1532         return;
1533     }
1534     pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1535     qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
1536                           qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC));
1537 
1538     /* OCC SRAM model */
1539     memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1540                                 &chip8->occ.sram_regs);
1541 
1542     /* HOMER */
1543     object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1544                              &error_abort);
1545     if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1546         return;
1547     }
1548     /* Homer Xscom region */
1549     pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1550 
1551     /* Homer mmio region */
1552     memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1553                                 &chip8->homer.regs);
1554 
1555     /* PHB controllers */
1556     for (i = 0; i < chip8->num_phbs; i++) {
1557         PnvPHB *phb = chip8->phbs[i];
1558 
1559         object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1560         object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1561                                 &error_fatal);
1562         object_property_set_link(OBJECT(phb), "chip", OBJECT(chip),
1563                                  &error_fatal);
1564         if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1565             return;
1566         }
1567     }
1568 }
1569 
1570 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1571 {
1572     addr &= (PNV_XSCOM_SIZE - 1);
1573     return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1574 }
1575 
1576 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1577 {
1578     DeviceClass *dc = DEVICE_CLASS(klass);
1579     PnvChipClass *k = PNV_CHIP_CLASS(klass);
1580 
1581     k->chip_cfam_id = 0x221ef04980000000ull;  /* P8 Murano DD2.1 */
1582     k->cores_mask = POWER8E_CORE_MASK;
1583     k->num_phbs = 3;
1584     k->get_pir_tir = pnv_get_pir_tir_p8;
1585     k->intc_create = pnv_chip_power8_intc_create;
1586     k->intc_reset = pnv_chip_power8_intc_reset;
1587     k->intc_destroy = pnv_chip_power8_intc_destroy;
1588     k->intc_print_info = pnv_chip_power8_intc_print_info;
1589     k->isa_create = pnv_chip_power8_isa_create;
1590     k->dt_populate = pnv_chip_power8_dt_populate;
1591     k->pic_print_info = pnv_chip_power8_pic_print_info;
1592     k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1593     k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1594     dc->desc = "PowerNV Chip POWER8E";
1595 
1596     device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1597                                     &k->parent_realize);
1598 }
1599 
1600 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1601 {
1602     DeviceClass *dc = DEVICE_CLASS(klass);
1603     PnvChipClass *k = PNV_CHIP_CLASS(klass);
1604 
1605     k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1606     k->cores_mask = POWER8_CORE_MASK;
1607     k->num_phbs = 3;
1608     k->get_pir_tir = pnv_get_pir_tir_p8;
1609     k->intc_create = pnv_chip_power8_intc_create;
1610     k->intc_reset = pnv_chip_power8_intc_reset;
1611     k->intc_destroy = pnv_chip_power8_intc_destroy;
1612     k->intc_print_info = pnv_chip_power8_intc_print_info;
1613     k->isa_create = pnv_chip_power8_isa_create;
1614     k->dt_populate = pnv_chip_power8_dt_populate;
1615     k->pic_print_info = pnv_chip_power8_pic_print_info;
1616     k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1617     k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1618     dc->desc = "PowerNV Chip POWER8";
1619 
1620     device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1621                                     &k->parent_realize);
1622 }
1623 
1624 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1625 {
1626     DeviceClass *dc = DEVICE_CLASS(klass);
1627     PnvChipClass *k = PNV_CHIP_CLASS(klass);
1628 
1629     k->chip_cfam_id = 0x120d304980000000ull;  /* P8 Naples DD1.0 */
1630     k->cores_mask = POWER8_CORE_MASK;
1631     k->num_phbs = 4;
1632     k->get_pir_tir = pnv_get_pir_tir_p8;
1633     k->intc_create = pnv_chip_power8_intc_create;
1634     k->intc_reset = pnv_chip_power8_intc_reset;
1635     k->intc_destroy = pnv_chip_power8_intc_destroy;
1636     k->intc_print_info = pnv_chip_power8_intc_print_info;
1637     k->isa_create = pnv_chip_power8nvl_isa_create;
1638     k->dt_populate = pnv_chip_power8_dt_populate;
1639     k->pic_print_info = pnv_chip_power8_pic_print_info;
1640     k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1641     k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1642     dc->desc = "PowerNV Chip POWER8NVL";
1643 
1644     device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1645                                     &k->parent_realize);
1646 }
1647 
1648 static void pnv_chip_power9_instance_init(Object *obj)
1649 {
1650     PnvChip *chip = PNV_CHIP(obj);
1651     Pnv9Chip *chip9 = PNV9_CHIP(obj);
1652     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1653     int i;
1654 
1655     object_initialize_child(obj, "adu",  &chip9->adu, TYPE_PNV_ADU);
1656     object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1657     object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1658                               "xive-fabric");
1659 
1660     object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1661 
1662     object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1663 
1664     object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD);
1665 
1666     object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1667 
1668     object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE);
1669 
1670     object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1671 
1672     /* Number of PECs is the chip default */
1673     chip->num_pecs = pcc->num_pecs;
1674 
1675     for (i = 0; i < chip->num_pecs; i++) {
1676         object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1677                                 TYPE_PNV_PHB4_PEC);
1678     }
1679 
1680     for (i = 0; i < pcc->i2c_num_engines; i++) {
1681         object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C);
1682     }
1683 }
1684 
1685 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
1686                                       PnvCore *pnv_core,
1687                                       const char *type)
1688 {
1689     char eq_name[32];
1690     int core_id = CPU_CORE(pnv_core)->core_id;
1691 
1692     snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1693     object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1694                                        sizeof(*eq), type,
1695                                        &error_fatal, NULL);
1696 
1697     object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
1698     qdev_realize(DEVICE(eq), NULL, &error_fatal);
1699 }
1700 
1701 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1702 {
1703     PnvChip *chip = PNV_CHIP(chip9);
1704     int i;
1705 
1706     chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1707     chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1708 
1709     for (i = 0; i < chip9->nr_quads; i++) {
1710         PnvQuad *eq = &chip9->quads[i];
1711 
1712         pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
1713                                   PNV_QUAD_TYPE_NAME("power9"));
1714 
1715         pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
1716                                 &eq->xscom_regs);
1717     }
1718 }
1719 
1720 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp)
1721 {
1722     Pnv9Chip *chip9 = PNV9_CHIP(chip);
1723     int i;
1724 
1725     for (i = 0; i < chip->num_pecs; i++) {
1726         PnvPhb4PecState *pec = &chip9->pecs[i];
1727         PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1728         uint32_t pec_nest_base;
1729         uint32_t pec_pci_base;
1730 
1731         object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1732         object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1733                                 &error_fatal);
1734         object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1735                                  &error_fatal);
1736         if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1737             return;
1738         }
1739 
1740         pec_nest_base = pecc->xscom_nest_base(pec);
1741         pec_pci_base = pecc->xscom_pci_base(pec);
1742 
1743         pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1744         pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1745     }
1746 }
1747 
1748 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1749 {
1750     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1751     Pnv9Chip *chip9 = PNV9_CHIP(dev);
1752     PnvChip *chip = PNV_CHIP(dev);
1753     Pnv9Psi *psi9 = &chip9->psi;
1754     Error *local_err = NULL;
1755     int i;
1756 
1757     /* XSCOM bridge is first */
1758     pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip));
1759 
1760     pcc->parent_realize(dev, &local_err);
1761     if (local_err) {
1762         error_propagate(errp, local_err);
1763         return;
1764     }
1765 
1766     /* ADU */
1767     object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc),
1768                              &error_abort);
1769     if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) {
1770         return;
1771     }
1772     pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE,
1773                             &chip9->adu.xscom_regs);
1774 
1775     pnv_chip_quad_realize(chip9, &local_err);
1776     if (local_err) {
1777         error_propagate(errp, local_err);
1778         return;
1779     }
1780 
1781     /* XIVE interrupt controller (POWER9) */
1782     object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
1783                             PNV9_XIVE_IC_BASE(chip), &error_fatal);
1784     object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
1785                             PNV9_XIVE_VC_BASE(chip), &error_fatal);
1786     object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
1787                             PNV9_XIVE_PC_BASE(chip), &error_fatal);
1788     object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
1789                             PNV9_XIVE_TM_BASE(chip), &error_fatal);
1790     object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
1791                              &error_abort);
1792     if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
1793         return;
1794     }
1795     pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1796                             &chip9->xive.xscom_regs);
1797 
1798     /* Processor Service Interface (PSI) Host Bridge */
1799     object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip),
1800                             &error_fatal);
1801     /* This is the only device with 4k ESB pages */
1802     object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K,
1803                             &error_fatal);
1804     if (!qdev_realize(DEVICE(psi9), NULL, errp)) {
1805         return;
1806     }
1807     pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1808                             &PNV_PSI(psi9)->xscom_regs);
1809 
1810     /* LPC */
1811     if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
1812         return;
1813     }
1814     memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1815                                 &chip9->lpc.xscom_regs);
1816 
1817     chip->fw_mr = &chip9->lpc.isa_fw;
1818     chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1819                                             (uint64_t) PNV9_LPCM_BASE(chip));
1820 
1821     /* ChipTOD */
1822     object_property_set_bool(OBJECT(&chip9->chiptod), "primary",
1823                              chip->chip_id == 0, &error_abort);
1824     object_property_set_bool(OBJECT(&chip9->chiptod), "secondary",
1825                              chip->chip_id == 1, &error_abort);
1826     object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip),
1827                              &error_abort);
1828     if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) {
1829         return;
1830     }
1831     pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE,
1832                             &chip9->chiptod.xscom_regs);
1833 
1834     /* Create the simplified OCC model */
1835     if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
1836         return;
1837     }
1838     pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1839     qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
1840                               DEVICE(psi9), PSIHB9_IRQ_OCC));
1841 
1842     /* OCC SRAM model */
1843     memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1844                                 &chip9->occ.sram_regs);
1845 
1846     /* SBE */
1847     if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) {
1848         return;
1849     }
1850     pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE,
1851                             &chip9->sbe.xscom_ctrl_regs);
1852     pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE,
1853                             &chip9->sbe.xscom_mbox_regs);
1854     qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in(
1855                               DEVICE(psi9), PSIHB9_IRQ_PSU));
1856 
1857     /* HOMER */
1858     object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
1859                              &error_abort);
1860     if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
1861         return;
1862     }
1863     /* Homer Xscom region */
1864     pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1865 
1866     /* Homer mmio region */
1867     memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1868                                 &chip9->homer.regs);
1869 
1870     /* PEC PHBs */
1871     pnv_chip_power9_pec_realize(chip, &local_err);
1872     if (local_err) {
1873         error_propagate(errp, local_err);
1874         return;
1875     }
1876 
1877     /*
1878      * I2C
1879      */
1880     for (i = 0; i < pcc->i2c_num_engines; i++) {
1881         Object *obj =  OBJECT(&chip9->i2c[i]);
1882 
1883         object_property_set_int(obj, "engine", i + 1, &error_fatal);
1884         object_property_set_int(obj, "num-busses",
1885                                 pcc->i2c_ports_per_engine[i],
1886                                 &error_fatal);
1887         object_property_set_link(obj, "chip", OBJECT(chip), &error_abort);
1888         if (!qdev_realize(DEVICE(obj), NULL, errp)) {
1889             return;
1890         }
1891         pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE +
1892                                 (chip9->i2c[i].engine - 1) *
1893                                         PNV9_XSCOM_I2CM_SIZE,
1894                                 &chip9->i2c[i].xscom_regs);
1895         qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0,
1896                               qdev_get_gpio_in(DEVICE(psi9),
1897                                                PSIHB9_IRQ_SBE_I2C));
1898     }
1899 }
1900 
1901 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1902 {
1903     addr &= (PNV9_XSCOM_SIZE - 1);
1904     return addr >> 3;
1905 }
1906 
1907 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1908 {
1909     DeviceClass *dc = DEVICE_CLASS(klass);
1910     PnvChipClass *k = PNV_CHIP_CLASS(klass);
1911     static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2};
1912 
1913     k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1914     k->cores_mask = POWER9_CORE_MASK;
1915     k->get_pir_tir = pnv_get_pir_tir_p9;
1916     k->intc_create = pnv_chip_power9_intc_create;
1917     k->intc_reset = pnv_chip_power9_intc_reset;
1918     k->intc_destroy = pnv_chip_power9_intc_destroy;
1919     k->intc_print_info = pnv_chip_power9_intc_print_info;
1920     k->isa_create = pnv_chip_power9_isa_create;
1921     k->dt_populate = pnv_chip_power9_dt_populate;
1922     k->pic_print_info = pnv_chip_power9_pic_print_info;
1923     k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1924     k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1925     dc->desc = "PowerNV Chip POWER9";
1926     k->num_pecs = PNV9_CHIP_MAX_PEC;
1927     k->i2c_num_engines = PNV9_CHIP_MAX_I2C;
1928     k->i2c_ports_per_engine = i2c_ports_per_engine;
1929 
1930     device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1931                                     &k->parent_realize);
1932 }
1933 
1934 static void pnv_chip_power10_instance_init(Object *obj)
1935 {
1936     PnvChip *chip = PNV_CHIP(obj);
1937     Pnv10Chip *chip10 = PNV10_CHIP(obj);
1938     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1939     int i;
1940 
1941     object_initialize_child(obj, "adu",  &chip10->adu, TYPE_PNV_ADU);
1942     object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2);
1943     object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive),
1944                               "xive-fabric");
1945     object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1946     object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
1947     object_initialize_child(obj, "chiptod", &chip10->chiptod,
1948                             TYPE_PNV10_CHIPTOD);
1949     object_initialize_child(obj, "occ",  &chip10->occ, TYPE_PNV10_OCC);
1950     object_initialize_child(obj, "sbe",  &chip10->sbe, TYPE_PNV10_SBE);
1951     object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
1952     object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet,
1953                             TYPE_PNV_N1_CHIPLET);
1954 
1955     chip->num_pecs = pcc->num_pecs;
1956 
1957     for (i = 0; i < chip->num_pecs; i++) {
1958         object_initialize_child(obj, "pec[*]", &chip10->pecs[i],
1959                                 TYPE_PNV_PHB5_PEC);
1960     }
1961 
1962     for (i = 0; i < pcc->i2c_num_engines; i++) {
1963         object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C);
1964     }
1965 
1966     for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) {
1967         object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i],
1968                                 TYPE_PNV_SPI);
1969     }
1970 }
1971 
1972 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
1973 {
1974     PnvChip *chip = PNV_CHIP(chip10);
1975     int i;
1976 
1977     chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1978     chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
1979 
1980     for (i = 0; i < chip10->nr_quads; i++) {
1981         PnvQuad *eq = &chip10->quads[i];
1982 
1983         pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
1984                                   PNV_QUAD_TYPE_NAME("power10"));
1985 
1986         pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
1987                                 &eq->xscom_regs);
1988 
1989         pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id),
1990                                 &eq->xscom_qme_regs);
1991     }
1992 }
1993 
1994 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp)
1995 {
1996     Pnv10Chip *chip10 = PNV10_CHIP(chip);
1997     int i;
1998 
1999     for (i = 0; i < chip->num_pecs; i++) {
2000         PnvPhb4PecState *pec = &chip10->pecs[i];
2001         PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
2002         uint32_t pec_nest_base;
2003         uint32_t pec_pci_base;
2004 
2005         object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
2006         object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
2007                                 &error_fatal);
2008         object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
2009                                  &error_fatal);
2010         if (!qdev_realize(DEVICE(pec), NULL, errp)) {
2011             return;
2012         }
2013 
2014         pec_nest_base = pecc->xscom_nest_base(pec);
2015         pec_pci_base = pecc->xscom_pci_base(pec);
2016 
2017         pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
2018         pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
2019     }
2020 }
2021 
2022 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
2023 {
2024     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
2025     PnvChip *chip = PNV_CHIP(dev);
2026     Pnv10Chip *chip10 = PNV10_CHIP(dev);
2027     Error *local_err = NULL;
2028     int i;
2029 
2030     /* XSCOM bridge is first */
2031     pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip));
2032 
2033     pcc->parent_realize(dev, &local_err);
2034     if (local_err) {
2035         error_propagate(errp, local_err);
2036         return;
2037     }
2038 
2039     /* ADU */
2040     object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc),
2041                              &error_abort);
2042     if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) {
2043         return;
2044     }
2045     pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE,
2046                             &chip10->adu.xscom_regs);
2047 
2048     pnv_chip_power10_quad_realize(chip10, &local_err);
2049     if (local_err) {
2050         error_propagate(errp, local_err);
2051         return;
2052     }
2053 
2054     /* XIVE2 interrupt controller (POWER10) */
2055     object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
2056                             PNV10_XIVE2_IC_BASE(chip), &error_fatal);
2057     object_property_set_int(OBJECT(&chip10->xive), "esb-bar",
2058                             PNV10_XIVE2_ESB_BASE(chip), &error_fatal);
2059     object_property_set_int(OBJECT(&chip10->xive), "end-bar",
2060                             PNV10_XIVE2_END_BASE(chip), &error_fatal);
2061     object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar",
2062                             PNV10_XIVE2_NVPG_BASE(chip), &error_fatal);
2063     object_property_set_int(OBJECT(&chip10->xive), "nvc-bar",
2064                             PNV10_XIVE2_NVC_BASE(chip), &error_fatal);
2065     object_property_set_int(OBJECT(&chip10->xive), "tm-bar",
2066                             PNV10_XIVE2_TM_BASE(chip), &error_fatal);
2067     object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip),
2068                              &error_abort);
2069     if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) {
2070         return;
2071     }
2072     pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE,
2073                             &chip10->xive.xscom_regs);
2074 
2075     /* Processor Service Interface (PSI) Host Bridge */
2076     object_property_set_int(OBJECT(&chip10->psi), "bar",
2077                             PNV10_PSIHB_BASE(chip), &error_fatal);
2078     /* PSI can now be configured to use 64k ESB pages on POWER10 */
2079     object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K,
2080                             &error_fatal);
2081     if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
2082         return;
2083     }
2084     pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
2085                             &PNV_PSI(&chip10->psi)->xscom_regs);
2086 
2087     /* LPC */
2088     if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
2089         return;
2090     }
2091     memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
2092                                 &chip10->lpc.xscom_regs);
2093 
2094     chip->fw_mr = &chip10->lpc.isa_fw;
2095     chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
2096                                             (uint64_t) PNV10_LPCM_BASE(chip));
2097 
2098     /* ChipTOD */
2099     object_property_set_bool(OBJECT(&chip10->chiptod), "primary",
2100                              chip->chip_id == 0, &error_abort);
2101     object_property_set_bool(OBJECT(&chip10->chiptod), "secondary",
2102                              chip->chip_id == 1, &error_abort);
2103     object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip),
2104                              &error_abort);
2105     if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) {
2106         return;
2107     }
2108     pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE,
2109                             &chip10->chiptod.xscom_regs);
2110 
2111     /* Create the simplified OCC model */
2112     if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
2113         return;
2114     }
2115     pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
2116                             &chip10->occ.xscom_regs);
2117     qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
2118                               DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
2119 
2120     /* OCC SRAM model */
2121     memory_region_add_subregion(get_system_memory(),
2122                                 PNV10_OCC_SENSOR_BASE(chip),
2123                                 &chip10->occ.sram_regs);
2124 
2125     /* SBE */
2126     if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) {
2127         return;
2128     }
2129     pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE,
2130                             &chip10->sbe.xscom_ctrl_regs);
2131     pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE,
2132                             &chip10->sbe.xscom_mbox_regs);
2133     qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in(
2134                               DEVICE(&chip10->psi), PSIHB9_IRQ_PSU));
2135 
2136     /* HOMER */
2137     object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip),
2138                              &error_abort);
2139     if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) {
2140         return;
2141     }
2142     /* Homer Xscom region */
2143     pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE,
2144                             &chip10->homer.pba_regs);
2145 
2146     /* Homer mmio region */
2147     memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
2148                                 &chip10->homer.regs);
2149 
2150     /* N1 chiplet */
2151     if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) {
2152         return;
2153     }
2154     pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE,
2155              &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr);
2156 
2157     pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE,
2158                            &chip10->n1_chiplet.xscom_pb_eq_mr);
2159 
2160     pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE,
2161                            &chip10->n1_chiplet.xscom_pb_es_mr);
2162 
2163     /* PHBs */
2164     pnv_chip_power10_phb_realize(chip, &local_err);
2165     if (local_err) {
2166         error_propagate(errp, local_err);
2167         return;
2168     }
2169 
2170 
2171     /*
2172      * I2C
2173      */
2174     for (i = 0; i < pcc->i2c_num_engines; i++) {
2175         Object *obj =  OBJECT(&chip10->i2c[i]);
2176 
2177         object_property_set_int(obj, "engine", i + 1, &error_fatal);
2178         object_property_set_int(obj, "num-busses",
2179                                 pcc->i2c_ports_per_engine[i],
2180                                 &error_fatal);
2181         object_property_set_link(obj, "chip", OBJECT(chip), &error_abort);
2182         if (!qdev_realize(DEVICE(obj), NULL, errp)) {
2183             return;
2184         }
2185         pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE +
2186                                 (chip10->i2c[i].engine - 1) *
2187                                         PNV10_XSCOM_I2CM_SIZE,
2188                                 &chip10->i2c[i].xscom_regs);
2189         qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0,
2190                               qdev_get_gpio_in(DEVICE(&chip10->psi),
2191                                                PSIHB9_IRQ_SBE_I2C));
2192     }
2193     /* PIB SPI Controller */
2194     for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) {
2195         object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num",
2196                                 i, &error_fatal);
2197         /* pib_spic[2] connected to 25csm04 which implements 1 byte transfer */
2198         object_property_set_int(OBJECT(&chip10->pib_spic[i]), "transfer_len",
2199                                 (i == 2) ? 1 : 4, &error_fatal);
2200         if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT
2201                                         (&chip10->pib_spic[i])), errp)) {
2202             return;
2203         }
2204         pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE +
2205                                 i * PNV10_XSCOM_PIB_SPIC_SIZE,
2206                                 &chip10->pib_spic[i].xscom_spic_regs);
2207     }
2208 }
2209 
2210 static void pnv_rainier_i2c_init(PnvMachineState *pnv)
2211 {
2212     int i;
2213     for (i = 0; i < pnv->num_chips; i++) {
2214         Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
2215 
2216         /*
2217          * Add a PCA9552 I2C device for PCIe hotplug control
2218          * to engine 2, bus 1, address 0x63
2219          */
2220         I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1],
2221                                                 "pca9552", 0x63);
2222 
2223         /*
2224          * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9
2225          * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots
2226          * after hypervisor code sets a SLOTx_EN pin high.
2227          */
2228         qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5));
2229         qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6));
2230         qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7));
2231         qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8));
2232         qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9));
2233 
2234         /*
2235          * Add a PCA9554 I2C device for cable card presence detection
2236          * to engine 2, bus 1, address 0x25
2237          */
2238         i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25);
2239     }
2240 }
2241 
2242 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
2243 {
2244     addr &= (PNV10_XSCOM_SIZE - 1);
2245     return addr >> 3;
2246 }
2247 
2248 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
2249 {
2250     DeviceClass *dc = DEVICE_CLASS(klass);
2251     PnvChipClass *k = PNV_CHIP_CLASS(klass);
2252     static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16};
2253 
2254     k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */
2255     k->cores_mask = POWER10_CORE_MASK;
2256     k->get_pir_tir = pnv_get_pir_tir_p10;
2257     k->intc_create = pnv_chip_power10_intc_create;
2258     k->intc_reset = pnv_chip_power10_intc_reset;
2259     k->intc_destroy = pnv_chip_power10_intc_destroy;
2260     k->intc_print_info = pnv_chip_power10_intc_print_info;
2261     k->isa_create = pnv_chip_power10_isa_create;
2262     k->dt_populate = pnv_chip_power10_dt_populate;
2263     k->pic_print_info = pnv_chip_power10_pic_print_info;
2264     k->xscom_core_base = pnv_chip_power10_xscom_core_base;
2265     k->xscom_pcba = pnv_chip_power10_xscom_pcba;
2266     dc->desc = "PowerNV Chip POWER10";
2267     k->num_pecs = PNV10_CHIP_MAX_PEC;
2268     k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
2269     k->i2c_ports_per_engine = i2c_ports_per_engine;
2270 
2271     device_class_set_parent_realize(dc, pnv_chip_power10_realize,
2272                                     &k->parent_realize);
2273 }
2274 
2275 static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip,
2276                                    Error **errp)
2277 {
2278     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
2279     int cores_max;
2280 
2281     /*
2282      * No custom mask for this chip, let's use the default one from *
2283      * the chip class
2284      */
2285     if (!chip->cores_mask) {
2286         chip->cores_mask = pcc->cores_mask;
2287     }
2288 
2289     /* filter alien core ids ! some are reserved */
2290     if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
2291         error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
2292                    chip->cores_mask);
2293         return;
2294     }
2295     chip->cores_mask &= pcc->cores_mask;
2296 
2297     /* Ensure small-cores a paired up in big-core mode */
2298     if (pnv->big_core) {
2299         uint64_t even_cores = chip->cores_mask & 0x5555555555555555ULL;
2300         uint64_t odd_cores = chip->cores_mask & 0xaaaaaaaaaaaaaaaaULL;
2301 
2302         if (even_cores ^ (odd_cores >> 1)) {
2303             error_setg(errp, "warning: unpaired cores in big-core mode !");
2304             return;
2305         }
2306     }
2307 
2308     /* now that we have a sane layout, let check the number of cores */
2309     cores_max = ctpop64(chip->cores_mask);
2310     if (chip->nr_cores > cores_max) {
2311         error_setg(errp, "warning: too many cores for chip ! Limit is %d",
2312                    cores_max);
2313         return;
2314     }
2315 }
2316 
2317 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
2318 {
2319     PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
2320     PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(pnv);
2321     Error *error = NULL;
2322     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
2323     const char *typename = pnv_chip_core_typename(chip);
2324     int i, core_hwid;
2325 
2326     if (!object_class_by_name(typename)) {
2327         error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
2328         return;
2329     }
2330 
2331     /* Cores */
2332     pnv_chip_core_sanitize(pnv, chip, &error);
2333     if (error) {
2334         error_propagate(errp, error);
2335         return;
2336     }
2337 
2338     chip->cores = g_new0(PnvCore *, chip->nr_cores);
2339 
2340     for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
2341              && (i < chip->nr_cores); core_hwid++) {
2342         char core_name[32];
2343         PnvCore *pnv_core;
2344         uint64_t xscom_core_base;
2345 
2346         if (!(chip->cores_mask & (1ull << core_hwid))) {
2347             continue;
2348         }
2349 
2350         pnv_core = PNV_CORE(object_new(typename));
2351 
2352         snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
2353         object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
2354         chip->cores[i] = pnv_core;
2355         object_property_set_int(OBJECT(pnv_core), "nr-threads",
2356                                 chip->nr_threads, &error_fatal);
2357         object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
2358                                 core_hwid, &error_fatal);
2359         object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid,
2360                                 &error_fatal);
2361         object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
2362                                 &error_fatal);
2363         object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core,
2364                                 &error_fatal);
2365         object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core",
2366                                 pmc->quirk_tb_big_core, &error_fatal);
2367         object_property_set_bool(OBJECT(pnv_core), "lpar-per-core",
2368                                 chip->lpar_per_core, &error_fatal);
2369         object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
2370                                  &error_abort);
2371 
2372         qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
2373 
2374         /* Each core has an XSCOM MMIO region */
2375         xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
2376 
2377         pnv_xscom_add_subregion(chip, xscom_core_base,
2378                                 &pnv_core->xscom_regs);
2379         i++;
2380     }
2381 }
2382 
2383 static void pnv_chip_realize(DeviceState *dev, Error **errp)
2384 {
2385     PnvChip *chip = PNV_CHIP(dev);
2386     Error *error = NULL;
2387 
2388     /* Cores */
2389     pnv_chip_core_realize(chip, &error);
2390     if (error) {
2391         error_propagate(errp, error);
2392         return;
2393     }
2394 }
2395 
2396 static Property pnv_chip_properties[] = {
2397     DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
2398     DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
2399     DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
2400     DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
2401     DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
2402     DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
2403     DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false),
2404     DEFINE_PROP_BOOL("lpar-per-core", PnvChip, lpar_per_core, false),
2405     DEFINE_PROP_END_OF_LIST(),
2406 };
2407 
2408 static void pnv_chip_class_init(ObjectClass *klass, void *data)
2409 {
2410     DeviceClass *dc = DEVICE_CLASS(klass);
2411 
2412     set_bit(DEVICE_CATEGORY_CPU, dc->categories);
2413     dc->realize = pnv_chip_realize;
2414     device_class_set_props(dc, pnv_chip_properties);
2415     dc->desc = "PowerNV Chip";
2416 }
2417 
2418 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id)
2419 {
2420     int i;
2421 
2422     for (i = 0; i < chip->nr_cores; i++) {
2423         PnvCore *pc = chip->cores[i];
2424         CPUCore *cc = CPU_CORE(pc);
2425 
2426         if (cc->core_id == core_id) {
2427             return pc;
2428         }
2429     }
2430     return NULL;
2431 }
2432 
2433 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
2434 {
2435     int i, j;
2436 
2437     for (i = 0; i < chip->nr_cores; i++) {
2438         PnvCore *pc = chip->cores[i];
2439         CPUCore *cc = CPU_CORE(pc);
2440 
2441         for (j = 0; j < cc->nr_threads; j++) {
2442             if (ppc_cpu_pir(pc->threads[j]) == pir) {
2443                 return pc->threads[j];
2444             }
2445         }
2446     }
2447     return NULL;
2448 }
2449 
2450 static void pnv_chip_foreach_cpu(PnvChip *chip,
2451                    void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque),
2452                    void *opaque)
2453 {
2454     int i, j;
2455 
2456     for (i = 0; i < chip->nr_cores; i++) {
2457         PnvCore *pc = chip->cores[i];
2458 
2459         for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) {
2460             fn(chip, pc->threads[j], opaque);
2461         }
2462     }
2463 }
2464 
2465 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
2466 {
2467     PnvMachineState *pnv = PNV_MACHINE(xi);
2468     int i, j;
2469 
2470     for (i = 0; i < pnv->num_chips; i++) {
2471         Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2472 
2473         if (ics_valid_irq(&chip8->psi.ics, irq)) {
2474             return &chip8->psi.ics;
2475         }
2476 
2477         for (j = 0; j < chip8->num_phbs; j++) {
2478             PnvPHB *phb = chip8->phbs[j];
2479             PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2480 
2481             if (ics_valid_irq(&phb3->lsis, irq)) {
2482                 return &phb3->lsis;
2483             }
2484 
2485             if (ics_valid_irq(ICS(&phb3->msis), irq)) {
2486                 return ICS(&phb3->msis);
2487             }
2488         }
2489     }
2490     return NULL;
2491 }
2492 
2493 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
2494 {
2495     int i;
2496 
2497     for (i = 0; i < pnv->num_chips; i++) {
2498         PnvChip *chip = pnv->chips[i];
2499         if (chip->chip_id == chip_id) {
2500             return chip;
2501         }
2502     }
2503     return NULL;
2504 }
2505 
2506 static void pnv_ics_resend(XICSFabric *xi)
2507 {
2508     PnvMachineState *pnv = PNV_MACHINE(xi);
2509     int i, j;
2510 
2511     for (i = 0; i < pnv->num_chips; i++) {
2512         Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2513 
2514         ics_resend(&chip8->psi.ics);
2515 
2516         for (j = 0; j < chip8->num_phbs; j++) {
2517             PnvPHB *phb = chip8->phbs[j];
2518             PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2519 
2520             ics_resend(&phb3->lsis);
2521             ics_resend(ICS(&phb3->msis));
2522         }
2523     }
2524 }
2525 
2526 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
2527 {
2528     PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
2529 
2530     return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
2531 }
2532 
2533 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
2534                                     void *opaque)
2535 {
2536     PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque);
2537 }
2538 
2539 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf)
2540 {
2541     PnvMachineState *pnv = PNV_MACHINE(obj);
2542     int i;
2543 
2544     for (i = 0; i < pnv->num_chips; i++) {
2545         PnvChip *chip = pnv->chips[i];
2546 
2547         /* First CPU presenters */
2548         pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf);
2549 
2550         /* Then other devices, PHB, PSI, XIVE */
2551         PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf);
2552     }
2553 }
2554 
2555 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
2556                          uint8_t nvt_blk, uint32_t nvt_idx,
2557                          bool cam_ignore, uint8_t priority,
2558                          uint32_t logic_serv,
2559                          XiveTCTXMatch *match)
2560 {
2561     PnvMachineState *pnv = PNV_MACHINE(xfb);
2562     int total_count = 0;
2563     int i;
2564 
2565     for (i = 0; i < pnv->num_chips; i++) {
2566         Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
2567         XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
2568         XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2569         int count;
2570 
2571         count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2572                                priority, logic_serv, match);
2573 
2574         if (count < 0) {
2575             return count;
2576         }
2577 
2578         total_count += count;
2579     }
2580 
2581     return total_count;
2582 }
2583 
2584 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
2585                                 uint8_t nvt_blk, uint32_t nvt_idx,
2586                                 bool cam_ignore, uint8_t priority,
2587                                 uint32_t logic_serv,
2588                                 XiveTCTXMatch *match)
2589 {
2590     PnvMachineState *pnv = PNV_MACHINE(xfb);
2591     int total_count = 0;
2592     int i;
2593 
2594     for (i = 0; i < pnv->num_chips; i++) {
2595         Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
2596         XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive);
2597         XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2598         int count;
2599 
2600         count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2601                                priority, logic_serv, match);
2602 
2603         if (count < 0) {
2604             return count;
2605         }
2606 
2607         total_count += count;
2608     }
2609 
2610     return total_count;
2611 }
2612 
2613 static bool pnv_machine_get_big_core(Object *obj, Error **errp)
2614 {
2615     PnvMachineState *pnv = PNV_MACHINE(obj);
2616     return pnv->big_core;
2617 }
2618 
2619 static void pnv_machine_set_big_core(Object *obj, bool value, Error **errp)
2620 {
2621     PnvMachineState *pnv = PNV_MACHINE(obj);
2622     pnv->big_core = value;
2623 }
2624 
2625 static bool pnv_machine_get_lpar_per_core(Object *obj, Error **errp)
2626 {
2627     PnvMachineState *pnv = PNV_MACHINE(obj);
2628     return pnv->lpar_per_core;
2629 }
2630 
2631 static void pnv_machine_set_lpar_per_core(Object *obj, bool value, Error **errp)
2632 {
2633     PnvMachineState *pnv = PNV_MACHINE(obj);
2634     pnv->lpar_per_core = value;
2635 }
2636 
2637 static bool pnv_machine_get_hb(Object *obj, Error **errp)
2638 {
2639     PnvMachineState *pnv = PNV_MACHINE(obj);
2640 
2641     return !!pnv->fw_load_addr;
2642 }
2643 
2644 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
2645 {
2646     PnvMachineState *pnv = PNV_MACHINE(obj);
2647 
2648     if (value) {
2649         pnv->fw_load_addr = 0x8000000;
2650     }
2651 }
2652 
2653 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
2654 {
2655     MachineClass *mc = MACHINE_CLASS(oc);
2656     XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
2657     PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2658     static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
2659 
2660     static GlobalProperty phb_compat[] = {
2661         { TYPE_PNV_PHB, "version", "3" },
2662         { TYPE_PNV_PHB_ROOT_PORT, "version", "3" },
2663     };
2664 
2665     mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
2666     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
2667     compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2668 
2669     xic->icp_get = pnv_icp_get;
2670     xic->ics_get = pnv_ics_get;
2671     xic->ics_resend = pnv_ics_resend;
2672 
2673     pmc->compat = compat;
2674     pmc->compat_size = sizeof(compat);
2675     pmc->max_smt_threads = 8;
2676     /* POWER8 is always lpar-per-core mode */
2677     pmc->has_lpar_per_thread = false;
2678 
2679     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2680 }
2681 
2682 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
2683 {
2684     MachineClass *mc = MACHINE_CLASS(oc);
2685     XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2686     PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2687     static const char compat[] = "qemu,powernv9\0ibm,powernv";
2688 
2689     static GlobalProperty phb_compat[] = {
2690         { TYPE_PNV_PHB, "version", "4" },
2691         { TYPE_PNV_PHB_ROOT_PORT, "version", "4" },
2692     };
2693 
2694     mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
2695     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2");
2696     compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2697 
2698     xfc->match_nvt = pnv_match_nvt;
2699 
2700     pmc->compat = compat;
2701     pmc->compat_size = sizeof(compat);
2702     pmc->max_smt_threads = 4;
2703     pmc->has_lpar_per_thread = true;
2704     pmc->dt_power_mgt = pnv_dt_power_mgt;
2705 
2706     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2707 
2708     object_class_property_add_bool(oc, "big-core",
2709                                    pnv_machine_get_big_core,
2710                                    pnv_machine_set_big_core);
2711     object_class_property_set_description(oc, "big-core",
2712                               "Use big-core (aka fused-core) mode");
2713 
2714     object_class_property_add_bool(oc, "lpar-per-core",
2715                                    pnv_machine_get_lpar_per_core,
2716                                    pnv_machine_set_lpar_per_core);
2717     object_class_property_set_description(oc, "lpar-per-core",
2718                               "Use 1 LPAR per core mode");
2719 }
2720 
2721 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data)
2722 {
2723     MachineClass *mc = MACHINE_CLASS(oc);
2724     PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2725     XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2726     static const char compat[] = "qemu,powernv10\0ibm,powernv";
2727 
2728     static GlobalProperty phb_compat[] = {
2729         { TYPE_PNV_PHB, "version", "5" },
2730         { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
2731     };
2732 
2733     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
2734     compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2735 
2736     mc->alias = "powernv";
2737 
2738     pmc->compat = compat;
2739     pmc->compat_size = sizeof(compat);
2740     pmc->max_smt_threads = 4;
2741     pmc->has_lpar_per_thread = true;
2742     pmc->quirk_tb_big_core = true;
2743     pmc->dt_power_mgt = pnv_dt_power_mgt;
2744 
2745     xfc->match_nvt = pnv10_xive_match_nvt;
2746 
2747     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2748 }
2749 
2750 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
2751 {
2752     MachineClass *mc = MACHINE_CLASS(oc);
2753 
2754     pnv_machine_p10_common_class_init(oc, data);
2755     mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
2756 
2757     /*
2758      * This is the parent of POWER10 Rainier class, so properies go here
2759      * rather than common init (which would add them to both parent and
2760      * child which is invalid).
2761      */
2762     object_class_property_add_bool(oc, "big-core",
2763                                    pnv_machine_get_big_core,
2764                                    pnv_machine_set_big_core);
2765     object_class_property_set_description(oc, "big-core",
2766                               "Use big-core (aka fused-core) mode");
2767 
2768     object_class_property_add_bool(oc, "lpar-per-core",
2769                                    pnv_machine_get_lpar_per_core,
2770                                    pnv_machine_set_lpar_per_core);
2771     object_class_property_set_description(oc, "lpar-per-core",
2772                               "Use 1 LPAR per core mode");
2773 }
2774 
2775 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data)
2776 {
2777     MachineClass *mc = MACHINE_CLASS(oc);
2778     PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2779 
2780     pnv_machine_p10_common_class_init(oc, data);
2781     mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier";
2782     pmc->i2c_init = pnv_rainier_i2c_init;
2783 }
2784 
2785 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
2786 {
2787     CPUPPCState *env = cpu_env(cs);
2788 
2789     cpu_synchronize_state(cs);
2790     ppc_cpu_do_system_reset(cs);
2791     if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
2792         /*
2793          * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
2794          * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
2795          * (PPC_BIT(43)).
2796          */
2797         if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
2798             warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2799             env->spr[SPR_SRR1] |= SRR1_WAKERESET;
2800         }
2801     } else {
2802         /*
2803          * For non-powersave system resets, SRR1[42:45] are defined to be
2804          * implementation-dependent. The POWER9 User Manual specifies that
2805          * an external (SCOM driven, which may come from a BMC nmi command or
2806          * another CPU requesting a NMI IPI) system reset exception should be
2807          * 0b0010 (PPC_BIT(44)).
2808          */
2809         env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
2810     }
2811     if (arg.host_int == 1) {
2812         cpu_resume(cs);
2813     }
2814 }
2815 
2816 /*
2817  * Send a SRESET (NMI) interrupt to the CPU, and resume execution if it was
2818  * paused.
2819  */
2820 void pnv_cpu_do_nmi_resume(CPUState *cs)
2821 {
2822     async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(1));
2823 }
2824 
2825 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque)
2826 {
2827     async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(0));
2828 }
2829 
2830 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
2831 {
2832     PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
2833     int i;
2834 
2835     for (i = 0; i < pnv->num_chips; i++) {
2836         pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL);
2837     }
2838 }
2839 
2840 static void pnv_machine_class_init(ObjectClass *oc, void *data)
2841 {
2842     MachineClass *mc = MACHINE_CLASS(oc);
2843     InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
2844     NMIClass *nc = NMI_CLASS(oc);
2845 
2846     mc->desc = "IBM PowerNV (Non-Virtualized)";
2847     mc->init = pnv_init;
2848     mc->reset = pnv_reset;
2849     mc->max_cpus = MAX_CPUS;
2850     /* Pnv provides a AHCI device for storage */
2851     mc->block_default_type = IF_IDE;
2852     mc->no_parallel = 1;
2853     mc->default_boot_order = NULL;
2854     /*
2855      * RAM defaults to less than 2048 for 32-bit hosts, and large
2856      * enough to fit the maximum initrd size at it's load address
2857      */
2858     mc->default_ram_size = 1 * GiB;
2859     mc->default_ram_id = "pnv.ram";
2860     ispc->print_info = pnv_pic_print_info;
2861     nc->nmi_monitor_handler = pnv_nmi;
2862 
2863     object_class_property_add_bool(oc, "hb-mode",
2864                                    pnv_machine_get_hb, pnv_machine_set_hb);
2865     object_class_property_set_description(oc, "hb-mode",
2866                               "Use a hostboot like boot loader");
2867 }
2868 
2869 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2870     {                                             \
2871         .name          = type,                    \
2872         .class_init    = class_initfn,            \
2873         .parent        = TYPE_PNV8_CHIP,          \
2874     }
2875 
2876 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2877     {                                             \
2878         .name          = type,                    \
2879         .class_init    = class_initfn,            \
2880         .parent        = TYPE_PNV9_CHIP,          \
2881     }
2882 
2883 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2884     {                                              \
2885         .name          = type,                     \
2886         .class_init    = class_initfn,             \
2887         .parent        = TYPE_PNV10_CHIP,          \
2888     }
2889 
2890 static const TypeInfo types[] = {
2891     {
2892         .name          = MACHINE_TYPE_NAME("powernv10-rainier"),
2893         .parent        = MACHINE_TYPE_NAME("powernv10"),
2894         .class_init    = pnv_machine_p10_rainier_class_init,
2895     },
2896     {
2897         .name          = MACHINE_TYPE_NAME("powernv10"),
2898         .parent        = TYPE_PNV_MACHINE,
2899         .class_init    = pnv_machine_power10_class_init,
2900         .interfaces = (InterfaceInfo[]) {
2901             { TYPE_XIVE_FABRIC },
2902             { },
2903         },
2904     },
2905     {
2906         .name          = MACHINE_TYPE_NAME("powernv9"),
2907         .parent        = TYPE_PNV_MACHINE,
2908         .class_init    = pnv_machine_power9_class_init,
2909         .interfaces = (InterfaceInfo[]) {
2910             { TYPE_XIVE_FABRIC },
2911             { },
2912         },
2913     },
2914     {
2915         .name          = MACHINE_TYPE_NAME("powernv8"),
2916         .parent        = TYPE_PNV_MACHINE,
2917         .class_init    = pnv_machine_power8_class_init,
2918         .interfaces = (InterfaceInfo[]) {
2919             { TYPE_XICS_FABRIC },
2920             { },
2921         },
2922     },
2923     {
2924         .name          = TYPE_PNV_MACHINE,
2925         .parent        = TYPE_MACHINE,
2926         .abstract       = true,
2927         .instance_size = sizeof(PnvMachineState),
2928         .class_init    = pnv_machine_class_init,
2929         .class_size    = sizeof(PnvMachineClass),
2930         .interfaces = (InterfaceInfo[]) {
2931             { TYPE_INTERRUPT_STATS_PROVIDER },
2932             { TYPE_NMI },
2933             { },
2934         },
2935     },
2936     {
2937         .name          = TYPE_PNV_CHIP,
2938         .parent        = TYPE_SYS_BUS_DEVICE,
2939         .class_init    = pnv_chip_class_init,
2940         .instance_size = sizeof(PnvChip),
2941         .class_size    = sizeof(PnvChipClass),
2942         .abstract      = true,
2943     },
2944 
2945     /*
2946      * P10 chip and variants
2947      */
2948     {
2949         .name          = TYPE_PNV10_CHIP,
2950         .parent        = TYPE_PNV_CHIP,
2951         .instance_init = pnv_chip_power10_instance_init,
2952         .instance_size = sizeof(Pnv10Chip),
2953     },
2954     DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2955 
2956     /*
2957      * P9 chip and variants
2958      */
2959     {
2960         .name          = TYPE_PNV9_CHIP,
2961         .parent        = TYPE_PNV_CHIP,
2962         .instance_init = pnv_chip_power9_instance_init,
2963         .instance_size = sizeof(Pnv9Chip),
2964     },
2965     DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2966 
2967     /*
2968      * P8 chip and variants
2969      */
2970     {
2971         .name          = TYPE_PNV8_CHIP,
2972         .parent        = TYPE_PNV_CHIP,
2973         .instance_init = pnv_chip_power8_instance_init,
2974         .instance_size = sizeof(Pnv8Chip),
2975     },
2976     DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2977     DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2978     DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2979                           pnv_chip_power8nvl_class_init),
2980 };
2981 
2982 DEFINE_TYPES(types)
2983