1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "qapi/type-helpers.h" 42 #include "monitor/monitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 #include "hw/pci-host/pnv_phb.h" 48 #include "hw/pci-host/pnv_phb3.h" 49 #include "hw/pci-host/pnv_phb4.h" 50 51 #include "hw/ppc/xics.h" 52 #include "hw/qdev-properties.h" 53 #include "hw/ppc/pnv_chip.h" 54 #include "hw/ppc/pnv_xscom.h" 55 #include "hw/ppc/pnv_pnor.h" 56 57 #include "hw/isa/isa.h" 58 #include "hw/char/serial.h" 59 #include "hw/rtc/mc146818rtc.h" 60 61 #include <libfdt.h> 62 63 #define FDT_MAX_SIZE (1 * MiB) 64 65 #define FW_FILE_NAME "skiboot.lid" 66 #define FW_LOAD_ADDR 0x0 67 #define FW_MAX_SIZE (16 * MiB) 68 69 #define KERNEL_LOAD_ADDR 0x20000000 70 #define KERNEL_MAX_SIZE (128 * MiB) 71 #define INITRD_LOAD_ADDR 0x28000000 72 #define INITRD_MAX_SIZE (128 * MiB) 73 74 static const char *pnv_chip_core_typename(const PnvChip *o) 75 { 76 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 77 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 78 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 79 const char *core_type = object_class_get_name(object_class_by_name(s)); 80 g_free(s); 81 return core_type; 82 } 83 84 /* 85 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 86 * 4 * 4 sockets * 12 cores * 8 threads = 1536 87 * Let's make it 2^11 88 */ 89 #define MAX_CPUS 2048 90 91 /* 92 * Memory nodes are created by hostboot, one for each range of memory 93 * that has a different "affinity". In practice, it means one range 94 * per chip. 95 */ 96 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 97 { 98 char *mem_name; 99 uint64_t mem_reg_property[2]; 100 int off; 101 102 mem_reg_property[0] = cpu_to_be64(start); 103 mem_reg_property[1] = cpu_to_be64(size); 104 105 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 106 off = fdt_add_subnode(fdt, 0, mem_name); 107 g_free(mem_name); 108 109 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 110 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 111 sizeof(mem_reg_property)))); 112 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 113 } 114 115 static int get_cpus_node(void *fdt) 116 { 117 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 118 119 if (cpus_offset < 0) { 120 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 121 if (cpus_offset) { 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 123 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 124 } 125 } 126 _FDT(cpus_offset); 127 return cpus_offset; 128 } 129 130 /* 131 * The PowerNV cores (and threads) need to use real HW ids and not an 132 * incremental index like it has been done on other platforms. This HW 133 * id is stored in the CPU PIR, it is used to create cpu nodes in the 134 * device tree, used in XSCOM to address cores and in interrupt 135 * servers. 136 */ 137 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 138 { 139 PowerPCCPU *cpu = pc->threads[0]; 140 CPUState *cs = CPU(cpu); 141 DeviceClass *dc = DEVICE_GET_CLASS(cs); 142 int smt_threads = CPU_CORE(pc)->nr_threads; 143 CPUPPCState *env = &cpu->env; 144 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 145 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 146 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 147 int i; 148 uint32_t pir; 149 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 150 0xffffffff, 0xffffffff}; 151 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 152 uint32_t cpufreq = 1000000000; 153 uint32_t page_sizes_prop[64]; 154 size_t page_sizes_prop_size; 155 int offset; 156 char *nodename; 157 int cpus_offset = get_cpus_node(fdt); 158 159 pir = pnv_cc->chip_pir(chip, pc->hwid, 0); 160 161 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 162 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 163 _FDT(offset); 164 g_free(nodename); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 170 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 171 172 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 176 env->dcache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 178 env->icache_line_size))); 179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 180 env->icache_line_size))); 181 182 if (pcc->l1_dcache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 184 pcc->l1_dcache_size))); 185 } else { 186 warn_report("Unknown L1 dcache size for cpu"); 187 } 188 if (pcc->l1_icache_size) { 189 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 190 pcc->l1_icache_size))); 191 } else { 192 warn_report("Unknown L1 icache size for cpu"); 193 } 194 195 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 196 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 198 cpu->hash64_opts->slb_size))); 199 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 200 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 201 202 if (ppc_has_spr(cpu, SPR_PURR)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 204 } 205 206 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 207 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 208 segs, sizeof(segs)))); 209 } 210 211 /* 212 * Advertise VMX/VSX (vector extensions) if available 213 * 0 / no property == no vector extensions 214 * 1 == VMX / Altivec available 215 * 2 == VSX available 216 */ 217 if (env->insns_flags & PPC_ALTIVEC) { 218 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 219 220 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 221 } 222 223 /* 224 * Advertise DFP (Decimal Floating Point) if available 225 * 0 / no property == no DFP 226 * 1 == DFP available 227 */ 228 if (env->insns_flags2 & PPC2_DFP) { 229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 230 } 231 232 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 233 sizeof(page_sizes_prop)); 234 if (page_sizes_prop_size) { 235 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 236 page_sizes_prop, page_sizes_prop_size))); 237 } 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i)); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(*servers_prop) * smt_threads))); 245 246 return offset; 247 } 248 249 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 250 uint32_t nr_threads) 251 { 252 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 253 uint32_t pir = pcc->chip_pir(chip, hwid, 0); 254 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 255 char *name; 256 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 257 uint32_t irange[2], i, rsize; 258 uint64_t *reg; 259 int offset; 260 261 irange[0] = cpu_to_be32(pir); 262 irange[1] = cpu_to_be32(nr_threads); 263 264 rsize = sizeof(uint64_t) * 2 * nr_threads; 265 reg = g_malloc(rsize); 266 for (i = 0; i < nr_threads; i++) { 267 /* We know P8 PIR is linear with thread id */ 268 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 269 reg[i * 2 + 1] = cpu_to_be64(0x1000); 270 } 271 272 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 273 offset = fdt_add_subnode(fdt, 0, name); 274 _FDT(offset); 275 g_free(name); 276 277 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 278 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 279 _FDT((fdt_setprop_string(fdt, offset, "device_type", 280 "PowerPC-External-Interrupt-Presentation"))); 281 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 282 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 283 irange, sizeof(irange)))); 284 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 285 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 286 g_free(reg); 287 } 288 289 /* 290 * Adds a PnvPHB to the chip on P8. 291 * Implemented here, like for defaults PHBs 292 */ 293 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 294 { 295 Pnv8Chip *chip8 = PNV8_CHIP(chip); 296 297 phb->chip = chip; 298 299 chip8->phbs[chip8->num_phbs] = phb; 300 chip8->num_phbs++; 301 return chip; 302 } 303 304 /* 305 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 306 * HTM is always enabled because TCG does implement HTM, it's just a 307 * degenerate implementation. 308 */ 309 static const uint8_t pa_features_207[] = { 24, 0, 310 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 311 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 312 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 313 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 314 315 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 316 { 317 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 318 int i; 319 320 pnv_dt_xscom(chip, fdt, 0, 321 cpu_to_be64(PNV_XSCOM_BASE(chip)), 322 cpu_to_be64(PNV_XSCOM_SIZE), 323 compat, sizeof(compat)); 324 325 for (i = 0; i < chip->nr_cores; i++) { 326 PnvCore *pnv_core = chip->cores[i]; 327 int offset; 328 329 offset = pnv_dt_core(chip, pnv_core, fdt); 330 331 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 332 pa_features_207, sizeof(pa_features_207)))); 333 334 /* Interrupt Control Presenters (ICP). One per core. */ 335 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 336 } 337 338 if (chip->ram_size) { 339 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 340 } 341 } 342 343 /* 344 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 345 */ 346 static const uint8_t pa_features_300[] = { 66, 0, 347 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 348 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 349 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 350 /* 6: DS207 */ 351 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 352 /* 16: Vector */ 353 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 354 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 355 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 356 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 357 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 358 /* 32: LE atomic, 34: EBB + ext EBB */ 359 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 360 /* 40: Radix MMU */ 361 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 362 /* 42: PM, 44: PC RA, 46: SC vec'd */ 363 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 364 /* 48: SIMD, 50: QP BFP, 52: String */ 365 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 366 /* 54: DecFP, 56: DecI, 58: SHA */ 367 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 368 /* 60: NM atomic, 62: RNG */ 369 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 370 }; 371 372 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 373 { 374 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 375 int i; 376 377 pnv_dt_xscom(chip, fdt, 0, 378 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 379 cpu_to_be64(PNV9_XSCOM_SIZE), 380 compat, sizeof(compat)); 381 382 for (i = 0; i < chip->nr_cores; i++) { 383 PnvCore *pnv_core = chip->cores[i]; 384 int offset; 385 386 offset = pnv_dt_core(chip, pnv_core, fdt); 387 388 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 389 pa_features_300, sizeof(pa_features_300)))); 390 } 391 392 if (chip->ram_size) { 393 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 394 } 395 396 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 397 } 398 399 /* 400 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 401 * always disables copy/paste. 402 */ 403 static const uint8_t pa_features_31[] = { 74, 0, 404 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 405 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 406 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 407 /* 6: DS207 */ 408 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 409 /* 16: Vector */ 410 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 411 /* 18: Vec. Scalar, 20: Vec. XOR */ 412 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 413 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 414 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 415 /* 32: LE atomic, 34: EBB + ext EBB */ 416 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 417 /* 40: Radix MMU */ 418 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 419 /* 42: PM, 44: PC RA, 46: SC vec'd */ 420 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 421 /* 48: SIMD, 50: QP BFP, 52: String */ 422 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 423 /* 54: DecFP, 56: DecI, 58: SHA */ 424 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 425 /* 60: NM atomic, 62: RNG */ 426 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 427 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 428 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 429 /* 72: [P]HASHST/[P]HASHCHK */ 430 0x80, 0x00, /* 72 - 73 */ 431 }; 432 433 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 434 { 435 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 436 int i; 437 438 pnv_dt_xscom(chip, fdt, 0, 439 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 440 cpu_to_be64(PNV10_XSCOM_SIZE), 441 compat, sizeof(compat)); 442 443 for (i = 0; i < chip->nr_cores; i++) { 444 PnvCore *pnv_core = chip->cores[i]; 445 int offset; 446 447 offset = pnv_dt_core(chip, pnv_core, fdt); 448 449 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 450 pa_features_31, sizeof(pa_features_31)))); 451 } 452 453 if (chip->ram_size) { 454 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 455 } 456 457 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 458 } 459 460 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 461 { 462 uint32_t io_base = d->ioport_id; 463 uint32_t io_regs[] = { 464 cpu_to_be32(1), 465 cpu_to_be32(io_base), 466 cpu_to_be32(2) 467 }; 468 char *name; 469 int node; 470 471 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 472 node = fdt_add_subnode(fdt, lpc_off, name); 473 _FDT(node); 474 g_free(name); 475 476 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 477 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 478 } 479 480 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 481 { 482 const char compatible[] = "ns16550\0pnpPNP,501"; 483 uint32_t io_base = d->ioport_id; 484 uint32_t io_regs[] = { 485 cpu_to_be32(1), 486 cpu_to_be32(io_base), 487 cpu_to_be32(8) 488 }; 489 uint32_t irq; 490 char *name; 491 int node; 492 493 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 494 495 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 496 node = fdt_add_subnode(fdt, lpc_off, name); 497 _FDT(node); 498 g_free(name); 499 500 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 501 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 502 sizeof(compatible)))); 503 504 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 505 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 506 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 507 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 508 fdt_get_phandle(fdt, lpc_off)))); 509 510 /* This is needed by Linux */ 511 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 512 } 513 514 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 515 { 516 const char compatible[] = "bt\0ipmi-bt"; 517 uint32_t io_base; 518 uint32_t io_regs[] = { 519 cpu_to_be32(1), 520 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 521 cpu_to_be32(3) 522 }; 523 uint32_t irq; 524 char *name; 525 int node; 526 527 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 528 io_regs[1] = cpu_to_be32(io_base); 529 530 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 531 532 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 533 node = fdt_add_subnode(fdt, lpc_off, name); 534 _FDT(node); 535 g_free(name); 536 537 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 538 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 539 sizeof(compatible)))); 540 541 /* Mark it as reserved to avoid Linux trying to claim it */ 542 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 543 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 544 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 545 fdt_get_phandle(fdt, lpc_off)))); 546 } 547 548 typedef struct ForeachPopulateArgs { 549 void *fdt; 550 int offset; 551 } ForeachPopulateArgs; 552 553 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 554 { 555 ForeachPopulateArgs *args = opaque; 556 ISADevice *d = ISA_DEVICE(dev); 557 558 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 559 pnv_dt_rtc(d, args->fdt, args->offset); 560 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 561 pnv_dt_serial(d, args->fdt, args->offset); 562 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 563 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 564 } else { 565 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 566 d->ioport_id); 567 } 568 569 return 0; 570 } 571 572 /* 573 * The default LPC bus of a multichip system is on chip 0. It's 574 * recognized by the firmware (skiboot) using a "primary" property. 575 */ 576 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 577 { 578 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 579 ForeachPopulateArgs args = { 580 .fdt = fdt, 581 .offset = isa_offset, 582 }; 583 uint32_t phandle; 584 585 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 586 587 phandle = qemu_fdt_alloc_phandle(fdt); 588 assert(phandle > 0); 589 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 590 591 /* 592 * ISA devices are not necessarily parented to the ISA bus so we 593 * can not use object_child_foreach() 594 */ 595 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 596 &args); 597 } 598 599 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 600 { 601 int off; 602 603 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 604 off = fdt_add_subnode(fdt, off, "power-mgt"); 605 606 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 607 } 608 609 static void *pnv_dt_create(MachineState *machine) 610 { 611 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 612 PnvMachineState *pnv = PNV_MACHINE(machine); 613 void *fdt; 614 char *buf; 615 int off; 616 int i; 617 618 fdt = g_malloc0(FDT_MAX_SIZE); 619 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 620 621 /* /qemu node */ 622 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 623 624 /* Root node */ 625 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 626 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 627 _FDT((fdt_setprop_string(fdt, 0, "model", 628 "IBM PowerNV (emulated by qemu)"))); 629 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 630 631 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 632 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 633 if (qemu_uuid_set) { 634 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 635 } 636 g_free(buf); 637 638 off = fdt_add_subnode(fdt, 0, "chosen"); 639 if (machine->kernel_cmdline) { 640 _FDT((fdt_setprop_string(fdt, off, "bootargs", 641 machine->kernel_cmdline))); 642 } 643 644 if (pnv->initrd_size) { 645 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 646 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 647 648 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 649 &start_prop, sizeof(start_prop)))); 650 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 651 &end_prop, sizeof(end_prop)))); 652 } 653 654 /* Populate device tree for each chip */ 655 for (i = 0; i < pnv->num_chips; i++) { 656 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 657 } 658 659 /* Populate ISA devices on chip 0 */ 660 pnv_dt_isa(pnv, fdt); 661 662 if (pnv->bmc) { 663 pnv_dt_bmc_sensors(pnv->bmc, fdt); 664 } 665 666 /* Create an extra node for power management on machines that support it */ 667 if (pmc->dt_power_mgt) { 668 pmc->dt_power_mgt(pnv, fdt); 669 } 670 671 return fdt; 672 } 673 674 static void pnv_powerdown_notify(Notifier *n, void *opaque) 675 { 676 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 677 678 if (pnv->bmc) { 679 pnv_bmc_powerdown(pnv->bmc); 680 } 681 } 682 683 static void pnv_reset(MachineState *machine, ShutdownCause reason) 684 { 685 PnvMachineState *pnv = PNV_MACHINE(machine); 686 IPMIBmc *bmc; 687 void *fdt; 688 689 qemu_devices_reset(reason); 690 691 /* 692 * The machine should provide by default an internal BMC simulator. 693 * If not, try to use the BMC device that was provided on the command 694 * line. 695 */ 696 bmc = pnv_bmc_find(&error_fatal); 697 if (!pnv->bmc) { 698 if (!bmc) { 699 if (!qtest_enabled()) { 700 warn_report("machine has no BMC device. Use '-device " 701 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 702 "to define one"); 703 } 704 } else { 705 pnv_bmc_set_pnor(bmc, pnv->pnor); 706 pnv->bmc = bmc; 707 } 708 } 709 710 fdt = pnv_dt_create(machine); 711 712 /* Pack resulting tree */ 713 _FDT((fdt_pack(fdt))); 714 715 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 716 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 717 718 /* 719 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 720 * the existing machine->fdt to avoid leaking it during 721 * a reset. 722 */ 723 g_free(machine->fdt); 724 machine->fdt = fdt; 725 } 726 727 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 728 { 729 Pnv8Chip *chip8 = PNV8_CHIP(chip); 730 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 731 732 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 733 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 734 } 735 736 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 737 { 738 Pnv8Chip *chip8 = PNV8_CHIP(chip); 739 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 740 741 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 742 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 743 } 744 745 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 746 { 747 Pnv9Chip *chip9 = PNV9_CHIP(chip); 748 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 749 750 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 751 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 752 } 753 754 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 755 { 756 Pnv10Chip *chip10 = PNV10_CHIP(chip); 757 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 758 759 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 760 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 761 } 762 763 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 764 { 765 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 766 } 767 768 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 769 { 770 Pnv8Chip *chip8 = PNV8_CHIP(chip); 771 int i; 772 773 g_autoptr(GString) buf = g_string_new(""); 774 g_autoptr(HumanReadableText) info = NULL; 775 776 ics_pic_print_info(&chip8->psi.ics, buf); 777 778 for (i = 0; i < chip8->num_phbs; i++) { 779 PnvPHB *phb = chip8->phbs[i]; 780 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 781 782 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 783 ics_pic_print_info(&phb3->lsis, buf); 784 } 785 786 info = human_readable_text_from_str(buf); 787 monitor_puts(mon, info->human_readable_text); 788 } 789 790 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 791 { 792 Monitor *mon = opaque; 793 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 794 g_autoptr(GString) buf = g_string_new(""); 795 g_autoptr(HumanReadableText) info = NULL; 796 797 if (!phb) { 798 return 0; 799 } 800 801 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 802 info = human_readable_text_from_str(buf); 803 monitor_puts(mon, info->human_readable_text); 804 805 return 0; 806 } 807 808 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 809 { 810 Pnv9Chip *chip9 = PNV9_CHIP(chip); 811 g_autoptr(GString) buf = g_string_new(""); 812 g_autoptr(HumanReadableText) info = NULL; 813 814 pnv_xive_pic_print_info(&chip9->xive, buf); 815 816 info = human_readable_text_from_str(buf); 817 monitor_puts(mon, info->human_readable_text); 818 819 pnv_psi_pic_print_info(&chip9->psi, mon); 820 821 object_child_foreach_recursive(OBJECT(chip), 822 pnv_chip_power9_pic_print_info_child, mon); 823 } 824 825 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 826 uint32_t core_id) 827 { 828 return PNV_XSCOM_EX_BASE(core_id); 829 } 830 831 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 832 uint32_t core_id) 833 { 834 return PNV9_XSCOM_EC_BASE(core_id); 835 } 836 837 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 838 uint32_t core_id) 839 { 840 return PNV10_XSCOM_EC_BASE(core_id); 841 } 842 843 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 844 { 845 PowerPCCPUClass *ppc_default = 846 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 847 PowerPCCPUClass *ppc = 848 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 849 850 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 851 } 852 853 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 854 { 855 ISADevice *dev = isa_new("isa-ipmi-bt"); 856 857 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 858 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 859 isa_realize_and_unref(dev, bus, &error_fatal); 860 } 861 862 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 863 { 864 Pnv10Chip *chip10 = PNV10_CHIP(chip); 865 866 pnv_xive2_pic_print_info(&chip10->xive, mon); 867 pnv_psi_pic_print_info(&chip10->psi, mon); 868 869 object_child_foreach_recursive(OBJECT(chip), 870 pnv_chip_power9_pic_print_info_child, mon); 871 } 872 873 /* Always give the first 1GB to chip 0 else we won't boot */ 874 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 875 { 876 MachineState *machine = MACHINE(pnv); 877 uint64_t ram_per_chip; 878 879 assert(machine->ram_size >= 1 * GiB); 880 881 ram_per_chip = machine->ram_size / pnv->num_chips; 882 if (ram_per_chip >= 1 * GiB) { 883 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 884 } 885 886 assert(pnv->num_chips > 1); 887 888 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 889 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 890 } 891 892 static void pnv_init(MachineState *machine) 893 { 894 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 895 PnvMachineState *pnv = PNV_MACHINE(machine); 896 MachineClass *mc = MACHINE_GET_CLASS(machine); 897 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 898 char *fw_filename; 899 long fw_size; 900 uint64_t chip_ram_start = 0; 901 int i; 902 char *chip_typename; 903 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 904 DeviceState *dev; 905 906 if (kvm_enabled()) { 907 error_report("machine %s does not support the KVM accelerator", 908 mc->name); 909 exit(EXIT_FAILURE); 910 } 911 912 /* allocate RAM */ 913 if (machine->ram_size < mc->default_ram_size) { 914 char *sz = size_to_str(mc->default_ram_size); 915 error_report("Invalid RAM size, should be bigger than %s", sz); 916 g_free(sz); 917 exit(EXIT_FAILURE); 918 } 919 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 920 921 /* 922 * Create our simple PNOR device 923 */ 924 dev = qdev_new(TYPE_PNV_PNOR); 925 if (pnor) { 926 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 927 } 928 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 929 pnv->pnor = PNV_PNOR(dev); 930 931 /* load skiboot firmware */ 932 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 933 if (!fw_filename) { 934 error_report("Could not find OPAL firmware '%s'", bios_name); 935 exit(1); 936 } 937 938 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 939 if (fw_size < 0) { 940 error_report("Could not load OPAL firmware '%s'", fw_filename); 941 exit(1); 942 } 943 g_free(fw_filename); 944 945 /* load kernel */ 946 if (machine->kernel_filename) { 947 long kernel_size; 948 949 kernel_size = load_image_targphys(machine->kernel_filename, 950 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 951 if (kernel_size < 0) { 952 error_report("Could not load kernel '%s'", 953 machine->kernel_filename); 954 exit(1); 955 } 956 } 957 958 /* load initrd */ 959 if (machine->initrd_filename) { 960 pnv->initrd_base = INITRD_LOAD_ADDR; 961 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 962 pnv->initrd_base, INITRD_MAX_SIZE); 963 if (pnv->initrd_size < 0) { 964 error_report("Could not load initial ram disk '%s'", 965 machine->initrd_filename); 966 exit(1); 967 } 968 } 969 970 /* MSIs are supported on this platform */ 971 msi_nonbroken = true; 972 973 /* 974 * Check compatibility of the specified CPU with the machine 975 * default. 976 */ 977 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 978 error_report("invalid CPU model '%s' for %s machine", 979 machine->cpu_type, mc->name); 980 exit(1); 981 } 982 983 /* Create the processor chips */ 984 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 985 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 986 i, machine->cpu_type); 987 if (!object_class_by_name(chip_typename)) { 988 error_report("invalid chip model '%.*s' for %s machine", 989 i, machine->cpu_type, mc->name); 990 exit(1); 991 } 992 993 pnv->num_chips = 994 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 995 996 if (machine->smp.threads > 8) { 997 error_report("Cannot support more than 8 threads/core " 998 "on a powernv machine"); 999 exit(1); 1000 } 1001 if (!is_power_of_2(machine->smp.threads)) { 1002 error_report("Cannot support %d threads/core on a powernv" 1003 "machine because it must be a power of 2", 1004 machine->smp.threads); 1005 exit(1); 1006 } 1007 /* 1008 * TODO: should we decide on how many chips we can create based 1009 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1010 */ 1011 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1012 error_report("invalid number of chips: '%d'", pnv->num_chips); 1013 error_printf( 1014 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1015 exit(1); 1016 } 1017 1018 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1019 for (i = 0; i < pnv->num_chips; i++) { 1020 char chip_name[32]; 1021 Object *chip = OBJECT(qdev_new(chip_typename)); 1022 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1023 1024 pnv->chips[i] = PNV_CHIP(chip); 1025 1026 /* Distribute RAM among the chips */ 1027 object_property_set_int(chip, "ram-start", chip_ram_start, 1028 &error_fatal); 1029 object_property_set_int(chip, "ram-size", chip_ram_size, 1030 &error_fatal); 1031 chip_ram_start += chip_ram_size; 1032 1033 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1034 object_property_add_child(OBJECT(pnv), chip_name, chip); 1035 object_property_set_int(chip, "chip-id", i, &error_fatal); 1036 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1037 &error_fatal); 1038 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1039 &error_fatal); 1040 /* 1041 * The POWER8 machine use the XICS interrupt interface. 1042 * Propagate the XICS fabric to the chip and its controllers. 1043 */ 1044 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1045 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1046 } 1047 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1048 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1049 &error_abort); 1050 } 1051 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1052 } 1053 g_free(chip_typename); 1054 1055 /* Instantiate ISA bus on chip 0 */ 1056 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1057 1058 /* Create serial port */ 1059 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1060 1061 /* Create an RTC ISA device too */ 1062 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1063 1064 /* 1065 * Create the machine BMC simulator and the IPMI BT device for 1066 * communication with the BMC 1067 */ 1068 if (defaults_enabled()) { 1069 pnv->bmc = pnv_bmc_create(pnv->pnor); 1070 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1071 } 1072 1073 /* 1074 * The PNOR is mapped on the LPC FW address space by the BMC. 1075 * Since we can not reach the remote BMC machine with LPC memops, 1076 * map it always for now. 1077 */ 1078 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1079 &pnv->pnor->mmio); 1080 1081 /* 1082 * OpenPOWER systems use a IPMI SEL Event message to notify the 1083 * host to powerdown 1084 */ 1085 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1086 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1087 1088 /* 1089 * Create/Connect any machine-specific I2C devices 1090 */ 1091 if (pmc->i2c_init) { 1092 pmc->i2c_init(pnv); 1093 } 1094 } 1095 1096 /* 1097 * 0:21 Reserved - Read as zeros 1098 * 22:24 Chip ID 1099 * 25:28 Core number 1100 * 29:31 Thread ID 1101 */ 1102 static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id, 1103 uint32_t thread_id) 1104 { 1105 return (chip->chip_id << 7) | (core_id << 3) | thread_id; 1106 } 1107 1108 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1109 Error **errp) 1110 { 1111 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1112 Error *local_err = NULL; 1113 Object *obj; 1114 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1115 1116 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1117 if (local_err) { 1118 error_propagate(errp, local_err); 1119 return; 1120 } 1121 1122 pnv_cpu->intc = obj; 1123 } 1124 1125 1126 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1127 { 1128 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1129 1130 icp_reset(ICP(pnv_cpu->intc)); 1131 } 1132 1133 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1134 { 1135 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1136 1137 icp_destroy(ICP(pnv_cpu->intc)); 1138 pnv_cpu->intc = NULL; 1139 } 1140 1141 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1142 GString *buf) 1143 { 1144 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1145 } 1146 1147 /* 1148 * 0:48 Reserved - Read as zeroes 1149 * 49:52 Node ID 1150 * 53:55 Chip ID 1151 * 56 Reserved - Read as zero 1152 * 57:61 Core number 1153 * 62:63 Thread ID 1154 * 1155 * We only care about the lower bits. uint32_t is fine for the moment. 1156 */ 1157 static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id, 1158 uint32_t thread_id) 1159 { 1160 if (chip->nr_threads == 8) { 1161 return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) | 1162 (thread_id >> 1); 1163 } else { 1164 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1165 } 1166 } 1167 1168 /* 1169 * 0:48 Reserved - Read as zeroes 1170 * 49:52 Node ID 1171 * 53:55 Chip ID 1172 * 56 Reserved - Read as zero 1173 * 57:59 Quad ID 1174 * 60 Core Chiplet Pair ID 1175 * 61:63 Thread/Core Chiplet ID t0-t2 1176 * 1177 * We only care about the lower bits. uint32_t is fine for the moment. 1178 */ 1179 static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id, 1180 uint32_t thread_id) 1181 { 1182 if (chip->nr_threads == 8) { 1183 return (chip->chip_id << 8) | ((core_id / 4) << 4) | 1184 ((core_id % 2) << 3) | thread_id; 1185 } else { 1186 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1187 } 1188 } 1189 1190 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1191 Error **errp) 1192 { 1193 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1194 Error *local_err = NULL; 1195 Object *obj; 1196 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1197 1198 /* 1199 * The core creates its interrupt presenter but the XIVE interrupt 1200 * controller object is initialized afterwards. Hopefully, it's 1201 * only used at runtime. 1202 */ 1203 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1204 &local_err); 1205 if (local_err) { 1206 error_propagate(errp, local_err); 1207 return; 1208 } 1209 1210 pnv_cpu->intc = obj; 1211 } 1212 1213 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1214 { 1215 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1216 1217 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1218 } 1219 1220 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1221 { 1222 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1223 1224 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1225 pnv_cpu->intc = NULL; 1226 } 1227 1228 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1229 GString *buf) 1230 { 1231 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1232 } 1233 1234 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1235 Error **errp) 1236 { 1237 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1238 Error *local_err = NULL; 1239 Object *obj; 1240 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1241 1242 /* 1243 * The core creates its interrupt presenter but the XIVE2 interrupt 1244 * controller object is initialized afterwards. Hopefully, it's 1245 * only used at runtime. 1246 */ 1247 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1248 &local_err); 1249 if (local_err) { 1250 error_propagate(errp, local_err); 1251 return; 1252 } 1253 1254 pnv_cpu->intc = obj; 1255 } 1256 1257 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1258 { 1259 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1260 1261 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1262 } 1263 1264 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1265 { 1266 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1267 1268 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1269 pnv_cpu->intc = NULL; 1270 } 1271 1272 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1273 GString *buf) 1274 { 1275 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1276 } 1277 1278 /* 1279 * Allowed core identifiers on a POWER8 Processor Chip : 1280 * 1281 * <EX0 reserved> 1282 * EX1 - Venice only 1283 * EX2 - Venice only 1284 * EX3 - Venice only 1285 * EX4 1286 * EX5 1287 * EX6 1288 * <EX7,8 reserved> <reserved> 1289 * EX9 - Venice only 1290 * EX10 - Venice only 1291 * EX11 - Venice only 1292 * EX12 1293 * EX13 1294 * EX14 1295 * <EX15 reserved> 1296 */ 1297 #define POWER8E_CORE_MASK (0x7070ull) 1298 #define POWER8_CORE_MASK (0x7e7eull) 1299 1300 /* 1301 * POWER9 has 24 cores, ids starting at 0x0 1302 */ 1303 #define POWER9_CORE_MASK (0xffffffffffffffull) 1304 1305 1306 #define POWER10_CORE_MASK (0xffffffffffffffull) 1307 1308 static void pnv_chip_power8_instance_init(Object *obj) 1309 { 1310 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1311 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1312 int i; 1313 1314 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1315 (Object **)&chip8->xics, 1316 object_property_allow_set_link, 1317 OBJ_PROP_LINK_STRONG); 1318 1319 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1320 1321 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1322 1323 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1324 1325 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1326 1327 if (defaults_enabled()) { 1328 chip8->num_phbs = pcc->num_phbs; 1329 1330 for (i = 0; i < chip8->num_phbs; i++) { 1331 Object *phb = object_new(TYPE_PNV_PHB); 1332 1333 /* 1334 * We need the chip to parent the PHB to allow the DT 1335 * to build correctly (via pnv_xscom_dt()). 1336 * 1337 * TODO: the PHB should be parented by a PEC device that, at 1338 * this moment, is not modelled powernv8/phb3. 1339 */ 1340 object_property_add_child(obj, "phb[*]", phb); 1341 chip8->phbs[i] = PNV_PHB(phb); 1342 } 1343 } 1344 1345 } 1346 1347 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1348 { 1349 PnvChip *chip = PNV_CHIP(chip8); 1350 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1351 int i, j; 1352 char *name; 1353 1354 name = g_strdup_printf("icp-%x", chip->chip_id); 1355 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1356 g_free(name); 1357 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1358 &chip8->icp_mmio); 1359 1360 /* Map the ICP registers for each thread */ 1361 for (i = 0; i < chip->nr_cores; i++) { 1362 PnvCore *pnv_core = chip->cores[i]; 1363 int core_hwid = CPU_CORE(pnv_core)->core_id; 1364 1365 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1366 uint32_t pir = pcc->chip_pir(chip, core_hwid, j); 1367 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1368 1369 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1370 &icp->mmio); 1371 } 1372 } 1373 } 1374 1375 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1376 { 1377 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1378 PnvChip *chip = PNV_CHIP(dev); 1379 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1380 Pnv8Psi *psi8 = &chip8->psi; 1381 Error *local_err = NULL; 1382 int i; 1383 1384 assert(chip8->xics); 1385 1386 /* XSCOM bridge is first */ 1387 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1388 1389 pcc->parent_realize(dev, &local_err); 1390 if (local_err) { 1391 error_propagate(errp, local_err); 1392 return; 1393 } 1394 1395 /* Processor Service Interface (PSI) Host Bridge */ 1396 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1397 &error_fatal); 1398 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1399 OBJECT(chip8->xics), &error_abort); 1400 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1401 return; 1402 } 1403 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1404 &PNV_PSI(psi8)->xscom_regs); 1405 1406 /* Create LPC controller */ 1407 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1408 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1409 1410 chip->fw_mr = &chip8->lpc.isa_fw; 1411 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1412 (uint64_t) PNV_XSCOM_BASE(chip), 1413 PNV_XSCOM_LPC_BASE); 1414 1415 /* 1416 * Interrupt Management Area. This is the memory region holding 1417 * all the Interrupt Control Presenter (ICP) registers 1418 */ 1419 pnv_chip_icp_realize(chip8, &local_err); 1420 if (local_err) { 1421 error_propagate(errp, local_err); 1422 return; 1423 } 1424 1425 /* Create the simplified OCC model */ 1426 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1427 return; 1428 } 1429 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1430 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1431 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1432 1433 /* OCC SRAM model */ 1434 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1435 &chip8->occ.sram_regs); 1436 1437 /* HOMER */ 1438 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1439 &error_abort); 1440 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1441 return; 1442 } 1443 /* Homer Xscom region */ 1444 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1445 1446 /* Homer mmio region */ 1447 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1448 &chip8->homer.regs); 1449 1450 /* PHB controllers */ 1451 for (i = 0; i < chip8->num_phbs; i++) { 1452 PnvPHB *phb = chip8->phbs[i]; 1453 1454 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1455 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1456 &error_fatal); 1457 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1458 &error_fatal); 1459 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1460 return; 1461 } 1462 } 1463 } 1464 1465 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1466 { 1467 addr &= (PNV_XSCOM_SIZE - 1); 1468 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1469 } 1470 1471 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1472 { 1473 DeviceClass *dc = DEVICE_CLASS(klass); 1474 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1475 1476 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1477 k->cores_mask = POWER8E_CORE_MASK; 1478 k->num_phbs = 3; 1479 k->chip_pir = pnv_chip_pir_p8; 1480 k->intc_create = pnv_chip_power8_intc_create; 1481 k->intc_reset = pnv_chip_power8_intc_reset; 1482 k->intc_destroy = pnv_chip_power8_intc_destroy; 1483 k->intc_print_info = pnv_chip_power8_intc_print_info; 1484 k->isa_create = pnv_chip_power8_isa_create; 1485 k->dt_populate = pnv_chip_power8_dt_populate; 1486 k->pic_print_info = pnv_chip_power8_pic_print_info; 1487 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1488 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1489 dc->desc = "PowerNV Chip POWER8E"; 1490 1491 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1492 &k->parent_realize); 1493 } 1494 1495 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1496 { 1497 DeviceClass *dc = DEVICE_CLASS(klass); 1498 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1499 1500 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1501 k->cores_mask = POWER8_CORE_MASK; 1502 k->num_phbs = 3; 1503 k->chip_pir = pnv_chip_pir_p8; 1504 k->intc_create = pnv_chip_power8_intc_create; 1505 k->intc_reset = pnv_chip_power8_intc_reset; 1506 k->intc_destroy = pnv_chip_power8_intc_destroy; 1507 k->intc_print_info = pnv_chip_power8_intc_print_info; 1508 k->isa_create = pnv_chip_power8_isa_create; 1509 k->dt_populate = pnv_chip_power8_dt_populate; 1510 k->pic_print_info = pnv_chip_power8_pic_print_info; 1511 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1512 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1513 dc->desc = "PowerNV Chip POWER8"; 1514 1515 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1516 &k->parent_realize); 1517 } 1518 1519 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1520 { 1521 DeviceClass *dc = DEVICE_CLASS(klass); 1522 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1523 1524 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1525 k->cores_mask = POWER8_CORE_MASK; 1526 k->num_phbs = 4; 1527 k->chip_pir = pnv_chip_pir_p8; 1528 k->intc_create = pnv_chip_power8_intc_create; 1529 k->intc_reset = pnv_chip_power8_intc_reset; 1530 k->intc_destroy = pnv_chip_power8_intc_destroy; 1531 k->intc_print_info = pnv_chip_power8_intc_print_info; 1532 k->isa_create = pnv_chip_power8nvl_isa_create; 1533 k->dt_populate = pnv_chip_power8_dt_populate; 1534 k->pic_print_info = pnv_chip_power8_pic_print_info; 1535 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1536 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1537 dc->desc = "PowerNV Chip POWER8NVL"; 1538 1539 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1540 &k->parent_realize); 1541 } 1542 1543 static void pnv_chip_power9_instance_init(Object *obj) 1544 { 1545 PnvChip *chip = PNV_CHIP(obj); 1546 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1547 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1548 int i; 1549 1550 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1551 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1552 "xive-fabric"); 1553 1554 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1555 1556 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1557 1558 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1559 1560 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1561 1562 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1563 1564 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1565 1566 /* Number of PECs is the chip default */ 1567 chip->num_pecs = pcc->num_pecs; 1568 1569 for (i = 0; i < chip->num_pecs; i++) { 1570 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1571 TYPE_PNV_PHB4_PEC); 1572 } 1573 1574 for (i = 0; i < pcc->i2c_num_engines; i++) { 1575 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1576 } 1577 } 1578 1579 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1580 PnvCore *pnv_core, 1581 const char *type) 1582 { 1583 char eq_name[32]; 1584 int core_id = CPU_CORE(pnv_core)->core_id; 1585 1586 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1587 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1588 sizeof(*eq), type, 1589 &error_fatal, NULL); 1590 1591 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1592 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1593 } 1594 1595 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1596 { 1597 PnvChip *chip = PNV_CHIP(chip9); 1598 int i; 1599 1600 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1601 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1602 1603 for (i = 0; i < chip9->nr_quads; i++) { 1604 PnvQuad *eq = &chip9->quads[i]; 1605 1606 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1607 PNV_QUAD_TYPE_NAME("power9")); 1608 1609 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1610 &eq->xscom_regs); 1611 } 1612 } 1613 1614 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1615 { 1616 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1617 int i; 1618 1619 for (i = 0; i < chip->num_pecs; i++) { 1620 PnvPhb4PecState *pec = &chip9->pecs[i]; 1621 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1622 uint32_t pec_nest_base; 1623 uint32_t pec_pci_base; 1624 1625 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1626 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1627 &error_fatal); 1628 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1629 &error_fatal); 1630 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1631 return; 1632 } 1633 1634 pec_nest_base = pecc->xscom_nest_base(pec); 1635 pec_pci_base = pecc->xscom_pci_base(pec); 1636 1637 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1638 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1639 } 1640 } 1641 1642 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1643 { 1644 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1645 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1646 PnvChip *chip = PNV_CHIP(dev); 1647 Pnv9Psi *psi9 = &chip9->psi; 1648 Error *local_err = NULL; 1649 int i; 1650 1651 /* XSCOM bridge is first */ 1652 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1653 1654 pcc->parent_realize(dev, &local_err); 1655 if (local_err) { 1656 error_propagate(errp, local_err); 1657 return; 1658 } 1659 1660 pnv_chip_quad_realize(chip9, &local_err); 1661 if (local_err) { 1662 error_propagate(errp, local_err); 1663 return; 1664 } 1665 1666 /* XIVE interrupt controller (POWER9) */ 1667 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1668 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1669 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1670 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1671 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1672 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1673 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1674 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1675 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1676 &error_abort); 1677 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1678 return; 1679 } 1680 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1681 &chip9->xive.xscom_regs); 1682 1683 /* Processor Service Interface (PSI) Host Bridge */ 1684 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1685 &error_fatal); 1686 /* This is the only device with 4k ESB pages */ 1687 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1688 &error_fatal); 1689 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1690 return; 1691 } 1692 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1693 &PNV_PSI(psi9)->xscom_regs); 1694 1695 /* LPC */ 1696 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1697 return; 1698 } 1699 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1700 &chip9->lpc.xscom_regs); 1701 1702 chip->fw_mr = &chip9->lpc.isa_fw; 1703 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1704 (uint64_t) PNV9_LPCM_BASE(chip)); 1705 1706 /* ChipTOD */ 1707 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1708 chip->chip_id == 0, &error_abort); 1709 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1710 chip->chip_id == 1, &error_abort); 1711 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1712 &error_abort); 1713 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1714 return; 1715 } 1716 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1717 &chip9->chiptod.xscom_regs); 1718 1719 /* Create the simplified OCC model */ 1720 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1721 return; 1722 } 1723 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1724 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1725 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1726 1727 /* OCC SRAM model */ 1728 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1729 &chip9->occ.sram_regs); 1730 1731 /* SBE */ 1732 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1733 return; 1734 } 1735 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1736 &chip9->sbe.xscom_ctrl_regs); 1737 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1738 &chip9->sbe.xscom_mbox_regs); 1739 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1740 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1741 1742 /* HOMER */ 1743 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1744 &error_abort); 1745 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1746 return; 1747 } 1748 /* Homer Xscom region */ 1749 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1750 1751 /* Homer mmio region */ 1752 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1753 &chip9->homer.regs); 1754 1755 /* PEC PHBs */ 1756 pnv_chip_power9_pec_realize(chip, &local_err); 1757 if (local_err) { 1758 error_propagate(errp, local_err); 1759 return; 1760 } 1761 1762 /* 1763 * I2C 1764 */ 1765 for (i = 0; i < pcc->i2c_num_engines; i++) { 1766 Object *obj = OBJECT(&chip9->i2c[i]); 1767 1768 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1769 object_property_set_int(obj, "num-busses", 1770 pcc->i2c_ports_per_engine[i], 1771 &error_fatal); 1772 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1773 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1774 return; 1775 } 1776 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1777 (chip9->i2c[i].engine - 1) * 1778 PNV9_XSCOM_I2CM_SIZE, 1779 &chip9->i2c[i].xscom_regs); 1780 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1781 qdev_get_gpio_in(DEVICE(psi9), 1782 PSIHB9_IRQ_SBE_I2C)); 1783 } 1784 } 1785 1786 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1787 { 1788 addr &= (PNV9_XSCOM_SIZE - 1); 1789 return addr >> 3; 1790 } 1791 1792 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1793 { 1794 DeviceClass *dc = DEVICE_CLASS(klass); 1795 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1796 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1797 1798 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1799 k->cores_mask = POWER9_CORE_MASK; 1800 k->chip_pir = pnv_chip_pir_p9; 1801 k->intc_create = pnv_chip_power9_intc_create; 1802 k->intc_reset = pnv_chip_power9_intc_reset; 1803 k->intc_destroy = pnv_chip_power9_intc_destroy; 1804 k->intc_print_info = pnv_chip_power9_intc_print_info; 1805 k->isa_create = pnv_chip_power9_isa_create; 1806 k->dt_populate = pnv_chip_power9_dt_populate; 1807 k->pic_print_info = pnv_chip_power9_pic_print_info; 1808 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1809 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1810 dc->desc = "PowerNV Chip POWER9"; 1811 k->num_pecs = PNV9_CHIP_MAX_PEC; 1812 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1813 k->i2c_ports_per_engine = i2c_ports_per_engine; 1814 1815 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1816 &k->parent_realize); 1817 } 1818 1819 static void pnv_chip_power10_instance_init(Object *obj) 1820 { 1821 PnvChip *chip = PNV_CHIP(obj); 1822 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1823 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1824 int i; 1825 1826 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1827 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1828 "xive-fabric"); 1829 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1830 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1831 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1832 TYPE_PNV10_CHIPTOD); 1833 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1834 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1835 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1836 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1837 TYPE_PNV_N1_CHIPLET); 1838 1839 chip->num_pecs = pcc->num_pecs; 1840 1841 for (i = 0; i < chip->num_pecs; i++) { 1842 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1843 TYPE_PNV_PHB5_PEC); 1844 } 1845 1846 for (i = 0; i < pcc->i2c_num_engines; i++) { 1847 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1848 } 1849 } 1850 1851 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1852 { 1853 PnvChip *chip = PNV_CHIP(chip10); 1854 int i; 1855 1856 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1857 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1858 1859 for (i = 0; i < chip10->nr_quads; i++) { 1860 PnvQuad *eq = &chip10->quads[i]; 1861 1862 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1863 PNV_QUAD_TYPE_NAME("power10")); 1864 1865 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1866 &eq->xscom_regs); 1867 1868 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1869 &eq->xscom_qme_regs); 1870 } 1871 } 1872 1873 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1874 { 1875 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1876 int i; 1877 1878 for (i = 0; i < chip->num_pecs; i++) { 1879 PnvPhb4PecState *pec = &chip10->pecs[i]; 1880 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1881 uint32_t pec_nest_base; 1882 uint32_t pec_pci_base; 1883 1884 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1885 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1886 &error_fatal); 1887 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1888 &error_fatal); 1889 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1890 return; 1891 } 1892 1893 pec_nest_base = pecc->xscom_nest_base(pec); 1894 pec_pci_base = pecc->xscom_pci_base(pec); 1895 1896 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1897 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1898 } 1899 } 1900 1901 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1902 { 1903 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1904 PnvChip *chip = PNV_CHIP(dev); 1905 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1906 Error *local_err = NULL; 1907 int i; 1908 1909 /* XSCOM bridge is first */ 1910 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 1911 1912 pcc->parent_realize(dev, &local_err); 1913 if (local_err) { 1914 error_propagate(errp, local_err); 1915 return; 1916 } 1917 1918 pnv_chip_power10_quad_realize(chip10, &local_err); 1919 if (local_err) { 1920 error_propagate(errp, local_err); 1921 return; 1922 } 1923 1924 /* XIVE2 interrupt controller (POWER10) */ 1925 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1926 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1927 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1928 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1929 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1930 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1931 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1932 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1933 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1934 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1935 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1936 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1937 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1938 &error_abort); 1939 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1940 return; 1941 } 1942 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1943 &chip10->xive.xscom_regs); 1944 1945 /* Processor Service Interface (PSI) Host Bridge */ 1946 object_property_set_int(OBJECT(&chip10->psi), "bar", 1947 PNV10_PSIHB_BASE(chip), &error_fatal); 1948 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1949 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1950 &error_fatal); 1951 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1952 return; 1953 } 1954 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1955 &PNV_PSI(&chip10->psi)->xscom_regs); 1956 1957 /* LPC */ 1958 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1959 return; 1960 } 1961 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1962 &chip10->lpc.xscom_regs); 1963 1964 chip->fw_mr = &chip10->lpc.isa_fw; 1965 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1966 (uint64_t) PNV10_LPCM_BASE(chip)); 1967 1968 /* ChipTOD */ 1969 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 1970 chip->chip_id == 0, &error_abort); 1971 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 1972 chip->chip_id == 1, &error_abort); 1973 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 1974 &error_abort); 1975 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 1976 return; 1977 } 1978 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 1979 &chip10->chiptod.xscom_regs); 1980 1981 /* Create the simplified OCC model */ 1982 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1983 return; 1984 } 1985 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1986 &chip10->occ.xscom_regs); 1987 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1988 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1989 1990 /* OCC SRAM model */ 1991 memory_region_add_subregion(get_system_memory(), 1992 PNV10_OCC_SENSOR_BASE(chip), 1993 &chip10->occ.sram_regs); 1994 1995 /* SBE */ 1996 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1997 return; 1998 } 1999 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2000 &chip10->sbe.xscom_ctrl_regs); 2001 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2002 &chip10->sbe.xscom_mbox_regs); 2003 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2004 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2005 2006 /* HOMER */ 2007 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2008 &error_abort); 2009 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2010 return; 2011 } 2012 /* Homer Xscom region */ 2013 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2014 &chip10->homer.pba_regs); 2015 2016 /* Homer mmio region */ 2017 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 2018 &chip10->homer.regs); 2019 2020 /* N1 chiplet */ 2021 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2022 return; 2023 } 2024 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2025 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2026 2027 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2028 &chip10->n1_chiplet.xscom_pb_eq_mr); 2029 2030 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2031 &chip10->n1_chiplet.xscom_pb_es_mr); 2032 2033 /* PHBs */ 2034 pnv_chip_power10_phb_realize(chip, &local_err); 2035 if (local_err) { 2036 error_propagate(errp, local_err); 2037 return; 2038 } 2039 2040 2041 /* 2042 * I2C 2043 */ 2044 for (i = 0; i < pcc->i2c_num_engines; i++) { 2045 Object *obj = OBJECT(&chip10->i2c[i]); 2046 2047 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2048 object_property_set_int(obj, "num-busses", 2049 pcc->i2c_ports_per_engine[i], 2050 &error_fatal); 2051 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2052 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2053 return; 2054 } 2055 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2056 (chip10->i2c[i].engine - 1) * 2057 PNV10_XSCOM_I2CM_SIZE, 2058 &chip10->i2c[i].xscom_regs); 2059 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2060 qdev_get_gpio_in(DEVICE(&chip10->psi), 2061 PSIHB9_IRQ_SBE_I2C)); 2062 } 2063 2064 } 2065 2066 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2067 { 2068 int i; 2069 for (i = 0; i < pnv->num_chips; i++) { 2070 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2071 2072 /* 2073 * Add a PCA9552 I2C device for PCIe hotplug control 2074 * to engine 2, bus 1, address 0x63 2075 */ 2076 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2077 "pca9552", 0x63); 2078 2079 /* 2080 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2081 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2082 * after hypervisor code sets a SLOTx_EN pin high. 2083 */ 2084 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2085 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2086 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2087 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2088 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2089 2090 /* 2091 * Add a PCA9554 I2C device for cable card presence detection 2092 * to engine 2, bus 1, address 0x25 2093 */ 2094 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2095 } 2096 } 2097 2098 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2099 { 2100 addr &= (PNV10_XSCOM_SIZE - 1); 2101 return addr >> 3; 2102 } 2103 2104 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2105 { 2106 DeviceClass *dc = DEVICE_CLASS(klass); 2107 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2108 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2109 2110 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 2111 k->cores_mask = POWER10_CORE_MASK; 2112 k->chip_pir = pnv_chip_pir_p10; 2113 k->intc_create = pnv_chip_power10_intc_create; 2114 k->intc_reset = pnv_chip_power10_intc_reset; 2115 k->intc_destroy = pnv_chip_power10_intc_destroy; 2116 k->intc_print_info = pnv_chip_power10_intc_print_info; 2117 k->isa_create = pnv_chip_power10_isa_create; 2118 k->dt_populate = pnv_chip_power10_dt_populate; 2119 k->pic_print_info = pnv_chip_power10_pic_print_info; 2120 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2121 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2122 dc->desc = "PowerNV Chip POWER10"; 2123 k->num_pecs = PNV10_CHIP_MAX_PEC; 2124 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2125 k->i2c_ports_per_engine = i2c_ports_per_engine; 2126 2127 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2128 &k->parent_realize); 2129 } 2130 2131 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 2132 { 2133 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2134 int cores_max; 2135 2136 /* 2137 * No custom mask for this chip, let's use the default one from * 2138 * the chip class 2139 */ 2140 if (!chip->cores_mask) { 2141 chip->cores_mask = pcc->cores_mask; 2142 } 2143 2144 /* filter alien core ids ! some are reserved */ 2145 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2146 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2147 chip->cores_mask); 2148 return; 2149 } 2150 chip->cores_mask &= pcc->cores_mask; 2151 2152 /* now that we have a sane layout, let check the number of cores */ 2153 cores_max = ctpop64(chip->cores_mask); 2154 if (chip->nr_cores > cores_max) { 2155 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2156 cores_max); 2157 return; 2158 } 2159 } 2160 2161 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2162 { 2163 Error *error = NULL; 2164 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2165 const char *typename = pnv_chip_core_typename(chip); 2166 int i, core_hwid; 2167 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2168 2169 if (!object_class_by_name(typename)) { 2170 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2171 return; 2172 } 2173 2174 /* Cores */ 2175 pnv_chip_core_sanitize(chip, &error); 2176 if (error) { 2177 error_propagate(errp, error); 2178 return; 2179 } 2180 2181 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2182 2183 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2184 && (i < chip->nr_cores); core_hwid++) { 2185 char core_name[32]; 2186 PnvCore *pnv_core; 2187 uint64_t xscom_core_base; 2188 2189 if (!(chip->cores_mask & (1ull << core_hwid))) { 2190 continue; 2191 } 2192 2193 pnv_core = PNV_CORE(object_new(typename)); 2194 2195 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2196 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2197 chip->cores[i] = pnv_core; 2198 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2199 chip->nr_threads, &error_fatal); 2200 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2201 core_hwid, &error_fatal); 2202 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2203 &error_fatal); 2204 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2205 &error_fatal); 2206 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2207 &error_abort); 2208 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2209 2210 /* Each core has an XSCOM MMIO region */ 2211 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2212 2213 pnv_xscom_add_subregion(chip, xscom_core_base, 2214 &pnv_core->xscom_regs); 2215 i++; 2216 } 2217 } 2218 2219 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2220 { 2221 PnvChip *chip = PNV_CHIP(dev); 2222 Error *error = NULL; 2223 2224 /* Cores */ 2225 pnv_chip_core_realize(chip, &error); 2226 if (error) { 2227 error_propagate(errp, error); 2228 return; 2229 } 2230 } 2231 2232 static Property pnv_chip_properties[] = { 2233 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2234 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2235 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2236 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2237 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2238 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2239 DEFINE_PROP_END_OF_LIST(), 2240 }; 2241 2242 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2243 { 2244 DeviceClass *dc = DEVICE_CLASS(klass); 2245 2246 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2247 dc->realize = pnv_chip_realize; 2248 device_class_set_props(dc, pnv_chip_properties); 2249 dc->desc = "PowerNV Chip"; 2250 } 2251 2252 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2253 { 2254 int i; 2255 2256 for (i = 0; i < chip->nr_cores; i++) { 2257 PnvCore *pc = chip->cores[i]; 2258 CPUCore *cc = CPU_CORE(pc); 2259 2260 if (cc->core_id == core_id) { 2261 return pc; 2262 } 2263 } 2264 return NULL; 2265 } 2266 2267 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2268 { 2269 int i, j; 2270 2271 for (i = 0; i < chip->nr_cores; i++) { 2272 PnvCore *pc = chip->cores[i]; 2273 CPUCore *cc = CPU_CORE(pc); 2274 2275 for (j = 0; j < cc->nr_threads; j++) { 2276 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2277 return pc->threads[j]; 2278 } 2279 } 2280 } 2281 return NULL; 2282 } 2283 2284 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2285 { 2286 PnvMachineState *pnv = PNV_MACHINE(xi); 2287 int i, j; 2288 2289 for (i = 0; i < pnv->num_chips; i++) { 2290 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2291 2292 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2293 return &chip8->psi.ics; 2294 } 2295 2296 for (j = 0; j < chip8->num_phbs; j++) { 2297 PnvPHB *phb = chip8->phbs[j]; 2298 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2299 2300 if (ics_valid_irq(&phb3->lsis, irq)) { 2301 return &phb3->lsis; 2302 } 2303 2304 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2305 return ICS(&phb3->msis); 2306 } 2307 } 2308 } 2309 return NULL; 2310 } 2311 2312 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2313 { 2314 int i; 2315 2316 for (i = 0; i < pnv->num_chips; i++) { 2317 PnvChip *chip = pnv->chips[i]; 2318 if (chip->chip_id == chip_id) { 2319 return chip; 2320 } 2321 } 2322 return NULL; 2323 } 2324 2325 static void pnv_ics_resend(XICSFabric *xi) 2326 { 2327 PnvMachineState *pnv = PNV_MACHINE(xi); 2328 int i, j; 2329 2330 for (i = 0; i < pnv->num_chips; i++) { 2331 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2332 2333 ics_resend(&chip8->psi.ics); 2334 2335 for (j = 0; j < chip8->num_phbs; j++) { 2336 PnvPHB *phb = chip8->phbs[j]; 2337 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2338 2339 ics_resend(&phb3->lsis); 2340 ics_resend(ICS(&phb3->msis)); 2341 } 2342 } 2343 } 2344 2345 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2346 { 2347 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2348 2349 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2350 } 2351 2352 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2353 Monitor *mon) 2354 { 2355 PnvMachineState *pnv = PNV_MACHINE(obj); 2356 int i; 2357 CPUState *cs; 2358 g_autoptr(GString) buf = g_string_new(""); 2359 g_autoptr(HumanReadableText) info = NULL; 2360 2361 CPU_FOREACH(cs) { 2362 PowerPCCPU *cpu = POWERPC_CPU(cs); 2363 2364 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2365 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2366 buf); 2367 } 2368 info = human_readable_text_from_str(buf); 2369 monitor_puts(mon, info->human_readable_text); 2370 2371 for (i = 0; i < pnv->num_chips; i++) { 2372 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2373 } 2374 } 2375 2376 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2377 uint8_t nvt_blk, uint32_t nvt_idx, 2378 bool cam_ignore, uint8_t priority, 2379 uint32_t logic_serv, 2380 XiveTCTXMatch *match) 2381 { 2382 PnvMachineState *pnv = PNV_MACHINE(xfb); 2383 int total_count = 0; 2384 int i; 2385 2386 for (i = 0; i < pnv->num_chips; i++) { 2387 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2388 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2389 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2390 int count; 2391 2392 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2393 priority, logic_serv, match); 2394 2395 if (count < 0) { 2396 return count; 2397 } 2398 2399 total_count += count; 2400 } 2401 2402 return total_count; 2403 } 2404 2405 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2406 uint8_t nvt_blk, uint32_t nvt_idx, 2407 bool cam_ignore, uint8_t priority, 2408 uint32_t logic_serv, 2409 XiveTCTXMatch *match) 2410 { 2411 PnvMachineState *pnv = PNV_MACHINE(xfb); 2412 int total_count = 0; 2413 int i; 2414 2415 for (i = 0; i < pnv->num_chips; i++) { 2416 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2417 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2418 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2419 int count; 2420 2421 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2422 priority, logic_serv, match); 2423 2424 if (count < 0) { 2425 return count; 2426 } 2427 2428 total_count += count; 2429 } 2430 2431 return total_count; 2432 } 2433 2434 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2435 { 2436 MachineClass *mc = MACHINE_CLASS(oc); 2437 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2438 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2439 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2440 2441 static GlobalProperty phb_compat[] = { 2442 { TYPE_PNV_PHB, "version", "3" }, 2443 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2444 }; 2445 2446 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2447 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2448 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2449 2450 xic->icp_get = pnv_icp_get; 2451 xic->ics_get = pnv_ics_get; 2452 xic->ics_resend = pnv_ics_resend; 2453 2454 pmc->compat = compat; 2455 pmc->compat_size = sizeof(compat); 2456 2457 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2458 } 2459 2460 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2461 { 2462 MachineClass *mc = MACHINE_CLASS(oc); 2463 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2464 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2465 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2466 2467 static GlobalProperty phb_compat[] = { 2468 { TYPE_PNV_PHB, "version", "4" }, 2469 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2470 }; 2471 2472 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2473 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2474 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2475 2476 xfc->match_nvt = pnv_match_nvt; 2477 2478 pmc->compat = compat; 2479 pmc->compat_size = sizeof(compat); 2480 pmc->dt_power_mgt = pnv_dt_power_mgt; 2481 2482 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2483 } 2484 2485 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2486 { 2487 MachineClass *mc = MACHINE_CLASS(oc); 2488 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2489 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2490 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2491 2492 static GlobalProperty phb_compat[] = { 2493 { TYPE_PNV_PHB, "version", "5" }, 2494 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2495 }; 2496 2497 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2498 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2499 2500 mc->alias = "powernv"; 2501 2502 pmc->compat = compat; 2503 pmc->compat_size = sizeof(compat); 2504 pmc->dt_power_mgt = pnv_dt_power_mgt; 2505 2506 xfc->match_nvt = pnv10_xive_match_nvt; 2507 2508 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2509 } 2510 2511 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2512 { 2513 MachineClass *mc = MACHINE_CLASS(oc); 2514 2515 pnv_machine_p10_common_class_init(oc, data); 2516 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2517 } 2518 2519 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2520 { 2521 MachineClass *mc = MACHINE_CLASS(oc); 2522 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2523 2524 pnv_machine_p10_common_class_init(oc, data); 2525 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2526 pmc->i2c_init = pnv_rainier_i2c_init; 2527 } 2528 2529 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2530 { 2531 PnvMachineState *pnv = PNV_MACHINE(obj); 2532 2533 return !!pnv->fw_load_addr; 2534 } 2535 2536 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2537 { 2538 PnvMachineState *pnv = PNV_MACHINE(obj); 2539 2540 if (value) { 2541 pnv->fw_load_addr = 0x8000000; 2542 } 2543 } 2544 2545 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2546 { 2547 CPUPPCState *env = cpu_env(cs); 2548 2549 cpu_synchronize_state(cs); 2550 ppc_cpu_do_system_reset(cs); 2551 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2552 /* 2553 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2554 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2555 * (PPC_BIT(43)). 2556 */ 2557 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2558 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2559 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2560 } 2561 } else { 2562 /* 2563 * For non-powersave system resets, SRR1[42:45] are defined to be 2564 * implementation-dependent. The POWER9 User Manual specifies that 2565 * an external (SCOM driven, which may come from a BMC nmi command or 2566 * another CPU requesting a NMI IPI) system reset exception should be 2567 * 0b0010 (PPC_BIT(44)). 2568 */ 2569 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2570 } 2571 } 2572 2573 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2574 { 2575 CPUState *cs; 2576 2577 CPU_FOREACH(cs) { 2578 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2579 } 2580 } 2581 2582 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2583 { 2584 MachineClass *mc = MACHINE_CLASS(oc); 2585 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2586 NMIClass *nc = NMI_CLASS(oc); 2587 2588 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2589 mc->init = pnv_init; 2590 mc->reset = pnv_reset; 2591 mc->max_cpus = MAX_CPUS; 2592 /* Pnv provides a AHCI device for storage */ 2593 mc->block_default_type = IF_IDE; 2594 mc->no_parallel = 1; 2595 mc->default_boot_order = NULL; 2596 /* 2597 * RAM defaults to less than 2048 for 32-bit hosts, and large 2598 * enough to fit the maximum initrd size at it's load address 2599 */ 2600 mc->default_ram_size = 1 * GiB; 2601 mc->default_ram_id = "pnv.ram"; 2602 ispc->print_info = pnv_pic_print_info; 2603 nc->nmi_monitor_handler = pnv_nmi; 2604 2605 object_class_property_add_bool(oc, "hb-mode", 2606 pnv_machine_get_hb, pnv_machine_set_hb); 2607 object_class_property_set_description(oc, "hb-mode", 2608 "Use a hostboot like boot loader"); 2609 } 2610 2611 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2612 { \ 2613 .name = type, \ 2614 .class_init = class_initfn, \ 2615 .parent = TYPE_PNV8_CHIP, \ 2616 } 2617 2618 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2619 { \ 2620 .name = type, \ 2621 .class_init = class_initfn, \ 2622 .parent = TYPE_PNV9_CHIP, \ 2623 } 2624 2625 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2626 { \ 2627 .name = type, \ 2628 .class_init = class_initfn, \ 2629 .parent = TYPE_PNV10_CHIP, \ 2630 } 2631 2632 static const TypeInfo types[] = { 2633 { 2634 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2635 .parent = MACHINE_TYPE_NAME("powernv10"), 2636 .class_init = pnv_machine_p10_rainier_class_init, 2637 }, 2638 { 2639 .name = MACHINE_TYPE_NAME("powernv10"), 2640 .parent = TYPE_PNV_MACHINE, 2641 .class_init = pnv_machine_power10_class_init, 2642 .interfaces = (InterfaceInfo[]) { 2643 { TYPE_XIVE_FABRIC }, 2644 { }, 2645 }, 2646 }, 2647 { 2648 .name = MACHINE_TYPE_NAME("powernv9"), 2649 .parent = TYPE_PNV_MACHINE, 2650 .class_init = pnv_machine_power9_class_init, 2651 .interfaces = (InterfaceInfo[]) { 2652 { TYPE_XIVE_FABRIC }, 2653 { }, 2654 }, 2655 }, 2656 { 2657 .name = MACHINE_TYPE_NAME("powernv8"), 2658 .parent = TYPE_PNV_MACHINE, 2659 .class_init = pnv_machine_power8_class_init, 2660 .interfaces = (InterfaceInfo[]) { 2661 { TYPE_XICS_FABRIC }, 2662 { }, 2663 }, 2664 }, 2665 { 2666 .name = TYPE_PNV_MACHINE, 2667 .parent = TYPE_MACHINE, 2668 .abstract = true, 2669 .instance_size = sizeof(PnvMachineState), 2670 .class_init = pnv_machine_class_init, 2671 .class_size = sizeof(PnvMachineClass), 2672 .interfaces = (InterfaceInfo[]) { 2673 { TYPE_INTERRUPT_STATS_PROVIDER }, 2674 { TYPE_NMI }, 2675 { }, 2676 }, 2677 }, 2678 { 2679 .name = TYPE_PNV_CHIP, 2680 .parent = TYPE_SYS_BUS_DEVICE, 2681 .class_init = pnv_chip_class_init, 2682 .instance_size = sizeof(PnvChip), 2683 .class_size = sizeof(PnvChipClass), 2684 .abstract = true, 2685 }, 2686 2687 /* 2688 * P10 chip and variants 2689 */ 2690 { 2691 .name = TYPE_PNV10_CHIP, 2692 .parent = TYPE_PNV_CHIP, 2693 .instance_init = pnv_chip_power10_instance_init, 2694 .instance_size = sizeof(Pnv10Chip), 2695 }, 2696 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2697 2698 /* 2699 * P9 chip and variants 2700 */ 2701 { 2702 .name = TYPE_PNV9_CHIP, 2703 .parent = TYPE_PNV_CHIP, 2704 .instance_init = pnv_chip_power9_instance_init, 2705 .instance_size = sizeof(Pnv9Chip), 2706 }, 2707 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2708 2709 /* 2710 * P8 chip and variants 2711 */ 2712 { 2713 .name = TYPE_PNV8_CHIP, 2714 .parent = TYPE_PNV_CHIP, 2715 .instance_init = pnv_chip_power8_instance_init, 2716 .instance_size = sizeof(Pnv8Chip), 2717 }, 2718 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2719 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2720 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2721 pnv_chip_power8nvl_class_init), 2722 }; 2723 2724 DEFINE_TYPES(types) 2725