1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qemu/units.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "qemu/log.h" 35 #include "hw/ppc/fdt.h" 36 #include "hw/ppc/ppc.h" 37 #include "hw/ppc/pnv.h" 38 #include "hw/ppc/pnv_core.h" 39 #include "hw/loader.h" 40 #include "hw/nmi.h" 41 #include "exec/address-spaces.h" 42 #include "qapi/visitor.h" 43 #include "monitor/monitor.h" 44 #include "hw/intc/intc.h" 45 #include "hw/ipmi/ipmi.h" 46 #include "target/ppc/mmu-hash64.h" 47 #include "hw/pci/msi.h" 48 49 #include "hw/ppc/xics.h" 50 #include "hw/qdev-properties.h" 51 #include "hw/ppc/pnv_xscom.h" 52 #include "hw/ppc/pnv_pnor.h" 53 54 #include "hw/isa/isa.h" 55 #include "hw/boards.h" 56 #include "hw/char/serial.h" 57 #include "hw/rtc/mc146818rtc.h" 58 59 #include <libfdt.h> 60 61 #define FDT_MAX_SIZE (1 * MiB) 62 63 #define FW_FILE_NAME "skiboot.lid" 64 #define FW_LOAD_ADDR 0x0 65 #define FW_MAX_SIZE (16 * MiB) 66 67 #define KERNEL_LOAD_ADDR 0x20000000 68 #define KERNEL_MAX_SIZE (256 * MiB) 69 #define INITRD_LOAD_ADDR 0x60000000 70 #define INITRD_MAX_SIZE (256 * MiB) 71 72 static const char *pnv_chip_core_typename(const PnvChip *o) 73 { 74 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 75 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 76 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 77 const char *core_type = object_class_get_name(object_class_by_name(s)); 78 g_free(s); 79 return core_type; 80 } 81 82 /* 83 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 84 * 4 * 4 sockets * 12 cores * 8 threads = 1536 85 * Let's make it 2^11 86 */ 87 #define MAX_CPUS 2048 88 89 /* 90 * Memory nodes are created by hostboot, one for each range of memory 91 * that has a different "affinity". In practice, it means one range 92 * per chip. 93 */ 94 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 95 { 96 char *mem_name; 97 uint64_t mem_reg_property[2]; 98 int off; 99 100 mem_reg_property[0] = cpu_to_be64(start); 101 mem_reg_property[1] = cpu_to_be64(size); 102 103 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 104 off = fdt_add_subnode(fdt, 0, mem_name); 105 g_free(mem_name); 106 107 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 108 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 109 sizeof(mem_reg_property)))); 110 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 111 } 112 113 static int get_cpus_node(void *fdt) 114 { 115 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 116 117 if (cpus_offset < 0) { 118 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 119 if (cpus_offset) { 120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 122 } 123 } 124 _FDT(cpus_offset); 125 return cpus_offset; 126 } 127 128 /* 129 * The PowerNV cores (and threads) need to use real HW ids and not an 130 * incremental index like it has been done on other platforms. This HW 131 * id is stored in the CPU PIR, it is used to create cpu nodes in the 132 * device tree, used in XSCOM to address cores and in interrupt 133 * servers. 134 */ 135 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 136 { 137 PowerPCCPU *cpu = pc->threads[0]; 138 CPUState *cs = CPU(cpu); 139 DeviceClass *dc = DEVICE_GET_CLASS(cs); 140 int smt_threads = CPU_CORE(pc)->nr_threads; 141 CPUPPCState *env = &cpu->env; 142 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 143 uint32_t servers_prop[smt_threads]; 144 int i; 145 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 146 0xffffffff, 0xffffffff}; 147 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 148 uint32_t cpufreq = 1000000000; 149 uint32_t page_sizes_prop[64]; 150 size_t page_sizes_prop_size; 151 const uint8_t pa_features[] = { 24, 0, 152 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 153 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 154 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 155 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 156 int offset; 157 char *nodename; 158 int cpus_offset = get_cpus_node(fdt); 159 160 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 161 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 162 _FDT(offset); 163 g_free(nodename); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 166 167 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 168 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 169 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 170 171 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 175 env->dcache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 177 env->icache_line_size))); 178 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 179 env->icache_line_size))); 180 181 if (pcc->l1_dcache_size) { 182 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 183 pcc->l1_dcache_size))); 184 } else { 185 warn_report("Unknown L1 dcache size for cpu"); 186 } 187 if (pcc->l1_icache_size) { 188 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 189 pcc->l1_icache_size))); 190 } else { 191 warn_report("Unknown L1 icache size for cpu"); 192 } 193 194 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 195 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 196 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 197 cpu->hash64_opts->slb_size))); 198 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 199 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 200 201 if (env->spr_cb[SPR_PURR].oea_read) { 202 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 203 } 204 205 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 206 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 207 segs, sizeof(segs)))); 208 } 209 210 /* 211 * Advertise VMX/VSX (vector extensions) if available 212 * 0 / no property == no vector extensions 213 * 1 == VMX / Altivec available 214 * 2 == VSX available 215 */ 216 if (env->insns_flags & PPC_ALTIVEC) { 217 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 218 219 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 220 } 221 222 /* 223 * Advertise DFP (Decimal Floating Point) if available 224 * 0 / no property == no DFP 225 * 1 == DFP available 226 */ 227 if (env->insns_flags2 & PPC2_DFP) { 228 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 229 } 230 231 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 232 sizeof(page_sizes_prop)); 233 if (page_sizes_prop_size) { 234 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 235 page_sizes_prop, page_sizes_prop_size))); 236 } 237 238 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 239 pa_features, sizeof(pa_features)))); 240 241 /* Build interrupt servers properties */ 242 for (i = 0; i < smt_threads; i++) { 243 servers_prop[i] = cpu_to_be32(pc->pir + i); 244 } 245 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 246 servers_prop, sizeof(servers_prop)))); 247 } 248 249 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 250 uint32_t nr_threads) 251 { 252 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 253 char *name; 254 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 255 uint32_t irange[2], i, rsize; 256 uint64_t *reg; 257 int offset; 258 259 irange[0] = cpu_to_be32(pir); 260 irange[1] = cpu_to_be32(nr_threads); 261 262 rsize = sizeof(uint64_t) * 2 * nr_threads; 263 reg = g_malloc(rsize); 264 for (i = 0; i < nr_threads; i++) { 265 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 266 reg[i * 2 + 1] = cpu_to_be64(0x1000); 267 } 268 269 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 270 offset = fdt_add_subnode(fdt, 0, name); 271 _FDT(offset); 272 g_free(name); 273 274 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 275 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 276 _FDT((fdt_setprop_string(fdt, offset, "device_type", 277 "PowerPC-External-Interrupt-Presentation"))); 278 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 279 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 280 irange, sizeof(irange)))); 281 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 282 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 283 g_free(reg); 284 } 285 286 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 287 { 288 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 289 int i; 290 291 pnv_dt_xscom(chip, fdt, 0, 292 cpu_to_be64(PNV_XSCOM_BASE(chip)), 293 cpu_to_be64(PNV_XSCOM_SIZE), 294 compat, sizeof(compat)); 295 296 for (i = 0; i < chip->nr_cores; i++) { 297 PnvCore *pnv_core = chip->cores[i]; 298 299 pnv_dt_core(chip, pnv_core, fdt); 300 301 /* Interrupt Control Presenters (ICP). One per core. */ 302 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 303 } 304 305 if (chip->ram_size) { 306 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 307 } 308 } 309 310 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 311 { 312 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 313 int i; 314 315 pnv_dt_xscom(chip, fdt, 0, 316 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 317 cpu_to_be64(PNV9_XSCOM_SIZE), 318 compat, sizeof(compat)); 319 320 for (i = 0; i < chip->nr_cores; i++) { 321 PnvCore *pnv_core = chip->cores[i]; 322 323 pnv_dt_core(chip, pnv_core, fdt); 324 } 325 326 if (chip->ram_size) { 327 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 328 } 329 330 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 331 } 332 333 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 334 { 335 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 336 int i; 337 338 pnv_dt_xscom(chip, fdt, 0, 339 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 340 cpu_to_be64(PNV10_XSCOM_SIZE), 341 compat, sizeof(compat)); 342 343 for (i = 0; i < chip->nr_cores; i++) { 344 PnvCore *pnv_core = chip->cores[i]; 345 346 pnv_dt_core(chip, pnv_core, fdt); 347 } 348 349 if (chip->ram_size) { 350 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 351 } 352 353 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 354 } 355 356 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 357 { 358 uint32_t io_base = d->ioport_id; 359 uint32_t io_regs[] = { 360 cpu_to_be32(1), 361 cpu_to_be32(io_base), 362 cpu_to_be32(2) 363 }; 364 char *name; 365 int node; 366 367 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 368 node = fdt_add_subnode(fdt, lpc_off, name); 369 _FDT(node); 370 g_free(name); 371 372 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 373 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 374 } 375 376 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 377 { 378 const char compatible[] = "ns16550\0pnpPNP,501"; 379 uint32_t io_base = d->ioport_id; 380 uint32_t io_regs[] = { 381 cpu_to_be32(1), 382 cpu_to_be32(io_base), 383 cpu_to_be32(8) 384 }; 385 char *name; 386 int node; 387 388 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 389 node = fdt_add_subnode(fdt, lpc_off, name); 390 _FDT(node); 391 g_free(name); 392 393 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 394 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 395 sizeof(compatible)))); 396 397 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 398 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 399 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 400 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 401 fdt_get_phandle(fdt, lpc_off)))); 402 403 /* This is needed by Linux */ 404 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 405 } 406 407 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 408 { 409 const char compatible[] = "bt\0ipmi-bt"; 410 uint32_t io_base; 411 uint32_t io_regs[] = { 412 cpu_to_be32(1), 413 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 414 cpu_to_be32(3) 415 }; 416 uint32_t irq; 417 char *name; 418 int node; 419 420 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 421 io_regs[1] = cpu_to_be32(io_base); 422 423 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 424 425 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 426 node = fdt_add_subnode(fdt, lpc_off, name); 427 _FDT(node); 428 g_free(name); 429 430 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 431 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 432 sizeof(compatible)))); 433 434 /* Mark it as reserved to avoid Linux trying to claim it */ 435 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 436 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 437 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 438 fdt_get_phandle(fdt, lpc_off)))); 439 } 440 441 typedef struct ForeachPopulateArgs { 442 void *fdt; 443 int offset; 444 } ForeachPopulateArgs; 445 446 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 447 { 448 ForeachPopulateArgs *args = opaque; 449 ISADevice *d = ISA_DEVICE(dev); 450 451 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 452 pnv_dt_rtc(d, args->fdt, args->offset); 453 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 454 pnv_dt_serial(d, args->fdt, args->offset); 455 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 456 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 457 } else { 458 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 459 d->ioport_id); 460 } 461 462 return 0; 463 } 464 465 /* 466 * The default LPC bus of a multichip system is on chip 0. It's 467 * recognized by the firmware (skiboot) using a "primary" property. 468 */ 469 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 470 { 471 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 472 ForeachPopulateArgs args = { 473 .fdt = fdt, 474 .offset = isa_offset, 475 }; 476 uint32_t phandle; 477 478 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 479 480 phandle = qemu_fdt_alloc_phandle(fdt); 481 assert(phandle > 0); 482 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 483 484 /* 485 * ISA devices are not necessarily parented to the ISA bus so we 486 * can not use object_child_foreach() 487 */ 488 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 489 &args); 490 } 491 492 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 493 { 494 int off; 495 496 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 497 off = fdt_add_subnode(fdt, off, "power-mgt"); 498 499 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 500 } 501 502 static void *pnv_dt_create(MachineState *machine) 503 { 504 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 505 PnvMachineState *pnv = PNV_MACHINE(machine); 506 void *fdt; 507 char *buf; 508 int off; 509 int i; 510 511 fdt = g_malloc0(FDT_MAX_SIZE); 512 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 513 514 /* /qemu node */ 515 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 516 517 /* Root node */ 518 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 519 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 520 _FDT((fdt_setprop_string(fdt, 0, "model", 521 "IBM PowerNV (emulated by qemu)"))); 522 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 523 524 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 525 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 526 if (qemu_uuid_set) { 527 _FDT((fdt_property_string(fdt, "system-id", buf))); 528 } 529 g_free(buf); 530 531 off = fdt_add_subnode(fdt, 0, "chosen"); 532 if (machine->kernel_cmdline) { 533 _FDT((fdt_setprop_string(fdt, off, "bootargs", 534 machine->kernel_cmdline))); 535 } 536 537 if (pnv->initrd_size) { 538 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 539 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 540 541 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 542 &start_prop, sizeof(start_prop)))); 543 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 544 &end_prop, sizeof(end_prop)))); 545 } 546 547 /* Populate device tree for each chip */ 548 for (i = 0; i < pnv->num_chips; i++) { 549 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 550 } 551 552 /* Populate ISA devices on chip 0 */ 553 pnv_dt_isa(pnv, fdt); 554 555 if (pnv->bmc) { 556 pnv_dt_bmc_sensors(pnv->bmc, fdt); 557 } 558 559 /* Create an extra node for power management on machines that support it */ 560 if (pmc->dt_power_mgt) { 561 pmc->dt_power_mgt(pnv, fdt); 562 } 563 564 return fdt; 565 } 566 567 static void pnv_powerdown_notify(Notifier *n, void *opaque) 568 { 569 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 570 571 if (pnv->bmc) { 572 pnv_bmc_powerdown(pnv->bmc); 573 } 574 } 575 576 static void pnv_reset(MachineState *machine) 577 { 578 PnvMachineState *pnv = PNV_MACHINE(machine); 579 IPMIBmc *bmc; 580 void *fdt; 581 582 qemu_devices_reset(); 583 584 /* 585 * The machine should provide by default an internal BMC simulator. 586 * If not, try to use the BMC device that was provided on the command 587 * line. 588 */ 589 bmc = pnv_bmc_find(&error_fatal); 590 if (!pnv->bmc) { 591 if (!bmc) { 592 if (!qtest_enabled()) { 593 warn_report("machine has no BMC device. Use '-device " 594 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 595 "to define one"); 596 } 597 } else { 598 pnv_bmc_set_pnor(bmc, pnv->pnor); 599 pnv->bmc = bmc; 600 } 601 } 602 603 fdt = pnv_dt_create(machine); 604 605 /* Pack resulting tree */ 606 _FDT((fdt_pack(fdt))); 607 608 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 609 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 610 611 g_free(fdt); 612 } 613 614 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 615 { 616 Pnv8Chip *chip8 = PNV8_CHIP(chip); 617 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 618 } 619 620 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 621 { 622 Pnv8Chip *chip8 = PNV8_CHIP(chip); 623 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 624 } 625 626 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 627 { 628 Pnv9Chip *chip9 = PNV9_CHIP(chip); 629 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 630 } 631 632 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 633 { 634 Pnv10Chip *chip10 = PNV10_CHIP(chip); 635 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 636 } 637 638 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 639 { 640 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 641 } 642 643 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 644 { 645 Pnv8Chip *chip8 = PNV8_CHIP(chip); 646 int i; 647 648 ics_pic_print_info(&chip8->psi.ics, mon); 649 for (i = 0; i < chip->num_phbs; i++) { 650 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 651 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 652 } 653 } 654 655 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 656 { 657 Pnv9Chip *chip9 = PNV9_CHIP(chip); 658 int i, j; 659 660 pnv_xive_pic_print_info(&chip9->xive, mon); 661 pnv_psi_pic_print_info(&chip9->psi, mon); 662 663 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 664 PnvPhb4PecState *pec = &chip9->pecs[i]; 665 for (j = 0; j < pec->num_stacks; j++) { 666 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 667 } 668 } 669 } 670 671 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 672 uint32_t core_id) 673 { 674 return PNV_XSCOM_EX_BASE(core_id); 675 } 676 677 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 678 uint32_t core_id) 679 { 680 return PNV9_XSCOM_EC_BASE(core_id); 681 } 682 683 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 684 uint32_t core_id) 685 { 686 return PNV10_XSCOM_EC_BASE(core_id); 687 } 688 689 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 690 { 691 PowerPCCPUClass *ppc_default = 692 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 693 PowerPCCPUClass *ppc = 694 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 695 696 return ppc_default->pvr_match(ppc_default, ppc->pvr); 697 } 698 699 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 700 { 701 ISADevice *dev = isa_new("isa-ipmi-bt"); 702 703 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 704 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 705 isa_realize_and_unref(dev, bus, &error_fatal); 706 } 707 708 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 709 { 710 Pnv10Chip *chip10 = PNV10_CHIP(chip); 711 712 pnv_psi_pic_print_info(&chip10->psi, mon); 713 } 714 715 static void pnv_init(MachineState *machine) 716 { 717 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 718 PnvMachineState *pnv = PNV_MACHINE(machine); 719 MachineClass *mc = MACHINE_GET_CLASS(machine); 720 char *fw_filename; 721 long fw_size; 722 int i; 723 char *chip_typename; 724 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 725 DeviceState *dev; 726 727 /* allocate RAM */ 728 if (machine->ram_size < (1 * GiB)) { 729 warn_report("skiboot may not work with < 1GB of RAM"); 730 } 731 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 732 733 /* 734 * Create our simple PNOR device 735 */ 736 dev = qdev_new(TYPE_PNV_PNOR); 737 if (pnor) { 738 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 739 } 740 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 741 pnv->pnor = PNV_PNOR(dev); 742 743 /* load skiboot firmware */ 744 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 745 if (!fw_filename) { 746 error_report("Could not find OPAL firmware '%s'", bios_name); 747 exit(1); 748 } 749 750 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 751 if (fw_size < 0) { 752 error_report("Could not load OPAL firmware '%s'", fw_filename); 753 exit(1); 754 } 755 g_free(fw_filename); 756 757 /* load kernel */ 758 if (machine->kernel_filename) { 759 long kernel_size; 760 761 kernel_size = load_image_targphys(machine->kernel_filename, 762 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 763 if (kernel_size < 0) { 764 error_report("Could not load kernel '%s'", 765 machine->kernel_filename); 766 exit(1); 767 } 768 } 769 770 /* load initrd */ 771 if (machine->initrd_filename) { 772 pnv->initrd_base = INITRD_LOAD_ADDR; 773 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 774 pnv->initrd_base, INITRD_MAX_SIZE); 775 if (pnv->initrd_size < 0) { 776 error_report("Could not load initial ram disk '%s'", 777 machine->initrd_filename); 778 exit(1); 779 } 780 } 781 782 /* MSIs are supported on this platform */ 783 msi_nonbroken = true; 784 785 /* 786 * Check compatibility of the specified CPU with the machine 787 * default. 788 */ 789 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 790 error_report("invalid CPU model '%s' for %s machine", 791 machine->cpu_type, mc->name); 792 exit(1); 793 } 794 795 /* Create the processor chips */ 796 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 797 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 798 i, machine->cpu_type); 799 if (!object_class_by_name(chip_typename)) { 800 error_report("invalid chip model '%.*s' for %s machine", 801 i, machine->cpu_type, mc->name); 802 exit(1); 803 } 804 805 pnv->num_chips = 806 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 807 /* 808 * TODO: should we decide on how many chips we can create based 809 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 810 */ 811 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 812 error_report("invalid number of chips: '%d'", pnv->num_chips); 813 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 814 exit(1); 815 } 816 817 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 818 for (i = 0; i < pnv->num_chips; i++) { 819 char chip_name[32]; 820 Object *chip = OBJECT(qdev_new(chip_typename)); 821 822 pnv->chips[i] = PNV_CHIP(chip); 823 824 /* 825 * TODO: put all the memory in one node on chip 0 until we find a 826 * way to specify different ranges for each chip 827 */ 828 if (i == 0) { 829 object_property_set_int(chip, "ram-size", machine->ram_size, 830 &error_fatal); 831 } 832 833 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 834 object_property_add_child(OBJECT(pnv), chip_name, chip); 835 object_property_set_int(chip, "chip-id", PNV_CHIP_HWID(i), 836 &error_fatal); 837 object_property_set_int(chip, "nr-cores", machine->smp.cores, 838 &error_fatal); 839 object_property_set_int(chip, "nr-threads", machine->smp.threads, 840 &error_fatal); 841 /* 842 * The POWER8 machine use the XICS interrupt interface. 843 * Propagate the XICS fabric to the chip and its controllers. 844 */ 845 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 846 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 847 } 848 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 849 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 850 &error_abort); 851 } 852 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 853 } 854 g_free(chip_typename); 855 856 /* Instantiate ISA bus on chip 0 */ 857 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 858 859 /* Create serial port */ 860 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 861 862 /* Create an RTC ISA device too */ 863 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 864 865 /* 866 * Create the machine BMC simulator and the IPMI BT device for 867 * communication with the BMC 868 */ 869 if (defaults_enabled()) { 870 pnv->bmc = pnv_bmc_create(pnv->pnor); 871 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 872 } 873 874 /* 875 * OpenPOWER systems use a IPMI SEL Event message to notify the 876 * host to powerdown 877 */ 878 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 879 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 880 } 881 882 /* 883 * 0:21 Reserved - Read as zeros 884 * 22:24 Chip ID 885 * 25:28 Core number 886 * 29:31 Thread ID 887 */ 888 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 889 { 890 return (chip->chip_id << 7) | (core_id << 3); 891 } 892 893 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 894 Error **errp) 895 { 896 Pnv8Chip *chip8 = PNV8_CHIP(chip); 897 Error *local_err = NULL; 898 Object *obj; 899 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 900 901 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 902 if (local_err) { 903 error_propagate(errp, local_err); 904 return; 905 } 906 907 pnv_cpu->intc = obj; 908 } 909 910 911 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 912 { 913 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 914 915 icp_reset(ICP(pnv_cpu->intc)); 916 } 917 918 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 919 { 920 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 921 922 icp_destroy(ICP(pnv_cpu->intc)); 923 pnv_cpu->intc = NULL; 924 } 925 926 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 927 Monitor *mon) 928 { 929 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 930 } 931 932 /* 933 * 0:48 Reserved - Read as zeroes 934 * 49:52 Node ID 935 * 53:55 Chip ID 936 * 56 Reserved - Read as zero 937 * 57:61 Core number 938 * 62:63 Thread ID 939 * 940 * We only care about the lower bits. uint32_t is fine for the moment. 941 */ 942 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 943 { 944 return (chip->chip_id << 8) | (core_id << 2); 945 } 946 947 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 948 { 949 return (chip->chip_id << 8) | (core_id << 2); 950 } 951 952 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 953 Error **errp) 954 { 955 Pnv9Chip *chip9 = PNV9_CHIP(chip); 956 Error *local_err = NULL; 957 Object *obj; 958 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 959 960 /* 961 * The core creates its interrupt presenter but the XIVE interrupt 962 * controller object is initialized afterwards. Hopefully, it's 963 * only used at runtime. 964 */ 965 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 966 &local_err); 967 if (local_err) { 968 error_propagate(errp, local_err); 969 return; 970 } 971 972 pnv_cpu->intc = obj; 973 } 974 975 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 976 { 977 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 978 979 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 980 } 981 982 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 983 { 984 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 985 986 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 987 pnv_cpu->intc = NULL; 988 } 989 990 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 991 Monitor *mon) 992 { 993 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 994 } 995 996 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 997 Error **errp) 998 { 999 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1000 1001 /* Will be defined when the interrupt controller is */ 1002 pnv_cpu->intc = NULL; 1003 } 1004 1005 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1006 { 1007 ; 1008 } 1009 1010 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1011 { 1012 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1013 1014 pnv_cpu->intc = NULL; 1015 } 1016 1017 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1018 Monitor *mon) 1019 { 1020 } 1021 1022 /* 1023 * Allowed core identifiers on a POWER8 Processor Chip : 1024 * 1025 * <EX0 reserved> 1026 * EX1 - Venice only 1027 * EX2 - Venice only 1028 * EX3 - Venice only 1029 * EX4 1030 * EX5 1031 * EX6 1032 * <EX7,8 reserved> <reserved> 1033 * EX9 - Venice only 1034 * EX10 - Venice only 1035 * EX11 - Venice only 1036 * EX12 1037 * EX13 1038 * EX14 1039 * <EX15 reserved> 1040 */ 1041 #define POWER8E_CORE_MASK (0x7070ull) 1042 #define POWER8_CORE_MASK (0x7e7eull) 1043 1044 /* 1045 * POWER9 has 24 cores, ids starting at 0x0 1046 */ 1047 #define POWER9_CORE_MASK (0xffffffffffffffull) 1048 1049 1050 #define POWER10_CORE_MASK (0xffffffffffffffull) 1051 1052 static void pnv_chip_power8_instance_init(Object *obj) 1053 { 1054 PnvChip *chip = PNV_CHIP(obj); 1055 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1056 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1057 int i; 1058 1059 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1060 (Object **)&chip8->xics, 1061 object_property_allow_set_link, 1062 OBJ_PROP_LINK_STRONG); 1063 1064 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1065 1066 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1067 1068 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1069 1070 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1071 1072 for (i = 0; i < pcc->num_phbs; i++) { 1073 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1074 } 1075 1076 /* 1077 * Number of PHBs is the chip default 1078 */ 1079 chip->num_phbs = pcc->num_phbs; 1080 } 1081 1082 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1083 { 1084 PnvChip *chip = PNV_CHIP(chip8); 1085 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1086 int i, j; 1087 char *name; 1088 1089 name = g_strdup_printf("icp-%x", chip->chip_id); 1090 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1091 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1092 g_free(name); 1093 1094 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1095 1096 /* Map the ICP registers for each thread */ 1097 for (i = 0; i < chip->nr_cores; i++) { 1098 PnvCore *pnv_core = chip->cores[i]; 1099 int core_hwid = CPU_CORE(pnv_core)->core_id; 1100 1101 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1102 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1103 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1104 1105 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1106 &icp->mmio); 1107 } 1108 } 1109 } 1110 1111 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1112 { 1113 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1114 PnvChip *chip = PNV_CHIP(dev); 1115 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1116 Pnv8Psi *psi8 = &chip8->psi; 1117 Error *local_err = NULL; 1118 int i; 1119 1120 assert(chip8->xics); 1121 1122 /* XSCOM bridge is first */ 1123 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1124 if (local_err) { 1125 error_propagate(errp, local_err); 1126 return; 1127 } 1128 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1129 1130 pcc->parent_realize(dev, &local_err); 1131 if (local_err) { 1132 error_propagate(errp, local_err); 1133 return; 1134 } 1135 1136 /* Processor Service Interface (PSI) Host Bridge */ 1137 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1138 &error_fatal); 1139 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1140 OBJECT(chip8->xics), &error_abort); 1141 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1142 return; 1143 } 1144 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1145 &PNV_PSI(psi8)->xscom_regs); 1146 1147 /* Create LPC controller */ 1148 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi), 1149 &error_abort); 1150 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1151 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1152 1153 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1154 (uint64_t) PNV_XSCOM_BASE(chip), 1155 PNV_XSCOM_LPC_BASE); 1156 1157 /* 1158 * Interrupt Management Area. This is the memory region holding 1159 * all the Interrupt Control Presenter (ICP) registers 1160 */ 1161 pnv_chip_icp_realize(chip8, &local_err); 1162 if (local_err) { 1163 error_propagate(errp, local_err); 1164 return; 1165 } 1166 1167 /* Create the simplified OCC model */ 1168 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi), 1169 &error_abort); 1170 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1171 return; 1172 } 1173 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1174 1175 /* OCC SRAM model */ 1176 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1177 &chip8->occ.sram_regs); 1178 1179 /* HOMER */ 1180 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1181 &error_abort); 1182 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1183 return; 1184 } 1185 /* Homer Xscom region */ 1186 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1187 1188 /* Homer mmio region */ 1189 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1190 &chip8->homer.regs); 1191 1192 /* PHB3 controllers */ 1193 for (i = 0; i < chip->num_phbs; i++) { 1194 PnvPHB3 *phb = &chip8->phbs[i]; 1195 PnvPBCQState *pbcq = &phb->pbcq; 1196 1197 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1198 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1199 &error_fatal); 1200 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1201 return; 1202 } 1203 1204 /* Populate the XSCOM address space. */ 1205 pnv_xscom_add_subregion(chip, 1206 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1207 &pbcq->xscom_nest_regs); 1208 pnv_xscom_add_subregion(chip, 1209 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1210 &pbcq->xscom_pci_regs); 1211 pnv_xscom_add_subregion(chip, 1212 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1213 &pbcq->xscom_spci_regs); 1214 } 1215 } 1216 1217 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1218 { 1219 addr &= (PNV_XSCOM_SIZE - 1); 1220 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1221 } 1222 1223 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1224 { 1225 DeviceClass *dc = DEVICE_CLASS(klass); 1226 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1227 1228 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1229 k->cores_mask = POWER8E_CORE_MASK; 1230 k->num_phbs = 3; 1231 k->core_pir = pnv_chip_core_pir_p8; 1232 k->intc_create = pnv_chip_power8_intc_create; 1233 k->intc_reset = pnv_chip_power8_intc_reset; 1234 k->intc_destroy = pnv_chip_power8_intc_destroy; 1235 k->intc_print_info = pnv_chip_power8_intc_print_info; 1236 k->isa_create = pnv_chip_power8_isa_create; 1237 k->dt_populate = pnv_chip_power8_dt_populate; 1238 k->pic_print_info = pnv_chip_power8_pic_print_info; 1239 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1240 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1241 dc->desc = "PowerNV Chip POWER8E"; 1242 1243 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1244 &k->parent_realize); 1245 } 1246 1247 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1248 { 1249 DeviceClass *dc = DEVICE_CLASS(klass); 1250 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1251 1252 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1253 k->cores_mask = POWER8_CORE_MASK; 1254 k->num_phbs = 3; 1255 k->core_pir = pnv_chip_core_pir_p8; 1256 k->intc_create = pnv_chip_power8_intc_create; 1257 k->intc_reset = pnv_chip_power8_intc_reset; 1258 k->intc_destroy = pnv_chip_power8_intc_destroy; 1259 k->intc_print_info = pnv_chip_power8_intc_print_info; 1260 k->isa_create = pnv_chip_power8_isa_create; 1261 k->dt_populate = pnv_chip_power8_dt_populate; 1262 k->pic_print_info = pnv_chip_power8_pic_print_info; 1263 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1264 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1265 dc->desc = "PowerNV Chip POWER8"; 1266 1267 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1268 &k->parent_realize); 1269 } 1270 1271 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1272 { 1273 DeviceClass *dc = DEVICE_CLASS(klass); 1274 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1275 1276 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1277 k->cores_mask = POWER8_CORE_MASK; 1278 k->num_phbs = 3; 1279 k->core_pir = pnv_chip_core_pir_p8; 1280 k->intc_create = pnv_chip_power8_intc_create; 1281 k->intc_reset = pnv_chip_power8_intc_reset; 1282 k->intc_destroy = pnv_chip_power8_intc_destroy; 1283 k->intc_print_info = pnv_chip_power8_intc_print_info; 1284 k->isa_create = pnv_chip_power8nvl_isa_create; 1285 k->dt_populate = pnv_chip_power8_dt_populate; 1286 k->pic_print_info = pnv_chip_power8_pic_print_info; 1287 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1288 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1289 dc->desc = "PowerNV Chip POWER8NVL"; 1290 1291 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1292 &k->parent_realize); 1293 } 1294 1295 static void pnv_chip_power9_instance_init(Object *obj) 1296 { 1297 PnvChip *chip = PNV_CHIP(obj); 1298 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1299 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1300 int i; 1301 1302 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1303 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1304 "xive-fabric"); 1305 1306 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1307 1308 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1309 1310 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1311 1312 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1313 1314 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1315 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1316 TYPE_PNV_PHB4_PEC); 1317 } 1318 1319 /* 1320 * Number of PHBs is the chip default 1321 */ 1322 chip->num_phbs = pcc->num_phbs; 1323 } 1324 1325 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1326 { 1327 PnvChip *chip = PNV_CHIP(chip9); 1328 int i; 1329 1330 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1331 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1332 1333 for (i = 0; i < chip9->nr_quads; i++) { 1334 char eq_name[32]; 1335 PnvQuad *eq = &chip9->quads[i]; 1336 PnvCore *pnv_core = chip->cores[i * 4]; 1337 int core_id = CPU_CORE(pnv_core)->core_id; 1338 1339 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1340 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1341 sizeof(*eq), TYPE_PNV_QUAD, 1342 &error_fatal, NULL); 1343 1344 object_property_set_int(OBJECT(eq), "id", core_id, &error_fatal); 1345 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1346 1347 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1348 &eq->xscom_regs); 1349 } 1350 } 1351 1352 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1353 { 1354 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1355 int i, j; 1356 int phb_id = 0; 1357 1358 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1359 PnvPhb4PecState *pec = &chip9->pecs[i]; 1360 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1361 uint32_t pec_nest_base; 1362 uint32_t pec_pci_base; 1363 1364 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1365 /* 1366 * PEC0 -> 1 stack 1367 * PEC1 -> 2 stacks 1368 * PEC2 -> 3 stacks 1369 */ 1370 object_property_set_int(OBJECT(pec), "num-stacks", i + 1, 1371 &error_fatal); 1372 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1373 &error_fatal); 1374 object_property_set_link(OBJECT(pec), "system-memory", 1375 OBJECT(get_system_memory()), &error_abort); 1376 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1377 return; 1378 } 1379 1380 pec_nest_base = pecc->xscom_nest_base(pec); 1381 pec_pci_base = pecc->xscom_pci_base(pec); 1382 1383 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1384 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1385 1386 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1387 j++, phb_id++) { 1388 PnvPhb4PecStack *stack = &pec->stacks[j]; 1389 Object *obj = OBJECT(&stack->phb); 1390 1391 object_property_set_int(obj, "index", phb_id, &error_fatal); 1392 object_property_set_int(obj, "chip-id", chip->chip_id, 1393 &error_fatal); 1394 object_property_set_int(obj, "version", PNV_PHB4_VERSION, 1395 &error_fatal); 1396 object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID, 1397 &error_fatal); 1398 object_property_set_link(obj, "stack", OBJECT(stack), 1399 &error_abort); 1400 if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) { 1401 return; 1402 } 1403 1404 /* Populate the XSCOM address space. */ 1405 pnv_xscom_add_subregion(chip, 1406 pec_nest_base + 0x40 * (stack->stack_no + 1), 1407 &stack->nest_regs_mr); 1408 pnv_xscom_add_subregion(chip, 1409 pec_pci_base + 0x40 * (stack->stack_no + 1), 1410 &stack->pci_regs_mr); 1411 pnv_xscom_add_subregion(chip, 1412 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1413 0x40 * stack->stack_no, 1414 &stack->phb_regs_mr); 1415 } 1416 } 1417 } 1418 1419 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1420 { 1421 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1422 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1423 PnvChip *chip = PNV_CHIP(dev); 1424 Pnv9Psi *psi9 = &chip9->psi; 1425 Error *local_err = NULL; 1426 1427 /* XSCOM bridge is first */ 1428 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1429 if (local_err) { 1430 error_propagate(errp, local_err); 1431 return; 1432 } 1433 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1434 1435 pcc->parent_realize(dev, &local_err); 1436 if (local_err) { 1437 error_propagate(errp, local_err); 1438 return; 1439 } 1440 1441 pnv_chip_quad_realize(chip9, &local_err); 1442 if (local_err) { 1443 error_propagate(errp, local_err); 1444 return; 1445 } 1446 1447 /* XIVE interrupt controller (POWER9) */ 1448 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1449 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1450 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1451 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1452 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1453 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1454 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1455 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1456 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1457 &error_abort); 1458 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1459 return; 1460 } 1461 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1462 &chip9->xive.xscom_regs); 1463 1464 /* Processor Service Interface (PSI) Host Bridge */ 1465 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1466 &error_fatal); 1467 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1468 return; 1469 } 1470 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1471 &PNV_PSI(psi9)->xscom_regs); 1472 1473 /* LPC */ 1474 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi), 1475 &error_abort); 1476 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1477 return; 1478 } 1479 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1480 &chip9->lpc.xscom_regs); 1481 1482 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1483 (uint64_t) PNV9_LPCM_BASE(chip)); 1484 1485 /* Create the simplified OCC model */ 1486 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi), 1487 &error_abort); 1488 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1489 return; 1490 } 1491 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1492 1493 /* OCC SRAM model */ 1494 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1495 &chip9->occ.sram_regs); 1496 1497 /* HOMER */ 1498 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1499 &error_abort); 1500 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1501 return; 1502 } 1503 /* Homer Xscom region */ 1504 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1505 1506 /* Homer mmio region */ 1507 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1508 &chip9->homer.regs); 1509 1510 /* PHBs */ 1511 pnv_chip_power9_phb_realize(chip, &local_err); 1512 if (local_err) { 1513 error_propagate(errp, local_err); 1514 return; 1515 } 1516 } 1517 1518 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1519 { 1520 addr &= (PNV9_XSCOM_SIZE - 1); 1521 return addr >> 3; 1522 } 1523 1524 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1525 { 1526 DeviceClass *dc = DEVICE_CLASS(klass); 1527 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1528 1529 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1530 k->cores_mask = POWER9_CORE_MASK; 1531 k->core_pir = pnv_chip_core_pir_p9; 1532 k->intc_create = pnv_chip_power9_intc_create; 1533 k->intc_reset = pnv_chip_power9_intc_reset; 1534 k->intc_destroy = pnv_chip_power9_intc_destroy; 1535 k->intc_print_info = pnv_chip_power9_intc_print_info; 1536 k->isa_create = pnv_chip_power9_isa_create; 1537 k->dt_populate = pnv_chip_power9_dt_populate; 1538 k->pic_print_info = pnv_chip_power9_pic_print_info; 1539 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1540 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1541 dc->desc = "PowerNV Chip POWER9"; 1542 k->num_phbs = 6; 1543 1544 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1545 &k->parent_realize); 1546 } 1547 1548 static void pnv_chip_power10_instance_init(Object *obj) 1549 { 1550 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1551 1552 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1553 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1554 } 1555 1556 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1557 { 1558 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1559 PnvChip *chip = PNV_CHIP(dev); 1560 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1561 Error *local_err = NULL; 1562 1563 /* XSCOM bridge is first */ 1564 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1565 if (local_err) { 1566 error_propagate(errp, local_err); 1567 return; 1568 } 1569 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1570 1571 pcc->parent_realize(dev, &local_err); 1572 if (local_err) { 1573 error_propagate(errp, local_err); 1574 return; 1575 } 1576 1577 /* Processor Service Interface (PSI) Host Bridge */ 1578 object_property_set_int(OBJECT(&chip10->psi), "bar", 1579 PNV10_PSIHB_BASE(chip), &error_fatal); 1580 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1581 return; 1582 } 1583 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1584 &PNV_PSI(&chip10->psi)->xscom_regs); 1585 1586 /* LPC */ 1587 object_property_set_link(OBJECT(&chip10->lpc), "psi", 1588 OBJECT(&chip10->psi), &error_abort); 1589 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1590 return; 1591 } 1592 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1593 &chip10->lpc.xscom_regs); 1594 1595 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1596 (uint64_t) PNV10_LPCM_BASE(chip)); 1597 } 1598 1599 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1600 { 1601 addr &= (PNV10_XSCOM_SIZE - 1); 1602 return addr >> 3; 1603 } 1604 1605 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1606 { 1607 DeviceClass *dc = DEVICE_CLASS(klass); 1608 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1609 1610 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1611 k->cores_mask = POWER10_CORE_MASK; 1612 k->core_pir = pnv_chip_core_pir_p10; 1613 k->intc_create = pnv_chip_power10_intc_create; 1614 k->intc_reset = pnv_chip_power10_intc_reset; 1615 k->intc_destroy = pnv_chip_power10_intc_destroy; 1616 k->intc_print_info = pnv_chip_power10_intc_print_info; 1617 k->isa_create = pnv_chip_power10_isa_create; 1618 k->dt_populate = pnv_chip_power10_dt_populate; 1619 k->pic_print_info = pnv_chip_power10_pic_print_info; 1620 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1621 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1622 dc->desc = "PowerNV Chip POWER10"; 1623 1624 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1625 &k->parent_realize); 1626 } 1627 1628 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1629 { 1630 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1631 int cores_max; 1632 1633 /* 1634 * No custom mask for this chip, let's use the default one from * 1635 * the chip class 1636 */ 1637 if (!chip->cores_mask) { 1638 chip->cores_mask = pcc->cores_mask; 1639 } 1640 1641 /* filter alien core ids ! some are reserved */ 1642 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1643 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1644 chip->cores_mask); 1645 return; 1646 } 1647 chip->cores_mask &= pcc->cores_mask; 1648 1649 /* now that we have a sane layout, let check the number of cores */ 1650 cores_max = ctpop64(chip->cores_mask); 1651 if (chip->nr_cores > cores_max) { 1652 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1653 cores_max); 1654 return; 1655 } 1656 } 1657 1658 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1659 { 1660 Error *error = NULL; 1661 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1662 const char *typename = pnv_chip_core_typename(chip); 1663 int i, core_hwid; 1664 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1665 1666 if (!object_class_by_name(typename)) { 1667 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1668 return; 1669 } 1670 1671 /* Cores */ 1672 pnv_chip_core_sanitize(chip, &error); 1673 if (error) { 1674 error_propagate(errp, error); 1675 return; 1676 } 1677 1678 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1679 1680 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1681 && (i < chip->nr_cores); core_hwid++) { 1682 char core_name[32]; 1683 PnvCore *pnv_core; 1684 uint64_t xscom_core_base; 1685 1686 if (!(chip->cores_mask & (1ull << core_hwid))) { 1687 continue; 1688 } 1689 1690 pnv_core = PNV_CORE(object_new(typename)); 1691 1692 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1693 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1694 chip->cores[i] = pnv_core; 1695 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1696 chip->nr_threads, &error_fatal); 1697 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1698 core_hwid, &error_fatal); 1699 object_property_set_int(OBJECT(pnv_core), "pir", 1700 pcc->core_pir(chip, core_hwid), &error_fatal); 1701 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1702 &error_fatal); 1703 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1704 &error_abort); 1705 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1706 1707 /* Each core has an XSCOM MMIO region */ 1708 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1709 1710 pnv_xscom_add_subregion(chip, xscom_core_base, 1711 &pnv_core->xscom_regs); 1712 i++; 1713 } 1714 } 1715 1716 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1717 { 1718 PnvChip *chip = PNV_CHIP(dev); 1719 Error *error = NULL; 1720 1721 /* Cores */ 1722 pnv_chip_core_realize(chip, &error); 1723 if (error) { 1724 error_propagate(errp, error); 1725 return; 1726 } 1727 } 1728 1729 static Property pnv_chip_properties[] = { 1730 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1731 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1732 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1733 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1734 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1735 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1736 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1737 DEFINE_PROP_END_OF_LIST(), 1738 }; 1739 1740 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1741 { 1742 DeviceClass *dc = DEVICE_CLASS(klass); 1743 1744 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1745 dc->realize = pnv_chip_realize; 1746 device_class_set_props(dc, pnv_chip_properties); 1747 dc->desc = "PowerNV Chip"; 1748 } 1749 1750 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1751 { 1752 int i, j; 1753 1754 for (i = 0; i < chip->nr_cores; i++) { 1755 PnvCore *pc = chip->cores[i]; 1756 CPUCore *cc = CPU_CORE(pc); 1757 1758 for (j = 0; j < cc->nr_threads; j++) { 1759 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1760 return pc->threads[j]; 1761 } 1762 } 1763 } 1764 return NULL; 1765 } 1766 1767 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1768 { 1769 PnvMachineState *pnv = PNV_MACHINE(xi); 1770 int i, j; 1771 1772 for (i = 0; i < pnv->num_chips; i++) { 1773 PnvChip *chip = pnv->chips[i]; 1774 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1775 1776 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1777 return &chip8->psi.ics; 1778 } 1779 for (j = 0; j < chip->num_phbs; j++) { 1780 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1781 return &chip8->phbs[j].lsis; 1782 } 1783 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1784 return ICS(&chip8->phbs[j].msis); 1785 } 1786 } 1787 } 1788 return NULL; 1789 } 1790 1791 static void pnv_ics_resend(XICSFabric *xi) 1792 { 1793 PnvMachineState *pnv = PNV_MACHINE(xi); 1794 int i, j; 1795 1796 for (i = 0; i < pnv->num_chips; i++) { 1797 PnvChip *chip = pnv->chips[i]; 1798 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1799 1800 ics_resend(&chip8->psi.ics); 1801 for (j = 0; j < chip->num_phbs; j++) { 1802 ics_resend(&chip8->phbs[j].lsis); 1803 ics_resend(ICS(&chip8->phbs[j].msis)); 1804 } 1805 } 1806 } 1807 1808 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1809 { 1810 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1811 1812 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1813 } 1814 1815 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1816 Monitor *mon) 1817 { 1818 PnvMachineState *pnv = PNV_MACHINE(obj); 1819 int i; 1820 CPUState *cs; 1821 1822 CPU_FOREACH(cs) { 1823 PowerPCCPU *cpu = POWERPC_CPU(cs); 1824 1825 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1826 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1827 mon); 1828 } 1829 1830 for (i = 0; i < pnv->num_chips; i++) { 1831 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1832 } 1833 } 1834 1835 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1836 uint8_t nvt_blk, uint32_t nvt_idx, 1837 bool cam_ignore, uint8_t priority, 1838 uint32_t logic_serv, 1839 XiveTCTXMatch *match) 1840 { 1841 PnvMachineState *pnv = PNV_MACHINE(xfb); 1842 int total_count = 0; 1843 int i; 1844 1845 for (i = 0; i < pnv->num_chips; i++) { 1846 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1847 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1848 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1849 int count; 1850 1851 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1852 priority, logic_serv, match); 1853 1854 if (count < 0) { 1855 return count; 1856 } 1857 1858 total_count += count; 1859 } 1860 1861 return total_count; 1862 } 1863 1864 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1865 { 1866 MachineClass *mc = MACHINE_CLASS(oc); 1867 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1868 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1869 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1870 1871 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1872 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1873 1874 xic->icp_get = pnv_icp_get; 1875 xic->ics_get = pnv_ics_get; 1876 xic->ics_resend = pnv_ics_resend; 1877 1878 pmc->compat = compat; 1879 pmc->compat_size = sizeof(compat); 1880 } 1881 1882 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1883 { 1884 MachineClass *mc = MACHINE_CLASS(oc); 1885 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1886 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1887 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1888 1889 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1890 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1891 xfc->match_nvt = pnv_match_nvt; 1892 1893 mc->alias = "powernv"; 1894 1895 pmc->compat = compat; 1896 pmc->compat_size = sizeof(compat); 1897 pmc->dt_power_mgt = pnv_dt_power_mgt; 1898 } 1899 1900 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1901 { 1902 MachineClass *mc = MACHINE_CLASS(oc); 1903 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1904 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1905 1906 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1907 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1908 1909 pmc->compat = compat; 1910 pmc->compat_size = sizeof(compat); 1911 pmc->dt_power_mgt = pnv_dt_power_mgt; 1912 } 1913 1914 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1915 { 1916 PnvMachineState *pnv = PNV_MACHINE(obj); 1917 1918 return !!pnv->fw_load_addr; 1919 } 1920 1921 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1922 { 1923 PnvMachineState *pnv = PNV_MACHINE(obj); 1924 1925 if (value) { 1926 pnv->fw_load_addr = 0x8000000; 1927 } 1928 } 1929 1930 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 1931 { 1932 PowerPCCPU *cpu = POWERPC_CPU(cs); 1933 CPUPPCState *env = &cpu->env; 1934 1935 cpu_synchronize_state(cs); 1936 ppc_cpu_do_system_reset(cs); 1937 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 1938 /* 1939 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 1940 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 1941 * (PPC_BIT(43)). 1942 */ 1943 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 1944 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 1945 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 1946 } 1947 } else { 1948 /* 1949 * For non-powersave system resets, SRR1[42:45] are defined to be 1950 * implementation-dependent. The POWER9 User Manual specifies that 1951 * an external (SCOM driven, which may come from a BMC nmi command or 1952 * another CPU requesting a NMI IPI) system reset exception should be 1953 * 0b0010 (PPC_BIT(44)). 1954 */ 1955 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 1956 } 1957 } 1958 1959 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 1960 { 1961 CPUState *cs; 1962 1963 CPU_FOREACH(cs) { 1964 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 1965 } 1966 } 1967 1968 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1969 { 1970 MachineClass *mc = MACHINE_CLASS(oc); 1971 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1972 NMIClass *nc = NMI_CLASS(oc); 1973 1974 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1975 mc->init = pnv_init; 1976 mc->reset = pnv_reset; 1977 mc->max_cpus = MAX_CPUS; 1978 /* Pnv provides a AHCI device for storage */ 1979 mc->block_default_type = IF_IDE; 1980 mc->no_parallel = 1; 1981 mc->default_boot_order = NULL; 1982 /* 1983 * RAM defaults to less than 2048 for 32-bit hosts, and large 1984 * enough to fit the maximum initrd size at it's load address 1985 */ 1986 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1987 mc->default_ram_id = "pnv.ram"; 1988 ispc->print_info = pnv_pic_print_info; 1989 nc->nmi_monitor_handler = pnv_nmi; 1990 1991 object_class_property_add_bool(oc, "hb-mode", 1992 pnv_machine_get_hb, pnv_machine_set_hb); 1993 object_class_property_set_description(oc, "hb-mode", 1994 "Use a hostboot like boot loader"); 1995 } 1996 1997 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1998 { \ 1999 .name = type, \ 2000 .class_init = class_initfn, \ 2001 .parent = TYPE_PNV8_CHIP, \ 2002 } 2003 2004 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2005 { \ 2006 .name = type, \ 2007 .class_init = class_initfn, \ 2008 .parent = TYPE_PNV9_CHIP, \ 2009 } 2010 2011 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2012 { \ 2013 .name = type, \ 2014 .class_init = class_initfn, \ 2015 .parent = TYPE_PNV10_CHIP, \ 2016 } 2017 2018 static const TypeInfo types[] = { 2019 { 2020 .name = MACHINE_TYPE_NAME("powernv10"), 2021 .parent = TYPE_PNV_MACHINE, 2022 .class_init = pnv_machine_power10_class_init, 2023 }, 2024 { 2025 .name = MACHINE_TYPE_NAME("powernv9"), 2026 .parent = TYPE_PNV_MACHINE, 2027 .class_init = pnv_machine_power9_class_init, 2028 .interfaces = (InterfaceInfo[]) { 2029 { TYPE_XIVE_FABRIC }, 2030 { }, 2031 }, 2032 }, 2033 { 2034 .name = MACHINE_TYPE_NAME("powernv8"), 2035 .parent = TYPE_PNV_MACHINE, 2036 .class_init = pnv_machine_power8_class_init, 2037 .interfaces = (InterfaceInfo[]) { 2038 { TYPE_XICS_FABRIC }, 2039 { }, 2040 }, 2041 }, 2042 { 2043 .name = TYPE_PNV_MACHINE, 2044 .parent = TYPE_MACHINE, 2045 .abstract = true, 2046 .instance_size = sizeof(PnvMachineState), 2047 .class_init = pnv_machine_class_init, 2048 .class_size = sizeof(PnvMachineClass), 2049 .interfaces = (InterfaceInfo[]) { 2050 { TYPE_INTERRUPT_STATS_PROVIDER }, 2051 { TYPE_NMI }, 2052 { }, 2053 }, 2054 }, 2055 { 2056 .name = TYPE_PNV_CHIP, 2057 .parent = TYPE_SYS_BUS_DEVICE, 2058 .class_init = pnv_chip_class_init, 2059 .instance_size = sizeof(PnvChip), 2060 .class_size = sizeof(PnvChipClass), 2061 .abstract = true, 2062 }, 2063 2064 /* 2065 * P10 chip and variants 2066 */ 2067 { 2068 .name = TYPE_PNV10_CHIP, 2069 .parent = TYPE_PNV_CHIP, 2070 .instance_init = pnv_chip_power10_instance_init, 2071 .instance_size = sizeof(Pnv10Chip), 2072 }, 2073 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2074 2075 /* 2076 * P9 chip and variants 2077 */ 2078 { 2079 .name = TYPE_PNV9_CHIP, 2080 .parent = TYPE_PNV_CHIP, 2081 .instance_init = pnv_chip_power9_instance_init, 2082 .instance_size = sizeof(Pnv9Chip), 2083 }, 2084 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2085 2086 /* 2087 * P8 chip and variants 2088 */ 2089 { 2090 .name = TYPE_PNV8_CHIP, 2091 .parent = TYPE_PNV_CHIP, 2092 .instance_init = pnv_chip_power8_instance_init, 2093 .instance_size = sizeof(Pnv8Chip), 2094 }, 2095 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2096 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2097 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2098 pnv_chip_power8nvl_class_init), 2099 }; 2100 2101 DEFINE_TYPES(types) 2102