1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "sysemu/hw_accel.h" 31 #include "target/ppc/cpu.h" 32 #include "qemu/log.h" 33 #include "hw/ppc/fdt.h" 34 #include "hw/ppc/ppc.h" 35 #include "hw/ppc/pnv.h" 36 #include "hw/ppc/pnv_core.h" 37 #include "hw/loader.h" 38 #include "hw/nmi.h" 39 #include "exec/address-spaces.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 47 #include "hw/ppc/xics.h" 48 #include "hw/qdev-properties.h" 49 #include "hw/ppc/pnv_xscom.h" 50 #include "hw/ppc/pnv_pnor.h" 51 52 #include "hw/isa/isa.h" 53 #include "hw/boards.h" 54 #include "hw/char/serial.h" 55 #include "hw/rtc/mc146818rtc.h" 56 57 #include <libfdt.h> 58 59 #define FDT_MAX_SIZE (1 * MiB) 60 61 #define FW_FILE_NAME "skiboot.lid" 62 #define FW_LOAD_ADDR 0x0 63 #define FW_MAX_SIZE (4 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x20000000 66 #define KERNEL_MAX_SIZE (256 * MiB) 67 #define INITRD_LOAD_ADDR 0x60000000 68 #define INITRD_MAX_SIZE (256 * MiB) 69 70 static const char *pnv_chip_core_typename(const PnvChip *o) 71 { 72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 75 const char *core_type = object_class_get_name(object_class_by_name(s)); 76 g_free(s); 77 return core_type; 78 } 79 80 /* 81 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 82 * 4 * 4 sockets * 12 cores * 8 threads = 1536 83 * Let's make it 2^11 84 */ 85 #define MAX_CPUS 2048 86 87 /* 88 * Memory nodes are created by hostboot, one for each range of memory 89 * that has a different "affinity". In practice, it means one range 90 * per chip. 91 */ 92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 93 { 94 char *mem_name; 95 uint64_t mem_reg_property[2]; 96 int off; 97 98 mem_reg_property[0] = cpu_to_be64(start); 99 mem_reg_property[1] = cpu_to_be64(size); 100 101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 102 off = fdt_add_subnode(fdt, 0, mem_name); 103 g_free(mem_name); 104 105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 107 sizeof(mem_reg_property)))); 108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 109 } 110 111 static int get_cpus_node(void *fdt) 112 { 113 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 114 115 if (cpus_offset < 0) { 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 117 if (cpus_offset) { 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 120 } 121 } 122 _FDT(cpus_offset); 123 return cpus_offset; 124 } 125 126 /* 127 * The PowerNV cores (and threads) need to use real HW ids and not an 128 * incremental index like it has been done on other platforms. This HW 129 * id is stored in the CPU PIR, it is used to create cpu nodes in the 130 * device tree, used in XSCOM to address cores and in interrupt 131 * servers. 132 */ 133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 134 { 135 PowerPCCPU *cpu = pc->threads[0]; 136 CPUState *cs = CPU(cpu); 137 DeviceClass *dc = DEVICE_GET_CLASS(cs); 138 int smt_threads = CPU_CORE(pc)->nr_threads; 139 CPUPPCState *env = &cpu->env; 140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 141 uint32_t servers_prop[smt_threads]; 142 int i; 143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 144 0xffffffff, 0xffffffff}; 145 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 146 uint32_t cpufreq = 1000000000; 147 uint32_t page_sizes_prop[64]; 148 size_t page_sizes_prop_size; 149 const uint8_t pa_features[] = { 24, 0, 150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 154 int offset; 155 char *nodename; 156 int cpus_offset = get_cpus_node(fdt); 157 158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 159 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 160 _FDT(offset); 161 g_free(nodename); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 175 env->icache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 177 env->icache_line_size))); 178 179 if (pcc->l1_dcache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 181 pcc->l1_dcache_size))); 182 } else { 183 warn_report("Unknown L1 dcache size for cpu"); 184 } 185 if (pcc->l1_icache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 187 pcc->l1_icache_size))); 188 } else { 189 warn_report("Unknown L1 icache size for cpu"); 190 } 191 192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 195 cpu->hash64_opts->slb_size))); 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 198 199 if (env->spr_cb[SPR_PURR].oea_read) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 201 } 202 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 205 segs, sizeof(segs)))); 206 } 207 208 /* 209 * Advertise VMX/VSX (vector extensions) if available 210 * 0 / no property == no vector extensions 211 * 1 == VMX / Altivec available 212 * 2 == VSX available 213 */ 214 if (env->insns_flags & PPC_ALTIVEC) { 215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 216 217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 218 } 219 220 /* 221 * Advertise DFP (Decimal Floating Point) if available 222 * 0 / no property == no DFP 223 * 1 == DFP available 224 */ 225 if (env->insns_flags2 & PPC2_DFP) { 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 227 } 228 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 230 sizeof(page_sizes_prop)); 231 if (page_sizes_prop_size) { 232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 233 page_sizes_prop, page_sizes_prop_size))); 234 } 235 236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 237 pa_features, sizeof(pa_features)))); 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pc->pir + i); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(servers_prop)))); 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 248 uint32_t nr_threads) 249 { 250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 251 char *name; 252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 253 uint32_t irange[2], i, rsize; 254 uint64_t *reg; 255 int offset; 256 257 irange[0] = cpu_to_be32(pir); 258 irange[1] = cpu_to_be32(nr_threads); 259 260 rsize = sizeof(uint64_t) * 2 * nr_threads; 261 reg = g_malloc(rsize); 262 for (i = 0; i < nr_threads; i++) { 263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 264 reg[i * 2 + 1] = cpu_to_be64(0x1000); 265 } 266 267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 268 offset = fdt_add_subnode(fdt, 0, name); 269 _FDT(offset); 270 g_free(name); 271 272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 274 _FDT((fdt_setprop_string(fdt, offset, "device_type", 275 "PowerPC-External-Interrupt-Presentation"))); 276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 278 irange, sizeof(irange)))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 281 g_free(reg); 282 } 283 284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 285 { 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 287 int i; 288 289 pnv_dt_xscom(chip, fdt, 0, 290 cpu_to_be64(PNV_XSCOM_BASE(chip)), 291 cpu_to_be64(PNV_XSCOM_SIZE), 292 compat, sizeof(compat)); 293 294 for (i = 0; i < chip->nr_cores; i++) { 295 PnvCore *pnv_core = chip->cores[i]; 296 297 pnv_dt_core(chip, pnv_core, fdt); 298 299 /* Interrupt Control Presenters (ICP). One per core. */ 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 301 } 302 303 if (chip->ram_size) { 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 305 } 306 } 307 308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 309 { 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 311 int i; 312 313 pnv_dt_xscom(chip, fdt, 0, 314 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 315 cpu_to_be64(PNV9_XSCOM_SIZE), 316 compat, sizeof(compat)); 317 318 for (i = 0; i < chip->nr_cores; i++) { 319 PnvCore *pnv_core = chip->cores[i]; 320 321 pnv_dt_core(chip, pnv_core, fdt); 322 } 323 324 if (chip->ram_size) { 325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 326 } 327 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 329 } 330 331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 332 { 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 334 int i; 335 336 pnv_dt_xscom(chip, fdt, 0, 337 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 338 cpu_to_be64(PNV10_XSCOM_SIZE), 339 compat, sizeof(compat)); 340 341 for (i = 0; i < chip->nr_cores; i++) { 342 PnvCore *pnv_core = chip->cores[i]; 343 344 pnv_dt_core(chip, pnv_core, fdt); 345 } 346 347 if (chip->ram_size) { 348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 349 } 350 351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 352 } 353 354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 355 { 356 uint32_t io_base = d->ioport_id; 357 uint32_t io_regs[] = { 358 cpu_to_be32(1), 359 cpu_to_be32(io_base), 360 cpu_to_be32(2) 361 }; 362 char *name; 363 int node; 364 365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 366 node = fdt_add_subnode(fdt, lpc_off, name); 367 _FDT(node); 368 g_free(name); 369 370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 372 } 373 374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 375 { 376 const char compatible[] = "ns16550\0pnpPNP,501"; 377 uint32_t io_base = d->ioport_id; 378 uint32_t io_regs[] = { 379 cpu_to_be32(1), 380 cpu_to_be32(io_base), 381 cpu_to_be32(8) 382 }; 383 char *name; 384 int node; 385 386 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 387 node = fdt_add_subnode(fdt, lpc_off, name); 388 _FDT(node); 389 g_free(name); 390 391 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 392 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 393 sizeof(compatible)))); 394 395 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 396 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 397 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 398 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 399 fdt_get_phandle(fdt, lpc_off)))); 400 401 /* This is needed by Linux */ 402 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 403 } 404 405 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 406 { 407 const char compatible[] = "bt\0ipmi-bt"; 408 uint32_t io_base; 409 uint32_t io_regs[] = { 410 cpu_to_be32(1), 411 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 412 cpu_to_be32(3) 413 }; 414 uint32_t irq; 415 char *name; 416 int node; 417 418 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 419 io_regs[1] = cpu_to_be32(io_base); 420 421 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 422 423 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 424 node = fdt_add_subnode(fdt, lpc_off, name); 425 _FDT(node); 426 g_free(name); 427 428 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 429 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 430 sizeof(compatible)))); 431 432 /* Mark it as reserved to avoid Linux trying to claim it */ 433 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 434 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 435 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 436 fdt_get_phandle(fdt, lpc_off)))); 437 } 438 439 typedef struct ForeachPopulateArgs { 440 void *fdt; 441 int offset; 442 } ForeachPopulateArgs; 443 444 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 445 { 446 ForeachPopulateArgs *args = opaque; 447 ISADevice *d = ISA_DEVICE(dev); 448 449 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 450 pnv_dt_rtc(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 452 pnv_dt_serial(d, args->fdt, args->offset); 453 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 454 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 455 } else { 456 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 457 d->ioport_id); 458 } 459 460 return 0; 461 } 462 463 /* 464 * The default LPC bus of a multichip system is on chip 0. It's 465 * recognized by the firmware (skiboot) using a "primary" property. 466 */ 467 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 468 { 469 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 470 ForeachPopulateArgs args = { 471 .fdt = fdt, 472 .offset = isa_offset, 473 }; 474 uint32_t phandle; 475 476 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 477 478 phandle = qemu_fdt_alloc_phandle(fdt); 479 assert(phandle > 0); 480 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 481 482 /* 483 * ISA devices are not necessarily parented to the ISA bus so we 484 * can not use object_child_foreach() 485 */ 486 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 487 &args); 488 } 489 490 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 491 { 492 int off; 493 494 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 495 off = fdt_add_subnode(fdt, off, "power-mgt"); 496 497 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 498 } 499 500 static void *pnv_dt_create(MachineState *machine) 501 { 502 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 503 PnvMachineState *pnv = PNV_MACHINE(machine); 504 void *fdt; 505 char *buf; 506 int off; 507 int i; 508 509 fdt = g_malloc0(FDT_MAX_SIZE); 510 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 511 512 /* /qemu node */ 513 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 514 515 /* Root node */ 516 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 517 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 518 _FDT((fdt_setprop_string(fdt, 0, "model", 519 "IBM PowerNV (emulated by qemu)"))); 520 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 521 522 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 523 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 524 if (qemu_uuid_set) { 525 _FDT((fdt_property_string(fdt, "system-id", buf))); 526 } 527 g_free(buf); 528 529 off = fdt_add_subnode(fdt, 0, "chosen"); 530 if (machine->kernel_cmdline) { 531 _FDT((fdt_setprop_string(fdt, off, "bootargs", 532 machine->kernel_cmdline))); 533 } 534 535 if (pnv->initrd_size) { 536 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 537 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 538 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 540 &start_prop, sizeof(start_prop)))); 541 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 542 &end_prop, sizeof(end_prop)))); 543 } 544 545 /* Populate device tree for each chip */ 546 for (i = 0; i < pnv->num_chips; i++) { 547 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 548 } 549 550 /* Populate ISA devices on chip 0 */ 551 pnv_dt_isa(pnv, fdt); 552 553 if (pnv->bmc) { 554 pnv_dt_bmc_sensors(pnv->bmc, fdt); 555 } 556 557 /* Create an extra node for power management on machines that support it */ 558 if (pmc->dt_power_mgt) { 559 pmc->dt_power_mgt(pnv, fdt); 560 } 561 562 return fdt; 563 } 564 565 static void pnv_powerdown_notify(Notifier *n, void *opaque) 566 { 567 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 568 569 if (pnv->bmc) { 570 pnv_bmc_powerdown(pnv->bmc); 571 } 572 } 573 574 static void pnv_reset(MachineState *machine) 575 { 576 PnvMachineState *pnv = PNV_MACHINE(machine); 577 IPMIBmc *bmc; 578 void *fdt; 579 580 qemu_devices_reset(); 581 582 /* 583 * The machine should provide by default an internal BMC simulator. 584 * If not, try to use the BMC device that was provided on the command 585 * line. 586 */ 587 bmc = pnv_bmc_find(&error_fatal); 588 if (!pnv->bmc) { 589 if (!bmc) { 590 warn_report("machine has no BMC device. Use '-device " 591 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 592 "to define one"); 593 } else { 594 pnv_bmc_set_pnor(bmc, pnv->pnor); 595 pnv->bmc = bmc; 596 } 597 } 598 599 fdt = pnv_dt_create(machine); 600 601 /* Pack resulting tree */ 602 _FDT((fdt_pack(fdt))); 603 604 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 605 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 606 607 g_free(fdt); 608 } 609 610 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 611 { 612 Pnv8Chip *chip8 = PNV8_CHIP(chip); 613 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 614 } 615 616 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 617 { 618 Pnv8Chip *chip8 = PNV8_CHIP(chip); 619 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 620 } 621 622 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 623 { 624 Pnv9Chip *chip9 = PNV9_CHIP(chip); 625 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 626 } 627 628 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 629 { 630 Pnv10Chip *chip10 = PNV10_CHIP(chip); 631 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 632 } 633 634 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 635 { 636 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 637 } 638 639 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 640 { 641 Pnv8Chip *chip8 = PNV8_CHIP(chip); 642 int i; 643 644 ics_pic_print_info(&chip8->psi.ics, mon); 645 for (i = 0; i < chip->num_phbs; i++) { 646 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 647 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 648 } 649 } 650 651 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 652 { 653 Pnv9Chip *chip9 = PNV9_CHIP(chip); 654 int i, j; 655 656 pnv_xive_pic_print_info(&chip9->xive, mon); 657 pnv_psi_pic_print_info(&chip9->psi, mon); 658 659 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 660 PnvPhb4PecState *pec = &chip9->pecs[i]; 661 for (j = 0; j < pec->num_stacks; j++) { 662 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 663 } 664 } 665 } 666 667 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 668 uint32_t core_id) 669 { 670 return PNV_XSCOM_EX_BASE(core_id); 671 } 672 673 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 674 uint32_t core_id) 675 { 676 return PNV9_XSCOM_EC_BASE(core_id); 677 } 678 679 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 680 uint32_t core_id) 681 { 682 return PNV10_XSCOM_EC_BASE(core_id); 683 } 684 685 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 686 { 687 PowerPCCPUClass *ppc_default = 688 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 689 PowerPCCPUClass *ppc = 690 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 691 692 return ppc_default->pvr_match(ppc_default, ppc->pvr); 693 } 694 695 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 696 { 697 ISADevice *dev = isa_new("isa-ipmi-bt"); 698 699 object_property_set_link(OBJECT(dev), OBJECT(bmc), "bmc", &error_fatal); 700 object_property_set_int(OBJECT(dev), irq, "irq", &error_fatal); 701 isa_realize_and_unref(dev, bus, &error_fatal); 702 } 703 704 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 705 { 706 Pnv10Chip *chip10 = PNV10_CHIP(chip); 707 708 pnv_psi_pic_print_info(&chip10->psi, mon); 709 } 710 711 static void pnv_init(MachineState *machine) 712 { 713 PnvMachineState *pnv = PNV_MACHINE(machine); 714 MachineClass *mc = MACHINE_GET_CLASS(machine); 715 char *fw_filename; 716 long fw_size; 717 int i; 718 char *chip_typename; 719 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 720 DeviceState *dev; 721 722 /* allocate RAM */ 723 if (machine->ram_size < (1 * GiB)) { 724 warn_report("skiboot may not work with < 1GB of RAM"); 725 } 726 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 727 728 /* 729 * Create our simple PNOR device 730 */ 731 dev = qdev_new(TYPE_PNV_PNOR); 732 if (pnor) { 733 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 734 &error_abort); 735 } 736 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 737 pnv->pnor = PNV_PNOR(dev); 738 739 /* load skiboot firmware */ 740 if (bios_name == NULL) { 741 bios_name = FW_FILE_NAME; 742 } 743 744 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 745 if (!fw_filename) { 746 error_report("Could not find OPAL firmware '%s'", bios_name); 747 exit(1); 748 } 749 750 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 751 if (fw_size < 0) { 752 error_report("Could not load OPAL firmware '%s'", fw_filename); 753 exit(1); 754 } 755 g_free(fw_filename); 756 757 /* load kernel */ 758 if (machine->kernel_filename) { 759 long kernel_size; 760 761 kernel_size = load_image_targphys(machine->kernel_filename, 762 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 763 if (kernel_size < 0) { 764 error_report("Could not load kernel '%s'", 765 machine->kernel_filename); 766 exit(1); 767 } 768 } 769 770 /* load initrd */ 771 if (machine->initrd_filename) { 772 pnv->initrd_base = INITRD_LOAD_ADDR; 773 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 774 pnv->initrd_base, INITRD_MAX_SIZE); 775 if (pnv->initrd_size < 0) { 776 error_report("Could not load initial ram disk '%s'", 777 machine->initrd_filename); 778 exit(1); 779 } 780 } 781 782 /* MSIs are supported on this platform */ 783 msi_nonbroken = true; 784 785 /* 786 * Check compatibility of the specified CPU with the machine 787 * default. 788 */ 789 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 790 error_report("invalid CPU model '%s' for %s machine", 791 machine->cpu_type, mc->name); 792 exit(1); 793 } 794 795 /* Create the processor chips */ 796 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 797 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 798 i, machine->cpu_type); 799 if (!object_class_by_name(chip_typename)) { 800 error_report("invalid chip model '%.*s' for %s machine", 801 i, machine->cpu_type, mc->name); 802 exit(1); 803 } 804 805 pnv->num_chips = 806 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 807 /* 808 * TODO: should we decide on how many chips we can create based 809 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 810 */ 811 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 812 error_report("invalid number of chips: '%d'", pnv->num_chips); 813 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 814 exit(1); 815 } 816 817 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 818 for (i = 0; i < pnv->num_chips; i++) { 819 char chip_name[32]; 820 Object *chip = OBJECT(qdev_new(chip_typename)); 821 822 pnv->chips[i] = PNV_CHIP(chip); 823 824 /* 825 * TODO: put all the memory in one node on chip 0 until we find a 826 * way to specify different ranges for each chip 827 */ 828 if (i == 0) { 829 object_property_set_int(chip, machine->ram_size, "ram-size", 830 &error_fatal); 831 } 832 833 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 834 object_property_add_child(OBJECT(pnv), chip_name, chip); 835 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 836 &error_fatal); 837 object_property_set_int(chip, machine->smp.cores, 838 "nr-cores", &error_fatal); 839 object_property_set_int(chip, machine->smp.threads, 840 "nr-threads", &error_fatal); 841 /* 842 * The POWER8 machine use the XICS interrupt interface. 843 * Propagate the XICS fabric to the chip and its controllers. 844 */ 845 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 846 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); 847 } 848 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 849 object_property_set_link(chip, OBJECT(pnv), "xive-fabric", 850 &error_abort); 851 } 852 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 853 } 854 g_free(chip_typename); 855 856 /* Instantiate ISA bus on chip 0 */ 857 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 858 859 /* Create serial port */ 860 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 861 862 /* Create an RTC ISA device too */ 863 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 864 865 /* 866 * Create the machine BMC simulator and the IPMI BT device for 867 * communication with the BMC 868 */ 869 if (defaults_enabled()) { 870 pnv->bmc = pnv_bmc_create(pnv->pnor); 871 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 872 } 873 874 /* 875 * OpenPOWER systems use a IPMI SEL Event message to notify the 876 * host to powerdown 877 */ 878 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 879 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 880 } 881 882 /* 883 * 0:21 Reserved - Read as zeros 884 * 22:24 Chip ID 885 * 25:28 Core number 886 * 29:31 Thread ID 887 */ 888 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 889 { 890 return (chip->chip_id << 7) | (core_id << 3); 891 } 892 893 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 894 Error **errp) 895 { 896 Pnv8Chip *chip8 = PNV8_CHIP(chip); 897 Error *local_err = NULL; 898 Object *obj; 899 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 900 901 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 902 if (local_err) { 903 error_propagate(errp, local_err); 904 return; 905 } 906 907 pnv_cpu->intc = obj; 908 } 909 910 911 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 912 { 913 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 914 915 icp_reset(ICP(pnv_cpu->intc)); 916 } 917 918 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 919 { 920 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 921 922 icp_destroy(ICP(pnv_cpu->intc)); 923 pnv_cpu->intc = NULL; 924 } 925 926 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 927 Monitor *mon) 928 { 929 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 930 } 931 932 /* 933 * 0:48 Reserved - Read as zeroes 934 * 49:52 Node ID 935 * 53:55 Chip ID 936 * 56 Reserved - Read as zero 937 * 57:61 Core number 938 * 62:63 Thread ID 939 * 940 * We only care about the lower bits. uint32_t is fine for the moment. 941 */ 942 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 943 { 944 return (chip->chip_id << 8) | (core_id << 2); 945 } 946 947 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 948 { 949 return (chip->chip_id << 8) | (core_id << 2); 950 } 951 952 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 953 Error **errp) 954 { 955 Pnv9Chip *chip9 = PNV9_CHIP(chip); 956 Error *local_err = NULL; 957 Object *obj; 958 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 959 960 /* 961 * The core creates its interrupt presenter but the XIVE interrupt 962 * controller object is initialized afterwards. Hopefully, it's 963 * only used at runtime. 964 */ 965 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 966 &local_err); 967 if (local_err) { 968 error_propagate(errp, local_err); 969 return; 970 } 971 972 pnv_cpu->intc = obj; 973 } 974 975 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 976 { 977 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 978 979 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 980 } 981 982 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 983 { 984 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 985 986 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 987 pnv_cpu->intc = NULL; 988 } 989 990 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 991 Monitor *mon) 992 { 993 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 994 } 995 996 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 997 Error **errp) 998 { 999 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1000 1001 /* Will be defined when the interrupt controller is */ 1002 pnv_cpu->intc = NULL; 1003 } 1004 1005 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1006 { 1007 ; 1008 } 1009 1010 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1011 { 1012 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1013 1014 pnv_cpu->intc = NULL; 1015 } 1016 1017 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1018 Monitor *mon) 1019 { 1020 } 1021 1022 /* 1023 * Allowed core identifiers on a POWER8 Processor Chip : 1024 * 1025 * <EX0 reserved> 1026 * EX1 - Venice only 1027 * EX2 - Venice only 1028 * EX3 - Venice only 1029 * EX4 1030 * EX5 1031 * EX6 1032 * <EX7,8 reserved> <reserved> 1033 * EX9 - Venice only 1034 * EX10 - Venice only 1035 * EX11 - Venice only 1036 * EX12 1037 * EX13 1038 * EX14 1039 * <EX15 reserved> 1040 */ 1041 #define POWER8E_CORE_MASK (0x7070ull) 1042 #define POWER8_CORE_MASK (0x7e7eull) 1043 1044 /* 1045 * POWER9 has 24 cores, ids starting at 0x0 1046 */ 1047 #define POWER9_CORE_MASK (0xffffffffffffffull) 1048 1049 1050 #define POWER10_CORE_MASK (0xffffffffffffffull) 1051 1052 static void pnv_chip_power8_instance_init(Object *obj) 1053 { 1054 PnvChip *chip = PNV_CHIP(obj); 1055 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1056 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1057 int i; 1058 1059 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1060 (Object **)&chip8->xics, 1061 object_property_allow_set_link, 1062 OBJ_PROP_LINK_STRONG); 1063 1064 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1065 1066 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1067 1068 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1069 1070 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1071 1072 for (i = 0; i < pcc->num_phbs; i++) { 1073 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1074 } 1075 1076 /* 1077 * Number of PHBs is the chip default 1078 */ 1079 chip->num_phbs = pcc->num_phbs; 1080 } 1081 1082 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1083 { 1084 PnvChip *chip = PNV_CHIP(chip8); 1085 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1086 int i, j; 1087 char *name; 1088 1089 name = g_strdup_printf("icp-%x", chip->chip_id); 1090 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1091 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1092 g_free(name); 1093 1094 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1095 1096 /* Map the ICP registers for each thread */ 1097 for (i = 0; i < chip->nr_cores; i++) { 1098 PnvCore *pnv_core = chip->cores[i]; 1099 int core_hwid = CPU_CORE(pnv_core)->core_id; 1100 1101 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1102 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1103 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1104 1105 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1106 &icp->mmio); 1107 } 1108 } 1109 } 1110 1111 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1112 { 1113 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1114 PnvChip *chip = PNV_CHIP(dev); 1115 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1116 Pnv8Psi *psi8 = &chip8->psi; 1117 Error *local_err = NULL; 1118 int i; 1119 1120 assert(chip8->xics); 1121 1122 /* XSCOM bridge is first */ 1123 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1124 if (local_err) { 1125 error_propagate(errp, local_err); 1126 return; 1127 } 1128 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1129 1130 pcc->parent_realize(dev, &local_err); 1131 if (local_err) { 1132 error_propagate(errp, local_err); 1133 return; 1134 } 1135 1136 /* Processor Service Interface (PSI) Host Bridge */ 1137 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1138 "bar", &error_fatal); 1139 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), 1140 ICS_PROP_XICS, &error_abort); 1141 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 1142 if (local_err) { 1143 error_propagate(errp, local_err); 1144 return; 1145 } 1146 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1147 &PNV_PSI(psi8)->xscom_regs); 1148 1149 /* Create LPC controller */ 1150 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1151 &error_abort); 1152 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 1153 &error_fatal); 1154 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1155 1156 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1157 (uint64_t) PNV_XSCOM_BASE(chip), 1158 PNV_XSCOM_LPC_BASE); 1159 1160 /* 1161 * Interrupt Management Area. This is the memory region holding 1162 * all the Interrupt Control Presenter (ICP) registers 1163 */ 1164 pnv_chip_icp_realize(chip8, &local_err); 1165 if (local_err) { 1166 error_propagate(errp, local_err); 1167 return; 1168 } 1169 1170 /* Create the simplified OCC model */ 1171 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1172 &error_abort); 1173 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1174 if (local_err) { 1175 error_propagate(errp, local_err); 1176 return; 1177 } 1178 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1179 1180 /* OCC SRAM model */ 1181 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1182 &chip8->occ.sram_regs); 1183 1184 /* HOMER */ 1185 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1186 &error_abort); 1187 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1188 &local_err); 1189 if (local_err) { 1190 error_propagate(errp, local_err); 1191 return; 1192 } 1193 /* Homer Xscom region */ 1194 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1195 1196 /* Homer mmio region */ 1197 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1198 &chip8->homer.regs); 1199 1200 /* PHB3 controllers */ 1201 for (i = 0; i < chip->num_phbs; i++) { 1202 PnvPHB3 *phb = &chip8->phbs[i]; 1203 PnvPBCQState *pbcq = &phb->pbcq; 1204 1205 object_property_set_int(OBJECT(phb), i, "index", &error_fatal); 1206 object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id", 1207 &error_fatal); 1208 sysbus_realize(SYS_BUS_DEVICE(phb), &local_err); 1209 if (local_err) { 1210 error_propagate(errp, local_err); 1211 return; 1212 } 1213 1214 /* Populate the XSCOM address space. */ 1215 pnv_xscom_add_subregion(chip, 1216 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1217 &pbcq->xscom_nest_regs); 1218 pnv_xscom_add_subregion(chip, 1219 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1220 &pbcq->xscom_pci_regs); 1221 pnv_xscom_add_subregion(chip, 1222 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1223 &pbcq->xscom_spci_regs); 1224 } 1225 } 1226 1227 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1228 { 1229 addr &= (PNV_XSCOM_SIZE - 1); 1230 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1231 } 1232 1233 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1234 { 1235 DeviceClass *dc = DEVICE_CLASS(klass); 1236 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1237 1238 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1239 k->cores_mask = POWER8E_CORE_MASK; 1240 k->num_phbs = 3; 1241 k->core_pir = pnv_chip_core_pir_p8; 1242 k->intc_create = pnv_chip_power8_intc_create; 1243 k->intc_reset = pnv_chip_power8_intc_reset; 1244 k->intc_destroy = pnv_chip_power8_intc_destroy; 1245 k->intc_print_info = pnv_chip_power8_intc_print_info; 1246 k->isa_create = pnv_chip_power8_isa_create; 1247 k->dt_populate = pnv_chip_power8_dt_populate; 1248 k->pic_print_info = pnv_chip_power8_pic_print_info; 1249 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1250 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1251 dc->desc = "PowerNV Chip POWER8E"; 1252 1253 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1254 &k->parent_realize); 1255 } 1256 1257 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1258 { 1259 DeviceClass *dc = DEVICE_CLASS(klass); 1260 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1261 1262 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1263 k->cores_mask = POWER8_CORE_MASK; 1264 k->num_phbs = 3; 1265 k->core_pir = pnv_chip_core_pir_p8; 1266 k->intc_create = pnv_chip_power8_intc_create; 1267 k->intc_reset = pnv_chip_power8_intc_reset; 1268 k->intc_destroy = pnv_chip_power8_intc_destroy; 1269 k->intc_print_info = pnv_chip_power8_intc_print_info; 1270 k->isa_create = pnv_chip_power8_isa_create; 1271 k->dt_populate = pnv_chip_power8_dt_populate; 1272 k->pic_print_info = pnv_chip_power8_pic_print_info; 1273 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1274 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1275 dc->desc = "PowerNV Chip POWER8"; 1276 1277 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1278 &k->parent_realize); 1279 } 1280 1281 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1282 { 1283 DeviceClass *dc = DEVICE_CLASS(klass); 1284 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1285 1286 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1287 k->cores_mask = POWER8_CORE_MASK; 1288 k->num_phbs = 3; 1289 k->core_pir = pnv_chip_core_pir_p8; 1290 k->intc_create = pnv_chip_power8_intc_create; 1291 k->intc_reset = pnv_chip_power8_intc_reset; 1292 k->intc_destroy = pnv_chip_power8_intc_destroy; 1293 k->intc_print_info = pnv_chip_power8_intc_print_info; 1294 k->isa_create = pnv_chip_power8nvl_isa_create; 1295 k->dt_populate = pnv_chip_power8_dt_populate; 1296 k->pic_print_info = pnv_chip_power8_pic_print_info; 1297 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1298 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1299 dc->desc = "PowerNV Chip POWER8NVL"; 1300 1301 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1302 &k->parent_realize); 1303 } 1304 1305 static void pnv_chip_power9_instance_init(Object *obj) 1306 { 1307 PnvChip *chip = PNV_CHIP(obj); 1308 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1309 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1310 int i; 1311 1312 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1313 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1314 "xive-fabric"); 1315 1316 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1317 1318 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1319 1320 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1321 1322 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1323 1324 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1325 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1326 TYPE_PNV_PHB4_PEC); 1327 } 1328 1329 /* 1330 * Number of PHBs is the chip default 1331 */ 1332 chip->num_phbs = pcc->num_phbs; 1333 } 1334 1335 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1336 { 1337 PnvChip *chip = PNV_CHIP(chip9); 1338 int i; 1339 1340 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1341 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1342 1343 for (i = 0; i < chip9->nr_quads; i++) { 1344 char eq_name[32]; 1345 PnvQuad *eq = &chip9->quads[i]; 1346 PnvCore *pnv_core = chip->cores[i * 4]; 1347 int core_id = CPU_CORE(pnv_core)->core_id; 1348 1349 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1350 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1351 sizeof(*eq), TYPE_PNV_QUAD, 1352 &error_fatal, NULL); 1353 1354 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1355 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1356 1357 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1358 &eq->xscom_regs); 1359 } 1360 } 1361 1362 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1363 { 1364 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1365 Error *local_err = NULL; 1366 int i, j; 1367 int phb_id = 0; 1368 1369 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1370 PnvPhb4PecState *pec = &chip9->pecs[i]; 1371 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1372 uint32_t pec_nest_base; 1373 uint32_t pec_pci_base; 1374 1375 object_property_set_int(OBJECT(pec), i, "index", &error_fatal); 1376 /* 1377 * PEC0 -> 1 stack 1378 * PEC1 -> 2 stacks 1379 * PEC2 -> 3 stacks 1380 */ 1381 object_property_set_int(OBJECT(pec), i + 1, "num-stacks", 1382 &error_fatal); 1383 object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id", 1384 &error_fatal); 1385 object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()), 1386 "system-memory", &error_abort); 1387 object_property_set_bool(OBJECT(pec), true, "realized", &local_err); 1388 if (local_err) { 1389 error_propagate(errp, local_err); 1390 return; 1391 } 1392 1393 pec_nest_base = pecc->xscom_nest_base(pec); 1394 pec_pci_base = pecc->xscom_pci_base(pec); 1395 1396 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1397 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1398 1399 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1400 j++, phb_id++) { 1401 PnvPhb4PecStack *stack = &pec->stacks[j]; 1402 Object *obj = OBJECT(&stack->phb); 1403 1404 object_property_set_int(obj, phb_id, "index", &error_fatal); 1405 object_property_set_int(obj, chip->chip_id, "chip-id", 1406 &error_fatal); 1407 object_property_set_int(obj, PNV_PHB4_VERSION, "version", 1408 &error_fatal); 1409 object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id", 1410 &error_fatal); 1411 object_property_set_link(obj, OBJECT(stack), "stack", &error_abort); 1412 sysbus_realize(SYS_BUS_DEVICE(obj), &local_err); 1413 if (local_err) { 1414 error_propagate(errp, local_err); 1415 return; 1416 } 1417 1418 /* Populate the XSCOM address space. */ 1419 pnv_xscom_add_subregion(chip, 1420 pec_nest_base + 0x40 * (stack->stack_no + 1), 1421 &stack->nest_regs_mr); 1422 pnv_xscom_add_subregion(chip, 1423 pec_pci_base + 0x40 * (stack->stack_no + 1), 1424 &stack->pci_regs_mr); 1425 pnv_xscom_add_subregion(chip, 1426 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1427 0x40 * stack->stack_no, 1428 &stack->phb_regs_mr); 1429 } 1430 } 1431 } 1432 1433 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1434 { 1435 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1436 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1437 PnvChip *chip = PNV_CHIP(dev); 1438 Pnv9Psi *psi9 = &chip9->psi; 1439 Error *local_err = NULL; 1440 1441 /* XSCOM bridge is first */ 1442 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1443 if (local_err) { 1444 error_propagate(errp, local_err); 1445 return; 1446 } 1447 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1448 1449 pcc->parent_realize(dev, &local_err); 1450 if (local_err) { 1451 error_propagate(errp, local_err); 1452 return; 1453 } 1454 1455 pnv_chip_quad_realize(chip9, &local_err); 1456 if (local_err) { 1457 error_propagate(errp, local_err); 1458 return; 1459 } 1460 1461 /* XIVE interrupt controller (POWER9) */ 1462 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1463 "ic-bar", &error_fatal); 1464 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1465 "vc-bar", &error_fatal); 1466 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1467 "pc-bar", &error_fatal); 1468 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1469 "tm-bar", &error_fatal); 1470 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1471 &error_abort); 1472 sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), &local_err); 1473 if (local_err) { 1474 error_propagate(errp, local_err); 1475 return; 1476 } 1477 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1478 &chip9->xive.xscom_regs); 1479 1480 /* Processor Service Interface (PSI) Host Bridge */ 1481 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1482 "bar", &error_fatal); 1483 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1484 if (local_err) { 1485 error_propagate(errp, local_err); 1486 return; 1487 } 1488 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1489 &PNV_PSI(psi9)->xscom_regs); 1490 1491 /* LPC */ 1492 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1493 &error_abort); 1494 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1495 if (local_err) { 1496 error_propagate(errp, local_err); 1497 return; 1498 } 1499 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1500 &chip9->lpc.xscom_regs); 1501 1502 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1503 (uint64_t) PNV9_LPCM_BASE(chip)); 1504 1505 /* Create the simplified OCC model */ 1506 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1507 &error_abort); 1508 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1509 if (local_err) { 1510 error_propagate(errp, local_err); 1511 return; 1512 } 1513 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1514 1515 /* OCC SRAM model */ 1516 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1517 &chip9->occ.sram_regs); 1518 1519 /* HOMER */ 1520 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1521 &error_abort); 1522 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1523 &local_err); 1524 if (local_err) { 1525 error_propagate(errp, local_err); 1526 return; 1527 } 1528 /* Homer Xscom region */ 1529 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1530 1531 /* Homer mmio region */ 1532 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1533 &chip9->homer.regs); 1534 1535 /* PHBs */ 1536 pnv_chip_power9_phb_realize(chip, &local_err); 1537 if (local_err) { 1538 error_propagate(errp, local_err); 1539 return; 1540 } 1541 } 1542 1543 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1544 { 1545 addr &= (PNV9_XSCOM_SIZE - 1); 1546 return addr >> 3; 1547 } 1548 1549 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1550 { 1551 DeviceClass *dc = DEVICE_CLASS(klass); 1552 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1553 1554 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1555 k->cores_mask = POWER9_CORE_MASK; 1556 k->core_pir = pnv_chip_core_pir_p9; 1557 k->intc_create = pnv_chip_power9_intc_create; 1558 k->intc_reset = pnv_chip_power9_intc_reset; 1559 k->intc_destroy = pnv_chip_power9_intc_destroy; 1560 k->intc_print_info = pnv_chip_power9_intc_print_info; 1561 k->isa_create = pnv_chip_power9_isa_create; 1562 k->dt_populate = pnv_chip_power9_dt_populate; 1563 k->pic_print_info = pnv_chip_power9_pic_print_info; 1564 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1565 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1566 dc->desc = "PowerNV Chip POWER9"; 1567 k->num_phbs = 6; 1568 1569 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1570 &k->parent_realize); 1571 } 1572 1573 static void pnv_chip_power10_instance_init(Object *obj) 1574 { 1575 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1576 1577 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1578 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1579 } 1580 1581 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1582 { 1583 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1584 PnvChip *chip = PNV_CHIP(dev); 1585 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1586 Error *local_err = NULL; 1587 1588 /* XSCOM bridge is first */ 1589 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1590 if (local_err) { 1591 error_propagate(errp, local_err); 1592 return; 1593 } 1594 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1595 1596 pcc->parent_realize(dev, &local_err); 1597 if (local_err) { 1598 error_propagate(errp, local_err); 1599 return; 1600 } 1601 1602 /* Processor Service Interface (PSI) Host Bridge */ 1603 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1604 "bar", &error_fatal); 1605 object_property_set_bool(OBJECT(&chip10->psi), true, "realized", 1606 &local_err); 1607 if (local_err) { 1608 error_propagate(errp, local_err); 1609 return; 1610 } 1611 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1612 &PNV_PSI(&chip10->psi)->xscom_regs); 1613 1614 /* LPC */ 1615 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1616 &error_abort); 1617 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", 1618 &local_err); 1619 if (local_err) { 1620 error_propagate(errp, local_err); 1621 return; 1622 } 1623 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1624 &chip10->lpc.xscom_regs); 1625 1626 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1627 (uint64_t) PNV10_LPCM_BASE(chip)); 1628 } 1629 1630 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1631 { 1632 addr &= (PNV10_XSCOM_SIZE - 1); 1633 return addr >> 3; 1634 } 1635 1636 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1637 { 1638 DeviceClass *dc = DEVICE_CLASS(klass); 1639 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1640 1641 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1642 k->cores_mask = POWER10_CORE_MASK; 1643 k->core_pir = pnv_chip_core_pir_p10; 1644 k->intc_create = pnv_chip_power10_intc_create; 1645 k->intc_reset = pnv_chip_power10_intc_reset; 1646 k->intc_destroy = pnv_chip_power10_intc_destroy; 1647 k->intc_print_info = pnv_chip_power10_intc_print_info; 1648 k->isa_create = pnv_chip_power10_isa_create; 1649 k->dt_populate = pnv_chip_power10_dt_populate; 1650 k->pic_print_info = pnv_chip_power10_pic_print_info; 1651 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1652 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1653 dc->desc = "PowerNV Chip POWER10"; 1654 1655 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1656 &k->parent_realize); 1657 } 1658 1659 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1660 { 1661 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1662 int cores_max; 1663 1664 /* 1665 * No custom mask for this chip, let's use the default one from * 1666 * the chip class 1667 */ 1668 if (!chip->cores_mask) { 1669 chip->cores_mask = pcc->cores_mask; 1670 } 1671 1672 /* filter alien core ids ! some are reserved */ 1673 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1674 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1675 chip->cores_mask); 1676 return; 1677 } 1678 chip->cores_mask &= pcc->cores_mask; 1679 1680 /* now that we have a sane layout, let check the number of cores */ 1681 cores_max = ctpop64(chip->cores_mask); 1682 if (chip->nr_cores > cores_max) { 1683 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1684 cores_max); 1685 return; 1686 } 1687 } 1688 1689 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1690 { 1691 Error *error = NULL; 1692 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1693 const char *typename = pnv_chip_core_typename(chip); 1694 int i, core_hwid; 1695 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1696 1697 if (!object_class_by_name(typename)) { 1698 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1699 return; 1700 } 1701 1702 /* Cores */ 1703 pnv_chip_core_sanitize(chip, &error); 1704 if (error) { 1705 error_propagate(errp, error); 1706 return; 1707 } 1708 1709 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1710 1711 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1712 && (i < chip->nr_cores); core_hwid++) { 1713 char core_name[32]; 1714 PnvCore *pnv_core; 1715 uint64_t xscom_core_base; 1716 1717 if (!(chip->cores_mask & (1ull << core_hwid))) { 1718 continue; 1719 } 1720 1721 pnv_core = PNV_CORE(object_new(typename)); 1722 1723 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1724 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1725 chip->cores[i] = pnv_core; 1726 object_property_set_int(OBJECT(pnv_core), chip->nr_threads, 1727 "nr-threads", &error_fatal); 1728 object_property_set_int(OBJECT(pnv_core), core_hwid, 1729 CPU_CORE_PROP_CORE_ID, &error_fatal); 1730 object_property_set_int(OBJECT(pnv_core), 1731 pcc->core_pir(chip, core_hwid), 1732 "pir", &error_fatal); 1733 object_property_set_int(OBJECT(pnv_core), pnv->fw_load_addr, 1734 "hrmor", &error_fatal); 1735 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1736 &error_abort); 1737 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1738 &error_fatal); 1739 1740 /* Each core has an XSCOM MMIO region */ 1741 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1742 1743 pnv_xscom_add_subregion(chip, xscom_core_base, 1744 &pnv_core->xscom_regs); 1745 i++; 1746 } 1747 } 1748 1749 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1750 { 1751 PnvChip *chip = PNV_CHIP(dev); 1752 Error *error = NULL; 1753 1754 /* Cores */ 1755 pnv_chip_core_realize(chip, &error); 1756 if (error) { 1757 error_propagate(errp, error); 1758 return; 1759 } 1760 } 1761 1762 static Property pnv_chip_properties[] = { 1763 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1764 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1765 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1766 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1767 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1768 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1769 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1770 DEFINE_PROP_END_OF_LIST(), 1771 }; 1772 1773 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1774 { 1775 DeviceClass *dc = DEVICE_CLASS(klass); 1776 1777 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1778 dc->realize = pnv_chip_realize; 1779 device_class_set_props(dc, pnv_chip_properties); 1780 dc->desc = "PowerNV Chip"; 1781 } 1782 1783 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1784 { 1785 int i, j; 1786 1787 for (i = 0; i < chip->nr_cores; i++) { 1788 PnvCore *pc = chip->cores[i]; 1789 CPUCore *cc = CPU_CORE(pc); 1790 1791 for (j = 0; j < cc->nr_threads; j++) { 1792 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1793 return pc->threads[j]; 1794 } 1795 } 1796 } 1797 return NULL; 1798 } 1799 1800 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1801 { 1802 PnvMachineState *pnv = PNV_MACHINE(xi); 1803 int i, j; 1804 1805 for (i = 0; i < pnv->num_chips; i++) { 1806 PnvChip *chip = pnv->chips[i]; 1807 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1808 1809 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1810 return &chip8->psi.ics; 1811 } 1812 for (j = 0; j < chip->num_phbs; j++) { 1813 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1814 return &chip8->phbs[j].lsis; 1815 } 1816 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1817 return ICS(&chip8->phbs[j].msis); 1818 } 1819 } 1820 } 1821 return NULL; 1822 } 1823 1824 static void pnv_ics_resend(XICSFabric *xi) 1825 { 1826 PnvMachineState *pnv = PNV_MACHINE(xi); 1827 int i, j; 1828 1829 for (i = 0; i < pnv->num_chips; i++) { 1830 PnvChip *chip = pnv->chips[i]; 1831 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1832 1833 ics_resend(&chip8->psi.ics); 1834 for (j = 0; j < chip->num_phbs; j++) { 1835 ics_resend(&chip8->phbs[j].lsis); 1836 ics_resend(ICS(&chip8->phbs[j].msis)); 1837 } 1838 } 1839 } 1840 1841 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1842 { 1843 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1844 1845 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1846 } 1847 1848 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1849 Monitor *mon) 1850 { 1851 PnvMachineState *pnv = PNV_MACHINE(obj); 1852 int i; 1853 CPUState *cs; 1854 1855 CPU_FOREACH(cs) { 1856 PowerPCCPU *cpu = POWERPC_CPU(cs); 1857 1858 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1859 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1860 mon); 1861 } 1862 1863 for (i = 0; i < pnv->num_chips; i++) { 1864 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1865 } 1866 } 1867 1868 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1869 uint8_t nvt_blk, uint32_t nvt_idx, 1870 bool cam_ignore, uint8_t priority, 1871 uint32_t logic_serv, 1872 XiveTCTXMatch *match) 1873 { 1874 PnvMachineState *pnv = PNV_MACHINE(xfb); 1875 int total_count = 0; 1876 int i; 1877 1878 for (i = 0; i < pnv->num_chips; i++) { 1879 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1880 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1881 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1882 int count; 1883 1884 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1885 priority, logic_serv, match); 1886 1887 if (count < 0) { 1888 return count; 1889 } 1890 1891 total_count += count; 1892 } 1893 1894 return total_count; 1895 } 1896 1897 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1898 { 1899 MachineClass *mc = MACHINE_CLASS(oc); 1900 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1901 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1902 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1903 1904 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1905 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1906 1907 xic->icp_get = pnv_icp_get; 1908 xic->ics_get = pnv_ics_get; 1909 xic->ics_resend = pnv_ics_resend; 1910 1911 pmc->compat = compat; 1912 pmc->compat_size = sizeof(compat); 1913 } 1914 1915 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1916 { 1917 MachineClass *mc = MACHINE_CLASS(oc); 1918 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1919 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1920 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1921 1922 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1923 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1924 xfc->match_nvt = pnv_match_nvt; 1925 1926 mc->alias = "powernv"; 1927 1928 pmc->compat = compat; 1929 pmc->compat_size = sizeof(compat); 1930 pmc->dt_power_mgt = pnv_dt_power_mgt; 1931 } 1932 1933 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1934 { 1935 MachineClass *mc = MACHINE_CLASS(oc); 1936 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1937 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1938 1939 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1940 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1941 1942 pmc->compat = compat; 1943 pmc->compat_size = sizeof(compat); 1944 pmc->dt_power_mgt = pnv_dt_power_mgt; 1945 } 1946 1947 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1948 { 1949 PnvMachineState *pnv = PNV_MACHINE(obj); 1950 1951 return !!pnv->fw_load_addr; 1952 } 1953 1954 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1955 { 1956 PnvMachineState *pnv = PNV_MACHINE(obj); 1957 1958 if (value) { 1959 pnv->fw_load_addr = 0x8000000; 1960 } 1961 } 1962 1963 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 1964 { 1965 PowerPCCPU *cpu = POWERPC_CPU(cs); 1966 CPUPPCState *env = &cpu->env; 1967 1968 cpu_synchronize_state(cs); 1969 ppc_cpu_do_system_reset(cs); 1970 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 1971 /* 1972 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 1973 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 1974 * (PPC_BIT(43)). 1975 */ 1976 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 1977 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 1978 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 1979 } 1980 } else { 1981 /* 1982 * For non-powersave system resets, SRR1[42:45] are defined to be 1983 * implementation-dependent. The POWER9 User Manual specifies that 1984 * an external (SCOM driven, which may come from a BMC nmi command or 1985 * another CPU requesting a NMI IPI) system reset exception should be 1986 * 0b0010 (PPC_BIT(44)). 1987 */ 1988 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 1989 } 1990 } 1991 1992 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 1993 { 1994 CPUState *cs; 1995 1996 CPU_FOREACH(cs) { 1997 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 1998 } 1999 } 2000 2001 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2002 { 2003 MachineClass *mc = MACHINE_CLASS(oc); 2004 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2005 NMIClass *nc = NMI_CLASS(oc); 2006 2007 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2008 mc->init = pnv_init; 2009 mc->reset = pnv_reset; 2010 mc->max_cpus = MAX_CPUS; 2011 /* Pnv provides a AHCI device for storage */ 2012 mc->block_default_type = IF_IDE; 2013 mc->no_parallel = 1; 2014 mc->default_boot_order = NULL; 2015 /* 2016 * RAM defaults to less than 2048 for 32-bit hosts, and large 2017 * enough to fit the maximum initrd size at it's load address 2018 */ 2019 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 2020 mc->default_ram_id = "pnv.ram"; 2021 ispc->print_info = pnv_pic_print_info; 2022 nc->nmi_monitor_handler = pnv_nmi; 2023 2024 object_class_property_add_bool(oc, "hb-mode", 2025 pnv_machine_get_hb, pnv_machine_set_hb); 2026 object_class_property_set_description(oc, "hb-mode", 2027 "Use a hostboot like boot loader"); 2028 } 2029 2030 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2031 { \ 2032 .name = type, \ 2033 .class_init = class_initfn, \ 2034 .parent = TYPE_PNV8_CHIP, \ 2035 } 2036 2037 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2038 { \ 2039 .name = type, \ 2040 .class_init = class_initfn, \ 2041 .parent = TYPE_PNV9_CHIP, \ 2042 } 2043 2044 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2045 { \ 2046 .name = type, \ 2047 .class_init = class_initfn, \ 2048 .parent = TYPE_PNV10_CHIP, \ 2049 } 2050 2051 static const TypeInfo types[] = { 2052 { 2053 .name = MACHINE_TYPE_NAME("powernv10"), 2054 .parent = TYPE_PNV_MACHINE, 2055 .class_init = pnv_machine_power10_class_init, 2056 }, 2057 { 2058 .name = MACHINE_TYPE_NAME("powernv9"), 2059 .parent = TYPE_PNV_MACHINE, 2060 .class_init = pnv_machine_power9_class_init, 2061 .interfaces = (InterfaceInfo[]) { 2062 { TYPE_XIVE_FABRIC }, 2063 { }, 2064 }, 2065 }, 2066 { 2067 .name = MACHINE_TYPE_NAME("powernv8"), 2068 .parent = TYPE_PNV_MACHINE, 2069 .class_init = pnv_machine_power8_class_init, 2070 .interfaces = (InterfaceInfo[]) { 2071 { TYPE_XICS_FABRIC }, 2072 { }, 2073 }, 2074 }, 2075 { 2076 .name = TYPE_PNV_MACHINE, 2077 .parent = TYPE_MACHINE, 2078 .abstract = true, 2079 .instance_size = sizeof(PnvMachineState), 2080 .class_init = pnv_machine_class_init, 2081 .class_size = sizeof(PnvMachineClass), 2082 .interfaces = (InterfaceInfo[]) { 2083 { TYPE_INTERRUPT_STATS_PROVIDER }, 2084 { TYPE_NMI }, 2085 { }, 2086 }, 2087 }, 2088 { 2089 .name = TYPE_PNV_CHIP, 2090 .parent = TYPE_SYS_BUS_DEVICE, 2091 .class_init = pnv_chip_class_init, 2092 .instance_size = sizeof(PnvChip), 2093 .class_size = sizeof(PnvChipClass), 2094 .abstract = true, 2095 }, 2096 2097 /* 2098 * P10 chip and variants 2099 */ 2100 { 2101 .name = TYPE_PNV10_CHIP, 2102 .parent = TYPE_PNV_CHIP, 2103 .instance_init = pnv_chip_power10_instance_init, 2104 .instance_size = sizeof(Pnv10Chip), 2105 }, 2106 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2107 2108 /* 2109 * P9 chip and variants 2110 */ 2111 { 2112 .name = TYPE_PNV9_CHIP, 2113 .parent = TYPE_PNV_CHIP, 2114 .instance_init = pnv_chip_power9_instance_init, 2115 .instance_size = sizeof(Pnv9Chip), 2116 }, 2117 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2118 2119 /* 2120 * P8 chip and variants 2121 */ 2122 { 2123 .name = TYPE_PNV8_CHIP, 2124 .parent = TYPE_PNV_CHIP, 2125 .instance_init = pnv_chip_power8_instance_init, 2126 .instance_size = sizeof(Pnv8Chip), 2127 }, 2128 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2129 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2130 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2131 pnv_chip_power8nvl_class_init), 2132 }; 2133 2134 DEFINE_TYPES(types) 2135