1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "qapi/type-helpers.h" 42 #include "monitor/monitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 #include "hw/pci-host/pnv_phb.h" 48 #include "hw/pci-host/pnv_phb3.h" 49 #include "hw/pci-host/pnv_phb4.h" 50 51 #include "hw/ppc/xics.h" 52 #include "hw/qdev-properties.h" 53 #include "hw/ppc/pnv_chip.h" 54 #include "hw/ppc/pnv_xscom.h" 55 #include "hw/ppc/pnv_pnor.h" 56 57 #include "hw/isa/isa.h" 58 #include "hw/char/serial.h" 59 #include "hw/rtc/mc146818rtc.h" 60 61 #include <libfdt.h> 62 63 #define FDT_MAX_SIZE (1 * MiB) 64 65 #define FW_FILE_NAME "skiboot.lid" 66 #define FW_LOAD_ADDR 0x0 67 #define FW_MAX_SIZE (16 * MiB) 68 69 #define KERNEL_LOAD_ADDR 0x20000000 70 #define KERNEL_MAX_SIZE (128 * MiB) 71 #define INITRD_LOAD_ADDR 0x28000000 72 #define INITRD_MAX_SIZE (128 * MiB) 73 74 static const char *pnv_chip_core_typename(const PnvChip *o) 75 { 76 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 77 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 78 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 79 const char *core_type = object_class_get_name(object_class_by_name(s)); 80 g_free(s); 81 return core_type; 82 } 83 84 /* 85 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 86 * 4 * 4 sockets * 12 cores * 8 threads = 1536 87 * Let's make it 2^11 88 */ 89 #define MAX_CPUS 2048 90 91 /* 92 * Memory nodes are created by hostboot, one for each range of memory 93 * that has a different "affinity". In practice, it means one range 94 * per chip. 95 */ 96 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 97 { 98 char *mem_name; 99 uint64_t mem_reg_property[2]; 100 int off; 101 102 mem_reg_property[0] = cpu_to_be64(start); 103 mem_reg_property[1] = cpu_to_be64(size); 104 105 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 106 off = fdt_add_subnode(fdt, 0, mem_name); 107 g_free(mem_name); 108 109 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 110 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 111 sizeof(mem_reg_property)))); 112 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 113 } 114 115 static int get_cpus_node(void *fdt) 116 { 117 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 118 119 if (cpus_offset < 0) { 120 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 121 if (cpus_offset) { 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 123 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 124 } 125 } 126 _FDT(cpus_offset); 127 return cpus_offset; 128 } 129 130 /* 131 * The PowerNV cores (and threads) need to use real HW ids and not an 132 * incremental index like it has been done on other platforms. This HW 133 * id is stored in the CPU PIR, it is used to create cpu nodes in the 134 * device tree, used in XSCOM to address cores and in interrupt 135 * servers. 136 */ 137 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 138 { 139 PowerPCCPU *cpu = pc->threads[0]; 140 CPUState *cs = CPU(cpu); 141 DeviceClass *dc = DEVICE_GET_CLASS(cs); 142 int smt_threads = CPU_CORE(pc)->nr_threads; 143 CPUPPCState *env = &cpu->env; 144 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 145 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 146 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 147 int i; 148 uint32_t pir; 149 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 150 0xffffffff, 0xffffffff}; 151 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 152 uint32_t cpufreq = 1000000000; 153 uint32_t page_sizes_prop[64]; 154 size_t page_sizes_prop_size; 155 int offset; 156 char *nodename; 157 int cpus_offset = get_cpus_node(fdt); 158 159 pir = pnv_cc->chip_pir(chip, pc->hwid, 0); 160 161 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 162 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 163 _FDT(offset); 164 g_free(nodename); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 170 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 171 172 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 176 env->dcache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 178 env->icache_line_size))); 179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 180 env->icache_line_size))); 181 182 if (pcc->l1_dcache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 184 pcc->l1_dcache_size))); 185 } else { 186 warn_report("Unknown L1 dcache size for cpu"); 187 } 188 if (pcc->l1_icache_size) { 189 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 190 pcc->l1_icache_size))); 191 } else { 192 warn_report("Unknown L1 icache size for cpu"); 193 } 194 195 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 196 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 198 cpu->hash64_opts->slb_size))); 199 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 200 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 201 202 if (ppc_has_spr(cpu, SPR_PURR)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 204 } 205 206 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 207 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 208 segs, sizeof(segs)))); 209 } 210 211 /* 212 * Advertise VMX/VSX (vector extensions) if available 213 * 0 / no property == no vector extensions 214 * 1 == VMX / Altivec available 215 * 2 == VSX available 216 */ 217 if (env->insns_flags & PPC_ALTIVEC) { 218 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 219 220 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 221 } 222 223 /* 224 * Advertise DFP (Decimal Floating Point) if available 225 * 0 / no property == no DFP 226 * 1 == DFP available 227 */ 228 if (env->insns_flags2 & PPC2_DFP) { 229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 230 } 231 232 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 233 sizeof(page_sizes_prop)); 234 if (page_sizes_prop_size) { 235 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 236 page_sizes_prop, page_sizes_prop_size))); 237 } 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i)); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(*servers_prop) * smt_threads))); 245 246 return offset; 247 } 248 249 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 250 uint32_t nr_threads) 251 { 252 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 253 uint32_t pir = pcc->chip_pir(chip, hwid, 0); 254 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 255 char *name; 256 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 257 uint32_t irange[2], i, rsize; 258 uint64_t *reg; 259 int offset; 260 261 irange[0] = cpu_to_be32(pir); 262 irange[1] = cpu_to_be32(nr_threads); 263 264 rsize = sizeof(uint64_t) * 2 * nr_threads; 265 reg = g_malloc(rsize); 266 for (i = 0; i < nr_threads; i++) { 267 /* We know P8 PIR is linear with thread id */ 268 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 269 reg[i * 2 + 1] = cpu_to_be64(0x1000); 270 } 271 272 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 273 offset = fdt_add_subnode(fdt, 0, name); 274 _FDT(offset); 275 g_free(name); 276 277 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 278 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 279 _FDT((fdt_setprop_string(fdt, offset, "device_type", 280 "PowerPC-External-Interrupt-Presentation"))); 281 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 282 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 283 irange, sizeof(irange)))); 284 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 285 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 286 g_free(reg); 287 } 288 289 /* 290 * Adds a PnvPHB to the chip on P8. 291 * Implemented here, like for defaults PHBs 292 */ 293 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 294 { 295 Pnv8Chip *chip8 = PNV8_CHIP(chip); 296 297 phb->chip = chip; 298 299 chip8->phbs[chip8->num_phbs] = phb; 300 chip8->num_phbs++; 301 return chip; 302 } 303 304 /* 305 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 306 * HTM is always enabled because TCG does implement HTM, it's just a 307 * degenerate implementation. 308 */ 309 static const uint8_t pa_features_207[] = { 24, 0, 310 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 311 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 312 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 313 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 314 315 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 316 { 317 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 318 int i; 319 320 pnv_dt_xscom(chip, fdt, 0, 321 cpu_to_be64(PNV_XSCOM_BASE(chip)), 322 cpu_to_be64(PNV_XSCOM_SIZE), 323 compat, sizeof(compat)); 324 325 for (i = 0; i < chip->nr_cores; i++) { 326 PnvCore *pnv_core = chip->cores[i]; 327 int offset; 328 329 offset = pnv_dt_core(chip, pnv_core, fdt); 330 331 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 332 pa_features_207, sizeof(pa_features_207)))); 333 334 /* Interrupt Control Presenters (ICP). One per core. */ 335 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 336 } 337 338 if (chip->ram_size) { 339 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 340 } 341 } 342 343 /* 344 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 345 */ 346 static const uint8_t pa_features_300[] = { 66, 0, 347 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 348 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 349 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 350 /* 6: DS207 */ 351 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 352 /* 16: Vector */ 353 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 354 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 355 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 356 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 357 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 358 /* 32: LE atomic, 34: EBB + ext EBB */ 359 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 360 /* 40: Radix MMU */ 361 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 362 /* 42: PM, 44: PC RA, 46: SC vec'd */ 363 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 364 /* 48: SIMD, 50: QP BFP, 52: String */ 365 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 366 /* 54: DecFP, 56: DecI, 58: SHA */ 367 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 368 /* 60: NM atomic, 62: RNG */ 369 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 370 }; 371 372 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 373 { 374 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 375 int i; 376 377 pnv_dt_xscom(chip, fdt, 0, 378 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 379 cpu_to_be64(PNV9_XSCOM_SIZE), 380 compat, sizeof(compat)); 381 382 for (i = 0; i < chip->nr_cores; i++) { 383 PnvCore *pnv_core = chip->cores[i]; 384 int offset; 385 386 offset = pnv_dt_core(chip, pnv_core, fdt); 387 388 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 389 pa_features_300, sizeof(pa_features_300)))); 390 } 391 392 if (chip->ram_size) { 393 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 394 } 395 396 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 397 } 398 399 /* 400 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 401 * always disables copy/paste. 402 */ 403 static const uint8_t pa_features_31[] = { 74, 0, 404 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 405 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 406 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 407 /* 6: DS207 */ 408 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 409 /* 16: Vector */ 410 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 411 /* 18: Vec. Scalar, 20: Vec. XOR */ 412 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 413 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 414 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 415 /* 32: LE atomic, 34: EBB + ext EBB */ 416 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 417 /* 40: Radix MMU */ 418 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 419 /* 42: PM, 44: PC RA, 46: SC vec'd */ 420 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 421 /* 48: SIMD, 50: QP BFP, 52: String */ 422 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 423 /* 54: DecFP, 56: DecI, 58: SHA */ 424 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 425 /* 60: NM atomic, 62: RNG */ 426 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 427 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 428 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 429 /* 72: [P]HASHST/[P]HASHCHK */ 430 0x80, 0x00, /* 72 - 73 */ 431 }; 432 433 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 434 { 435 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 436 int i; 437 438 pnv_dt_xscom(chip, fdt, 0, 439 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 440 cpu_to_be64(PNV10_XSCOM_SIZE), 441 compat, sizeof(compat)); 442 443 for (i = 0; i < chip->nr_cores; i++) { 444 PnvCore *pnv_core = chip->cores[i]; 445 int offset; 446 447 offset = pnv_dt_core(chip, pnv_core, fdt); 448 449 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 450 pa_features_31, sizeof(pa_features_31)))); 451 } 452 453 if (chip->ram_size) { 454 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 455 } 456 457 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 458 } 459 460 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 461 { 462 uint32_t io_base = d->ioport_id; 463 uint32_t io_regs[] = { 464 cpu_to_be32(1), 465 cpu_to_be32(io_base), 466 cpu_to_be32(2) 467 }; 468 char *name; 469 int node; 470 471 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 472 node = fdt_add_subnode(fdt, lpc_off, name); 473 _FDT(node); 474 g_free(name); 475 476 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 477 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 478 } 479 480 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 481 { 482 const char compatible[] = "ns16550\0pnpPNP,501"; 483 uint32_t io_base = d->ioport_id; 484 uint32_t io_regs[] = { 485 cpu_to_be32(1), 486 cpu_to_be32(io_base), 487 cpu_to_be32(8) 488 }; 489 uint32_t irq; 490 char *name; 491 int node; 492 493 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 494 495 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 496 node = fdt_add_subnode(fdt, lpc_off, name); 497 _FDT(node); 498 g_free(name); 499 500 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 501 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 502 sizeof(compatible)))); 503 504 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 505 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 506 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 507 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 508 fdt_get_phandle(fdt, lpc_off)))); 509 510 /* This is needed by Linux */ 511 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 512 } 513 514 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 515 { 516 const char compatible[] = "bt\0ipmi-bt"; 517 uint32_t io_base; 518 uint32_t io_regs[] = { 519 cpu_to_be32(1), 520 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 521 cpu_to_be32(3) 522 }; 523 uint32_t irq; 524 char *name; 525 int node; 526 527 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 528 io_regs[1] = cpu_to_be32(io_base); 529 530 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 531 532 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 533 node = fdt_add_subnode(fdt, lpc_off, name); 534 _FDT(node); 535 g_free(name); 536 537 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 538 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 539 sizeof(compatible)))); 540 541 /* Mark it as reserved to avoid Linux trying to claim it */ 542 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 543 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 544 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 545 fdt_get_phandle(fdt, lpc_off)))); 546 } 547 548 typedef struct ForeachPopulateArgs { 549 void *fdt; 550 int offset; 551 } ForeachPopulateArgs; 552 553 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 554 { 555 ForeachPopulateArgs *args = opaque; 556 ISADevice *d = ISA_DEVICE(dev); 557 558 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 559 pnv_dt_rtc(d, args->fdt, args->offset); 560 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 561 pnv_dt_serial(d, args->fdt, args->offset); 562 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 563 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 564 } else { 565 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 566 d->ioport_id); 567 } 568 569 return 0; 570 } 571 572 /* 573 * The default LPC bus of a multichip system is on chip 0. It's 574 * recognized by the firmware (skiboot) using a "primary" property. 575 */ 576 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 577 { 578 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 579 ForeachPopulateArgs args = { 580 .fdt = fdt, 581 .offset = isa_offset, 582 }; 583 uint32_t phandle; 584 585 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 586 587 phandle = qemu_fdt_alloc_phandle(fdt); 588 assert(phandle > 0); 589 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 590 591 /* 592 * ISA devices are not necessarily parented to the ISA bus so we 593 * can not use object_child_foreach() 594 */ 595 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 596 &args); 597 } 598 599 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 600 { 601 int off; 602 603 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 604 off = fdt_add_subnode(fdt, off, "power-mgt"); 605 606 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 607 } 608 609 static void *pnv_dt_create(MachineState *machine) 610 { 611 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 612 PnvMachineState *pnv = PNV_MACHINE(machine); 613 void *fdt; 614 char *buf; 615 int off; 616 int i; 617 618 fdt = g_malloc0(FDT_MAX_SIZE); 619 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 620 621 /* /qemu node */ 622 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 623 624 /* Root node */ 625 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 626 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 627 _FDT((fdt_setprop_string(fdt, 0, "model", 628 "IBM PowerNV (emulated by qemu)"))); 629 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 630 631 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 632 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 633 if (qemu_uuid_set) { 634 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 635 } 636 g_free(buf); 637 638 off = fdt_add_subnode(fdt, 0, "chosen"); 639 if (machine->kernel_cmdline) { 640 _FDT((fdt_setprop_string(fdt, off, "bootargs", 641 machine->kernel_cmdline))); 642 } 643 644 if (pnv->initrd_size) { 645 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 646 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 647 648 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 649 &start_prop, sizeof(start_prop)))); 650 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 651 &end_prop, sizeof(end_prop)))); 652 } 653 654 /* Populate device tree for each chip */ 655 for (i = 0; i < pnv->num_chips; i++) { 656 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 657 } 658 659 /* Populate ISA devices on chip 0 */ 660 pnv_dt_isa(pnv, fdt); 661 662 if (pnv->bmc) { 663 pnv_dt_bmc_sensors(pnv->bmc, fdt); 664 } 665 666 /* Create an extra node for power management on machines that support it */ 667 if (pmc->dt_power_mgt) { 668 pmc->dt_power_mgt(pnv, fdt); 669 } 670 671 return fdt; 672 } 673 674 static void pnv_powerdown_notify(Notifier *n, void *opaque) 675 { 676 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 677 678 if (pnv->bmc) { 679 pnv_bmc_powerdown(pnv->bmc); 680 } 681 } 682 683 static void pnv_reset(MachineState *machine, ShutdownCause reason) 684 { 685 PnvMachineState *pnv = PNV_MACHINE(machine); 686 IPMIBmc *bmc; 687 void *fdt; 688 689 qemu_devices_reset(reason); 690 691 /* 692 * The machine should provide by default an internal BMC simulator. 693 * If not, try to use the BMC device that was provided on the command 694 * line. 695 */ 696 bmc = pnv_bmc_find(&error_fatal); 697 if (!pnv->bmc) { 698 if (!bmc) { 699 if (!qtest_enabled()) { 700 warn_report("machine has no BMC device. Use '-device " 701 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 702 "to define one"); 703 } 704 } else { 705 pnv_bmc_set_pnor(bmc, pnv->pnor); 706 pnv->bmc = bmc; 707 } 708 } 709 710 fdt = pnv_dt_create(machine); 711 712 /* Pack resulting tree */ 713 _FDT((fdt_pack(fdt))); 714 715 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 716 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 717 718 /* 719 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 720 * the existing machine->fdt to avoid leaking it during 721 * a reset. 722 */ 723 g_free(machine->fdt); 724 machine->fdt = fdt; 725 } 726 727 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 728 { 729 Pnv8Chip *chip8 = PNV8_CHIP(chip); 730 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 731 732 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 733 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 734 } 735 736 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 737 { 738 Pnv8Chip *chip8 = PNV8_CHIP(chip); 739 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 740 741 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 742 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 743 } 744 745 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 746 { 747 Pnv9Chip *chip9 = PNV9_CHIP(chip); 748 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 749 750 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 751 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 752 } 753 754 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 755 { 756 Pnv10Chip *chip10 = PNV10_CHIP(chip); 757 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 758 759 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 760 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 761 } 762 763 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 764 { 765 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 766 } 767 768 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 769 { 770 Pnv8Chip *chip8 = PNV8_CHIP(chip); 771 int i; 772 773 g_autoptr(GString) buf = g_string_new(""); 774 g_autoptr(HumanReadableText) info = NULL; 775 776 ics_pic_print_info(&chip8->psi.ics, buf); 777 778 for (i = 0; i < chip8->num_phbs; i++) { 779 PnvPHB *phb = chip8->phbs[i]; 780 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 781 782 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 783 ics_pic_print_info(&phb3->lsis, buf); 784 } 785 786 info = human_readable_text_from_str(buf); 787 monitor_puts(mon, info->human_readable_text); 788 } 789 790 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 791 { 792 Monitor *mon = opaque; 793 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 794 g_autoptr(GString) buf = g_string_new(""); 795 g_autoptr(HumanReadableText) info = NULL; 796 797 if (!phb) { 798 return 0; 799 } 800 801 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 802 info = human_readable_text_from_str(buf); 803 monitor_puts(mon, info->human_readable_text); 804 805 return 0; 806 } 807 808 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 809 { 810 Pnv9Chip *chip9 = PNV9_CHIP(chip); 811 g_autoptr(GString) buf = g_string_new(""); 812 g_autoptr(HumanReadableText) info = NULL; 813 814 pnv_xive_pic_print_info(&chip9->xive, buf); 815 pnv_psi_pic_print_info(&chip9->psi, buf); 816 817 info = human_readable_text_from_str(buf); 818 monitor_puts(mon, info->human_readable_text); 819 820 object_child_foreach_recursive(OBJECT(chip), 821 pnv_chip_power9_pic_print_info_child, mon); 822 } 823 824 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 825 uint32_t core_id) 826 { 827 return PNV_XSCOM_EX_BASE(core_id); 828 } 829 830 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 831 uint32_t core_id) 832 { 833 return PNV9_XSCOM_EC_BASE(core_id); 834 } 835 836 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 837 uint32_t core_id) 838 { 839 return PNV10_XSCOM_EC_BASE(core_id); 840 } 841 842 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 843 { 844 PowerPCCPUClass *ppc_default = 845 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 846 PowerPCCPUClass *ppc = 847 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 848 849 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 850 } 851 852 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 853 { 854 ISADevice *dev = isa_new("isa-ipmi-bt"); 855 856 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 857 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 858 isa_realize_and_unref(dev, bus, &error_fatal); 859 } 860 861 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 862 { 863 Pnv10Chip *chip10 = PNV10_CHIP(chip); 864 g_autoptr(GString) buf = g_string_new(""); 865 g_autoptr(HumanReadableText) info = NULL; 866 867 pnv_xive2_pic_print_info(&chip10->xive, mon); 868 869 pnv_psi_pic_print_info(&chip10->psi, buf); 870 info = human_readable_text_from_str(buf); 871 monitor_puts(mon, info->human_readable_text); 872 873 object_child_foreach_recursive(OBJECT(chip), 874 pnv_chip_power9_pic_print_info_child, mon); 875 } 876 877 /* Always give the first 1GB to chip 0 else we won't boot */ 878 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 879 { 880 MachineState *machine = MACHINE(pnv); 881 uint64_t ram_per_chip; 882 883 assert(machine->ram_size >= 1 * GiB); 884 885 ram_per_chip = machine->ram_size / pnv->num_chips; 886 if (ram_per_chip >= 1 * GiB) { 887 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 888 } 889 890 assert(pnv->num_chips > 1); 891 892 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 893 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 894 } 895 896 static void pnv_init(MachineState *machine) 897 { 898 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 899 PnvMachineState *pnv = PNV_MACHINE(machine); 900 MachineClass *mc = MACHINE_GET_CLASS(machine); 901 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 902 char *fw_filename; 903 long fw_size; 904 uint64_t chip_ram_start = 0; 905 int i; 906 char *chip_typename; 907 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 908 DeviceState *dev; 909 910 if (kvm_enabled()) { 911 error_report("machine %s does not support the KVM accelerator", 912 mc->name); 913 exit(EXIT_FAILURE); 914 } 915 916 /* allocate RAM */ 917 if (machine->ram_size < mc->default_ram_size) { 918 char *sz = size_to_str(mc->default_ram_size); 919 error_report("Invalid RAM size, should be bigger than %s", sz); 920 g_free(sz); 921 exit(EXIT_FAILURE); 922 } 923 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 924 925 /* 926 * Create our simple PNOR device 927 */ 928 dev = qdev_new(TYPE_PNV_PNOR); 929 if (pnor) { 930 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 931 } 932 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 933 pnv->pnor = PNV_PNOR(dev); 934 935 /* load skiboot firmware */ 936 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 937 if (!fw_filename) { 938 error_report("Could not find OPAL firmware '%s'", bios_name); 939 exit(1); 940 } 941 942 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 943 if (fw_size < 0) { 944 error_report("Could not load OPAL firmware '%s'", fw_filename); 945 exit(1); 946 } 947 g_free(fw_filename); 948 949 /* load kernel */ 950 if (machine->kernel_filename) { 951 long kernel_size; 952 953 kernel_size = load_image_targphys(machine->kernel_filename, 954 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 955 if (kernel_size < 0) { 956 error_report("Could not load kernel '%s'", 957 machine->kernel_filename); 958 exit(1); 959 } 960 } 961 962 /* load initrd */ 963 if (machine->initrd_filename) { 964 pnv->initrd_base = INITRD_LOAD_ADDR; 965 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 966 pnv->initrd_base, INITRD_MAX_SIZE); 967 if (pnv->initrd_size < 0) { 968 error_report("Could not load initial ram disk '%s'", 969 machine->initrd_filename); 970 exit(1); 971 } 972 } 973 974 /* MSIs are supported on this platform */ 975 msi_nonbroken = true; 976 977 /* 978 * Check compatibility of the specified CPU with the machine 979 * default. 980 */ 981 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 982 error_report("invalid CPU model '%s' for %s machine", 983 machine->cpu_type, mc->name); 984 exit(1); 985 } 986 987 /* Create the processor chips */ 988 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 989 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 990 i, machine->cpu_type); 991 if (!object_class_by_name(chip_typename)) { 992 error_report("invalid chip model '%.*s' for %s machine", 993 i, machine->cpu_type, mc->name); 994 exit(1); 995 } 996 997 pnv->num_chips = 998 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 999 1000 if (machine->smp.threads > 8) { 1001 error_report("Cannot support more than 8 threads/core " 1002 "on a powernv machine"); 1003 exit(1); 1004 } 1005 if (!is_power_of_2(machine->smp.threads)) { 1006 error_report("Cannot support %d threads/core on a powernv" 1007 "machine because it must be a power of 2", 1008 machine->smp.threads); 1009 exit(1); 1010 } 1011 /* 1012 * TODO: should we decide on how many chips we can create based 1013 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1014 */ 1015 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1016 error_report("invalid number of chips: '%d'", pnv->num_chips); 1017 error_printf( 1018 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1019 exit(1); 1020 } 1021 1022 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1023 for (i = 0; i < pnv->num_chips; i++) { 1024 char chip_name[32]; 1025 Object *chip = OBJECT(qdev_new(chip_typename)); 1026 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1027 1028 pnv->chips[i] = PNV_CHIP(chip); 1029 1030 /* Distribute RAM among the chips */ 1031 object_property_set_int(chip, "ram-start", chip_ram_start, 1032 &error_fatal); 1033 object_property_set_int(chip, "ram-size", chip_ram_size, 1034 &error_fatal); 1035 chip_ram_start += chip_ram_size; 1036 1037 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1038 object_property_add_child(OBJECT(pnv), chip_name, chip); 1039 object_property_set_int(chip, "chip-id", i, &error_fatal); 1040 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1041 &error_fatal); 1042 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1043 &error_fatal); 1044 /* 1045 * The POWER8 machine use the XICS interrupt interface. 1046 * Propagate the XICS fabric to the chip and its controllers. 1047 */ 1048 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1049 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1050 } 1051 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1052 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1053 &error_abort); 1054 } 1055 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1056 } 1057 g_free(chip_typename); 1058 1059 /* Instantiate ISA bus on chip 0 */ 1060 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1061 1062 /* Create serial port */ 1063 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1064 1065 /* Create an RTC ISA device too */ 1066 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1067 1068 /* 1069 * Create the machine BMC simulator and the IPMI BT device for 1070 * communication with the BMC 1071 */ 1072 if (defaults_enabled()) { 1073 pnv->bmc = pnv_bmc_create(pnv->pnor); 1074 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1075 } 1076 1077 /* 1078 * The PNOR is mapped on the LPC FW address space by the BMC. 1079 * Since we can not reach the remote BMC machine with LPC memops, 1080 * map it always for now. 1081 */ 1082 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1083 &pnv->pnor->mmio); 1084 1085 /* 1086 * OpenPOWER systems use a IPMI SEL Event message to notify the 1087 * host to powerdown 1088 */ 1089 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1090 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1091 1092 /* 1093 * Create/Connect any machine-specific I2C devices 1094 */ 1095 if (pmc->i2c_init) { 1096 pmc->i2c_init(pnv); 1097 } 1098 } 1099 1100 /* 1101 * 0:21 Reserved - Read as zeros 1102 * 22:24 Chip ID 1103 * 25:28 Core number 1104 * 29:31 Thread ID 1105 */ 1106 static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id, 1107 uint32_t thread_id) 1108 { 1109 return (chip->chip_id << 7) | (core_id << 3) | thread_id; 1110 } 1111 1112 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1113 Error **errp) 1114 { 1115 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1116 Error *local_err = NULL; 1117 Object *obj; 1118 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1119 1120 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1121 if (local_err) { 1122 error_propagate(errp, local_err); 1123 return; 1124 } 1125 1126 pnv_cpu->intc = obj; 1127 } 1128 1129 1130 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1131 { 1132 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1133 1134 icp_reset(ICP(pnv_cpu->intc)); 1135 } 1136 1137 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1138 { 1139 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1140 1141 icp_destroy(ICP(pnv_cpu->intc)); 1142 pnv_cpu->intc = NULL; 1143 } 1144 1145 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1146 GString *buf) 1147 { 1148 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1149 } 1150 1151 /* 1152 * 0:48 Reserved - Read as zeroes 1153 * 49:52 Node ID 1154 * 53:55 Chip ID 1155 * 56 Reserved - Read as zero 1156 * 57:61 Core number 1157 * 62:63 Thread ID 1158 * 1159 * We only care about the lower bits. uint32_t is fine for the moment. 1160 */ 1161 static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id, 1162 uint32_t thread_id) 1163 { 1164 if (chip->nr_threads == 8) { 1165 return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) | 1166 (thread_id >> 1); 1167 } else { 1168 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1169 } 1170 } 1171 1172 /* 1173 * 0:48 Reserved - Read as zeroes 1174 * 49:52 Node ID 1175 * 53:55 Chip ID 1176 * 56 Reserved - Read as zero 1177 * 57:59 Quad ID 1178 * 60 Core Chiplet Pair ID 1179 * 61:63 Thread/Core Chiplet ID t0-t2 1180 * 1181 * We only care about the lower bits. uint32_t is fine for the moment. 1182 */ 1183 static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id, 1184 uint32_t thread_id) 1185 { 1186 if (chip->nr_threads == 8) { 1187 return (chip->chip_id << 8) | ((core_id / 4) << 4) | 1188 ((core_id % 2) << 3) | thread_id; 1189 } else { 1190 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1191 } 1192 } 1193 1194 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1195 Error **errp) 1196 { 1197 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1198 Error *local_err = NULL; 1199 Object *obj; 1200 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1201 1202 /* 1203 * The core creates its interrupt presenter but the XIVE interrupt 1204 * controller object is initialized afterwards. Hopefully, it's 1205 * only used at runtime. 1206 */ 1207 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1208 &local_err); 1209 if (local_err) { 1210 error_propagate(errp, local_err); 1211 return; 1212 } 1213 1214 pnv_cpu->intc = obj; 1215 } 1216 1217 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1218 { 1219 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1220 1221 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1222 } 1223 1224 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1225 { 1226 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1227 1228 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1229 pnv_cpu->intc = NULL; 1230 } 1231 1232 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1233 GString *buf) 1234 { 1235 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1236 } 1237 1238 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1239 Error **errp) 1240 { 1241 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1242 Error *local_err = NULL; 1243 Object *obj; 1244 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1245 1246 /* 1247 * The core creates its interrupt presenter but the XIVE2 interrupt 1248 * controller object is initialized afterwards. Hopefully, it's 1249 * only used at runtime. 1250 */ 1251 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1252 &local_err); 1253 if (local_err) { 1254 error_propagate(errp, local_err); 1255 return; 1256 } 1257 1258 pnv_cpu->intc = obj; 1259 } 1260 1261 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1262 { 1263 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1264 1265 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1266 } 1267 1268 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1269 { 1270 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1271 1272 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1273 pnv_cpu->intc = NULL; 1274 } 1275 1276 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1277 GString *buf) 1278 { 1279 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1280 } 1281 1282 /* 1283 * Allowed core identifiers on a POWER8 Processor Chip : 1284 * 1285 * <EX0 reserved> 1286 * EX1 - Venice only 1287 * EX2 - Venice only 1288 * EX3 - Venice only 1289 * EX4 1290 * EX5 1291 * EX6 1292 * <EX7,8 reserved> <reserved> 1293 * EX9 - Venice only 1294 * EX10 - Venice only 1295 * EX11 - Venice only 1296 * EX12 1297 * EX13 1298 * EX14 1299 * <EX15 reserved> 1300 */ 1301 #define POWER8E_CORE_MASK (0x7070ull) 1302 #define POWER8_CORE_MASK (0x7e7eull) 1303 1304 /* 1305 * POWER9 has 24 cores, ids starting at 0x0 1306 */ 1307 #define POWER9_CORE_MASK (0xffffffffffffffull) 1308 1309 1310 #define POWER10_CORE_MASK (0xffffffffffffffull) 1311 1312 static void pnv_chip_power8_instance_init(Object *obj) 1313 { 1314 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1315 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1316 int i; 1317 1318 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1319 (Object **)&chip8->xics, 1320 object_property_allow_set_link, 1321 OBJ_PROP_LINK_STRONG); 1322 1323 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1324 1325 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1326 1327 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1328 1329 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1330 1331 if (defaults_enabled()) { 1332 chip8->num_phbs = pcc->num_phbs; 1333 1334 for (i = 0; i < chip8->num_phbs; i++) { 1335 Object *phb = object_new(TYPE_PNV_PHB); 1336 1337 /* 1338 * We need the chip to parent the PHB to allow the DT 1339 * to build correctly (via pnv_xscom_dt()). 1340 * 1341 * TODO: the PHB should be parented by a PEC device that, at 1342 * this moment, is not modelled powernv8/phb3. 1343 */ 1344 object_property_add_child(obj, "phb[*]", phb); 1345 chip8->phbs[i] = PNV_PHB(phb); 1346 } 1347 } 1348 1349 } 1350 1351 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1352 { 1353 PnvChip *chip = PNV_CHIP(chip8); 1354 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1355 int i, j; 1356 char *name; 1357 1358 name = g_strdup_printf("icp-%x", chip->chip_id); 1359 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1360 g_free(name); 1361 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1362 &chip8->icp_mmio); 1363 1364 /* Map the ICP registers for each thread */ 1365 for (i = 0; i < chip->nr_cores; i++) { 1366 PnvCore *pnv_core = chip->cores[i]; 1367 int core_hwid = CPU_CORE(pnv_core)->core_id; 1368 1369 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1370 uint32_t pir = pcc->chip_pir(chip, core_hwid, j); 1371 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1372 1373 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1374 &icp->mmio); 1375 } 1376 } 1377 } 1378 1379 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1380 { 1381 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1382 PnvChip *chip = PNV_CHIP(dev); 1383 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1384 Pnv8Psi *psi8 = &chip8->psi; 1385 Error *local_err = NULL; 1386 int i; 1387 1388 assert(chip8->xics); 1389 1390 /* XSCOM bridge is first */ 1391 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1392 1393 pcc->parent_realize(dev, &local_err); 1394 if (local_err) { 1395 error_propagate(errp, local_err); 1396 return; 1397 } 1398 1399 /* Processor Service Interface (PSI) Host Bridge */ 1400 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1401 &error_fatal); 1402 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1403 OBJECT(chip8->xics), &error_abort); 1404 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1405 return; 1406 } 1407 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1408 &PNV_PSI(psi8)->xscom_regs); 1409 1410 /* Create LPC controller */ 1411 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1412 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1413 1414 chip->fw_mr = &chip8->lpc.isa_fw; 1415 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1416 (uint64_t) PNV_XSCOM_BASE(chip), 1417 PNV_XSCOM_LPC_BASE); 1418 1419 /* 1420 * Interrupt Management Area. This is the memory region holding 1421 * all the Interrupt Control Presenter (ICP) registers 1422 */ 1423 pnv_chip_icp_realize(chip8, &local_err); 1424 if (local_err) { 1425 error_propagate(errp, local_err); 1426 return; 1427 } 1428 1429 /* Create the simplified OCC model */ 1430 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1431 return; 1432 } 1433 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1434 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1435 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1436 1437 /* OCC SRAM model */ 1438 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1439 &chip8->occ.sram_regs); 1440 1441 /* HOMER */ 1442 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1443 &error_abort); 1444 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1445 return; 1446 } 1447 /* Homer Xscom region */ 1448 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1449 1450 /* Homer mmio region */ 1451 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1452 &chip8->homer.regs); 1453 1454 /* PHB controllers */ 1455 for (i = 0; i < chip8->num_phbs; i++) { 1456 PnvPHB *phb = chip8->phbs[i]; 1457 1458 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1459 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1460 &error_fatal); 1461 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1462 &error_fatal); 1463 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1464 return; 1465 } 1466 } 1467 } 1468 1469 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1470 { 1471 addr &= (PNV_XSCOM_SIZE - 1); 1472 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1473 } 1474 1475 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1476 { 1477 DeviceClass *dc = DEVICE_CLASS(klass); 1478 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1479 1480 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1481 k->cores_mask = POWER8E_CORE_MASK; 1482 k->num_phbs = 3; 1483 k->chip_pir = pnv_chip_pir_p8; 1484 k->intc_create = pnv_chip_power8_intc_create; 1485 k->intc_reset = pnv_chip_power8_intc_reset; 1486 k->intc_destroy = pnv_chip_power8_intc_destroy; 1487 k->intc_print_info = pnv_chip_power8_intc_print_info; 1488 k->isa_create = pnv_chip_power8_isa_create; 1489 k->dt_populate = pnv_chip_power8_dt_populate; 1490 k->pic_print_info = pnv_chip_power8_pic_print_info; 1491 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1492 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1493 dc->desc = "PowerNV Chip POWER8E"; 1494 1495 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1496 &k->parent_realize); 1497 } 1498 1499 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1500 { 1501 DeviceClass *dc = DEVICE_CLASS(klass); 1502 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1503 1504 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1505 k->cores_mask = POWER8_CORE_MASK; 1506 k->num_phbs = 3; 1507 k->chip_pir = pnv_chip_pir_p8; 1508 k->intc_create = pnv_chip_power8_intc_create; 1509 k->intc_reset = pnv_chip_power8_intc_reset; 1510 k->intc_destroy = pnv_chip_power8_intc_destroy; 1511 k->intc_print_info = pnv_chip_power8_intc_print_info; 1512 k->isa_create = pnv_chip_power8_isa_create; 1513 k->dt_populate = pnv_chip_power8_dt_populate; 1514 k->pic_print_info = pnv_chip_power8_pic_print_info; 1515 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1516 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1517 dc->desc = "PowerNV Chip POWER8"; 1518 1519 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1520 &k->parent_realize); 1521 } 1522 1523 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1524 { 1525 DeviceClass *dc = DEVICE_CLASS(klass); 1526 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1527 1528 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1529 k->cores_mask = POWER8_CORE_MASK; 1530 k->num_phbs = 4; 1531 k->chip_pir = pnv_chip_pir_p8; 1532 k->intc_create = pnv_chip_power8_intc_create; 1533 k->intc_reset = pnv_chip_power8_intc_reset; 1534 k->intc_destroy = pnv_chip_power8_intc_destroy; 1535 k->intc_print_info = pnv_chip_power8_intc_print_info; 1536 k->isa_create = pnv_chip_power8nvl_isa_create; 1537 k->dt_populate = pnv_chip_power8_dt_populate; 1538 k->pic_print_info = pnv_chip_power8_pic_print_info; 1539 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1540 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1541 dc->desc = "PowerNV Chip POWER8NVL"; 1542 1543 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1544 &k->parent_realize); 1545 } 1546 1547 static void pnv_chip_power9_instance_init(Object *obj) 1548 { 1549 PnvChip *chip = PNV_CHIP(obj); 1550 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1551 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1552 int i; 1553 1554 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1555 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1556 "xive-fabric"); 1557 1558 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1559 1560 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1561 1562 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1563 1564 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1565 1566 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1567 1568 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1569 1570 /* Number of PECs is the chip default */ 1571 chip->num_pecs = pcc->num_pecs; 1572 1573 for (i = 0; i < chip->num_pecs; i++) { 1574 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1575 TYPE_PNV_PHB4_PEC); 1576 } 1577 1578 for (i = 0; i < pcc->i2c_num_engines; i++) { 1579 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1580 } 1581 } 1582 1583 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1584 PnvCore *pnv_core, 1585 const char *type) 1586 { 1587 char eq_name[32]; 1588 int core_id = CPU_CORE(pnv_core)->core_id; 1589 1590 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1591 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1592 sizeof(*eq), type, 1593 &error_fatal, NULL); 1594 1595 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1596 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1597 } 1598 1599 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1600 { 1601 PnvChip *chip = PNV_CHIP(chip9); 1602 int i; 1603 1604 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1605 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1606 1607 for (i = 0; i < chip9->nr_quads; i++) { 1608 PnvQuad *eq = &chip9->quads[i]; 1609 1610 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1611 PNV_QUAD_TYPE_NAME("power9")); 1612 1613 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1614 &eq->xscom_regs); 1615 } 1616 } 1617 1618 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1619 { 1620 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1621 int i; 1622 1623 for (i = 0; i < chip->num_pecs; i++) { 1624 PnvPhb4PecState *pec = &chip9->pecs[i]; 1625 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1626 uint32_t pec_nest_base; 1627 uint32_t pec_pci_base; 1628 1629 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1630 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1631 &error_fatal); 1632 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1633 &error_fatal); 1634 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1635 return; 1636 } 1637 1638 pec_nest_base = pecc->xscom_nest_base(pec); 1639 pec_pci_base = pecc->xscom_pci_base(pec); 1640 1641 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1642 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1643 } 1644 } 1645 1646 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1647 { 1648 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1649 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1650 PnvChip *chip = PNV_CHIP(dev); 1651 Pnv9Psi *psi9 = &chip9->psi; 1652 Error *local_err = NULL; 1653 int i; 1654 1655 /* XSCOM bridge is first */ 1656 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1657 1658 pcc->parent_realize(dev, &local_err); 1659 if (local_err) { 1660 error_propagate(errp, local_err); 1661 return; 1662 } 1663 1664 pnv_chip_quad_realize(chip9, &local_err); 1665 if (local_err) { 1666 error_propagate(errp, local_err); 1667 return; 1668 } 1669 1670 /* XIVE interrupt controller (POWER9) */ 1671 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1672 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1673 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1674 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1675 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1676 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1677 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1678 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1679 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1680 &error_abort); 1681 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1682 return; 1683 } 1684 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1685 &chip9->xive.xscom_regs); 1686 1687 /* Processor Service Interface (PSI) Host Bridge */ 1688 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1689 &error_fatal); 1690 /* This is the only device with 4k ESB pages */ 1691 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1692 &error_fatal); 1693 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1694 return; 1695 } 1696 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1697 &PNV_PSI(psi9)->xscom_regs); 1698 1699 /* LPC */ 1700 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1701 return; 1702 } 1703 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1704 &chip9->lpc.xscom_regs); 1705 1706 chip->fw_mr = &chip9->lpc.isa_fw; 1707 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1708 (uint64_t) PNV9_LPCM_BASE(chip)); 1709 1710 /* ChipTOD */ 1711 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1712 chip->chip_id == 0, &error_abort); 1713 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1714 chip->chip_id == 1, &error_abort); 1715 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1716 &error_abort); 1717 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1718 return; 1719 } 1720 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1721 &chip9->chiptod.xscom_regs); 1722 1723 /* Create the simplified OCC model */ 1724 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1725 return; 1726 } 1727 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1728 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1729 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1730 1731 /* OCC SRAM model */ 1732 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1733 &chip9->occ.sram_regs); 1734 1735 /* SBE */ 1736 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1737 return; 1738 } 1739 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1740 &chip9->sbe.xscom_ctrl_regs); 1741 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1742 &chip9->sbe.xscom_mbox_regs); 1743 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1744 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1745 1746 /* HOMER */ 1747 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1748 &error_abort); 1749 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1750 return; 1751 } 1752 /* Homer Xscom region */ 1753 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1754 1755 /* Homer mmio region */ 1756 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1757 &chip9->homer.regs); 1758 1759 /* PEC PHBs */ 1760 pnv_chip_power9_pec_realize(chip, &local_err); 1761 if (local_err) { 1762 error_propagate(errp, local_err); 1763 return; 1764 } 1765 1766 /* 1767 * I2C 1768 */ 1769 for (i = 0; i < pcc->i2c_num_engines; i++) { 1770 Object *obj = OBJECT(&chip9->i2c[i]); 1771 1772 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1773 object_property_set_int(obj, "num-busses", 1774 pcc->i2c_ports_per_engine[i], 1775 &error_fatal); 1776 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1777 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1778 return; 1779 } 1780 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1781 (chip9->i2c[i].engine - 1) * 1782 PNV9_XSCOM_I2CM_SIZE, 1783 &chip9->i2c[i].xscom_regs); 1784 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1785 qdev_get_gpio_in(DEVICE(psi9), 1786 PSIHB9_IRQ_SBE_I2C)); 1787 } 1788 } 1789 1790 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1791 { 1792 addr &= (PNV9_XSCOM_SIZE - 1); 1793 return addr >> 3; 1794 } 1795 1796 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1797 { 1798 DeviceClass *dc = DEVICE_CLASS(klass); 1799 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1800 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1801 1802 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1803 k->cores_mask = POWER9_CORE_MASK; 1804 k->chip_pir = pnv_chip_pir_p9; 1805 k->intc_create = pnv_chip_power9_intc_create; 1806 k->intc_reset = pnv_chip_power9_intc_reset; 1807 k->intc_destroy = pnv_chip_power9_intc_destroy; 1808 k->intc_print_info = pnv_chip_power9_intc_print_info; 1809 k->isa_create = pnv_chip_power9_isa_create; 1810 k->dt_populate = pnv_chip_power9_dt_populate; 1811 k->pic_print_info = pnv_chip_power9_pic_print_info; 1812 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1813 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1814 dc->desc = "PowerNV Chip POWER9"; 1815 k->num_pecs = PNV9_CHIP_MAX_PEC; 1816 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1817 k->i2c_ports_per_engine = i2c_ports_per_engine; 1818 1819 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1820 &k->parent_realize); 1821 } 1822 1823 static void pnv_chip_power10_instance_init(Object *obj) 1824 { 1825 PnvChip *chip = PNV_CHIP(obj); 1826 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1827 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1828 int i; 1829 1830 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1831 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1832 "xive-fabric"); 1833 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1834 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1835 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1836 TYPE_PNV10_CHIPTOD); 1837 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1838 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1839 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1840 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1841 TYPE_PNV_N1_CHIPLET); 1842 1843 chip->num_pecs = pcc->num_pecs; 1844 1845 for (i = 0; i < chip->num_pecs; i++) { 1846 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1847 TYPE_PNV_PHB5_PEC); 1848 } 1849 1850 for (i = 0; i < pcc->i2c_num_engines; i++) { 1851 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1852 } 1853 } 1854 1855 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1856 { 1857 PnvChip *chip = PNV_CHIP(chip10); 1858 int i; 1859 1860 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1861 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1862 1863 for (i = 0; i < chip10->nr_quads; i++) { 1864 PnvQuad *eq = &chip10->quads[i]; 1865 1866 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1867 PNV_QUAD_TYPE_NAME("power10")); 1868 1869 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1870 &eq->xscom_regs); 1871 1872 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1873 &eq->xscom_qme_regs); 1874 } 1875 } 1876 1877 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1878 { 1879 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1880 int i; 1881 1882 for (i = 0; i < chip->num_pecs; i++) { 1883 PnvPhb4PecState *pec = &chip10->pecs[i]; 1884 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1885 uint32_t pec_nest_base; 1886 uint32_t pec_pci_base; 1887 1888 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1889 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1890 &error_fatal); 1891 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1892 &error_fatal); 1893 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1894 return; 1895 } 1896 1897 pec_nest_base = pecc->xscom_nest_base(pec); 1898 pec_pci_base = pecc->xscom_pci_base(pec); 1899 1900 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1901 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1902 } 1903 } 1904 1905 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1906 { 1907 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1908 PnvChip *chip = PNV_CHIP(dev); 1909 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1910 Error *local_err = NULL; 1911 int i; 1912 1913 /* XSCOM bridge is first */ 1914 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 1915 1916 pcc->parent_realize(dev, &local_err); 1917 if (local_err) { 1918 error_propagate(errp, local_err); 1919 return; 1920 } 1921 1922 pnv_chip_power10_quad_realize(chip10, &local_err); 1923 if (local_err) { 1924 error_propagate(errp, local_err); 1925 return; 1926 } 1927 1928 /* XIVE2 interrupt controller (POWER10) */ 1929 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1930 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1931 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1932 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1933 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1934 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1935 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1936 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1937 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1938 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1939 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1940 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1941 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1942 &error_abort); 1943 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1944 return; 1945 } 1946 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1947 &chip10->xive.xscom_regs); 1948 1949 /* Processor Service Interface (PSI) Host Bridge */ 1950 object_property_set_int(OBJECT(&chip10->psi), "bar", 1951 PNV10_PSIHB_BASE(chip), &error_fatal); 1952 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1953 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1954 &error_fatal); 1955 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1956 return; 1957 } 1958 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1959 &PNV_PSI(&chip10->psi)->xscom_regs); 1960 1961 /* LPC */ 1962 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1963 return; 1964 } 1965 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1966 &chip10->lpc.xscom_regs); 1967 1968 chip->fw_mr = &chip10->lpc.isa_fw; 1969 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1970 (uint64_t) PNV10_LPCM_BASE(chip)); 1971 1972 /* ChipTOD */ 1973 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 1974 chip->chip_id == 0, &error_abort); 1975 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 1976 chip->chip_id == 1, &error_abort); 1977 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 1978 &error_abort); 1979 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 1980 return; 1981 } 1982 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 1983 &chip10->chiptod.xscom_regs); 1984 1985 /* Create the simplified OCC model */ 1986 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1987 return; 1988 } 1989 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1990 &chip10->occ.xscom_regs); 1991 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1992 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1993 1994 /* OCC SRAM model */ 1995 memory_region_add_subregion(get_system_memory(), 1996 PNV10_OCC_SENSOR_BASE(chip), 1997 &chip10->occ.sram_regs); 1998 1999 /* SBE */ 2000 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 2001 return; 2002 } 2003 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2004 &chip10->sbe.xscom_ctrl_regs); 2005 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2006 &chip10->sbe.xscom_mbox_regs); 2007 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2008 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2009 2010 /* HOMER */ 2011 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2012 &error_abort); 2013 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2014 return; 2015 } 2016 /* Homer Xscom region */ 2017 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2018 &chip10->homer.pba_regs); 2019 2020 /* Homer mmio region */ 2021 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 2022 &chip10->homer.regs); 2023 2024 /* N1 chiplet */ 2025 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2026 return; 2027 } 2028 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2029 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2030 2031 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2032 &chip10->n1_chiplet.xscom_pb_eq_mr); 2033 2034 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2035 &chip10->n1_chiplet.xscom_pb_es_mr); 2036 2037 /* PHBs */ 2038 pnv_chip_power10_phb_realize(chip, &local_err); 2039 if (local_err) { 2040 error_propagate(errp, local_err); 2041 return; 2042 } 2043 2044 2045 /* 2046 * I2C 2047 */ 2048 for (i = 0; i < pcc->i2c_num_engines; i++) { 2049 Object *obj = OBJECT(&chip10->i2c[i]); 2050 2051 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2052 object_property_set_int(obj, "num-busses", 2053 pcc->i2c_ports_per_engine[i], 2054 &error_fatal); 2055 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2056 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2057 return; 2058 } 2059 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2060 (chip10->i2c[i].engine - 1) * 2061 PNV10_XSCOM_I2CM_SIZE, 2062 &chip10->i2c[i].xscom_regs); 2063 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2064 qdev_get_gpio_in(DEVICE(&chip10->psi), 2065 PSIHB9_IRQ_SBE_I2C)); 2066 } 2067 2068 } 2069 2070 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2071 { 2072 int i; 2073 for (i = 0; i < pnv->num_chips; i++) { 2074 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2075 2076 /* 2077 * Add a PCA9552 I2C device for PCIe hotplug control 2078 * to engine 2, bus 1, address 0x63 2079 */ 2080 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2081 "pca9552", 0x63); 2082 2083 /* 2084 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2085 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2086 * after hypervisor code sets a SLOTx_EN pin high. 2087 */ 2088 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2089 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2090 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2091 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2092 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2093 2094 /* 2095 * Add a PCA9554 I2C device for cable card presence detection 2096 * to engine 2, bus 1, address 0x25 2097 */ 2098 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2099 } 2100 } 2101 2102 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2103 { 2104 addr &= (PNV10_XSCOM_SIZE - 1); 2105 return addr >> 3; 2106 } 2107 2108 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2109 { 2110 DeviceClass *dc = DEVICE_CLASS(klass); 2111 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2112 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2113 2114 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 2115 k->cores_mask = POWER10_CORE_MASK; 2116 k->chip_pir = pnv_chip_pir_p10; 2117 k->intc_create = pnv_chip_power10_intc_create; 2118 k->intc_reset = pnv_chip_power10_intc_reset; 2119 k->intc_destroy = pnv_chip_power10_intc_destroy; 2120 k->intc_print_info = pnv_chip_power10_intc_print_info; 2121 k->isa_create = pnv_chip_power10_isa_create; 2122 k->dt_populate = pnv_chip_power10_dt_populate; 2123 k->pic_print_info = pnv_chip_power10_pic_print_info; 2124 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2125 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2126 dc->desc = "PowerNV Chip POWER10"; 2127 k->num_pecs = PNV10_CHIP_MAX_PEC; 2128 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2129 k->i2c_ports_per_engine = i2c_ports_per_engine; 2130 2131 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2132 &k->parent_realize); 2133 } 2134 2135 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 2136 { 2137 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2138 int cores_max; 2139 2140 /* 2141 * No custom mask for this chip, let's use the default one from * 2142 * the chip class 2143 */ 2144 if (!chip->cores_mask) { 2145 chip->cores_mask = pcc->cores_mask; 2146 } 2147 2148 /* filter alien core ids ! some are reserved */ 2149 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2150 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2151 chip->cores_mask); 2152 return; 2153 } 2154 chip->cores_mask &= pcc->cores_mask; 2155 2156 /* now that we have a sane layout, let check the number of cores */ 2157 cores_max = ctpop64(chip->cores_mask); 2158 if (chip->nr_cores > cores_max) { 2159 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2160 cores_max); 2161 return; 2162 } 2163 } 2164 2165 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2166 { 2167 Error *error = NULL; 2168 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2169 const char *typename = pnv_chip_core_typename(chip); 2170 int i, core_hwid; 2171 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2172 2173 if (!object_class_by_name(typename)) { 2174 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2175 return; 2176 } 2177 2178 /* Cores */ 2179 pnv_chip_core_sanitize(chip, &error); 2180 if (error) { 2181 error_propagate(errp, error); 2182 return; 2183 } 2184 2185 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2186 2187 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2188 && (i < chip->nr_cores); core_hwid++) { 2189 char core_name[32]; 2190 PnvCore *pnv_core; 2191 uint64_t xscom_core_base; 2192 2193 if (!(chip->cores_mask & (1ull << core_hwid))) { 2194 continue; 2195 } 2196 2197 pnv_core = PNV_CORE(object_new(typename)); 2198 2199 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2200 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2201 chip->cores[i] = pnv_core; 2202 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2203 chip->nr_threads, &error_fatal); 2204 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2205 core_hwid, &error_fatal); 2206 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2207 &error_fatal); 2208 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2209 &error_fatal); 2210 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2211 &error_abort); 2212 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2213 2214 /* Each core has an XSCOM MMIO region */ 2215 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2216 2217 pnv_xscom_add_subregion(chip, xscom_core_base, 2218 &pnv_core->xscom_regs); 2219 i++; 2220 } 2221 } 2222 2223 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2224 { 2225 PnvChip *chip = PNV_CHIP(dev); 2226 Error *error = NULL; 2227 2228 /* Cores */ 2229 pnv_chip_core_realize(chip, &error); 2230 if (error) { 2231 error_propagate(errp, error); 2232 return; 2233 } 2234 } 2235 2236 static Property pnv_chip_properties[] = { 2237 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2238 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2239 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2240 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2241 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2242 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2243 DEFINE_PROP_END_OF_LIST(), 2244 }; 2245 2246 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2247 { 2248 DeviceClass *dc = DEVICE_CLASS(klass); 2249 2250 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2251 dc->realize = pnv_chip_realize; 2252 device_class_set_props(dc, pnv_chip_properties); 2253 dc->desc = "PowerNV Chip"; 2254 } 2255 2256 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2257 { 2258 int i; 2259 2260 for (i = 0; i < chip->nr_cores; i++) { 2261 PnvCore *pc = chip->cores[i]; 2262 CPUCore *cc = CPU_CORE(pc); 2263 2264 if (cc->core_id == core_id) { 2265 return pc; 2266 } 2267 } 2268 return NULL; 2269 } 2270 2271 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2272 { 2273 int i, j; 2274 2275 for (i = 0; i < chip->nr_cores; i++) { 2276 PnvCore *pc = chip->cores[i]; 2277 CPUCore *cc = CPU_CORE(pc); 2278 2279 for (j = 0; j < cc->nr_threads; j++) { 2280 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2281 return pc->threads[j]; 2282 } 2283 } 2284 } 2285 return NULL; 2286 } 2287 2288 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2289 { 2290 PnvMachineState *pnv = PNV_MACHINE(xi); 2291 int i, j; 2292 2293 for (i = 0; i < pnv->num_chips; i++) { 2294 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2295 2296 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2297 return &chip8->psi.ics; 2298 } 2299 2300 for (j = 0; j < chip8->num_phbs; j++) { 2301 PnvPHB *phb = chip8->phbs[j]; 2302 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2303 2304 if (ics_valid_irq(&phb3->lsis, irq)) { 2305 return &phb3->lsis; 2306 } 2307 2308 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2309 return ICS(&phb3->msis); 2310 } 2311 } 2312 } 2313 return NULL; 2314 } 2315 2316 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2317 { 2318 int i; 2319 2320 for (i = 0; i < pnv->num_chips; i++) { 2321 PnvChip *chip = pnv->chips[i]; 2322 if (chip->chip_id == chip_id) { 2323 return chip; 2324 } 2325 } 2326 return NULL; 2327 } 2328 2329 static void pnv_ics_resend(XICSFabric *xi) 2330 { 2331 PnvMachineState *pnv = PNV_MACHINE(xi); 2332 int i, j; 2333 2334 for (i = 0; i < pnv->num_chips; i++) { 2335 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2336 2337 ics_resend(&chip8->psi.ics); 2338 2339 for (j = 0; j < chip8->num_phbs; j++) { 2340 PnvPHB *phb = chip8->phbs[j]; 2341 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2342 2343 ics_resend(&phb3->lsis); 2344 ics_resend(ICS(&phb3->msis)); 2345 } 2346 } 2347 } 2348 2349 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2350 { 2351 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2352 2353 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2354 } 2355 2356 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2357 Monitor *mon) 2358 { 2359 PnvMachineState *pnv = PNV_MACHINE(obj); 2360 int i; 2361 CPUState *cs; 2362 g_autoptr(GString) buf = g_string_new(""); 2363 g_autoptr(HumanReadableText) info = NULL; 2364 2365 CPU_FOREACH(cs) { 2366 PowerPCCPU *cpu = POWERPC_CPU(cs); 2367 2368 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2369 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2370 buf); 2371 } 2372 info = human_readable_text_from_str(buf); 2373 monitor_puts(mon, info->human_readable_text); 2374 2375 for (i = 0; i < pnv->num_chips; i++) { 2376 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2377 } 2378 } 2379 2380 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2381 uint8_t nvt_blk, uint32_t nvt_idx, 2382 bool cam_ignore, uint8_t priority, 2383 uint32_t logic_serv, 2384 XiveTCTXMatch *match) 2385 { 2386 PnvMachineState *pnv = PNV_MACHINE(xfb); 2387 int total_count = 0; 2388 int i; 2389 2390 for (i = 0; i < pnv->num_chips; i++) { 2391 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2392 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2393 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2394 int count; 2395 2396 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2397 priority, logic_serv, match); 2398 2399 if (count < 0) { 2400 return count; 2401 } 2402 2403 total_count += count; 2404 } 2405 2406 return total_count; 2407 } 2408 2409 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2410 uint8_t nvt_blk, uint32_t nvt_idx, 2411 bool cam_ignore, uint8_t priority, 2412 uint32_t logic_serv, 2413 XiveTCTXMatch *match) 2414 { 2415 PnvMachineState *pnv = PNV_MACHINE(xfb); 2416 int total_count = 0; 2417 int i; 2418 2419 for (i = 0; i < pnv->num_chips; i++) { 2420 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2421 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2422 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2423 int count; 2424 2425 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2426 priority, logic_serv, match); 2427 2428 if (count < 0) { 2429 return count; 2430 } 2431 2432 total_count += count; 2433 } 2434 2435 return total_count; 2436 } 2437 2438 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2439 { 2440 MachineClass *mc = MACHINE_CLASS(oc); 2441 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2442 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2443 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2444 2445 static GlobalProperty phb_compat[] = { 2446 { TYPE_PNV_PHB, "version", "3" }, 2447 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2448 }; 2449 2450 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2451 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2452 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2453 2454 xic->icp_get = pnv_icp_get; 2455 xic->ics_get = pnv_ics_get; 2456 xic->ics_resend = pnv_ics_resend; 2457 2458 pmc->compat = compat; 2459 pmc->compat_size = sizeof(compat); 2460 2461 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2462 } 2463 2464 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2465 { 2466 MachineClass *mc = MACHINE_CLASS(oc); 2467 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2468 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2469 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2470 2471 static GlobalProperty phb_compat[] = { 2472 { TYPE_PNV_PHB, "version", "4" }, 2473 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2474 }; 2475 2476 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2477 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2478 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2479 2480 xfc->match_nvt = pnv_match_nvt; 2481 2482 pmc->compat = compat; 2483 pmc->compat_size = sizeof(compat); 2484 pmc->dt_power_mgt = pnv_dt_power_mgt; 2485 2486 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2487 } 2488 2489 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2490 { 2491 MachineClass *mc = MACHINE_CLASS(oc); 2492 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2493 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2494 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2495 2496 static GlobalProperty phb_compat[] = { 2497 { TYPE_PNV_PHB, "version", "5" }, 2498 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2499 }; 2500 2501 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2502 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2503 2504 mc->alias = "powernv"; 2505 2506 pmc->compat = compat; 2507 pmc->compat_size = sizeof(compat); 2508 pmc->dt_power_mgt = pnv_dt_power_mgt; 2509 2510 xfc->match_nvt = pnv10_xive_match_nvt; 2511 2512 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2513 } 2514 2515 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2516 { 2517 MachineClass *mc = MACHINE_CLASS(oc); 2518 2519 pnv_machine_p10_common_class_init(oc, data); 2520 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2521 } 2522 2523 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2524 { 2525 MachineClass *mc = MACHINE_CLASS(oc); 2526 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2527 2528 pnv_machine_p10_common_class_init(oc, data); 2529 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2530 pmc->i2c_init = pnv_rainier_i2c_init; 2531 } 2532 2533 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2534 { 2535 PnvMachineState *pnv = PNV_MACHINE(obj); 2536 2537 return !!pnv->fw_load_addr; 2538 } 2539 2540 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2541 { 2542 PnvMachineState *pnv = PNV_MACHINE(obj); 2543 2544 if (value) { 2545 pnv->fw_load_addr = 0x8000000; 2546 } 2547 } 2548 2549 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2550 { 2551 CPUPPCState *env = cpu_env(cs); 2552 2553 cpu_synchronize_state(cs); 2554 ppc_cpu_do_system_reset(cs); 2555 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2556 /* 2557 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2558 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2559 * (PPC_BIT(43)). 2560 */ 2561 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2562 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2563 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2564 } 2565 } else { 2566 /* 2567 * For non-powersave system resets, SRR1[42:45] are defined to be 2568 * implementation-dependent. The POWER9 User Manual specifies that 2569 * an external (SCOM driven, which may come from a BMC nmi command or 2570 * another CPU requesting a NMI IPI) system reset exception should be 2571 * 0b0010 (PPC_BIT(44)). 2572 */ 2573 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2574 } 2575 } 2576 2577 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2578 { 2579 CPUState *cs; 2580 2581 CPU_FOREACH(cs) { 2582 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2583 } 2584 } 2585 2586 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2587 { 2588 MachineClass *mc = MACHINE_CLASS(oc); 2589 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2590 NMIClass *nc = NMI_CLASS(oc); 2591 2592 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2593 mc->init = pnv_init; 2594 mc->reset = pnv_reset; 2595 mc->max_cpus = MAX_CPUS; 2596 /* Pnv provides a AHCI device for storage */ 2597 mc->block_default_type = IF_IDE; 2598 mc->no_parallel = 1; 2599 mc->default_boot_order = NULL; 2600 /* 2601 * RAM defaults to less than 2048 for 32-bit hosts, and large 2602 * enough to fit the maximum initrd size at it's load address 2603 */ 2604 mc->default_ram_size = 1 * GiB; 2605 mc->default_ram_id = "pnv.ram"; 2606 ispc->print_info = pnv_pic_print_info; 2607 nc->nmi_monitor_handler = pnv_nmi; 2608 2609 object_class_property_add_bool(oc, "hb-mode", 2610 pnv_machine_get_hb, pnv_machine_set_hb); 2611 object_class_property_set_description(oc, "hb-mode", 2612 "Use a hostboot like boot loader"); 2613 } 2614 2615 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2616 { \ 2617 .name = type, \ 2618 .class_init = class_initfn, \ 2619 .parent = TYPE_PNV8_CHIP, \ 2620 } 2621 2622 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2623 { \ 2624 .name = type, \ 2625 .class_init = class_initfn, \ 2626 .parent = TYPE_PNV9_CHIP, \ 2627 } 2628 2629 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2630 { \ 2631 .name = type, \ 2632 .class_init = class_initfn, \ 2633 .parent = TYPE_PNV10_CHIP, \ 2634 } 2635 2636 static const TypeInfo types[] = { 2637 { 2638 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2639 .parent = MACHINE_TYPE_NAME("powernv10"), 2640 .class_init = pnv_machine_p10_rainier_class_init, 2641 }, 2642 { 2643 .name = MACHINE_TYPE_NAME("powernv10"), 2644 .parent = TYPE_PNV_MACHINE, 2645 .class_init = pnv_machine_power10_class_init, 2646 .interfaces = (InterfaceInfo[]) { 2647 { TYPE_XIVE_FABRIC }, 2648 { }, 2649 }, 2650 }, 2651 { 2652 .name = MACHINE_TYPE_NAME("powernv9"), 2653 .parent = TYPE_PNV_MACHINE, 2654 .class_init = pnv_machine_power9_class_init, 2655 .interfaces = (InterfaceInfo[]) { 2656 { TYPE_XIVE_FABRIC }, 2657 { }, 2658 }, 2659 }, 2660 { 2661 .name = MACHINE_TYPE_NAME("powernv8"), 2662 .parent = TYPE_PNV_MACHINE, 2663 .class_init = pnv_machine_power8_class_init, 2664 .interfaces = (InterfaceInfo[]) { 2665 { TYPE_XICS_FABRIC }, 2666 { }, 2667 }, 2668 }, 2669 { 2670 .name = TYPE_PNV_MACHINE, 2671 .parent = TYPE_MACHINE, 2672 .abstract = true, 2673 .instance_size = sizeof(PnvMachineState), 2674 .class_init = pnv_machine_class_init, 2675 .class_size = sizeof(PnvMachineClass), 2676 .interfaces = (InterfaceInfo[]) { 2677 { TYPE_INTERRUPT_STATS_PROVIDER }, 2678 { TYPE_NMI }, 2679 { }, 2680 }, 2681 }, 2682 { 2683 .name = TYPE_PNV_CHIP, 2684 .parent = TYPE_SYS_BUS_DEVICE, 2685 .class_init = pnv_chip_class_init, 2686 .instance_size = sizeof(PnvChip), 2687 .class_size = sizeof(PnvChipClass), 2688 .abstract = true, 2689 }, 2690 2691 /* 2692 * P10 chip and variants 2693 */ 2694 { 2695 .name = TYPE_PNV10_CHIP, 2696 .parent = TYPE_PNV_CHIP, 2697 .instance_init = pnv_chip_power10_instance_init, 2698 .instance_size = sizeof(Pnv10Chip), 2699 }, 2700 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2701 2702 /* 2703 * P9 chip and variants 2704 */ 2705 { 2706 .name = TYPE_PNV9_CHIP, 2707 .parent = TYPE_PNV_CHIP, 2708 .instance_init = pnv_chip_power9_instance_init, 2709 .instance_size = sizeof(Pnv9Chip), 2710 }, 2711 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2712 2713 /* 2714 * P8 chip and variants 2715 */ 2716 { 2717 .name = TYPE_PNV8_CHIP, 2718 .parent = TYPE_PNV_CHIP, 2719 .instance_init = pnv_chip_power8_instance_init, 2720 .instance_size = sizeof(Pnv8Chip), 2721 }, 2722 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2723 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2724 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2725 pnv_chip_power8nvl_class_init), 2726 }; 2727 2728 DEFINE_TYPES(types) 2729