1 /* 2 * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator 3 * 4 * Copyright (c) 2018-2021 BALATON Zoltan 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 * 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu-common.h" 12 #include "qemu/units.h" 13 #include "qapi/error.h" 14 #include "hw/hw.h" 15 #include "hw/ppc/ppc.h" 16 #include "hw/sysbus.h" 17 #include "hw/pci/pci_host.h" 18 #include "hw/irq.h" 19 #include "hw/pci-host/mv64361.h" 20 #include "hw/isa/vt82c686.h" 21 #include "hw/ide/pci.h" 22 #include "hw/i2c/smbus_eeprom.h" 23 #include "hw/qdev-properties.h" 24 #include "sysemu/reset.h" 25 #include "sysemu/runstate.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/fw-path-provider.h" 29 #include "elf.h" 30 #include "qemu/log.h" 31 #include "qemu/error-report.h" 32 #include "sysemu/kvm.h" 33 #include "kvm_ppc.h" 34 #include "exec/address-spaces.h" 35 #include "qom/qom-qobject.h" 36 #include "qapi/qmp/qdict.h" 37 #include "trace.h" 38 #include "qemu/datadir.h" 39 #include "sysemu/device_tree.h" 40 #include "hw/ppc/vof.h" 41 42 #include <libfdt.h> 43 44 #define PROM_FILENAME "vof.bin" 45 #define PROM_ADDR 0xfff00000 46 #define PROM_SIZE 0x80000 47 48 #define KVMPPC_HCALL_BASE 0xf000 49 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 50 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 51 52 #define H_SUCCESS 0 53 #define H_PRIVILEGE -3 /* Caller not privileged */ 54 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 55 56 #define BUS_FREQ_HZ 133333333 57 58 #define PCI0_CFG_ADDR 0xcf8 59 #define PCI0_MEM_BASE 0xc0000000 60 #define PCI0_MEM_SIZE 0x20000000 61 #define PCI0_IO_BASE 0xf8000000 62 #define PCI0_IO_SIZE 0x10000 63 64 #define PCI1_CFG_ADDR 0xc78 65 #define PCI1_MEM_BASE 0x80000000 66 #define PCI1_MEM_SIZE 0x40000000 67 #define PCI1_IO_BASE 0xfe000000 68 #define PCI1_IO_SIZE 0x10000 69 70 #define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2") 71 OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE) 72 73 struct Pegasos2MachineState { 74 MachineState parent_obj; 75 PowerPCCPU *cpu; 76 DeviceState *mv; 77 Vof *vof; 78 void *fdt_blob; 79 uint64_t kernel_addr; 80 uint64_t kernel_entry; 81 uint64_t kernel_size; 82 }; 83 84 static void *build_fdt(MachineState *machine, int *fdt_size); 85 86 static void pegasos2_cpu_reset(void *opaque) 87 { 88 PowerPCCPU *cpu = opaque; 89 Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine); 90 91 cpu_reset(CPU(cpu)); 92 cpu->env.spr[SPR_HID1] = 7ULL << 28; 93 if (pm->vof) { 94 cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20; 95 cpu->env.nip = 0x100; 96 } 97 } 98 99 static void pegasos2_init(MachineState *machine) 100 { 101 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 102 CPUPPCState *env; 103 MemoryRegion *rom = g_new(MemoryRegion, 1); 104 PCIBus *pci_bus; 105 PCIDevice *dev; 106 I2CBus *i2c_bus; 107 const char *fwname = machine->firmware ?: PROM_FILENAME; 108 char *filename; 109 int sz; 110 uint8_t *spd_data; 111 112 /* init CPU */ 113 pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 114 env = &pm->cpu->env; 115 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 116 error_report("Incompatible CPU, only 6xx bus supported"); 117 exit(1); 118 } 119 120 /* Set time-base frequency */ 121 cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4); 122 qemu_register_reset(pegasos2_cpu_reset, pm->cpu); 123 124 /* RAM */ 125 if (machine->ram_size > 2 * GiB) { 126 error_report("RAM size more than 2 GiB is not supported"); 127 exit(1); 128 } 129 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 130 131 /* allocate and load firmware */ 132 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname); 133 if (!filename) { 134 error_report("Could not find firmware '%s'", fwname); 135 exit(1); 136 } 137 if (!machine->firmware && !pm->vof) { 138 pm->vof = g_malloc0(sizeof(*pm->vof)); 139 } 140 memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal); 141 memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom); 142 sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1, 143 PPC_ELF_MACHINE, 0, 0); 144 if (sz <= 0) { 145 sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE); 146 } 147 if (sz <= 0 || sz > PROM_SIZE) { 148 error_report("Could not load firmware '%s'", filename); 149 exit(1); 150 } 151 g_free(filename); 152 if (pm->vof) { 153 pm->vof->fw_size = sz; 154 } 155 156 /* Marvell Discovery II system controller */ 157 pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1, 158 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT])); 159 pci_bus = mv64361_get_pci_bus(pm->mv, 1); 160 161 /* VIA VT8231 South Bridge (multifunction PCI device) */ 162 /* VT8231 function 0: PCI-to-ISA Bridge */ 163 dev = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), true, 164 TYPE_VT8231_ISA); 165 qdev_connect_gpio_out(DEVICE(dev), 0, 166 qdev_get_gpio_in_named(pm->mv, "gpp", 31)); 167 168 /* VT8231 function 1: IDE Controller */ 169 dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 1), "via-ide"); 170 pci_ide_create_devs(dev); 171 172 /* VT8231 function 2-3: USB Ports */ 173 pci_create_simple(pci_bus, PCI_DEVFN(12, 2), "vt82c686b-usb-uhci"); 174 pci_create_simple(pci_bus, PCI_DEVFN(12, 3), "vt82c686b-usb-uhci"); 175 176 /* VT8231 function 4: Power Management Controller */ 177 dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 4), TYPE_VT8231_PM); 178 i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c")); 179 spd_data = spd_data_generate(DDR, machine->ram_size); 180 smbus_eeprom_init_one(i2c_bus, 0x57, spd_data); 181 182 /* VT8231 function 5-6: AC97 Audio & Modem */ 183 pci_create_simple(pci_bus, PCI_DEVFN(12, 5), TYPE_VIA_AC97); 184 pci_create_simple(pci_bus, PCI_DEVFN(12, 6), TYPE_VIA_MC97); 185 186 /* other PC hardware */ 187 pci_vga_init(pci_bus); 188 189 if (machine->kernel_filename) { 190 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL, 191 &pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1, 192 PPC_ELF_MACHINE, 0, 0); 193 if (sz <= 0) { 194 error_report("Could not load kernel '%s'", 195 machine->kernel_filename); 196 exit(1); 197 } 198 pm->kernel_size = sz; 199 if (!pm->vof) { 200 warn_report("Option -kernel may be ineffective with -bios."); 201 } 202 } else if (pm->vof) { 203 warn_report("Using Virtual OpenFirmware but no -kernel option."); 204 } 205 206 if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) { 207 warn_report("Option -append may be ineffective with -bios."); 208 } 209 } 210 211 static uint32_t pegasos2_mv_reg_read(Pegasos2MachineState *pm, 212 uint32_t addr, uint32_t len) 213 { 214 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); 215 uint64_t val = 0xffffffffULL; 216 memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE, 217 MEMTXATTRS_UNSPECIFIED); 218 return val; 219 } 220 221 static void pegasos2_mv_reg_write(Pegasos2MachineState *pm, uint32_t addr, 222 uint32_t len, uint32_t val) 223 { 224 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); 225 memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE, 226 MEMTXATTRS_UNSPECIFIED); 227 } 228 229 static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus, 230 uint32_t addr, uint32_t len) 231 { 232 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; 233 uint64_t val = 0xffffffffULL; 234 235 if (len <= 4) { 236 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); 237 val = pegasos2_mv_reg_read(pm, pcicfg + 4, len); 238 } 239 return val; 240 } 241 242 static void pegasos2_pci_config_write(Pegasos2MachineState *pm, int bus, 243 uint32_t addr, uint32_t len, uint32_t val) 244 { 245 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; 246 247 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); 248 pegasos2_mv_reg_write(pm, pcicfg + 4, len, val); 249 } 250 251 static void pegasos2_machine_reset(MachineState *machine) 252 { 253 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 254 void *fdt; 255 uint64_t d[2]; 256 int sz; 257 258 qemu_devices_reset(); 259 if (!pm->vof) { 260 return; /* Firmware should set up machine so nothing to do */ 261 } 262 263 /* Otherwise, set up devices that board firmware would normally do */ 264 pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff); 265 pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc); 266 pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400); 267 pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000); 268 pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000); 269 pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO | 270 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 271 pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO | 272 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 273 274 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 275 PCI_INTERRUPT_LINE, 2, 0x9); 276 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 277 0x50, 1, 0x2); 278 279 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 280 PCI_INTERRUPT_LINE, 2, 0x109); 281 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 282 PCI_CLASS_PROG, 1, 0xf); 283 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 284 0x40, 1, 0xb); 285 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 286 0x50, 4, 0x17171717); 287 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 288 PCI_COMMAND, 2, 0x87); 289 290 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) | 291 PCI_INTERRUPT_LINE, 2, 0x409); 292 293 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) | 294 PCI_INTERRUPT_LINE, 2, 0x409); 295 296 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 297 PCI_INTERRUPT_LINE, 2, 0x9); 298 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 299 0x48, 4, 0xf00); 300 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 301 0x40, 4, 0x558020); 302 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 303 0x90, 4, 0xd00); 304 305 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) | 306 PCI_INTERRUPT_LINE, 2, 0x309); 307 308 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) | 309 PCI_INTERRUPT_LINE, 2, 0x309); 310 311 /* Device tree and VOF set up */ 312 vof_init(pm->vof, machine->ram_size, &error_fatal); 313 if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) { 314 error_report("Memory allocation for stack failed"); 315 exit(1); 316 } 317 if (pm->kernel_size && 318 vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) { 319 error_report("Memory for kernel is in use"); 320 exit(1); 321 } 322 fdt = build_fdt(machine, &sz); 323 /* FIXME: VOF assumes entry is same as load address */ 324 d[0] = cpu_to_be64(pm->kernel_entry); 325 d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr)); 326 qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d)); 327 328 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 329 g_free(pm->fdt_blob); 330 pm->fdt_blob = fdt; 331 332 vof_build_dt(fdt, pm->vof); 333 vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe"); 334 pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine); 335 } 336 337 enum pegasos2_rtas_tokens { 338 RTAS_RESTART_RTAS = 0, 339 RTAS_NVRAM_FETCH = 1, 340 RTAS_NVRAM_STORE = 2, 341 RTAS_GET_TIME_OF_DAY = 3, 342 RTAS_SET_TIME_OF_DAY = 4, 343 RTAS_EVENT_SCAN = 6, 344 RTAS_CHECK_EXCEPTION = 7, 345 RTAS_READ_PCI_CONFIG = 8, 346 RTAS_WRITE_PCI_CONFIG = 9, 347 RTAS_DISPLAY_CHARACTER = 10, 348 RTAS_SET_INDICATOR = 11, 349 RTAS_POWER_OFF = 17, 350 RTAS_SUSPEND = 18, 351 RTAS_HIBERNATE = 19, 352 RTAS_SYSTEM_REBOOT = 20, 353 }; 354 355 static target_ulong pegasos2_rtas(PowerPCCPU *cpu, Pegasos2MachineState *pm, 356 target_ulong args_real) 357 { 358 AddressSpace *as = CPU(cpu)->as; 359 uint32_t token = ldl_be_phys(as, args_real); 360 uint32_t nargs = ldl_be_phys(as, args_real + 4); 361 uint32_t nrets = ldl_be_phys(as, args_real + 8); 362 uint32_t args = args_real + 12; 363 uint32_t rets = args_real + 12 + nargs * 4; 364 365 if (nrets < 1) { 366 qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n"); 367 return H_PARAMETER; 368 } 369 switch (token) { 370 case RTAS_GET_TIME_OF_DAY: 371 { 372 QObject *qo = object_property_get_qobject(qdev_get_machine(), 373 "rtc-time", &error_fatal); 374 QDict *qd = qobject_to(QDict, qo); 375 376 if (nargs != 0 || nrets != 8 || !qd) { 377 stl_be_phys(as, rets, -1); 378 qobject_unref(qo); 379 return H_PARAMETER; 380 } 381 382 stl_be_phys(as, rets, 0); 383 stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900); 384 stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1); 385 stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday")); 386 stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour")); 387 stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min")); 388 stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec")); 389 stl_be_phys(as, rets + 28, 0); 390 qobject_unref(qo); 391 return H_SUCCESS; 392 } 393 case RTAS_READ_PCI_CONFIG: 394 { 395 uint32_t addr, len, val; 396 397 if (nargs != 2 || nrets != 2) { 398 stl_be_phys(as, rets, -1); 399 return H_PARAMETER; 400 } 401 addr = ldl_be_phys(as, args); 402 len = ldl_be_phys(as, args + 4); 403 val = pegasos2_pci_config_read(pm, !(addr >> 24), 404 addr & 0x0fffffff, len); 405 stl_be_phys(as, rets, 0); 406 stl_be_phys(as, rets + 4, val); 407 return H_SUCCESS; 408 } 409 case RTAS_WRITE_PCI_CONFIG: 410 { 411 uint32_t addr, len, val; 412 413 if (nargs != 3 || nrets != 1) { 414 stl_be_phys(as, rets, -1); 415 return H_PARAMETER; 416 } 417 addr = ldl_be_phys(as, args); 418 len = ldl_be_phys(as, args + 4); 419 val = ldl_be_phys(as, args + 8); 420 pegasos2_pci_config_write(pm, !(addr >> 24), 421 addr & 0x0fffffff, len, val); 422 stl_be_phys(as, rets, 0); 423 return H_SUCCESS; 424 } 425 case RTAS_DISPLAY_CHARACTER: 426 if (nargs != 1 || nrets != 1) { 427 stl_be_phys(as, rets, -1); 428 return H_PARAMETER; 429 } 430 qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args)); 431 stl_be_phys(as, rets, 0); 432 return H_SUCCESS; 433 case RTAS_POWER_OFF: 434 { 435 if (nargs != 2 || nrets != 1) { 436 stl_be_phys(as, rets, -1); 437 return H_PARAMETER; 438 } 439 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 440 stl_be_phys(as, rets, 0); 441 return H_SUCCESS; 442 } 443 default: 444 qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n", 445 token, nargs, nrets); 446 stl_be_phys(as, rets, 0); 447 return H_SUCCESS; 448 } 449 } 450 451 static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 452 { 453 Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp); 454 CPUPPCState *env = &cpu->env; 455 456 /* The TCG path should also be holding the BQL at this point */ 457 g_assert(qemu_mutex_iothread_locked()); 458 459 if (msr_pr) { 460 qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n"); 461 env->gpr[3] = H_PRIVILEGE; 462 } else if (env->gpr[3] == KVMPPC_H_RTAS) { 463 env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]); 464 } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) { 465 int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob, 466 env->gpr[4]); 467 env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS); 468 } else { 469 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx 470 "\n", env->gpr[3]); 471 env->gpr[3] = -1; 472 } 473 } 474 475 static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 476 { 477 } 478 479 static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 480 { 481 return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1]; 482 } 483 484 static bool pegasos2_setprop(MachineState *ms, const char *path, 485 const char *propname, void *val, int vallen) 486 { 487 return true; 488 } 489 490 static void pegasos2_machine_class_init(ObjectClass *oc, void *data) 491 { 492 MachineClass *mc = MACHINE_CLASS(oc); 493 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 494 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 495 496 mc->desc = "Genesi/bPlan Pegasos II"; 497 mc->init = pegasos2_init; 498 mc->reset = pegasos2_machine_reset; 499 mc->block_default_type = IF_IDE; 500 mc->default_boot_order = "cd"; 501 mc->default_display = "std"; 502 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); 503 mc->default_ram_id = "pegasos2.ram"; 504 mc->default_ram_size = 512 * MiB; 505 506 vhc->hypercall = pegasos2_hypercall; 507 vhc->cpu_exec_enter = vhyp_nop; 508 vhc->cpu_exec_exit = vhyp_nop; 509 vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr; 510 511 vmc->setprop = pegasos2_setprop; 512 } 513 514 static const TypeInfo pegasos2_machine_info = { 515 .name = TYPE_PEGASOS2_MACHINE, 516 .parent = TYPE_MACHINE, 517 .class_init = pegasos2_machine_class_init, 518 .instance_size = sizeof(Pegasos2MachineState), 519 .interfaces = (InterfaceInfo[]) { 520 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 521 { TYPE_VOF_MACHINE_IF }, 522 { } 523 }, 524 }; 525 526 static void pegasos2_machine_register_types(void) 527 { 528 type_register_static(&pegasos2_machine_info); 529 } 530 531 type_init(pegasos2_machine_register_types) 532 533 /* FDT creation for passing to firmware */ 534 535 typedef struct { 536 void *fdt; 537 const char *path; 538 } FDTInfo; 539 540 /* We do everything in reverse order so it comes out right in the tree */ 541 542 static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 543 { 544 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi"); 545 } 546 547 static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 548 { 549 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0); 550 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1); 551 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb"); 552 } 553 554 static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 555 { 556 GString *name = g_string_sized_new(64); 557 uint32_t cells[3]; 558 559 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1); 560 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2); 561 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa"); 562 qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa"); 563 564 /* addional devices */ 565 g_string_printf(name, "%s/lpt@i3bc", fi->path); 566 qemu_fdt_add_subnode(fi->fdt, name->str); 567 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 568 cells[0] = cpu_to_be32(7); 569 cells[1] = 0; 570 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 571 cells, 2 * sizeof(cells[0])); 572 cells[0] = cpu_to_be32(1); 573 cells[1] = cpu_to_be32(0x3bc); 574 cells[2] = cpu_to_be32(8); 575 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 576 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt"); 577 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt"); 578 579 g_string_printf(name, "%s/fdc@i3f0", fi->path); 580 qemu_fdt_add_subnode(fi->fdt, name->str); 581 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 582 cells[0] = cpu_to_be32(6); 583 cells[1] = 0; 584 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 585 cells, 2 * sizeof(cells[0])); 586 cells[0] = cpu_to_be32(1); 587 cells[1] = cpu_to_be32(0x3f0); 588 cells[2] = cpu_to_be32(8); 589 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 590 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc"); 591 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc"); 592 593 g_string_printf(name, "%s/timer@i40", fi->path); 594 qemu_fdt_add_subnode(fi->fdt, name->str); 595 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 596 cells[0] = cpu_to_be32(1); 597 cells[1] = cpu_to_be32(0x40); 598 cells[2] = cpu_to_be32(8); 599 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 600 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer"); 601 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer"); 602 603 g_string_printf(name, "%s/rtc@i70", fi->path); 604 qemu_fdt_add_subnode(fi->fdt, name->str); 605 qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc"); 606 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 607 cells[0] = cpu_to_be32(8); 608 cells[1] = 0; 609 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 610 cells, 2 * sizeof(cells[0])); 611 cells[0] = cpu_to_be32(1); 612 cells[1] = cpu_to_be32(0x70); 613 cells[2] = cpu_to_be32(2); 614 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 615 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc"); 616 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc"); 617 618 g_string_printf(name, "%s/keyboard@i60", fi->path); 619 qemu_fdt_add_subnode(fi->fdt, name->str); 620 cells[0] = cpu_to_be32(1); 621 cells[1] = 0; 622 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 623 cells, 2 * sizeof(cells[0])); 624 cells[0] = cpu_to_be32(1); 625 cells[1] = cpu_to_be32(0x60); 626 cells[2] = cpu_to_be32(5); 627 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 628 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard"); 629 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard"); 630 631 g_string_printf(name, "%s/8042@i60", fi->path); 632 qemu_fdt_add_subnode(fi->fdt, name->str); 633 qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2); 634 qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0); 635 qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1); 636 qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", ""); 637 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 638 cells[0] = cpu_to_be32(1); 639 cells[1] = cpu_to_be32(0x60); 640 cells[2] = cpu_to_be32(5); 641 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 642 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", ""); 643 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042"); 644 645 g_string_printf(name, "%s/serial@i2f8", fi->path); 646 qemu_fdt_add_subnode(fi->fdt, name->str); 647 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 648 cells[0] = cpu_to_be32(3); 649 cells[1] = 0; 650 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 651 cells, 2 * sizeof(cells[0])); 652 cells[0] = cpu_to_be32(1); 653 cells[1] = cpu_to_be32(0x2f8); 654 cells[2] = cpu_to_be32(8); 655 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 656 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial"); 657 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial"); 658 659 g_string_free(name, TRUE); 660 } 661 662 static struct { 663 const char *id; 664 const char *name; 665 void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi); 666 } device_map[] = { 667 { "pci11ab,6460", "host", NULL }, 668 { "pci1106,8231", "isa", dt_isa }, 669 { "pci1106,571", "ide", dt_ide }, 670 { "pci1106,3044", "firewire", NULL }, 671 { "pci1106,3038", "usb", dt_usb }, 672 { "pci1106,8235", "other", NULL }, 673 { "pci1106,3058", "sound", NULL }, 674 { NULL, NULL } 675 }; 676 677 static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque) 678 { 679 FDTInfo *fi = opaque; 680 GString *node = g_string_new(NULL); 681 uint32_t cells[(PCI_NUM_REGIONS + 1) * 5]; 682 int i, j; 683 const char *name = NULL; 684 g_autofree const gchar *pn = g_strdup_printf("pci%x,%x", 685 pci_get_word(&d->config[PCI_VENDOR_ID]), 686 pci_get_word(&d->config[PCI_DEVICE_ID])); 687 688 for (i = 0; device_map[i].id; i++) { 689 if (!strcmp(pn, device_map[i].id)) { 690 name = device_map[i].name; 691 break; 692 } 693 } 694 g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn), 695 PCI_SLOT(d->devfn)); 696 if (PCI_FUNC(d->devfn)) { 697 g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn)); 698 } 699 700 qemu_fdt_add_subnode(fi->fdt, node->str); 701 if (device_map[i].dtf) { 702 FDTInfo cfi = { fi->fdt, node->str }; 703 device_map[i].dtf(bus, d, &cfi); 704 } 705 cells[0] = cpu_to_be32(d->devfn << 8); 706 cells[1] = 0; 707 cells[2] = 0; 708 cells[3] = 0; 709 cells[4] = 0; 710 j = 5; 711 for (i = 0; i < PCI_NUM_REGIONS; i++) { 712 if (!d->io_regions[i].size) { 713 continue; 714 } 715 cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4)); 716 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 717 cells[j] |= cpu_to_be32(1 << 24); 718 } else { 719 cells[j] |= cpu_to_be32(2 << 24); 720 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 721 cells[j] |= cpu_to_be32(4 << 28); 722 } 723 } 724 cells[j + 1] = 0; 725 cells[j + 2] = 0; 726 cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32); 727 cells[j + 4] = cpu_to_be32(d->io_regions[i].size); 728 j += 5; 729 } 730 qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0])); 731 qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn); 732 if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) { 733 qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts", 734 pci_get_byte(&d->config[PCI_INTERRUPT_PIN])); 735 } 736 /* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */ 737 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id", 738 pci_get_word(&d->config[PCI_SUBSYSTEM_ID])); 739 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id", 740 pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID])); 741 cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]); 742 qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8); 743 qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff); 744 qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id", 745 pci_get_word(&d->config[PCI_DEVICE_ID])); 746 qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id", 747 pci_get_word(&d->config[PCI_VENDOR_ID])); 748 749 g_string_free(node, TRUE); 750 } 751 752 static void *build_fdt(MachineState *machine, int *fdt_size) 753 { 754 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 755 PowerPCCPU *cpu = pm->cpu; 756 PCIBus *pci_bus; 757 FDTInfo fi; 758 uint32_t cells[16]; 759 void *fdt = create_device_tree(fdt_size); 760 761 fi.fdt = fdt; 762 763 /* root node */ 764 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description", 765 "Pegasos CHRP PowerPC System"); 766 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2"); 767 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH"); 768 qemu_fdt_setprop_string(fdt, "/", "revision", "2B"); 769 qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2"); 770 qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp"); 771 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1); 772 qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2"); 773 774 /* pci@c0000000 */ 775 qemu_fdt_add_subnode(fdt, "/pci@c0000000"); 776 cells[0] = 0; 777 cells[1] = 0; 778 qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range", 779 cells, 2 * sizeof(cells[0])); 780 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1); 781 cells[0] = cpu_to_be32(PCI0_MEM_BASE); 782 cells[1] = cpu_to_be32(PCI0_MEM_SIZE); 783 qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0])); 784 cells[0] = cpu_to_be32(0x01000000); 785 cells[1] = 0; 786 cells[2] = 0; 787 cells[3] = cpu_to_be32(PCI0_IO_BASE); 788 cells[4] = 0; 789 cells[5] = cpu_to_be32(PCI0_IO_SIZE); 790 cells[6] = cpu_to_be32(0x02000000); 791 cells[7] = 0; 792 cells[8] = cpu_to_be32(PCI0_MEM_BASE); 793 cells[9] = cpu_to_be32(PCI0_MEM_BASE); 794 cells[10] = 0; 795 cells[11] = cpu_to_be32(PCI0_MEM_SIZE); 796 qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges", 797 cells, 12 * sizeof(cells[0])); 798 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2); 799 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3); 800 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci"); 801 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci"); 802 803 fi.path = "/pci@c0000000"; 804 pci_bus = mv64361_get_pci_bus(pm->mv, 0); 805 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); 806 807 /* pci@80000000 */ 808 qemu_fdt_add_subnode(fdt, "/pci@80000000"); 809 cells[0] = 0; 810 cells[1] = 0; 811 qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range", 812 cells, 2 * sizeof(cells[0])); 813 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0); 814 cells[0] = cpu_to_be32(PCI1_MEM_BASE); 815 cells[1] = cpu_to_be32(PCI1_MEM_SIZE); 816 qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0])); 817 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge", 818 0xf1000cb4); 819 cells[0] = cpu_to_be32(0x01000000); 820 cells[1] = 0; 821 cells[2] = 0; 822 cells[3] = cpu_to_be32(PCI1_IO_BASE); 823 cells[4] = 0; 824 cells[5] = cpu_to_be32(PCI1_IO_SIZE); 825 cells[6] = cpu_to_be32(0x02000000); 826 cells[7] = 0; 827 cells[8] = cpu_to_be32(PCI1_MEM_BASE); 828 cells[9] = cpu_to_be32(PCI1_MEM_BASE); 829 cells[10] = 0; 830 cells[11] = cpu_to_be32(PCI1_MEM_SIZE); 831 qemu_fdt_setprop(fdt, "/pci@80000000", "ranges", 832 cells, 12 * sizeof(cells[0])); 833 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2); 834 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3); 835 qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci"); 836 qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci"); 837 838 fi.path = "/pci@80000000"; 839 pci_bus = mv64361_get_pci_bus(pm->mv, 1); 840 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); 841 842 qemu_fdt_add_subnode(fdt, "/failsafe"); 843 qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial"); 844 qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe"); 845 846 qemu_fdt_add_subnode(fdt, "/rtas"); 847 qemu_fdt_setprop_cell(fdt, "/rtas", "system-reboot", RTAS_SYSTEM_REBOOT); 848 qemu_fdt_setprop_cell(fdt, "/rtas", "hibernate", RTAS_HIBERNATE); 849 qemu_fdt_setprop_cell(fdt, "/rtas", "suspend", RTAS_SUSPEND); 850 qemu_fdt_setprop_cell(fdt, "/rtas", "power-off", RTAS_POWER_OFF); 851 qemu_fdt_setprop_cell(fdt, "/rtas", "set-indicator", RTAS_SET_INDICATOR); 852 qemu_fdt_setprop_cell(fdt, "/rtas", "display-character", 853 RTAS_DISPLAY_CHARACTER); 854 qemu_fdt_setprop_cell(fdt, "/rtas", "write-pci-config", 855 RTAS_WRITE_PCI_CONFIG); 856 qemu_fdt_setprop_cell(fdt, "/rtas", "read-pci-config", 857 RTAS_READ_PCI_CONFIG); 858 /* Pegasos2 firmware misspells check-exception and guests use that */ 859 qemu_fdt_setprop_cell(fdt, "/rtas", "check-execption", 860 RTAS_CHECK_EXCEPTION); 861 qemu_fdt_setprop_cell(fdt, "/rtas", "event-scan", RTAS_EVENT_SCAN); 862 qemu_fdt_setprop_cell(fdt, "/rtas", "set-time-of-day", 863 RTAS_SET_TIME_OF_DAY); 864 qemu_fdt_setprop_cell(fdt, "/rtas", "get-time-of-day", 865 RTAS_GET_TIME_OF_DAY); 866 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-store", RTAS_NVRAM_STORE); 867 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-fetch", RTAS_NVRAM_FETCH); 868 qemu_fdt_setprop_cell(fdt, "/rtas", "restart-rtas", RTAS_RESTART_RTAS); 869 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-error-log-max", 0); 870 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-event-scan-rate", 0); 871 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0); 872 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20); 873 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1); 874 875 /* cpus */ 876 qemu_fdt_add_subnode(fdt, "/cpus"); 877 qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1); 878 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 879 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 880 qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus"); 881 882 /* FIXME Get CPU name from CPU object */ 883 const char *cp = "/cpus/PowerPC,G4"; 884 qemu_fdt_add_subnode(fdt, cp); 885 qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0); 886 qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000); 887 qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size", 888 cpu->env.dcache_line_size); 889 qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size", 890 cpu->env.dcache_line_size); 891 qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000); 892 qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size", 893 cpu->env.icache_line_size); 894 qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size", 895 cpu->env.icache_line_size); 896 if (cpu->env.id_tlbs) { 897 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways); 898 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way); 899 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways); 900 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way); 901 qemu_fdt_setprop_string(fdt, cp, "tlb-split", ""); 902 } 903 qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways); 904 qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb); 905 qemu_fdt_setprop_string(fdt, cp, "state", "running"); 906 if (cpu->env.insns_flags & PPC_ALTIVEC) { 907 qemu_fdt_setprop_string(fdt, cp, "altivec", ""); 908 qemu_fdt_setprop_string(fdt, cp, "data-streams", ""); 909 } 910 /* 911 * FIXME What flags do data-streams, external-control and 912 * performance-monitor depend on? 913 */ 914 qemu_fdt_setprop_string(fdt, cp, "external-control", ""); 915 if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) { 916 qemu_fdt_setprop_string(fdt, cp, "general-purpose", ""); 917 } 918 qemu_fdt_setprop_string(fdt, cp, "performance-monitor", ""); 919 if (cpu->env.insns_flags & PPC_FLOAT_FRES) { 920 qemu_fdt_setprop_string(fdt, cp, "graphics", ""); 921 } 922 qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4); 923 qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency", 924 cpu->env.tb_env->tb_freq); 925 qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ); 926 qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5); 927 qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]); 928 cells[0] = 0; 929 cells[1] = 0; 930 qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0])); 931 qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu"); 932 qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1); 933 934 /* memory */ 935 qemu_fdt_add_subnode(fdt, "/memory@0"); 936 cells[0] = 0; 937 cells[1] = cpu_to_be32(machine->ram_size); 938 qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0])); 939 qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory"); 940 qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory"); 941 942 qemu_fdt_add_subnode(fdt, "/chosen"); 943 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 944 machine->kernel_cmdline ?: ""); 945 qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen"); 946 947 qemu_fdt_add_subnode(fdt, "/openprom"); 948 qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1"); 949 950 return fdt; 951 } 952