1 /* 2 * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator 3 * 4 * Copyright (c) 2018-2021 BALATON Zoltan 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 * 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/units.h" 12 #include "qapi/error.h" 13 #include "hw/ppc/ppc.h" 14 #include "hw/sysbus.h" 15 #include "hw/pci/pci_host.h" 16 #include "hw/irq.h" 17 #include "hw/pci-host/mv64361.h" 18 #include "hw/isa/vt82c686.h" 19 #include "hw/ide/pci.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/qdev-properties.h" 22 #include "sysemu/reset.h" 23 #include "sysemu/runstate.h" 24 #include "sysemu/qtest.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/fw-path-provider.h" 28 #include "elf.h" 29 #include "qemu/log.h" 30 #include "qemu/error-report.h" 31 #include "sysemu/kvm.h" 32 #include "kvm_ppc.h" 33 #include "exec/address-spaces.h" 34 #include "qom/qom-qobject.h" 35 #include "qapi/qmp/qdict.h" 36 #include "trace.h" 37 #include "qemu/datadir.h" 38 #include "sysemu/device_tree.h" 39 #include "hw/ppc/vof.h" 40 41 #include <libfdt.h> 42 43 #define PROM_FILENAME "vof.bin" 44 #define PROM_ADDR 0xfff00000 45 #define PROM_SIZE 0x80000 46 47 #define INITRD_MIN_ADDR 0x600000 48 49 #define KVMPPC_HCALL_BASE 0xf000 50 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 51 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 52 53 #define H_SUCCESS 0 54 #define H_PRIVILEGE -3 /* Caller not privileged */ 55 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 56 57 #define BUS_FREQ_HZ 133333333 58 59 #define PCI0_CFG_ADDR 0xcf8 60 #define PCI0_MEM_BASE 0xc0000000 61 #define PCI0_MEM_SIZE 0x20000000 62 #define PCI0_IO_BASE 0xf8000000 63 #define PCI0_IO_SIZE 0x10000 64 65 #define PCI1_CFG_ADDR 0xc78 66 #define PCI1_MEM_BASE 0x80000000 67 #define PCI1_MEM_SIZE 0x40000000 68 #define PCI1_IO_BASE 0xfe000000 69 #define PCI1_IO_SIZE 0x10000 70 71 #define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2") 72 OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE) 73 74 struct Pegasos2MachineState { 75 MachineState parent_obj; 76 PowerPCCPU *cpu; 77 DeviceState *mv; 78 qemu_irq mv_pirq[PCI_NUM_PINS]; 79 qemu_irq via_pirq[PCI_NUM_PINS]; 80 Vof *vof; 81 void *fdt_blob; 82 uint64_t kernel_addr; 83 uint64_t kernel_entry; 84 uint64_t kernel_size; 85 uint64_t initrd_addr; 86 uint64_t initrd_size; 87 }; 88 89 static void *build_fdt(MachineState *machine, int *fdt_size); 90 91 static void pegasos2_cpu_reset(void *opaque) 92 { 93 PowerPCCPU *cpu = opaque; 94 Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine); 95 96 cpu_reset(CPU(cpu)); 97 cpu->env.spr[SPR_HID1] = 7ULL << 28; 98 if (pm->vof) { 99 cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20; 100 cpu->env.nip = 0x100; 101 } 102 cpu_ppc_tb_reset(&cpu->env); 103 } 104 105 static void pegasos2_pci_irq(void *opaque, int n, int level) 106 { 107 Pegasos2MachineState *pm = opaque; 108 109 /* PCI interrupt lines are connected to both MV64361 and VT8231 */ 110 qemu_set_irq(pm->mv_pirq[n], level); 111 qemu_set_irq(pm->via_pirq[n], level); 112 } 113 114 static void pegasos2_init(MachineState *machine) 115 { 116 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 117 CPUPPCState *env; 118 MemoryRegion *rom = g_new(MemoryRegion, 1); 119 PCIBus *pci_bus; 120 Object *via; 121 PCIDevice *dev; 122 I2CBus *i2c_bus; 123 const char *fwname = machine->firmware ?: PROM_FILENAME; 124 char *filename; 125 int i; 126 ssize_t sz; 127 uint8_t *spd_data; 128 129 /* init CPU */ 130 pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 131 env = &pm->cpu->env; 132 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 133 error_report("Incompatible CPU, only 6xx bus supported"); 134 exit(1); 135 } 136 137 /* Set time-base frequency */ 138 cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4); 139 qemu_register_reset(pegasos2_cpu_reset, pm->cpu); 140 141 /* RAM */ 142 if (machine->ram_size > 2 * GiB) { 143 error_report("RAM size more than 2 GiB is not supported"); 144 exit(1); 145 } 146 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 147 148 /* allocate and load firmware */ 149 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname); 150 if (!filename) { 151 error_report("Could not find firmware '%s'", fwname); 152 exit(1); 153 } 154 if (!machine->firmware && !pm->vof) { 155 pm->vof = g_malloc0(sizeof(*pm->vof)); 156 } 157 memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal); 158 memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom); 159 sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1, 160 PPC_ELF_MACHINE, 0, 0); 161 if (sz <= 0) { 162 sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE); 163 } 164 if (sz <= 0 || sz > PROM_SIZE) { 165 error_report("Could not load firmware '%s'", filename); 166 exit(1); 167 } 168 g_free(filename); 169 if (pm->vof) { 170 pm->vof->fw_size = sz; 171 } 172 173 /* Marvell Discovery II system controller */ 174 pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1, 175 qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_INT))); 176 for (i = 0; i < PCI_NUM_PINS; i++) { 177 pm->mv_pirq[i] = qdev_get_gpio_in_named(pm->mv, "gpp", 12 + i); 178 } 179 pci_bus = mv64361_get_pci_bus(pm->mv, 1); 180 pci_bus_irqs(pci_bus, pegasos2_pci_irq, pm, PCI_NUM_PINS); 181 182 /* VIA VT8231 South Bridge (multifunction PCI device) */ 183 via = OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), 184 TYPE_VT8231_ISA)); 185 for (i = 0; i < PCI_NUM_PINS; i++) { 186 pm->via_pirq[i] = qdev_get_gpio_in_named(DEVICE(via), "pirq", i); 187 } 188 object_property_add_alias(OBJECT(machine), "rtc-time", 189 object_resolve_path_component(via, "rtc"), 190 "date"); 191 qdev_connect_gpio_out(DEVICE(via), 0, 192 qdev_get_gpio_in_named(pm->mv, "gpp", 31)); 193 194 dev = PCI_DEVICE(object_resolve_path_component(via, "ide")); 195 pci_ide_create_devs(dev); 196 197 dev = PCI_DEVICE(object_resolve_path_component(via, "pm")); 198 i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c")); 199 spd_data = spd_data_generate(DDR, machine->ram_size); 200 smbus_eeprom_init_one(i2c_bus, 0x57, spd_data); 201 202 /* other PC hardware */ 203 pci_vga_init(pci_bus); 204 205 if (machine->kernel_filename) { 206 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL, 207 &pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1, 208 PPC_ELF_MACHINE, 0, 0); 209 if (sz <= 0) { 210 error_report("Could not load kernel '%s'", 211 machine->kernel_filename); 212 exit(1); 213 } 214 pm->kernel_size = sz; 215 if (!pm->vof) { 216 warn_report("Option -kernel may be ineffective with -bios."); 217 } 218 } else if (pm->vof && !qtest_enabled()) { 219 warn_report("Using Virtual OpenFirmware but no -kernel option."); 220 } 221 222 if (machine->initrd_filename) { 223 pm->initrd_addr = pm->kernel_addr + pm->kernel_size + 64 * KiB; 224 pm->initrd_addr = ROUND_UP(pm->initrd_addr, 4); 225 pm->initrd_addr = MAX(pm->initrd_addr, INITRD_MIN_ADDR); 226 sz = load_image_targphys(machine->initrd_filename, pm->initrd_addr, 227 machine->ram_size - pm->initrd_addr); 228 if (sz <= 0) { 229 error_report("Could not load initrd '%s'", 230 machine->initrd_filename); 231 exit(1); 232 } 233 pm->initrd_size = sz; 234 } 235 236 if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) { 237 warn_report("Option -append may be ineffective with -bios."); 238 } 239 } 240 241 static uint32_t pegasos2_mv_reg_read(Pegasos2MachineState *pm, 242 uint32_t addr, uint32_t len) 243 { 244 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); 245 uint64_t val = 0xffffffffULL; 246 memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE, 247 MEMTXATTRS_UNSPECIFIED); 248 return val; 249 } 250 251 static void pegasos2_mv_reg_write(Pegasos2MachineState *pm, uint32_t addr, 252 uint32_t len, uint32_t val) 253 { 254 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); 255 memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE, 256 MEMTXATTRS_UNSPECIFIED); 257 } 258 259 static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus, 260 uint32_t addr, uint32_t len) 261 { 262 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; 263 uint64_t val = 0xffffffffULL; 264 265 if (len <= 4) { 266 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); 267 val = pegasos2_mv_reg_read(pm, pcicfg + 4, len); 268 } 269 return val; 270 } 271 272 static void pegasos2_pci_config_write(Pegasos2MachineState *pm, int bus, 273 uint32_t addr, uint32_t len, uint32_t val) 274 { 275 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; 276 277 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); 278 pegasos2_mv_reg_write(pm, pcicfg + 4, len, val); 279 } 280 281 static void pegasos2_machine_reset(MachineState *machine, ShutdownCause reason) 282 { 283 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 284 void *fdt; 285 uint64_t d[2]; 286 int sz; 287 288 qemu_devices_reset(reason); 289 if (!pm->vof) { 290 return; /* Firmware should set up machine so nothing to do */ 291 } 292 293 /* Otherwise, set up devices that board firmware would normally do */ 294 pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff); 295 pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc); 296 pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400); 297 pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000); 298 pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000); 299 pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO | 300 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 301 pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO | 302 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 303 304 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 305 PCI_INTERRUPT_LINE, 2, 0x9); 306 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 307 0x50, 1, 0x2); 308 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 309 0x55, 1, 0x90); 310 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 311 0x56, 1, 0x99); 312 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 313 0x57, 1, 0x90); 314 315 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 316 PCI_INTERRUPT_LINE, 2, 0x109); 317 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 318 PCI_CLASS_PROG, 1, 0xf); 319 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 320 0x40, 1, 0xb); 321 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 322 0x50, 4, 0x17171717); 323 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 324 PCI_COMMAND, 2, 0x87); 325 326 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) | 327 PCI_INTERRUPT_LINE, 2, 0x409); 328 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) | 329 PCI_COMMAND, 2, 0x7); 330 331 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) | 332 PCI_INTERRUPT_LINE, 2, 0x409); 333 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) | 334 PCI_COMMAND, 2, 0x7); 335 336 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 337 PCI_INTERRUPT_LINE, 2, 0x9); 338 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 339 0x48, 4, 0xf00); 340 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 341 0x40, 4, 0x558020); 342 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 343 0x90, 4, 0xd00); 344 345 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) | 346 PCI_INTERRUPT_LINE, 2, 0x309); 347 348 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) | 349 PCI_INTERRUPT_LINE, 2, 0x309); 350 351 /* Device tree and VOF set up */ 352 vof_init(pm->vof, machine->ram_size, &error_fatal); 353 if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) { 354 error_report("Memory allocation for stack failed"); 355 exit(1); 356 } 357 if (pm->kernel_size && 358 vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) { 359 error_report("Memory for kernel is in use"); 360 exit(1); 361 } 362 if (pm->initrd_size && 363 vof_claim(pm->vof, pm->initrd_addr, pm->initrd_size, 0) == -1) { 364 error_report("Memory for initrd is in use"); 365 exit(1); 366 } 367 fdt = build_fdt(machine, &sz); 368 /* FIXME: VOF assumes entry is same as load address */ 369 d[0] = cpu_to_be64(pm->kernel_entry); 370 d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr)); 371 qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d)); 372 373 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 374 g_free(pm->fdt_blob); 375 pm->fdt_blob = fdt; 376 377 vof_build_dt(fdt, pm->vof); 378 vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe"); 379 380 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 381 machine->fdt = fdt; 382 383 pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine); 384 } 385 386 enum pegasos2_rtas_tokens { 387 RTAS_RESTART_RTAS = 0, 388 RTAS_NVRAM_FETCH = 1, 389 RTAS_NVRAM_STORE = 2, 390 RTAS_GET_TIME_OF_DAY = 3, 391 RTAS_SET_TIME_OF_DAY = 4, 392 RTAS_EVENT_SCAN = 6, 393 RTAS_CHECK_EXCEPTION = 7, 394 RTAS_READ_PCI_CONFIG = 8, 395 RTAS_WRITE_PCI_CONFIG = 9, 396 RTAS_DISPLAY_CHARACTER = 10, 397 RTAS_SET_INDICATOR = 11, 398 RTAS_POWER_OFF = 17, 399 RTAS_SUSPEND = 18, 400 RTAS_HIBERNATE = 19, 401 RTAS_SYSTEM_REBOOT = 20, 402 }; 403 404 static target_ulong pegasos2_rtas(PowerPCCPU *cpu, Pegasos2MachineState *pm, 405 target_ulong args_real) 406 { 407 AddressSpace *as = CPU(cpu)->as; 408 uint32_t token = ldl_be_phys(as, args_real); 409 uint32_t nargs = ldl_be_phys(as, args_real + 4); 410 uint32_t nrets = ldl_be_phys(as, args_real + 8); 411 uint32_t args = args_real + 12; 412 uint32_t rets = args_real + 12 + nargs * 4; 413 414 if (nrets < 1) { 415 qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n"); 416 return H_PARAMETER; 417 } 418 switch (token) { 419 case RTAS_GET_TIME_OF_DAY: 420 { 421 QObject *qo = object_property_get_qobject(qdev_get_machine(), 422 "rtc-time", &error_fatal); 423 QDict *qd = qobject_to(QDict, qo); 424 425 if (nargs != 0 || nrets != 8 || !qd) { 426 stl_be_phys(as, rets, -1); 427 qobject_unref(qo); 428 return H_PARAMETER; 429 } 430 431 stl_be_phys(as, rets, 0); 432 stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900); 433 stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1); 434 stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday")); 435 stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour")); 436 stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min")); 437 stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec")); 438 stl_be_phys(as, rets + 28, 0); 439 qobject_unref(qo); 440 return H_SUCCESS; 441 } 442 case RTAS_READ_PCI_CONFIG: 443 { 444 uint32_t addr, len, val; 445 446 if (nargs != 2 || nrets != 2) { 447 stl_be_phys(as, rets, -1); 448 return H_PARAMETER; 449 } 450 addr = ldl_be_phys(as, args); 451 len = ldl_be_phys(as, args + 4); 452 val = pegasos2_pci_config_read(pm, !(addr >> 24), 453 addr & 0x0fffffff, len); 454 stl_be_phys(as, rets, 0); 455 stl_be_phys(as, rets + 4, val); 456 return H_SUCCESS; 457 } 458 case RTAS_WRITE_PCI_CONFIG: 459 { 460 uint32_t addr, len, val; 461 462 if (nargs != 3 || nrets != 1) { 463 stl_be_phys(as, rets, -1); 464 return H_PARAMETER; 465 } 466 addr = ldl_be_phys(as, args); 467 len = ldl_be_phys(as, args + 4); 468 val = ldl_be_phys(as, args + 8); 469 pegasos2_pci_config_write(pm, !(addr >> 24), 470 addr & 0x0fffffff, len, val); 471 stl_be_phys(as, rets, 0); 472 return H_SUCCESS; 473 } 474 case RTAS_DISPLAY_CHARACTER: 475 if (nargs != 1 || nrets != 1) { 476 stl_be_phys(as, rets, -1); 477 return H_PARAMETER; 478 } 479 qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args)); 480 stl_be_phys(as, rets, 0); 481 return H_SUCCESS; 482 case RTAS_POWER_OFF: 483 { 484 if (nargs != 2 || nrets != 1) { 485 stl_be_phys(as, rets, -1); 486 return H_PARAMETER; 487 } 488 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 489 stl_be_phys(as, rets, 0); 490 return H_SUCCESS; 491 } 492 default: 493 qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n", 494 token, nargs, nrets); 495 stl_be_phys(as, rets, 0); 496 return H_SUCCESS; 497 } 498 } 499 500 static bool pegasos2_cpu_in_nested(PowerPCCPU *cpu) 501 { 502 return false; 503 } 504 505 static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 506 { 507 Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp); 508 CPUPPCState *env = &cpu->env; 509 510 /* The TCG path should also be holding the BQL at this point */ 511 g_assert(qemu_mutex_iothread_locked()); 512 513 if (FIELD_EX64(env->msr, MSR, PR)) { 514 qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n"); 515 env->gpr[3] = H_PRIVILEGE; 516 } else if (env->gpr[3] == KVMPPC_H_RTAS) { 517 env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]); 518 } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) { 519 int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob, 520 env->gpr[4]); 521 env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS); 522 } else { 523 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx 524 "\n", env->gpr[3]); 525 env->gpr[3] = -1; 526 } 527 } 528 529 static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 530 { 531 } 532 533 static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 534 { 535 return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1]; 536 } 537 538 static bool pegasos2_setprop(MachineState *ms, const char *path, 539 const char *propname, void *val, int vallen) 540 { 541 return true; 542 } 543 544 static void pegasos2_machine_class_init(ObjectClass *oc, void *data) 545 { 546 MachineClass *mc = MACHINE_CLASS(oc); 547 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 548 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 549 550 mc->desc = "Genesi/bPlan Pegasos II"; 551 mc->init = pegasos2_init; 552 mc->reset = pegasos2_machine_reset; 553 mc->block_default_type = IF_IDE; 554 mc->default_boot_order = "cd"; 555 mc->default_display = "std"; 556 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7457_v1.2"); 557 mc->default_ram_id = "pegasos2.ram"; 558 mc->default_ram_size = 512 * MiB; 559 560 vhc->cpu_in_nested = pegasos2_cpu_in_nested; 561 vhc->hypercall = pegasos2_hypercall; 562 vhc->cpu_exec_enter = vhyp_nop; 563 vhc->cpu_exec_exit = vhyp_nop; 564 vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr; 565 566 vmc->setprop = pegasos2_setprop; 567 } 568 569 static const TypeInfo pegasos2_machine_info = { 570 .name = TYPE_PEGASOS2_MACHINE, 571 .parent = TYPE_MACHINE, 572 .class_init = pegasos2_machine_class_init, 573 .instance_size = sizeof(Pegasos2MachineState), 574 .interfaces = (InterfaceInfo[]) { 575 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 576 { TYPE_VOF_MACHINE_IF }, 577 { } 578 }, 579 }; 580 581 static void pegasos2_machine_register_types(void) 582 { 583 type_register_static(&pegasos2_machine_info); 584 } 585 586 type_init(pegasos2_machine_register_types) 587 588 /* FDT creation for passing to firmware */ 589 590 typedef struct { 591 void *fdt; 592 const char *path; 593 } FDTInfo; 594 595 /* We do everything in reverse order so it comes out right in the tree */ 596 597 static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 598 { 599 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi"); 600 } 601 602 static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 603 { 604 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0); 605 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1); 606 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb"); 607 } 608 609 static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 610 { 611 GString *name = g_string_sized_new(64); 612 uint32_t cells[3]; 613 614 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1); 615 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2); 616 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa"); 617 qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa"); 618 619 /* additional devices */ 620 g_string_printf(name, "%s/lpt@i3bc", fi->path); 621 qemu_fdt_add_subnode(fi->fdt, name->str); 622 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 623 cells[0] = cpu_to_be32(7); 624 cells[1] = 0; 625 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 626 cells, 2 * sizeof(cells[0])); 627 cells[0] = cpu_to_be32(1); 628 cells[1] = cpu_to_be32(0x3bc); 629 cells[2] = cpu_to_be32(8); 630 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 631 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt"); 632 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt"); 633 634 g_string_printf(name, "%s/fdc@i3f0", fi->path); 635 qemu_fdt_add_subnode(fi->fdt, name->str); 636 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 637 cells[0] = cpu_to_be32(6); 638 cells[1] = 0; 639 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 640 cells, 2 * sizeof(cells[0])); 641 cells[0] = cpu_to_be32(1); 642 cells[1] = cpu_to_be32(0x3f0); 643 cells[2] = cpu_to_be32(8); 644 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 645 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc"); 646 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc"); 647 648 g_string_printf(name, "%s/timer@i40", fi->path); 649 qemu_fdt_add_subnode(fi->fdt, name->str); 650 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 651 cells[0] = cpu_to_be32(1); 652 cells[1] = cpu_to_be32(0x40); 653 cells[2] = cpu_to_be32(8); 654 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 655 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer"); 656 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer"); 657 658 g_string_printf(name, "%s/rtc@i70", fi->path); 659 qemu_fdt_add_subnode(fi->fdt, name->str); 660 qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc"); 661 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 662 cells[0] = cpu_to_be32(8); 663 cells[1] = 0; 664 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 665 cells, 2 * sizeof(cells[0])); 666 cells[0] = cpu_to_be32(1); 667 cells[1] = cpu_to_be32(0x70); 668 cells[2] = cpu_to_be32(2); 669 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 670 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc"); 671 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc"); 672 673 g_string_printf(name, "%s/keyboard@i60", fi->path); 674 qemu_fdt_add_subnode(fi->fdt, name->str); 675 cells[0] = cpu_to_be32(1); 676 cells[1] = 0; 677 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 678 cells, 2 * sizeof(cells[0])); 679 cells[0] = cpu_to_be32(1); 680 cells[1] = cpu_to_be32(0x60); 681 cells[2] = cpu_to_be32(5); 682 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 683 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard"); 684 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard"); 685 686 g_string_printf(name, "%s/8042@i60", fi->path); 687 qemu_fdt_add_subnode(fi->fdt, name->str); 688 qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2); 689 qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0); 690 qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1); 691 qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", ""); 692 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 693 cells[0] = cpu_to_be32(1); 694 cells[1] = cpu_to_be32(0x60); 695 cells[2] = cpu_to_be32(5); 696 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 697 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", ""); 698 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042"); 699 700 g_string_printf(name, "%s/serial@i2f8", fi->path); 701 qemu_fdt_add_subnode(fi->fdt, name->str); 702 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 703 cells[0] = cpu_to_be32(3); 704 cells[1] = 0; 705 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 706 cells, 2 * sizeof(cells[0])); 707 cells[0] = cpu_to_be32(1); 708 cells[1] = cpu_to_be32(0x2f8); 709 cells[2] = cpu_to_be32(8); 710 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 711 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial"); 712 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial"); 713 714 g_string_free(name, TRUE); 715 } 716 717 static struct { 718 const char *id; 719 const char *name; 720 void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi); 721 } device_map[] = { 722 { "pci11ab,6460", "host", NULL }, 723 { "pci1106,8231", "isa", dt_isa }, 724 { "pci1106,571", "ide", dt_ide }, 725 { "pci1106,3044", "firewire", NULL }, 726 { "pci1106,3038", "usb", dt_usb }, 727 { "pci1106,8235", "other", NULL }, 728 { "pci1106,3058", "sound", NULL }, 729 { NULL, NULL } 730 }; 731 732 static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque) 733 { 734 FDTInfo *fi = opaque; 735 GString *node = g_string_new(NULL); 736 uint32_t cells[(PCI_NUM_REGIONS + 1) * 5]; 737 int i, j; 738 const char *name = NULL; 739 g_autofree const gchar *pn = g_strdup_printf("pci%x,%x", 740 pci_get_word(&d->config[PCI_VENDOR_ID]), 741 pci_get_word(&d->config[PCI_DEVICE_ID])); 742 743 if (pci_get_word(&d->config[PCI_CLASS_DEVICE]) == 744 PCI_CLASS_NETWORK_ETHERNET) { 745 name = "ethernet"; 746 } else if (pci_get_word(&d->config[PCI_CLASS_DEVICE]) >> 8 == 747 PCI_BASE_CLASS_DISPLAY) { 748 name = "display"; 749 } 750 for (i = 0; device_map[i].id; i++) { 751 if (!strcmp(pn, device_map[i].id)) { 752 name = device_map[i].name; 753 break; 754 } 755 } 756 g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn), 757 PCI_SLOT(d->devfn)); 758 if (PCI_FUNC(d->devfn)) { 759 g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn)); 760 } 761 762 qemu_fdt_add_subnode(fi->fdt, node->str); 763 if (device_map[i].dtf) { 764 FDTInfo cfi = { fi->fdt, node->str }; 765 device_map[i].dtf(bus, d, &cfi); 766 } 767 cells[0] = cpu_to_be32(d->devfn << 8); 768 cells[1] = 0; 769 cells[2] = 0; 770 cells[3] = 0; 771 cells[4] = 0; 772 j = 5; 773 for (i = 0; i < PCI_NUM_REGIONS; i++) { 774 if (!d->io_regions[i].size) { 775 continue; 776 } 777 cells[j] = PCI_BASE_ADDRESS_0 + i * 4; 778 if (cells[j] == 0x28) { 779 cells[j] = 0x30; 780 } 781 cells[j] = cpu_to_be32(d->devfn << 8 | cells[j]); 782 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 783 cells[j] |= cpu_to_be32(1 << 24); 784 } else { 785 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 786 cells[j] |= cpu_to_be32(3 << 24); 787 } else { 788 cells[j] |= cpu_to_be32(2 << 24); 789 } 790 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 791 cells[j] |= cpu_to_be32(4 << 28); 792 } 793 } 794 cells[j + 1] = 0; 795 cells[j + 2] = 0; 796 cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32); 797 cells[j + 4] = cpu_to_be32(d->io_regions[i].size); 798 j += 5; 799 } 800 qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0])); 801 qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn); 802 if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) { 803 qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts", 804 pci_get_byte(&d->config[PCI_INTERRUPT_PIN])); 805 } 806 /* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */ 807 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id", 808 pci_get_word(&d->config[PCI_SUBSYSTEM_ID])); 809 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id", 810 pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID])); 811 cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]); 812 qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8); 813 qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff); 814 qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id", 815 pci_get_word(&d->config[PCI_DEVICE_ID])); 816 qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id", 817 pci_get_word(&d->config[PCI_VENDOR_ID])); 818 819 g_string_free(node, TRUE); 820 } 821 822 static void *build_fdt(MachineState *machine, int *fdt_size) 823 { 824 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 825 PowerPCCPU *cpu = pm->cpu; 826 PCIBus *pci_bus; 827 FDTInfo fi; 828 uint32_t cells[16]; 829 void *fdt = create_device_tree(fdt_size); 830 831 fi.fdt = fdt; 832 833 /* root node */ 834 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description", 835 "Pegasos CHRP PowerPC System"); 836 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2"); 837 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH"); 838 qemu_fdt_setprop_string(fdt, "/", "revision", "2B"); 839 qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2"); 840 qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp"); 841 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1); 842 qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2"); 843 844 /* pci@c0000000 */ 845 qemu_fdt_add_subnode(fdt, "/pci@c0000000"); 846 cells[0] = 0; 847 cells[1] = 0; 848 qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range", 849 cells, 2 * sizeof(cells[0])); 850 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1); 851 cells[0] = cpu_to_be32(PCI0_MEM_BASE); 852 cells[1] = cpu_to_be32(PCI0_MEM_SIZE); 853 qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0])); 854 cells[0] = cpu_to_be32(0x01000000); 855 cells[1] = 0; 856 cells[2] = 0; 857 cells[3] = cpu_to_be32(PCI0_IO_BASE); 858 cells[4] = 0; 859 cells[5] = cpu_to_be32(PCI0_IO_SIZE); 860 cells[6] = cpu_to_be32(0x02000000); 861 cells[7] = 0; 862 cells[8] = cpu_to_be32(PCI0_MEM_BASE); 863 cells[9] = cpu_to_be32(PCI0_MEM_BASE); 864 cells[10] = 0; 865 cells[11] = cpu_to_be32(PCI0_MEM_SIZE); 866 qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges", 867 cells, 12 * sizeof(cells[0])); 868 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2); 869 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3); 870 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci"); 871 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci"); 872 873 fi.path = "/pci@c0000000"; 874 pci_bus = mv64361_get_pci_bus(pm->mv, 0); 875 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); 876 877 /* pci@80000000 */ 878 qemu_fdt_add_subnode(fdt, "/pci@80000000"); 879 cells[0] = 0; 880 cells[1] = 0; 881 qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range", 882 cells, 2 * sizeof(cells[0])); 883 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0); 884 cells[0] = cpu_to_be32(PCI1_MEM_BASE); 885 cells[1] = cpu_to_be32(PCI1_MEM_SIZE); 886 qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0])); 887 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge", 888 0xf1000cb4); 889 cells[0] = cpu_to_be32(0x01000000); 890 cells[1] = 0; 891 cells[2] = 0; 892 cells[3] = cpu_to_be32(PCI1_IO_BASE); 893 cells[4] = 0; 894 cells[5] = cpu_to_be32(PCI1_IO_SIZE); 895 cells[6] = cpu_to_be32(0x02000000); 896 cells[7] = 0; 897 cells[8] = cpu_to_be32(PCI1_MEM_BASE); 898 cells[9] = cpu_to_be32(PCI1_MEM_BASE); 899 cells[10] = 0; 900 cells[11] = cpu_to_be32(PCI1_MEM_SIZE); 901 qemu_fdt_setprop(fdt, "/pci@80000000", "ranges", 902 cells, 12 * sizeof(cells[0])); 903 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2); 904 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3); 905 qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci"); 906 qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci"); 907 908 fi.path = "/pci@80000000"; 909 pci_bus = mv64361_get_pci_bus(pm->mv, 1); 910 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); 911 912 qemu_fdt_add_subnode(fdt, "/failsafe"); 913 qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial"); 914 qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe"); 915 916 qemu_fdt_add_subnode(fdt, "/rtas"); 917 qemu_fdt_setprop_cell(fdt, "/rtas", "system-reboot", RTAS_SYSTEM_REBOOT); 918 qemu_fdt_setprop_cell(fdt, "/rtas", "hibernate", RTAS_HIBERNATE); 919 qemu_fdt_setprop_cell(fdt, "/rtas", "suspend", RTAS_SUSPEND); 920 qemu_fdt_setprop_cell(fdt, "/rtas", "power-off", RTAS_POWER_OFF); 921 qemu_fdt_setprop_cell(fdt, "/rtas", "set-indicator", RTAS_SET_INDICATOR); 922 qemu_fdt_setprop_cell(fdt, "/rtas", "display-character", 923 RTAS_DISPLAY_CHARACTER); 924 qemu_fdt_setprop_cell(fdt, "/rtas", "write-pci-config", 925 RTAS_WRITE_PCI_CONFIG); 926 qemu_fdt_setprop_cell(fdt, "/rtas", "read-pci-config", 927 RTAS_READ_PCI_CONFIG); 928 /* Pegasos2 firmware misspells check-exception and guests use that */ 929 qemu_fdt_setprop_cell(fdt, "/rtas", "check-execption", 930 RTAS_CHECK_EXCEPTION); 931 qemu_fdt_setprop_cell(fdt, "/rtas", "event-scan", RTAS_EVENT_SCAN); 932 qemu_fdt_setprop_cell(fdt, "/rtas", "set-time-of-day", 933 RTAS_SET_TIME_OF_DAY); 934 qemu_fdt_setprop_cell(fdt, "/rtas", "get-time-of-day", 935 RTAS_GET_TIME_OF_DAY); 936 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-store", RTAS_NVRAM_STORE); 937 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-fetch", RTAS_NVRAM_FETCH); 938 qemu_fdt_setprop_cell(fdt, "/rtas", "restart-rtas", RTAS_RESTART_RTAS); 939 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-error-log-max", 0); 940 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-event-scan-rate", 0); 941 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0); 942 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20); 943 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1); 944 qemu_fdt_setprop_string(fdt, "/rtas", "name", "rtas"); 945 946 /* cpus */ 947 qemu_fdt_add_subnode(fdt, "/cpus"); 948 qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1); 949 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 950 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 951 qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus"); 952 953 /* FIXME Get CPU name from CPU object */ 954 const char *cp = "/cpus/PowerPC,G4"; 955 qemu_fdt_add_subnode(fdt, cp); 956 qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0); 957 qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000); 958 qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size", 959 cpu->env.dcache_line_size); 960 qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size", 961 cpu->env.dcache_line_size); 962 qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000); 963 qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size", 964 cpu->env.icache_line_size); 965 qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size", 966 cpu->env.icache_line_size); 967 if (cpu->env.id_tlbs) { 968 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways); 969 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way); 970 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways); 971 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way); 972 qemu_fdt_setprop_string(fdt, cp, "tlb-split", ""); 973 } 974 qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways); 975 qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb); 976 qemu_fdt_setprop_string(fdt, cp, "state", "running"); 977 if (cpu->env.insns_flags & PPC_ALTIVEC) { 978 qemu_fdt_setprop_string(fdt, cp, "altivec", ""); 979 qemu_fdt_setprop_string(fdt, cp, "data-streams", ""); 980 } 981 /* 982 * FIXME What flags do data-streams, external-control and 983 * performance-monitor depend on? 984 */ 985 qemu_fdt_setprop_string(fdt, cp, "external-control", ""); 986 if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) { 987 qemu_fdt_setprop_string(fdt, cp, "general-purpose", ""); 988 } 989 qemu_fdt_setprop_string(fdt, cp, "performance-monitor", ""); 990 if (cpu->env.insns_flags & PPC_FLOAT_FRES) { 991 qemu_fdt_setprop_string(fdt, cp, "graphics", ""); 992 } 993 qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4); 994 qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency", 995 cpu->env.tb_env->tb_freq); 996 qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ); 997 qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5); 998 qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]); 999 cells[0] = 0; 1000 cells[1] = 0; 1001 qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0])); 1002 qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu"); 1003 qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1); 1004 1005 /* memory */ 1006 qemu_fdt_add_subnode(fdt, "/memory@0"); 1007 cells[0] = 0; 1008 cells[1] = cpu_to_be32(machine->ram_size); 1009 qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0])); 1010 qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory"); 1011 qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory"); 1012 1013 qemu_fdt_add_subnode(fdt, "/chosen"); 1014 if (pm->initrd_addr && pm->initrd_size) { 1015 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 1016 pm->initrd_addr + pm->initrd_size); 1017 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 1018 pm->initrd_addr); 1019 } 1020 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 1021 machine->kernel_cmdline ?: ""); 1022 qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen"); 1023 1024 qemu_fdt_add_subnode(fdt, "/openprom"); 1025 qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1"); 1026 1027 return fdt; 1028 } 1029