1 /* 2 * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator 3 * 4 * Copyright (c) 2018-2021 BALATON Zoltan 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 * 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu-common.h" 12 #include "qemu/units.h" 13 #include "qapi/error.h" 14 #include "hw/hw.h" 15 #include "hw/ppc/ppc.h" 16 #include "hw/sysbus.h" 17 #include "hw/pci/pci_host.h" 18 #include "hw/irq.h" 19 #include "hw/pci-host/mv64361.h" 20 #include "hw/isa/vt82c686.h" 21 #include "hw/ide/pci.h" 22 #include "hw/i2c/smbus_eeprom.h" 23 #include "hw/qdev-properties.h" 24 #include "sysemu/reset.h" 25 #include "sysemu/runstate.h" 26 #include "sysemu/qtest.h" 27 #include "hw/boards.h" 28 #include "hw/loader.h" 29 #include "hw/fw-path-provider.h" 30 #include "elf.h" 31 #include "qemu/log.h" 32 #include "qemu/error-report.h" 33 #include "sysemu/kvm.h" 34 #include "kvm_ppc.h" 35 #include "exec/address-spaces.h" 36 #include "qom/qom-qobject.h" 37 #include "qapi/qmp/qdict.h" 38 #include "trace.h" 39 #include "qemu/datadir.h" 40 #include "sysemu/device_tree.h" 41 #include "hw/ppc/vof.h" 42 43 #include <libfdt.h> 44 45 #define PROM_FILENAME "vof.bin" 46 #define PROM_ADDR 0xfff00000 47 #define PROM_SIZE 0x80000 48 49 #define KVMPPC_HCALL_BASE 0xf000 50 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 51 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 52 53 #define H_SUCCESS 0 54 #define H_PRIVILEGE -3 /* Caller not privileged */ 55 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 56 57 #define BUS_FREQ_HZ 133333333 58 59 #define PCI0_CFG_ADDR 0xcf8 60 #define PCI0_MEM_BASE 0xc0000000 61 #define PCI0_MEM_SIZE 0x20000000 62 #define PCI0_IO_BASE 0xf8000000 63 #define PCI0_IO_SIZE 0x10000 64 65 #define PCI1_CFG_ADDR 0xc78 66 #define PCI1_MEM_BASE 0x80000000 67 #define PCI1_MEM_SIZE 0x40000000 68 #define PCI1_IO_BASE 0xfe000000 69 #define PCI1_IO_SIZE 0x10000 70 71 #define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2") 72 OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE) 73 74 struct Pegasos2MachineState { 75 MachineState parent_obj; 76 PowerPCCPU *cpu; 77 DeviceState *mv; 78 Vof *vof; 79 void *fdt_blob; 80 uint64_t kernel_addr; 81 uint64_t kernel_entry; 82 uint64_t kernel_size; 83 }; 84 85 static void *build_fdt(MachineState *machine, int *fdt_size); 86 87 static void pegasos2_cpu_reset(void *opaque) 88 { 89 PowerPCCPU *cpu = opaque; 90 Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine); 91 92 cpu_reset(CPU(cpu)); 93 cpu->env.spr[SPR_HID1] = 7ULL << 28; 94 if (pm->vof) { 95 cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20; 96 cpu->env.nip = 0x100; 97 } 98 } 99 100 static void pegasos2_init(MachineState *machine) 101 { 102 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 103 CPUPPCState *env; 104 MemoryRegion *rom = g_new(MemoryRegion, 1); 105 PCIBus *pci_bus; 106 PCIDevice *dev; 107 I2CBus *i2c_bus; 108 const char *fwname = machine->firmware ?: PROM_FILENAME; 109 char *filename; 110 int sz; 111 uint8_t *spd_data; 112 113 /* init CPU */ 114 pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 115 env = &pm->cpu->env; 116 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 117 error_report("Incompatible CPU, only 6xx bus supported"); 118 exit(1); 119 } 120 121 /* Set time-base frequency */ 122 cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4); 123 qemu_register_reset(pegasos2_cpu_reset, pm->cpu); 124 125 /* RAM */ 126 if (machine->ram_size > 2 * GiB) { 127 error_report("RAM size more than 2 GiB is not supported"); 128 exit(1); 129 } 130 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 131 132 /* allocate and load firmware */ 133 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname); 134 if (!filename) { 135 error_report("Could not find firmware '%s'", fwname); 136 exit(1); 137 } 138 if (!machine->firmware && !pm->vof) { 139 pm->vof = g_malloc0(sizeof(*pm->vof)); 140 } 141 memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal); 142 memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom); 143 sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1, 144 PPC_ELF_MACHINE, 0, 0); 145 if (sz <= 0) { 146 sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE); 147 } 148 if (sz <= 0 || sz > PROM_SIZE) { 149 error_report("Could not load firmware '%s'", filename); 150 exit(1); 151 } 152 g_free(filename); 153 if (pm->vof) { 154 pm->vof->fw_size = sz; 155 } 156 157 /* Marvell Discovery II system controller */ 158 pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1, 159 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT])); 160 pci_bus = mv64361_get_pci_bus(pm->mv, 1); 161 162 /* VIA VT8231 South Bridge (multifunction PCI device) */ 163 /* VT8231 function 0: PCI-to-ISA Bridge */ 164 dev = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), true, 165 TYPE_VT8231_ISA); 166 qdev_connect_gpio_out(DEVICE(dev), 0, 167 qdev_get_gpio_in_named(pm->mv, "gpp", 31)); 168 169 /* VT8231 function 1: IDE Controller */ 170 dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 1), "via-ide"); 171 pci_ide_create_devs(dev); 172 173 /* VT8231 function 2-3: USB Ports */ 174 pci_create_simple(pci_bus, PCI_DEVFN(12, 2), "vt82c686b-usb-uhci"); 175 pci_create_simple(pci_bus, PCI_DEVFN(12, 3), "vt82c686b-usb-uhci"); 176 177 /* VT8231 function 4: Power Management Controller */ 178 dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 4), TYPE_VT8231_PM); 179 i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c")); 180 spd_data = spd_data_generate(DDR, machine->ram_size); 181 smbus_eeprom_init_one(i2c_bus, 0x57, spd_data); 182 183 /* VT8231 function 5-6: AC97 Audio & Modem */ 184 pci_create_simple(pci_bus, PCI_DEVFN(12, 5), TYPE_VIA_AC97); 185 pci_create_simple(pci_bus, PCI_DEVFN(12, 6), TYPE_VIA_MC97); 186 187 /* other PC hardware */ 188 pci_vga_init(pci_bus); 189 190 if (machine->kernel_filename) { 191 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL, 192 &pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1, 193 PPC_ELF_MACHINE, 0, 0); 194 if (sz <= 0) { 195 error_report("Could not load kernel '%s'", 196 machine->kernel_filename); 197 exit(1); 198 } 199 pm->kernel_size = sz; 200 if (!pm->vof) { 201 warn_report("Option -kernel may be ineffective with -bios."); 202 } 203 } else if (pm->vof && !qtest_enabled()) { 204 warn_report("Using Virtual OpenFirmware but no -kernel option."); 205 } 206 207 if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) { 208 warn_report("Option -append may be ineffective with -bios."); 209 } 210 } 211 212 static uint32_t pegasos2_mv_reg_read(Pegasos2MachineState *pm, 213 uint32_t addr, uint32_t len) 214 { 215 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); 216 uint64_t val = 0xffffffffULL; 217 memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE, 218 MEMTXATTRS_UNSPECIFIED); 219 return val; 220 } 221 222 static void pegasos2_mv_reg_write(Pegasos2MachineState *pm, uint32_t addr, 223 uint32_t len, uint32_t val) 224 { 225 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); 226 memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE, 227 MEMTXATTRS_UNSPECIFIED); 228 } 229 230 static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus, 231 uint32_t addr, uint32_t len) 232 { 233 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; 234 uint64_t val = 0xffffffffULL; 235 236 if (len <= 4) { 237 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); 238 val = pegasos2_mv_reg_read(pm, pcicfg + 4, len); 239 } 240 return val; 241 } 242 243 static void pegasos2_pci_config_write(Pegasos2MachineState *pm, int bus, 244 uint32_t addr, uint32_t len, uint32_t val) 245 { 246 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; 247 248 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); 249 pegasos2_mv_reg_write(pm, pcicfg + 4, len, val); 250 } 251 252 static void pegasos2_machine_reset(MachineState *machine) 253 { 254 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 255 void *fdt; 256 uint64_t d[2]; 257 int sz; 258 259 qemu_devices_reset(); 260 if (!pm->vof) { 261 return; /* Firmware should set up machine so nothing to do */ 262 } 263 264 /* Otherwise, set up devices that board firmware would normally do */ 265 pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff); 266 pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc); 267 pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400); 268 pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000); 269 pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000); 270 pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO | 271 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 272 pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO | 273 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 274 275 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 276 PCI_INTERRUPT_LINE, 2, 0x9); 277 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 278 0x50, 1, 0x2); 279 280 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 281 PCI_INTERRUPT_LINE, 2, 0x109); 282 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 283 PCI_CLASS_PROG, 1, 0xf); 284 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 285 0x40, 1, 0xb); 286 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 287 0x50, 4, 0x17171717); 288 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 289 PCI_COMMAND, 2, 0x87); 290 291 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) | 292 PCI_INTERRUPT_LINE, 2, 0x409); 293 294 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) | 295 PCI_INTERRUPT_LINE, 2, 0x409); 296 297 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 298 PCI_INTERRUPT_LINE, 2, 0x9); 299 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 300 0x48, 4, 0xf00); 301 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 302 0x40, 4, 0x558020); 303 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 304 0x90, 4, 0xd00); 305 306 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) | 307 PCI_INTERRUPT_LINE, 2, 0x309); 308 309 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) | 310 PCI_INTERRUPT_LINE, 2, 0x309); 311 312 /* Device tree and VOF set up */ 313 vof_init(pm->vof, machine->ram_size, &error_fatal); 314 if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) { 315 error_report("Memory allocation for stack failed"); 316 exit(1); 317 } 318 if (pm->kernel_size && 319 vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) { 320 error_report("Memory for kernel is in use"); 321 exit(1); 322 } 323 fdt = build_fdt(machine, &sz); 324 /* FIXME: VOF assumes entry is same as load address */ 325 d[0] = cpu_to_be64(pm->kernel_entry); 326 d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr)); 327 qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d)); 328 329 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 330 g_free(pm->fdt_blob); 331 pm->fdt_blob = fdt; 332 333 vof_build_dt(fdt, pm->vof); 334 vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe"); 335 pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine); 336 } 337 338 enum pegasos2_rtas_tokens { 339 RTAS_RESTART_RTAS = 0, 340 RTAS_NVRAM_FETCH = 1, 341 RTAS_NVRAM_STORE = 2, 342 RTAS_GET_TIME_OF_DAY = 3, 343 RTAS_SET_TIME_OF_DAY = 4, 344 RTAS_EVENT_SCAN = 6, 345 RTAS_CHECK_EXCEPTION = 7, 346 RTAS_READ_PCI_CONFIG = 8, 347 RTAS_WRITE_PCI_CONFIG = 9, 348 RTAS_DISPLAY_CHARACTER = 10, 349 RTAS_SET_INDICATOR = 11, 350 RTAS_POWER_OFF = 17, 351 RTAS_SUSPEND = 18, 352 RTAS_HIBERNATE = 19, 353 RTAS_SYSTEM_REBOOT = 20, 354 }; 355 356 static target_ulong pegasos2_rtas(PowerPCCPU *cpu, Pegasos2MachineState *pm, 357 target_ulong args_real) 358 { 359 AddressSpace *as = CPU(cpu)->as; 360 uint32_t token = ldl_be_phys(as, args_real); 361 uint32_t nargs = ldl_be_phys(as, args_real + 4); 362 uint32_t nrets = ldl_be_phys(as, args_real + 8); 363 uint32_t args = args_real + 12; 364 uint32_t rets = args_real + 12 + nargs * 4; 365 366 if (nrets < 1) { 367 qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n"); 368 return H_PARAMETER; 369 } 370 switch (token) { 371 case RTAS_GET_TIME_OF_DAY: 372 { 373 QObject *qo = object_property_get_qobject(qdev_get_machine(), 374 "rtc-time", &error_fatal); 375 QDict *qd = qobject_to(QDict, qo); 376 377 if (nargs != 0 || nrets != 8 || !qd) { 378 stl_be_phys(as, rets, -1); 379 qobject_unref(qo); 380 return H_PARAMETER; 381 } 382 383 stl_be_phys(as, rets, 0); 384 stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900); 385 stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1); 386 stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday")); 387 stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour")); 388 stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min")); 389 stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec")); 390 stl_be_phys(as, rets + 28, 0); 391 qobject_unref(qo); 392 return H_SUCCESS; 393 } 394 case RTAS_READ_PCI_CONFIG: 395 { 396 uint32_t addr, len, val; 397 398 if (nargs != 2 || nrets != 2) { 399 stl_be_phys(as, rets, -1); 400 return H_PARAMETER; 401 } 402 addr = ldl_be_phys(as, args); 403 len = ldl_be_phys(as, args + 4); 404 val = pegasos2_pci_config_read(pm, !(addr >> 24), 405 addr & 0x0fffffff, len); 406 stl_be_phys(as, rets, 0); 407 stl_be_phys(as, rets + 4, val); 408 return H_SUCCESS; 409 } 410 case RTAS_WRITE_PCI_CONFIG: 411 { 412 uint32_t addr, len, val; 413 414 if (nargs != 3 || nrets != 1) { 415 stl_be_phys(as, rets, -1); 416 return H_PARAMETER; 417 } 418 addr = ldl_be_phys(as, args); 419 len = ldl_be_phys(as, args + 4); 420 val = ldl_be_phys(as, args + 8); 421 pegasos2_pci_config_write(pm, !(addr >> 24), 422 addr & 0x0fffffff, len, val); 423 stl_be_phys(as, rets, 0); 424 return H_SUCCESS; 425 } 426 case RTAS_DISPLAY_CHARACTER: 427 if (nargs != 1 || nrets != 1) { 428 stl_be_phys(as, rets, -1); 429 return H_PARAMETER; 430 } 431 qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args)); 432 stl_be_phys(as, rets, 0); 433 return H_SUCCESS; 434 case RTAS_POWER_OFF: 435 { 436 if (nargs != 2 || nrets != 1) { 437 stl_be_phys(as, rets, -1); 438 return H_PARAMETER; 439 } 440 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 441 stl_be_phys(as, rets, 0); 442 return H_SUCCESS; 443 } 444 default: 445 qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n", 446 token, nargs, nrets); 447 stl_be_phys(as, rets, 0); 448 return H_SUCCESS; 449 } 450 } 451 452 static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 453 { 454 Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp); 455 CPUPPCState *env = &cpu->env; 456 457 /* The TCG path should also be holding the BQL at this point */ 458 g_assert(qemu_mutex_iothread_locked()); 459 460 if (msr_pr) { 461 qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n"); 462 env->gpr[3] = H_PRIVILEGE; 463 } else if (env->gpr[3] == KVMPPC_H_RTAS) { 464 env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]); 465 } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) { 466 int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob, 467 env->gpr[4]); 468 env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS); 469 } else { 470 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx 471 "\n", env->gpr[3]); 472 env->gpr[3] = -1; 473 } 474 } 475 476 static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 477 { 478 } 479 480 static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 481 { 482 return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1]; 483 } 484 485 static bool pegasos2_setprop(MachineState *ms, const char *path, 486 const char *propname, void *val, int vallen) 487 { 488 return true; 489 } 490 491 static void pegasos2_machine_class_init(ObjectClass *oc, void *data) 492 { 493 MachineClass *mc = MACHINE_CLASS(oc); 494 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 495 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 496 497 mc->desc = "Genesi/bPlan Pegasos II"; 498 mc->init = pegasos2_init; 499 mc->reset = pegasos2_machine_reset; 500 mc->block_default_type = IF_IDE; 501 mc->default_boot_order = "cd"; 502 mc->default_display = "std"; 503 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); 504 mc->default_ram_id = "pegasos2.ram"; 505 mc->default_ram_size = 512 * MiB; 506 507 vhc->hypercall = pegasos2_hypercall; 508 vhc->cpu_exec_enter = vhyp_nop; 509 vhc->cpu_exec_exit = vhyp_nop; 510 vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr; 511 512 vmc->setprop = pegasos2_setprop; 513 } 514 515 static const TypeInfo pegasos2_machine_info = { 516 .name = TYPE_PEGASOS2_MACHINE, 517 .parent = TYPE_MACHINE, 518 .class_init = pegasos2_machine_class_init, 519 .instance_size = sizeof(Pegasos2MachineState), 520 .interfaces = (InterfaceInfo[]) { 521 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 522 { TYPE_VOF_MACHINE_IF }, 523 { } 524 }, 525 }; 526 527 static void pegasos2_machine_register_types(void) 528 { 529 type_register_static(&pegasos2_machine_info); 530 } 531 532 type_init(pegasos2_machine_register_types) 533 534 /* FDT creation for passing to firmware */ 535 536 typedef struct { 537 void *fdt; 538 const char *path; 539 } FDTInfo; 540 541 /* We do everything in reverse order so it comes out right in the tree */ 542 543 static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 544 { 545 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi"); 546 } 547 548 static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 549 { 550 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0); 551 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1); 552 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb"); 553 } 554 555 static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 556 { 557 GString *name = g_string_sized_new(64); 558 uint32_t cells[3]; 559 560 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1); 561 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2); 562 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa"); 563 qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa"); 564 565 /* addional devices */ 566 g_string_printf(name, "%s/lpt@i3bc", fi->path); 567 qemu_fdt_add_subnode(fi->fdt, name->str); 568 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 569 cells[0] = cpu_to_be32(7); 570 cells[1] = 0; 571 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 572 cells, 2 * sizeof(cells[0])); 573 cells[0] = cpu_to_be32(1); 574 cells[1] = cpu_to_be32(0x3bc); 575 cells[2] = cpu_to_be32(8); 576 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 577 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt"); 578 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt"); 579 580 g_string_printf(name, "%s/fdc@i3f0", fi->path); 581 qemu_fdt_add_subnode(fi->fdt, name->str); 582 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 583 cells[0] = cpu_to_be32(6); 584 cells[1] = 0; 585 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 586 cells, 2 * sizeof(cells[0])); 587 cells[0] = cpu_to_be32(1); 588 cells[1] = cpu_to_be32(0x3f0); 589 cells[2] = cpu_to_be32(8); 590 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 591 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc"); 592 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc"); 593 594 g_string_printf(name, "%s/timer@i40", fi->path); 595 qemu_fdt_add_subnode(fi->fdt, name->str); 596 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 597 cells[0] = cpu_to_be32(1); 598 cells[1] = cpu_to_be32(0x40); 599 cells[2] = cpu_to_be32(8); 600 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 601 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer"); 602 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer"); 603 604 g_string_printf(name, "%s/rtc@i70", fi->path); 605 qemu_fdt_add_subnode(fi->fdt, name->str); 606 qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc"); 607 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 608 cells[0] = cpu_to_be32(8); 609 cells[1] = 0; 610 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 611 cells, 2 * sizeof(cells[0])); 612 cells[0] = cpu_to_be32(1); 613 cells[1] = cpu_to_be32(0x70); 614 cells[2] = cpu_to_be32(2); 615 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 616 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc"); 617 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc"); 618 619 g_string_printf(name, "%s/keyboard@i60", fi->path); 620 qemu_fdt_add_subnode(fi->fdt, name->str); 621 cells[0] = cpu_to_be32(1); 622 cells[1] = 0; 623 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 624 cells, 2 * sizeof(cells[0])); 625 cells[0] = cpu_to_be32(1); 626 cells[1] = cpu_to_be32(0x60); 627 cells[2] = cpu_to_be32(5); 628 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 629 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard"); 630 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard"); 631 632 g_string_printf(name, "%s/8042@i60", fi->path); 633 qemu_fdt_add_subnode(fi->fdt, name->str); 634 qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2); 635 qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0); 636 qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1); 637 qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", ""); 638 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 639 cells[0] = cpu_to_be32(1); 640 cells[1] = cpu_to_be32(0x60); 641 cells[2] = cpu_to_be32(5); 642 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 643 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", ""); 644 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042"); 645 646 g_string_printf(name, "%s/serial@i2f8", fi->path); 647 qemu_fdt_add_subnode(fi->fdt, name->str); 648 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 649 cells[0] = cpu_to_be32(3); 650 cells[1] = 0; 651 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 652 cells, 2 * sizeof(cells[0])); 653 cells[0] = cpu_to_be32(1); 654 cells[1] = cpu_to_be32(0x2f8); 655 cells[2] = cpu_to_be32(8); 656 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 657 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial"); 658 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial"); 659 660 g_string_free(name, TRUE); 661 } 662 663 static struct { 664 const char *id; 665 const char *name; 666 void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi); 667 } device_map[] = { 668 { "pci11ab,6460", "host", NULL }, 669 { "pci1106,8231", "isa", dt_isa }, 670 { "pci1106,571", "ide", dt_ide }, 671 { "pci1106,3044", "firewire", NULL }, 672 { "pci1106,3038", "usb", dt_usb }, 673 { "pci1106,8235", "other", NULL }, 674 { "pci1106,3058", "sound", NULL }, 675 { NULL, NULL } 676 }; 677 678 static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque) 679 { 680 FDTInfo *fi = opaque; 681 GString *node = g_string_new(NULL); 682 uint32_t cells[(PCI_NUM_REGIONS + 1) * 5]; 683 int i, j; 684 const char *name = NULL; 685 g_autofree const gchar *pn = g_strdup_printf("pci%x,%x", 686 pci_get_word(&d->config[PCI_VENDOR_ID]), 687 pci_get_word(&d->config[PCI_DEVICE_ID])); 688 689 for (i = 0; device_map[i].id; i++) { 690 if (!strcmp(pn, device_map[i].id)) { 691 name = device_map[i].name; 692 break; 693 } 694 } 695 g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn), 696 PCI_SLOT(d->devfn)); 697 if (PCI_FUNC(d->devfn)) { 698 g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn)); 699 } 700 701 qemu_fdt_add_subnode(fi->fdt, node->str); 702 if (device_map[i].dtf) { 703 FDTInfo cfi = { fi->fdt, node->str }; 704 device_map[i].dtf(bus, d, &cfi); 705 } 706 cells[0] = cpu_to_be32(d->devfn << 8); 707 cells[1] = 0; 708 cells[2] = 0; 709 cells[3] = 0; 710 cells[4] = 0; 711 j = 5; 712 for (i = 0; i < PCI_NUM_REGIONS; i++) { 713 if (!d->io_regions[i].size) { 714 continue; 715 } 716 cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4)); 717 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 718 cells[j] |= cpu_to_be32(1 << 24); 719 } else { 720 cells[j] |= cpu_to_be32(2 << 24); 721 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 722 cells[j] |= cpu_to_be32(4 << 28); 723 } 724 } 725 cells[j + 1] = 0; 726 cells[j + 2] = 0; 727 cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32); 728 cells[j + 4] = cpu_to_be32(d->io_regions[i].size); 729 j += 5; 730 } 731 qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0])); 732 qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn); 733 if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) { 734 qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts", 735 pci_get_byte(&d->config[PCI_INTERRUPT_PIN])); 736 } 737 /* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */ 738 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id", 739 pci_get_word(&d->config[PCI_SUBSYSTEM_ID])); 740 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id", 741 pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID])); 742 cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]); 743 qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8); 744 qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff); 745 qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id", 746 pci_get_word(&d->config[PCI_DEVICE_ID])); 747 qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id", 748 pci_get_word(&d->config[PCI_VENDOR_ID])); 749 750 g_string_free(node, TRUE); 751 } 752 753 static void *build_fdt(MachineState *machine, int *fdt_size) 754 { 755 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 756 PowerPCCPU *cpu = pm->cpu; 757 PCIBus *pci_bus; 758 FDTInfo fi; 759 uint32_t cells[16]; 760 void *fdt = create_device_tree(fdt_size); 761 762 fi.fdt = fdt; 763 764 /* root node */ 765 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description", 766 "Pegasos CHRP PowerPC System"); 767 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2"); 768 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH"); 769 qemu_fdt_setprop_string(fdt, "/", "revision", "2B"); 770 qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2"); 771 qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp"); 772 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1); 773 qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2"); 774 775 /* pci@c0000000 */ 776 qemu_fdt_add_subnode(fdt, "/pci@c0000000"); 777 cells[0] = 0; 778 cells[1] = 0; 779 qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range", 780 cells, 2 * sizeof(cells[0])); 781 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1); 782 cells[0] = cpu_to_be32(PCI0_MEM_BASE); 783 cells[1] = cpu_to_be32(PCI0_MEM_SIZE); 784 qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0])); 785 cells[0] = cpu_to_be32(0x01000000); 786 cells[1] = 0; 787 cells[2] = 0; 788 cells[3] = cpu_to_be32(PCI0_IO_BASE); 789 cells[4] = 0; 790 cells[5] = cpu_to_be32(PCI0_IO_SIZE); 791 cells[6] = cpu_to_be32(0x02000000); 792 cells[7] = 0; 793 cells[8] = cpu_to_be32(PCI0_MEM_BASE); 794 cells[9] = cpu_to_be32(PCI0_MEM_BASE); 795 cells[10] = 0; 796 cells[11] = cpu_to_be32(PCI0_MEM_SIZE); 797 qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges", 798 cells, 12 * sizeof(cells[0])); 799 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2); 800 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3); 801 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci"); 802 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci"); 803 804 fi.path = "/pci@c0000000"; 805 pci_bus = mv64361_get_pci_bus(pm->mv, 0); 806 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); 807 808 /* pci@80000000 */ 809 qemu_fdt_add_subnode(fdt, "/pci@80000000"); 810 cells[0] = 0; 811 cells[1] = 0; 812 qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range", 813 cells, 2 * sizeof(cells[0])); 814 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0); 815 cells[0] = cpu_to_be32(PCI1_MEM_BASE); 816 cells[1] = cpu_to_be32(PCI1_MEM_SIZE); 817 qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0])); 818 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge", 819 0xf1000cb4); 820 cells[0] = cpu_to_be32(0x01000000); 821 cells[1] = 0; 822 cells[2] = 0; 823 cells[3] = cpu_to_be32(PCI1_IO_BASE); 824 cells[4] = 0; 825 cells[5] = cpu_to_be32(PCI1_IO_SIZE); 826 cells[6] = cpu_to_be32(0x02000000); 827 cells[7] = 0; 828 cells[8] = cpu_to_be32(PCI1_MEM_BASE); 829 cells[9] = cpu_to_be32(PCI1_MEM_BASE); 830 cells[10] = 0; 831 cells[11] = cpu_to_be32(PCI1_MEM_SIZE); 832 qemu_fdt_setprop(fdt, "/pci@80000000", "ranges", 833 cells, 12 * sizeof(cells[0])); 834 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2); 835 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3); 836 qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci"); 837 qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci"); 838 839 fi.path = "/pci@80000000"; 840 pci_bus = mv64361_get_pci_bus(pm->mv, 1); 841 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); 842 843 qemu_fdt_add_subnode(fdt, "/failsafe"); 844 qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial"); 845 qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe"); 846 847 qemu_fdt_add_subnode(fdt, "/rtas"); 848 qemu_fdt_setprop_cell(fdt, "/rtas", "system-reboot", RTAS_SYSTEM_REBOOT); 849 qemu_fdt_setprop_cell(fdt, "/rtas", "hibernate", RTAS_HIBERNATE); 850 qemu_fdt_setprop_cell(fdt, "/rtas", "suspend", RTAS_SUSPEND); 851 qemu_fdt_setprop_cell(fdt, "/rtas", "power-off", RTAS_POWER_OFF); 852 qemu_fdt_setprop_cell(fdt, "/rtas", "set-indicator", RTAS_SET_INDICATOR); 853 qemu_fdt_setprop_cell(fdt, "/rtas", "display-character", 854 RTAS_DISPLAY_CHARACTER); 855 qemu_fdt_setprop_cell(fdt, "/rtas", "write-pci-config", 856 RTAS_WRITE_PCI_CONFIG); 857 qemu_fdt_setprop_cell(fdt, "/rtas", "read-pci-config", 858 RTAS_READ_PCI_CONFIG); 859 /* Pegasos2 firmware misspells check-exception and guests use that */ 860 qemu_fdt_setprop_cell(fdt, "/rtas", "check-execption", 861 RTAS_CHECK_EXCEPTION); 862 qemu_fdt_setprop_cell(fdt, "/rtas", "event-scan", RTAS_EVENT_SCAN); 863 qemu_fdt_setprop_cell(fdt, "/rtas", "set-time-of-day", 864 RTAS_SET_TIME_OF_DAY); 865 qemu_fdt_setprop_cell(fdt, "/rtas", "get-time-of-day", 866 RTAS_GET_TIME_OF_DAY); 867 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-store", RTAS_NVRAM_STORE); 868 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-fetch", RTAS_NVRAM_FETCH); 869 qemu_fdt_setprop_cell(fdt, "/rtas", "restart-rtas", RTAS_RESTART_RTAS); 870 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-error-log-max", 0); 871 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-event-scan-rate", 0); 872 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0); 873 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20); 874 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1); 875 876 /* cpus */ 877 qemu_fdt_add_subnode(fdt, "/cpus"); 878 qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1); 879 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 880 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 881 qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus"); 882 883 /* FIXME Get CPU name from CPU object */ 884 const char *cp = "/cpus/PowerPC,G4"; 885 qemu_fdt_add_subnode(fdt, cp); 886 qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0); 887 qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000); 888 qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size", 889 cpu->env.dcache_line_size); 890 qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size", 891 cpu->env.dcache_line_size); 892 qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000); 893 qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size", 894 cpu->env.icache_line_size); 895 qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size", 896 cpu->env.icache_line_size); 897 if (cpu->env.id_tlbs) { 898 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways); 899 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way); 900 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways); 901 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way); 902 qemu_fdt_setprop_string(fdt, cp, "tlb-split", ""); 903 } 904 qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways); 905 qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb); 906 qemu_fdt_setprop_string(fdt, cp, "state", "running"); 907 if (cpu->env.insns_flags & PPC_ALTIVEC) { 908 qemu_fdt_setprop_string(fdt, cp, "altivec", ""); 909 qemu_fdt_setprop_string(fdt, cp, "data-streams", ""); 910 } 911 /* 912 * FIXME What flags do data-streams, external-control and 913 * performance-monitor depend on? 914 */ 915 qemu_fdt_setprop_string(fdt, cp, "external-control", ""); 916 if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) { 917 qemu_fdt_setprop_string(fdt, cp, "general-purpose", ""); 918 } 919 qemu_fdt_setprop_string(fdt, cp, "performance-monitor", ""); 920 if (cpu->env.insns_flags & PPC_FLOAT_FRES) { 921 qemu_fdt_setprop_string(fdt, cp, "graphics", ""); 922 } 923 qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4); 924 qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency", 925 cpu->env.tb_env->tb_freq); 926 qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ); 927 qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5); 928 qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]); 929 cells[0] = 0; 930 cells[1] = 0; 931 qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0])); 932 qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu"); 933 qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1); 934 935 /* memory */ 936 qemu_fdt_add_subnode(fdt, "/memory@0"); 937 cells[0] = 0; 938 cells[1] = cpu_to_be32(machine->ram_size); 939 qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0])); 940 qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory"); 941 qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory"); 942 943 qemu_fdt_add_subnode(fdt, "/chosen"); 944 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 945 machine->kernel_cmdline ?: ""); 946 qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen"); 947 948 qemu_fdt_add_subnode(fdt, "/openprom"); 949 qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1"); 950 951 return fdt; 952 } 953