1 /* 2 * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator 3 * 4 * Copyright (c) 2018-2021 BALATON Zoltan 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 * 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/units.h" 12 #include "qapi/error.h" 13 #include "hw/ppc/ppc.h" 14 #include "hw/sysbus.h" 15 #include "hw/pci/pci_host.h" 16 #include "hw/irq.h" 17 #include "hw/pci-host/mv64361.h" 18 #include "hw/isa/vt82c686.h" 19 #include "hw/ide/pci.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/qdev-properties.h" 22 #include "sysemu/reset.h" 23 #include "sysemu/runstate.h" 24 #include "sysemu/qtest.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/fw-path-provider.h" 28 #include "elf.h" 29 #include "qemu/log.h" 30 #include "qemu/error-report.h" 31 #include "sysemu/kvm.h" 32 #include "kvm_ppc.h" 33 #include "exec/address-spaces.h" 34 #include "qom/qom-qobject.h" 35 #include "qapi/qmp/qdict.h" 36 #include "trace.h" 37 #include "qemu/datadir.h" 38 #include "sysemu/device_tree.h" 39 #include "hw/ppc/vof.h" 40 41 #include <libfdt.h> 42 43 #define PROM_FILENAME "vof.bin" 44 #define PROM_ADDR 0xfff00000 45 #define PROM_SIZE 0x80000 46 47 #define INITRD_MIN_ADDR 0x600000 48 49 #define KVMPPC_HCALL_BASE 0xf000 50 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 51 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 52 53 #define H_SUCCESS 0 54 #define H_PRIVILEGE -3 /* Caller not privileged */ 55 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 56 57 #define BUS_FREQ_HZ 133333333 58 59 #define PCI0_CFG_ADDR 0xcf8 60 #define PCI0_MEM_BASE 0xc0000000 61 #define PCI0_MEM_SIZE 0x20000000 62 #define PCI0_IO_BASE 0xf8000000 63 #define PCI0_IO_SIZE 0x10000 64 65 #define PCI1_CFG_ADDR 0xc78 66 #define PCI1_MEM_BASE 0x80000000 67 #define PCI1_MEM_SIZE 0x40000000 68 #define PCI1_IO_BASE 0xfe000000 69 #define PCI1_IO_SIZE 0x10000 70 71 #define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2") 72 OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE) 73 74 struct Pegasos2MachineState { 75 MachineState parent_obj; 76 PowerPCCPU *cpu; 77 DeviceState *mv; 78 qemu_irq mv_pirq[PCI_NUM_PINS]; 79 qemu_irq via_pirq[PCI_NUM_PINS]; 80 Vof *vof; 81 void *fdt_blob; 82 uint64_t kernel_addr; 83 uint64_t kernel_entry; 84 uint64_t kernel_size; 85 uint64_t initrd_addr; 86 uint64_t initrd_size; 87 }; 88 89 static void *build_fdt(MachineState *machine, int *fdt_size); 90 91 static void pegasos2_cpu_reset(void *opaque) 92 { 93 PowerPCCPU *cpu = opaque; 94 Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine); 95 96 cpu_reset(CPU(cpu)); 97 cpu->env.spr[SPR_HID1] = 7ULL << 28; 98 if (pm->vof) { 99 cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20; 100 cpu->env.nip = 0x100; 101 } 102 } 103 104 static void pegasos2_pci_irq(void *opaque, int n, int level) 105 { 106 Pegasos2MachineState *pm = opaque; 107 108 /* PCI interrupt lines are connected to both MV64361 and VT8231 */ 109 qemu_set_irq(pm->mv_pirq[n], level); 110 qemu_set_irq(pm->via_pirq[n], level); 111 } 112 113 static void pegasos2_init(MachineState *machine) 114 { 115 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 116 CPUPPCState *env; 117 MemoryRegion *rom = g_new(MemoryRegion, 1); 118 PCIBus *pci_bus; 119 Object *via; 120 PCIDevice *dev; 121 I2CBus *i2c_bus; 122 const char *fwname = machine->firmware ?: PROM_FILENAME; 123 char *filename; 124 int i; 125 ssize_t sz; 126 uint8_t *spd_data; 127 128 /* init CPU */ 129 pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 130 env = &pm->cpu->env; 131 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 132 error_report("Incompatible CPU, only 6xx bus supported"); 133 exit(1); 134 } 135 136 /* Set time-base frequency */ 137 cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4); 138 qemu_register_reset(pegasos2_cpu_reset, pm->cpu); 139 140 /* RAM */ 141 if (machine->ram_size > 2 * GiB) { 142 error_report("RAM size more than 2 GiB is not supported"); 143 exit(1); 144 } 145 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 146 147 /* allocate and load firmware */ 148 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname); 149 if (!filename) { 150 error_report("Could not find firmware '%s'", fwname); 151 exit(1); 152 } 153 if (!machine->firmware && !pm->vof) { 154 pm->vof = g_malloc0(sizeof(*pm->vof)); 155 } 156 memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal); 157 memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom); 158 sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1, 159 PPC_ELF_MACHINE, 0, 0); 160 if (sz <= 0) { 161 sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE); 162 } 163 if (sz <= 0 || sz > PROM_SIZE) { 164 error_report("Could not load firmware '%s'", filename); 165 exit(1); 166 } 167 g_free(filename); 168 if (pm->vof) { 169 pm->vof->fw_size = sz; 170 } 171 172 /* Marvell Discovery II system controller */ 173 pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1, 174 qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_INT))); 175 for (i = 0; i < PCI_NUM_PINS; i++) { 176 pm->mv_pirq[i] = qdev_get_gpio_in_named(pm->mv, "gpp", 12 + i); 177 } 178 pci_bus = mv64361_get_pci_bus(pm->mv, 1); 179 pci_bus_irqs(pci_bus, pegasos2_pci_irq, pm, PCI_NUM_PINS); 180 181 /* VIA VT8231 South Bridge (multifunction PCI device) */ 182 via = OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), 183 TYPE_VT8231_ISA)); 184 for (i = 0; i < PCI_NUM_PINS; i++) { 185 pm->via_pirq[i] = qdev_get_gpio_in_named(DEVICE(via), "pirq", i); 186 } 187 object_property_add_alias(OBJECT(machine), "rtc-time", 188 object_resolve_path_component(via, "rtc"), 189 "date"); 190 qdev_connect_gpio_out(DEVICE(via), 0, 191 qdev_get_gpio_in_named(pm->mv, "gpp", 31)); 192 193 dev = PCI_DEVICE(object_resolve_path_component(via, "ide")); 194 pci_ide_create_devs(dev); 195 196 dev = PCI_DEVICE(object_resolve_path_component(via, "pm")); 197 i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c")); 198 spd_data = spd_data_generate(DDR, machine->ram_size); 199 smbus_eeprom_init_one(i2c_bus, 0x57, spd_data); 200 201 /* other PC hardware */ 202 pci_vga_init(pci_bus); 203 204 if (machine->kernel_filename) { 205 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL, 206 &pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1, 207 PPC_ELF_MACHINE, 0, 0); 208 if (sz <= 0) { 209 error_report("Could not load kernel '%s'", 210 machine->kernel_filename); 211 exit(1); 212 } 213 pm->kernel_size = sz; 214 if (!pm->vof) { 215 warn_report("Option -kernel may be ineffective with -bios."); 216 } 217 } else if (pm->vof && !qtest_enabled()) { 218 warn_report("Using Virtual OpenFirmware but no -kernel option."); 219 } 220 221 if (machine->initrd_filename) { 222 pm->initrd_addr = pm->kernel_addr + pm->kernel_size + 64 * KiB; 223 pm->initrd_addr = ROUND_UP(pm->initrd_addr, 4); 224 pm->initrd_addr = MAX(pm->initrd_addr, INITRD_MIN_ADDR); 225 sz = load_image_targphys(machine->initrd_filename, pm->initrd_addr, 226 machine->ram_size - pm->initrd_addr); 227 if (sz <= 0) { 228 error_report("Could not load initrd '%s'", 229 machine->initrd_filename); 230 exit(1); 231 } 232 pm->initrd_size = sz; 233 } 234 235 if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) { 236 warn_report("Option -append may be ineffective with -bios."); 237 } 238 } 239 240 static uint32_t pegasos2_mv_reg_read(Pegasos2MachineState *pm, 241 uint32_t addr, uint32_t len) 242 { 243 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); 244 uint64_t val = 0xffffffffULL; 245 memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE, 246 MEMTXATTRS_UNSPECIFIED); 247 return val; 248 } 249 250 static void pegasos2_mv_reg_write(Pegasos2MachineState *pm, uint32_t addr, 251 uint32_t len, uint32_t val) 252 { 253 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); 254 memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE, 255 MEMTXATTRS_UNSPECIFIED); 256 } 257 258 static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus, 259 uint32_t addr, uint32_t len) 260 { 261 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; 262 uint64_t val = 0xffffffffULL; 263 264 if (len <= 4) { 265 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); 266 val = pegasos2_mv_reg_read(pm, pcicfg + 4, len); 267 } 268 return val; 269 } 270 271 static void pegasos2_pci_config_write(Pegasos2MachineState *pm, int bus, 272 uint32_t addr, uint32_t len, uint32_t val) 273 { 274 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; 275 276 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); 277 pegasos2_mv_reg_write(pm, pcicfg + 4, len, val); 278 } 279 280 static void pegasos2_machine_reset(MachineState *machine, ShutdownCause reason) 281 { 282 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 283 void *fdt; 284 uint64_t d[2]; 285 int sz; 286 287 qemu_devices_reset(reason); 288 if (!pm->vof) { 289 return; /* Firmware should set up machine so nothing to do */ 290 } 291 292 /* Otherwise, set up devices that board firmware would normally do */ 293 pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff); 294 pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc); 295 pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400); 296 pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000); 297 pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000); 298 pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO | 299 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 300 pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO | 301 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 302 303 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 304 PCI_INTERRUPT_LINE, 2, 0x9); 305 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 306 0x50, 1, 0x2); 307 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 308 0x55, 1, 0x90); 309 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 310 0x56, 1, 0x99); 311 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 312 0x57, 1, 0x90); 313 314 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 315 PCI_INTERRUPT_LINE, 2, 0x109); 316 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 317 PCI_CLASS_PROG, 1, 0xf); 318 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 319 0x40, 1, 0xb); 320 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 321 0x50, 4, 0x17171717); 322 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 323 PCI_COMMAND, 2, 0x87); 324 325 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) | 326 PCI_INTERRUPT_LINE, 2, 0x409); 327 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) | 328 PCI_COMMAND, 2, 0x7); 329 330 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) | 331 PCI_INTERRUPT_LINE, 2, 0x409); 332 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) | 333 PCI_COMMAND, 2, 0x7); 334 335 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 336 PCI_INTERRUPT_LINE, 2, 0x9); 337 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 338 0x48, 4, 0xf00); 339 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 340 0x40, 4, 0x558020); 341 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 342 0x90, 4, 0xd00); 343 344 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) | 345 PCI_INTERRUPT_LINE, 2, 0x309); 346 347 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) | 348 PCI_INTERRUPT_LINE, 2, 0x309); 349 350 /* Device tree and VOF set up */ 351 vof_init(pm->vof, machine->ram_size, &error_fatal); 352 if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) { 353 error_report("Memory allocation for stack failed"); 354 exit(1); 355 } 356 if (pm->kernel_size && 357 vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) { 358 error_report("Memory for kernel is in use"); 359 exit(1); 360 } 361 if (pm->initrd_size && 362 vof_claim(pm->vof, pm->initrd_addr, pm->initrd_size, 0) == -1) { 363 error_report("Memory for initrd is in use"); 364 exit(1); 365 } 366 fdt = build_fdt(machine, &sz); 367 /* FIXME: VOF assumes entry is same as load address */ 368 d[0] = cpu_to_be64(pm->kernel_entry); 369 d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr)); 370 qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d)); 371 372 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 373 g_free(pm->fdt_blob); 374 pm->fdt_blob = fdt; 375 376 vof_build_dt(fdt, pm->vof); 377 vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe"); 378 379 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 380 machine->fdt = fdt; 381 382 pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine); 383 } 384 385 enum pegasos2_rtas_tokens { 386 RTAS_RESTART_RTAS = 0, 387 RTAS_NVRAM_FETCH = 1, 388 RTAS_NVRAM_STORE = 2, 389 RTAS_GET_TIME_OF_DAY = 3, 390 RTAS_SET_TIME_OF_DAY = 4, 391 RTAS_EVENT_SCAN = 6, 392 RTAS_CHECK_EXCEPTION = 7, 393 RTAS_READ_PCI_CONFIG = 8, 394 RTAS_WRITE_PCI_CONFIG = 9, 395 RTAS_DISPLAY_CHARACTER = 10, 396 RTAS_SET_INDICATOR = 11, 397 RTAS_POWER_OFF = 17, 398 RTAS_SUSPEND = 18, 399 RTAS_HIBERNATE = 19, 400 RTAS_SYSTEM_REBOOT = 20, 401 }; 402 403 static target_ulong pegasos2_rtas(PowerPCCPU *cpu, Pegasos2MachineState *pm, 404 target_ulong args_real) 405 { 406 AddressSpace *as = CPU(cpu)->as; 407 uint32_t token = ldl_be_phys(as, args_real); 408 uint32_t nargs = ldl_be_phys(as, args_real + 4); 409 uint32_t nrets = ldl_be_phys(as, args_real + 8); 410 uint32_t args = args_real + 12; 411 uint32_t rets = args_real + 12 + nargs * 4; 412 413 if (nrets < 1) { 414 qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n"); 415 return H_PARAMETER; 416 } 417 switch (token) { 418 case RTAS_GET_TIME_OF_DAY: 419 { 420 QObject *qo = object_property_get_qobject(qdev_get_machine(), 421 "rtc-time", &error_fatal); 422 QDict *qd = qobject_to(QDict, qo); 423 424 if (nargs != 0 || nrets != 8 || !qd) { 425 stl_be_phys(as, rets, -1); 426 qobject_unref(qo); 427 return H_PARAMETER; 428 } 429 430 stl_be_phys(as, rets, 0); 431 stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900); 432 stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1); 433 stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday")); 434 stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour")); 435 stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min")); 436 stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec")); 437 stl_be_phys(as, rets + 28, 0); 438 qobject_unref(qo); 439 return H_SUCCESS; 440 } 441 case RTAS_READ_PCI_CONFIG: 442 { 443 uint32_t addr, len, val; 444 445 if (nargs != 2 || nrets != 2) { 446 stl_be_phys(as, rets, -1); 447 return H_PARAMETER; 448 } 449 addr = ldl_be_phys(as, args); 450 len = ldl_be_phys(as, args + 4); 451 val = pegasos2_pci_config_read(pm, !(addr >> 24), 452 addr & 0x0fffffff, len); 453 stl_be_phys(as, rets, 0); 454 stl_be_phys(as, rets + 4, val); 455 return H_SUCCESS; 456 } 457 case RTAS_WRITE_PCI_CONFIG: 458 { 459 uint32_t addr, len, val; 460 461 if (nargs != 3 || nrets != 1) { 462 stl_be_phys(as, rets, -1); 463 return H_PARAMETER; 464 } 465 addr = ldl_be_phys(as, args); 466 len = ldl_be_phys(as, args + 4); 467 val = ldl_be_phys(as, args + 8); 468 pegasos2_pci_config_write(pm, !(addr >> 24), 469 addr & 0x0fffffff, len, val); 470 stl_be_phys(as, rets, 0); 471 return H_SUCCESS; 472 } 473 case RTAS_DISPLAY_CHARACTER: 474 if (nargs != 1 || nrets != 1) { 475 stl_be_phys(as, rets, -1); 476 return H_PARAMETER; 477 } 478 qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args)); 479 stl_be_phys(as, rets, 0); 480 return H_SUCCESS; 481 case RTAS_POWER_OFF: 482 { 483 if (nargs != 2 || nrets != 1) { 484 stl_be_phys(as, rets, -1); 485 return H_PARAMETER; 486 } 487 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 488 stl_be_phys(as, rets, 0); 489 return H_SUCCESS; 490 } 491 default: 492 qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n", 493 token, nargs, nrets); 494 stl_be_phys(as, rets, 0); 495 return H_SUCCESS; 496 } 497 } 498 499 static bool pegasos2_cpu_in_nested(PowerPCCPU *cpu) 500 { 501 return false; 502 } 503 504 static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 505 { 506 Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp); 507 CPUPPCState *env = &cpu->env; 508 509 /* The TCG path should also be holding the BQL at this point */ 510 g_assert(qemu_mutex_iothread_locked()); 511 512 if (FIELD_EX64(env->msr, MSR, PR)) { 513 qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n"); 514 env->gpr[3] = H_PRIVILEGE; 515 } else if (env->gpr[3] == KVMPPC_H_RTAS) { 516 env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]); 517 } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) { 518 int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob, 519 env->gpr[4]); 520 env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS); 521 } else { 522 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx 523 "\n", env->gpr[3]); 524 env->gpr[3] = -1; 525 } 526 } 527 528 static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 529 { 530 } 531 532 static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 533 { 534 return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1]; 535 } 536 537 static bool pegasos2_setprop(MachineState *ms, const char *path, 538 const char *propname, void *val, int vallen) 539 { 540 return true; 541 } 542 543 static void pegasos2_machine_class_init(ObjectClass *oc, void *data) 544 { 545 MachineClass *mc = MACHINE_CLASS(oc); 546 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 547 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 548 549 mc->desc = "Genesi/bPlan Pegasos II"; 550 mc->init = pegasos2_init; 551 mc->reset = pegasos2_machine_reset; 552 mc->block_default_type = IF_IDE; 553 mc->default_boot_order = "cd"; 554 mc->default_display = "std"; 555 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7457_v1.2"); 556 mc->default_ram_id = "pegasos2.ram"; 557 mc->default_ram_size = 512 * MiB; 558 559 vhc->cpu_in_nested = pegasos2_cpu_in_nested; 560 vhc->hypercall = pegasos2_hypercall; 561 vhc->cpu_exec_enter = vhyp_nop; 562 vhc->cpu_exec_exit = vhyp_nop; 563 vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr; 564 565 vmc->setprop = pegasos2_setprop; 566 } 567 568 static const TypeInfo pegasos2_machine_info = { 569 .name = TYPE_PEGASOS2_MACHINE, 570 .parent = TYPE_MACHINE, 571 .class_init = pegasos2_machine_class_init, 572 .instance_size = sizeof(Pegasos2MachineState), 573 .interfaces = (InterfaceInfo[]) { 574 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 575 { TYPE_VOF_MACHINE_IF }, 576 { } 577 }, 578 }; 579 580 static void pegasos2_machine_register_types(void) 581 { 582 type_register_static(&pegasos2_machine_info); 583 } 584 585 type_init(pegasos2_machine_register_types) 586 587 /* FDT creation for passing to firmware */ 588 589 typedef struct { 590 void *fdt; 591 const char *path; 592 } FDTInfo; 593 594 /* We do everything in reverse order so it comes out right in the tree */ 595 596 static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 597 { 598 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi"); 599 } 600 601 static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 602 { 603 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0); 604 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1); 605 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb"); 606 } 607 608 static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 609 { 610 GString *name = g_string_sized_new(64); 611 uint32_t cells[3]; 612 613 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1); 614 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2); 615 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa"); 616 qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa"); 617 618 /* additional devices */ 619 g_string_printf(name, "%s/lpt@i3bc", fi->path); 620 qemu_fdt_add_subnode(fi->fdt, name->str); 621 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 622 cells[0] = cpu_to_be32(7); 623 cells[1] = 0; 624 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 625 cells, 2 * sizeof(cells[0])); 626 cells[0] = cpu_to_be32(1); 627 cells[1] = cpu_to_be32(0x3bc); 628 cells[2] = cpu_to_be32(8); 629 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 630 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt"); 631 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt"); 632 633 g_string_printf(name, "%s/fdc@i3f0", fi->path); 634 qemu_fdt_add_subnode(fi->fdt, name->str); 635 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 636 cells[0] = cpu_to_be32(6); 637 cells[1] = 0; 638 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 639 cells, 2 * sizeof(cells[0])); 640 cells[0] = cpu_to_be32(1); 641 cells[1] = cpu_to_be32(0x3f0); 642 cells[2] = cpu_to_be32(8); 643 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 644 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc"); 645 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc"); 646 647 g_string_printf(name, "%s/timer@i40", fi->path); 648 qemu_fdt_add_subnode(fi->fdt, name->str); 649 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 650 cells[0] = cpu_to_be32(1); 651 cells[1] = cpu_to_be32(0x40); 652 cells[2] = cpu_to_be32(8); 653 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 654 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer"); 655 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer"); 656 657 g_string_printf(name, "%s/rtc@i70", fi->path); 658 qemu_fdt_add_subnode(fi->fdt, name->str); 659 qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc"); 660 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 661 cells[0] = cpu_to_be32(8); 662 cells[1] = 0; 663 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 664 cells, 2 * sizeof(cells[0])); 665 cells[0] = cpu_to_be32(1); 666 cells[1] = cpu_to_be32(0x70); 667 cells[2] = cpu_to_be32(2); 668 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 669 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc"); 670 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc"); 671 672 g_string_printf(name, "%s/keyboard@i60", fi->path); 673 qemu_fdt_add_subnode(fi->fdt, name->str); 674 cells[0] = cpu_to_be32(1); 675 cells[1] = 0; 676 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 677 cells, 2 * sizeof(cells[0])); 678 cells[0] = cpu_to_be32(1); 679 cells[1] = cpu_to_be32(0x60); 680 cells[2] = cpu_to_be32(5); 681 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 682 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard"); 683 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard"); 684 685 g_string_printf(name, "%s/8042@i60", fi->path); 686 qemu_fdt_add_subnode(fi->fdt, name->str); 687 qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2); 688 qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0); 689 qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1); 690 qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", ""); 691 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 692 cells[0] = cpu_to_be32(1); 693 cells[1] = cpu_to_be32(0x60); 694 cells[2] = cpu_to_be32(5); 695 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 696 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", ""); 697 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042"); 698 699 g_string_printf(name, "%s/serial@i2f8", fi->path); 700 qemu_fdt_add_subnode(fi->fdt, name->str); 701 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 702 cells[0] = cpu_to_be32(3); 703 cells[1] = 0; 704 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 705 cells, 2 * sizeof(cells[0])); 706 cells[0] = cpu_to_be32(1); 707 cells[1] = cpu_to_be32(0x2f8); 708 cells[2] = cpu_to_be32(8); 709 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 710 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial"); 711 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial"); 712 713 g_string_free(name, TRUE); 714 } 715 716 static struct { 717 const char *id; 718 const char *name; 719 void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi); 720 } device_map[] = { 721 { "pci11ab,6460", "host", NULL }, 722 { "pci1106,8231", "isa", dt_isa }, 723 { "pci1106,571", "ide", dt_ide }, 724 { "pci1106,3044", "firewire", NULL }, 725 { "pci1106,3038", "usb", dt_usb }, 726 { "pci1106,8235", "other", NULL }, 727 { "pci1106,3058", "sound", NULL }, 728 { NULL, NULL } 729 }; 730 731 static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque) 732 { 733 FDTInfo *fi = opaque; 734 GString *node = g_string_new(NULL); 735 uint32_t cells[(PCI_NUM_REGIONS + 1) * 5]; 736 int i, j; 737 const char *name = NULL; 738 g_autofree const gchar *pn = g_strdup_printf("pci%x,%x", 739 pci_get_word(&d->config[PCI_VENDOR_ID]), 740 pci_get_word(&d->config[PCI_DEVICE_ID])); 741 742 for (i = 0; device_map[i].id; i++) { 743 if (!strcmp(pn, device_map[i].id)) { 744 name = device_map[i].name; 745 break; 746 } 747 } 748 g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn), 749 PCI_SLOT(d->devfn)); 750 if (PCI_FUNC(d->devfn)) { 751 g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn)); 752 } 753 754 qemu_fdt_add_subnode(fi->fdt, node->str); 755 if (device_map[i].dtf) { 756 FDTInfo cfi = { fi->fdt, node->str }; 757 device_map[i].dtf(bus, d, &cfi); 758 } 759 cells[0] = cpu_to_be32(d->devfn << 8); 760 cells[1] = 0; 761 cells[2] = 0; 762 cells[3] = 0; 763 cells[4] = 0; 764 j = 5; 765 for (i = 0; i < PCI_NUM_REGIONS; i++) { 766 if (!d->io_regions[i].size) { 767 continue; 768 } 769 cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4)); 770 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 771 cells[j] |= cpu_to_be32(1 << 24); 772 } else { 773 cells[j] |= cpu_to_be32(2 << 24); 774 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 775 cells[j] |= cpu_to_be32(4 << 28); 776 } 777 } 778 cells[j + 1] = 0; 779 cells[j + 2] = 0; 780 cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32); 781 cells[j + 4] = cpu_to_be32(d->io_regions[i].size); 782 j += 5; 783 } 784 qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0])); 785 qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn); 786 if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) { 787 qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts", 788 pci_get_byte(&d->config[PCI_INTERRUPT_PIN])); 789 } 790 /* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */ 791 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id", 792 pci_get_word(&d->config[PCI_SUBSYSTEM_ID])); 793 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id", 794 pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID])); 795 cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]); 796 qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8); 797 qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff); 798 qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id", 799 pci_get_word(&d->config[PCI_DEVICE_ID])); 800 qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id", 801 pci_get_word(&d->config[PCI_VENDOR_ID])); 802 803 g_string_free(node, TRUE); 804 } 805 806 static void *build_fdt(MachineState *machine, int *fdt_size) 807 { 808 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 809 PowerPCCPU *cpu = pm->cpu; 810 PCIBus *pci_bus; 811 FDTInfo fi; 812 uint32_t cells[16]; 813 void *fdt = create_device_tree(fdt_size); 814 815 fi.fdt = fdt; 816 817 /* root node */ 818 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description", 819 "Pegasos CHRP PowerPC System"); 820 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2"); 821 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH"); 822 qemu_fdt_setprop_string(fdt, "/", "revision", "2B"); 823 qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2"); 824 qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp"); 825 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1); 826 qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2"); 827 828 /* pci@c0000000 */ 829 qemu_fdt_add_subnode(fdt, "/pci@c0000000"); 830 cells[0] = 0; 831 cells[1] = 0; 832 qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range", 833 cells, 2 * sizeof(cells[0])); 834 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1); 835 cells[0] = cpu_to_be32(PCI0_MEM_BASE); 836 cells[1] = cpu_to_be32(PCI0_MEM_SIZE); 837 qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0])); 838 cells[0] = cpu_to_be32(0x01000000); 839 cells[1] = 0; 840 cells[2] = 0; 841 cells[3] = cpu_to_be32(PCI0_IO_BASE); 842 cells[4] = 0; 843 cells[5] = cpu_to_be32(PCI0_IO_SIZE); 844 cells[6] = cpu_to_be32(0x02000000); 845 cells[7] = 0; 846 cells[8] = cpu_to_be32(PCI0_MEM_BASE); 847 cells[9] = cpu_to_be32(PCI0_MEM_BASE); 848 cells[10] = 0; 849 cells[11] = cpu_to_be32(PCI0_MEM_SIZE); 850 qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges", 851 cells, 12 * sizeof(cells[0])); 852 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2); 853 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3); 854 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci"); 855 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci"); 856 857 fi.path = "/pci@c0000000"; 858 pci_bus = mv64361_get_pci_bus(pm->mv, 0); 859 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); 860 861 /* pci@80000000 */ 862 qemu_fdt_add_subnode(fdt, "/pci@80000000"); 863 cells[0] = 0; 864 cells[1] = 0; 865 qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range", 866 cells, 2 * sizeof(cells[0])); 867 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0); 868 cells[0] = cpu_to_be32(PCI1_MEM_BASE); 869 cells[1] = cpu_to_be32(PCI1_MEM_SIZE); 870 qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0])); 871 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge", 872 0xf1000cb4); 873 cells[0] = cpu_to_be32(0x01000000); 874 cells[1] = 0; 875 cells[2] = 0; 876 cells[3] = cpu_to_be32(PCI1_IO_BASE); 877 cells[4] = 0; 878 cells[5] = cpu_to_be32(PCI1_IO_SIZE); 879 cells[6] = cpu_to_be32(0x02000000); 880 cells[7] = 0; 881 cells[8] = cpu_to_be32(PCI1_MEM_BASE); 882 cells[9] = cpu_to_be32(PCI1_MEM_BASE); 883 cells[10] = 0; 884 cells[11] = cpu_to_be32(PCI1_MEM_SIZE); 885 qemu_fdt_setprop(fdt, "/pci@80000000", "ranges", 886 cells, 12 * sizeof(cells[0])); 887 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2); 888 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3); 889 qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci"); 890 qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci"); 891 892 fi.path = "/pci@80000000"; 893 pci_bus = mv64361_get_pci_bus(pm->mv, 1); 894 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); 895 896 qemu_fdt_add_subnode(fdt, "/failsafe"); 897 qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial"); 898 qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe"); 899 900 qemu_fdt_add_subnode(fdt, "/rtas"); 901 qemu_fdt_setprop_cell(fdt, "/rtas", "system-reboot", RTAS_SYSTEM_REBOOT); 902 qemu_fdt_setprop_cell(fdt, "/rtas", "hibernate", RTAS_HIBERNATE); 903 qemu_fdt_setprop_cell(fdt, "/rtas", "suspend", RTAS_SUSPEND); 904 qemu_fdt_setprop_cell(fdt, "/rtas", "power-off", RTAS_POWER_OFF); 905 qemu_fdt_setprop_cell(fdt, "/rtas", "set-indicator", RTAS_SET_INDICATOR); 906 qemu_fdt_setprop_cell(fdt, "/rtas", "display-character", 907 RTAS_DISPLAY_CHARACTER); 908 qemu_fdt_setprop_cell(fdt, "/rtas", "write-pci-config", 909 RTAS_WRITE_PCI_CONFIG); 910 qemu_fdt_setprop_cell(fdt, "/rtas", "read-pci-config", 911 RTAS_READ_PCI_CONFIG); 912 /* Pegasos2 firmware misspells check-exception and guests use that */ 913 qemu_fdt_setprop_cell(fdt, "/rtas", "check-execption", 914 RTAS_CHECK_EXCEPTION); 915 qemu_fdt_setprop_cell(fdt, "/rtas", "event-scan", RTAS_EVENT_SCAN); 916 qemu_fdt_setprop_cell(fdt, "/rtas", "set-time-of-day", 917 RTAS_SET_TIME_OF_DAY); 918 qemu_fdt_setprop_cell(fdt, "/rtas", "get-time-of-day", 919 RTAS_GET_TIME_OF_DAY); 920 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-store", RTAS_NVRAM_STORE); 921 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-fetch", RTAS_NVRAM_FETCH); 922 qemu_fdt_setprop_cell(fdt, "/rtas", "restart-rtas", RTAS_RESTART_RTAS); 923 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-error-log-max", 0); 924 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-event-scan-rate", 0); 925 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0); 926 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20); 927 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1); 928 929 /* cpus */ 930 qemu_fdt_add_subnode(fdt, "/cpus"); 931 qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1); 932 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 933 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 934 qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus"); 935 936 /* FIXME Get CPU name from CPU object */ 937 const char *cp = "/cpus/PowerPC,G4"; 938 qemu_fdt_add_subnode(fdt, cp); 939 qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0); 940 qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000); 941 qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size", 942 cpu->env.dcache_line_size); 943 qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size", 944 cpu->env.dcache_line_size); 945 qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000); 946 qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size", 947 cpu->env.icache_line_size); 948 qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size", 949 cpu->env.icache_line_size); 950 if (cpu->env.id_tlbs) { 951 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways); 952 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way); 953 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways); 954 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way); 955 qemu_fdt_setprop_string(fdt, cp, "tlb-split", ""); 956 } 957 qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways); 958 qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb); 959 qemu_fdt_setprop_string(fdt, cp, "state", "running"); 960 if (cpu->env.insns_flags & PPC_ALTIVEC) { 961 qemu_fdt_setprop_string(fdt, cp, "altivec", ""); 962 qemu_fdt_setprop_string(fdt, cp, "data-streams", ""); 963 } 964 /* 965 * FIXME What flags do data-streams, external-control and 966 * performance-monitor depend on? 967 */ 968 qemu_fdt_setprop_string(fdt, cp, "external-control", ""); 969 if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) { 970 qemu_fdt_setprop_string(fdt, cp, "general-purpose", ""); 971 } 972 qemu_fdt_setprop_string(fdt, cp, "performance-monitor", ""); 973 if (cpu->env.insns_flags & PPC_FLOAT_FRES) { 974 qemu_fdt_setprop_string(fdt, cp, "graphics", ""); 975 } 976 qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4); 977 qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency", 978 cpu->env.tb_env->tb_freq); 979 qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ); 980 qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5); 981 qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]); 982 cells[0] = 0; 983 cells[1] = 0; 984 qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0])); 985 qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu"); 986 qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1); 987 988 /* memory */ 989 qemu_fdt_add_subnode(fdt, "/memory@0"); 990 cells[0] = 0; 991 cells[1] = cpu_to_be32(machine->ram_size); 992 qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0])); 993 qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory"); 994 qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory"); 995 996 qemu_fdt_add_subnode(fdt, "/chosen"); 997 if (pm->initrd_addr && pm->initrd_size) { 998 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 999 pm->initrd_addr + pm->initrd_size); 1000 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 1001 pm->initrd_addr); 1002 } 1003 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 1004 machine->kernel_cmdline ?: ""); 1005 qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen"); 1006 1007 qemu_fdt_add_subnode(fdt, "/openprom"); 1008 qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1"); 1009 1010 return fdt; 1011 } 1012