1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "hw/ppc/ppc.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/boards.h" 34 #include "hw/input/adb.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/isa/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_host.h" 40 #include "hw/pci-host/grackle.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/char/escc.h" 43 #include "hw/misc/macio/macio.h" 44 #include "hw/loader.h" 45 #include "hw/fw-path-provider.h" 46 #include "elf.h" 47 #include "qemu/error-report.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/reset.h" 50 #include "kvm_ppc.h" 51 52 #define MAX_IDE_BUS 2 53 #define CFG_ADDR 0xf0000510 54 #define TBFREQ 16600000UL 55 #define CLOCKFREQ 266000000UL 56 #define BUSFREQ 66000000UL 57 58 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 59 60 #define PROM_FILENAME "openbios-ppc" 61 #define PROM_BASE 0xffc00000 62 #define PROM_SIZE (4 * MiB) 63 64 #define KERNEL_LOAD_ADDR 0x01000000 65 #define KERNEL_GAP 0x00100000 66 67 #define GRACKLE_BASE 0xfec00000 68 69 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 70 Error **errp) 71 { 72 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 73 } 74 75 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 76 { 77 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 78 } 79 80 static void ppc_heathrow_reset(void *opaque) 81 { 82 PowerPCCPU *cpu = opaque; 83 84 cpu_reset(CPU(cpu)); 85 } 86 87 static void ppc_heathrow_init(MachineState *machine) 88 { 89 const char *bios_name = machine->firmware ?: PROM_FILENAME; 90 MachineClass *mc = MACHINE_GET_CLASS(machine); 91 PowerPCCPU *cpu = NULL; 92 CPUPPCState *env = NULL; 93 char *filename; 94 int i, bios_size = -1; 95 MemoryRegion *bios = g_new(MemoryRegion, 1); 96 uint64_t bios_addr; 97 uint32_t kernel_base = 0, initrd_base = 0, cmdline_base = 0; 98 int32_t kernel_size = 0, initrd_size = 0; 99 PCIBus *pci_bus; 100 Object *macio; 101 MACIOIDEState *macio_ide; 102 SysBusDevice *s; 103 DeviceState *dev, *pic_dev, *grackle_dev; 104 BusState *adb_bus; 105 uint16_t ppc_boot_device; 106 DriveInfo *dinfo, *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 107 void *fw_cfg; 108 uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ; 109 110 /* init CPUs */ 111 for (i = 0; i < machine->smp.cpus; i++) { 112 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 113 env = &cpu->env; 114 115 /* Set time-base frequency to 16.6 Mhz */ 116 cpu_ppc_tb_init(env, TBFREQ); 117 qemu_register_reset(ppc_heathrow_reset, cpu); 118 } 119 120 /* allocate RAM */ 121 if (machine->ram_size > 2047 * MiB) { 122 error_report("Too much memory for this machine: %" PRId64 " MB, " 123 "maximum 2047 MB", machine->ram_size / MiB); 124 exit(1); 125 } 126 127 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 128 129 /* allocate and load firmware ROM */ 130 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE, 131 &error_fatal); 132 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); 133 134 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 135 if (filename) { 136 /* Load OpenBIOS (ELF) */ 137 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr, 138 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 139 /* Unfortunately, load_elf sign-extends reading elf32 */ 140 bios_addr = (uint32_t)bios_addr; 141 142 if (bios_size <= 0) { 143 /* or if could not load ELF try loading a binary ROM image */ 144 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 145 bios_addr = PROM_BASE; 146 } 147 g_free(filename); 148 } 149 if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) { 150 error_report("could not load PowerPC bios '%s'", bios_name); 151 exit(1); 152 } 153 154 if (machine->kernel_filename) { 155 int bswap_needed = 0; 156 157 #ifdef BSWAP_NEEDED 158 bswap_needed = 1; 159 #endif 160 kernel_base = KERNEL_LOAD_ADDR; 161 kernel_size = load_elf(machine->kernel_filename, NULL, 162 translate_kernel_address, NULL, NULL, NULL, 163 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 164 if (kernel_size < 0) { 165 kernel_size = load_aout(machine->kernel_filename, kernel_base, 166 machine->ram_size - kernel_base, 167 bswap_needed, TARGET_PAGE_SIZE); 168 } 169 if (kernel_size < 0) { 170 kernel_size = load_image_targphys(machine->kernel_filename, 171 kernel_base, 172 machine->ram_size - kernel_base); 173 } 174 if (kernel_size < 0) { 175 error_report("could not load kernel '%s'", 176 machine->kernel_filename); 177 exit(1); 178 } 179 /* load initrd */ 180 if (machine->initrd_filename) { 181 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + 182 KERNEL_GAP); 183 initrd_size = load_image_targphys(machine->initrd_filename, 184 initrd_base, 185 machine->ram_size - initrd_base); 186 if (initrd_size < 0) { 187 error_report("could not load initial ram disk '%s'", 188 machine->initrd_filename); 189 exit(1); 190 } 191 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 192 } else { 193 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 194 } 195 ppc_boot_device = 'm'; 196 } else { 197 ppc_boot_device = '\0'; 198 for (i = 0; machine->boot_config.order[i] != '\0'; i++) { 199 /* 200 * TOFIX: for now, the second IDE channel is not properly 201 * used by OHW. The Mac floppy disk are not emulated. 202 * For now, OHW cannot boot from the network. 203 */ 204 #if 0 205 if (machine->boot_config.order[i] >= 'a' && 206 machine->boot_config.order[i] <= 'f') { 207 ppc_boot_device = machine->boot_config.order[i]; 208 break; 209 } 210 #else 211 if (machine->boot_config.order[i] >= 'c' && 212 machine->boot_config.order[i] <= 'd') { 213 ppc_boot_device = machine->boot_config.order[i]; 214 break; 215 } 216 #endif 217 } 218 if (ppc_boot_device == '\0') { 219 error_report("No valid boot device for G3 Beige machine"); 220 exit(1); 221 } 222 } 223 224 /* Grackle PCI host bridge */ 225 grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); 226 qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x80000000); 227 s = SYS_BUS_DEVICE(grackle_dev); 228 sysbus_realize_and_unref(s, &error_fatal); 229 230 sysbus_mmio_map(s, 0, GRACKLE_BASE); 231 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 232 /* PCI hole */ 233 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 234 sysbus_mmio_get_region(s, 2)); 235 /* Register 2 MB of ISA IO space */ 236 memory_region_add_subregion(get_system_memory(), 0xfe000000, 237 sysbus_mmio_get_region(s, 3)); 238 239 pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus; 240 241 /* MacIO */ 242 macio = OBJECT(pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO)); 243 qdev_prop_set_uint64(DEVICE(macio), "frequency", tbfreq); 244 245 dev = DEVICE(object_resolve_path_component(macio, "escc")); 246 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 247 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 248 249 dinfo = drive_get(IF_MTD, 0, 0); 250 if (dinfo) { 251 dev = DEVICE(object_resolve_path_component(macio, "nvram")); 252 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 253 } 254 255 pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal); 256 257 pic_dev = DEVICE(object_resolve_path_component(macio, "pic")); 258 for (i = 0; i < 4; i++) { 259 qdev_connect_gpio_out(grackle_dev, i, 260 qdev_get_gpio_in(pic_dev, 0x15 + i)); 261 } 262 263 /* Connect the heathrow PIC outputs to the 6xx bus */ 264 for (i = 0; i < machine->smp.cpus; i++) { 265 switch (PPC_INPUT(env)) { 266 case PPC_FLAGS_INPUT_6xx: 267 /* XXX: we register only 1 output pin for heathrow PIC */ 268 qdev_connect_gpio_out(pic_dev, 0, 269 qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT)); 270 break; 271 default: 272 error_report("Bus model not supported on OldWorld Mac machine"); 273 exit(1); 274 } 275 } 276 277 pci_vga_init(pci_bus); 278 279 for (i = 0; i < nb_nics; i++) { 280 pci_nic_init_nofail(&nd_table[i], pci_bus, mc->default_nic, NULL); 281 } 282 283 /* MacIO IDE */ 284 ide_drive_get(hd, ARRAY_SIZE(hd)); 285 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[0]")); 286 macio_ide_init_drives(macio_ide, hd); 287 288 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[1]")); 289 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 290 291 /* MacIO CUDA/ADB */ 292 dev = DEVICE(object_resolve_path_component(macio, "cuda")); 293 adb_bus = qdev_get_child_bus(dev, "adb.0"); 294 dev = qdev_new(TYPE_ADB_KEYBOARD); 295 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 296 dev = qdev_new(TYPE_ADB_MOUSE); 297 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 298 299 if (machine_usb(machine)) { 300 pci_create_simple(pci_bus, -1, "pci-ohci"); 301 } 302 303 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 304 graphic_depth = 15; 305 } 306 307 /* No PCI init: the BIOS will do it */ 308 309 dev = qdev_new(TYPE_FW_CFG_MEM); 310 fw_cfg = FW_CFG(dev); 311 qdev_prop_set_uint32(dev, "data_width", 1); 312 qdev_prop_set_bit(dev, "dma_enabled", false); 313 object_property_add_child(OBJECT(machine), TYPE_FW_CFG, OBJECT(fw_cfg)); 314 s = SYS_BUS_DEVICE(dev); 315 sysbus_realize_and_unref(s, &error_fatal); 316 sysbus_mmio_map(s, 0, CFG_ADDR); 317 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 318 319 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 320 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 321 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 322 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 323 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 324 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 325 if (machine->kernel_cmdline) { 326 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 327 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, 328 machine->kernel_cmdline); 329 } else { 330 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 331 } 332 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 333 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 334 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 335 336 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 337 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 338 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 339 340 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 341 if (kvm_enabled()) { 342 uint8_t *hypercall; 343 344 hypercall = g_malloc(16); 345 kvmppc_get_hypercall(env, hypercall, 16); 346 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 347 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 348 } 349 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 350 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 351 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 352 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 353 354 /* MacOS NDRV VGA driver */ 355 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 356 if (filename) { 357 gchar *ndrv_file; 358 gsize ndrv_size; 359 360 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 361 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 362 } 363 g_free(filename); 364 } 365 366 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 367 } 368 369 /* 370 * Implementation of an interface to adjust firmware path 371 * for the bootindex property handling. 372 */ 373 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, 374 DeviceState *dev) 375 { 376 PCIDevice *pci; 377 MACIOIDEState *macio_ide; 378 379 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { 380 pci = PCI_DEVICE(dev); 381 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 382 } 383 384 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 385 macio_ide = MACIO_IDE(dev); 386 return g_strdup_printf("ata-3@%x", macio_ide->addr); 387 } 388 389 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 390 return g_strdup("disk"); 391 } 392 393 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 394 return g_strdup("cdrom"); 395 } 396 397 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 398 return g_strdup("disk"); 399 } 400 401 return NULL; 402 } 403 404 static int heathrow_kvm_type(MachineState *machine, const char *arg) 405 { 406 /* Always force PR KVM */ 407 return 2; 408 } 409 410 static void heathrow_class_init(ObjectClass *oc, void *data) 411 { 412 MachineClass *mc = MACHINE_CLASS(oc); 413 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 414 415 mc->desc = "Heathrow based PowerMAC"; 416 mc->init = ppc_heathrow_init; 417 mc->block_default_type = IF_IDE; 418 /* SMP is not supported currently */ 419 mc->max_cpus = 1; 420 #ifndef TARGET_PPC64 421 mc->is_default = true; 422 #endif 423 /* TOFIX "cad" when Mac floppy is implemented */ 424 mc->default_boot_order = "cd"; 425 mc->kvm_type = heathrow_kvm_type; 426 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 427 mc->default_display = "std"; 428 mc->default_nic = "ne2k_pci"; 429 mc->ignore_boot_device_suffixes = true; 430 mc->default_ram_id = "ppc_heathrow.ram"; 431 fwc->get_dev_path = heathrow_fw_dev_path; 432 } 433 434 static const TypeInfo ppc_heathrow_machine_info = { 435 .name = MACHINE_TYPE_NAME("g3beige"), 436 .parent = TYPE_MACHINE, 437 .class_init = heathrow_class_init, 438 .interfaces = (InterfaceInfo[]) { 439 { TYPE_FW_PATH_PROVIDER }, 440 { } 441 }, 442 }; 443 444 static void ppc_heathrow_register_types(void) 445 { 446 type_register_static(&ppc_heathrow_machine_info); 447 } 448 449 type_init(ppc_heathrow_register_types); 450