1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "hw/ppc/ppc.h" 32 #include "hw/qdev-properties.h" 33 #include "mac.h" 34 #include "hw/input/adb.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/isa/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_host.h" 40 #include "hw/boards.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/char/escc.h" 43 #include "hw/misc/macio/macio.h" 44 #include "hw/loader.h" 45 #include "hw/fw-path-provider.h" 46 #include "elf.h" 47 #include "qemu/error-report.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/reset.h" 50 #include "kvm_ppc.h" 51 #include "exec/address-spaces.h" 52 53 #define MAX_IDE_BUS 2 54 #define CFG_ADDR 0xf0000510 55 #define TBFREQ 16600000UL 56 #define CLOCKFREQ 266000000UL 57 #define BUSFREQ 66000000UL 58 59 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 60 61 #define GRACKLE_BASE 0xfec00000 62 #define PROM_BASE 0xffc00000 63 #define PROM_SIZE (4 * MiB) 64 65 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 66 Error **errp) 67 { 68 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 69 } 70 71 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 72 { 73 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 74 } 75 76 static void ppc_heathrow_reset(void *opaque) 77 { 78 PowerPCCPU *cpu = opaque; 79 80 cpu_reset(CPU(cpu)); 81 } 82 83 static void ppc_heathrow_init(MachineState *machine) 84 { 85 ram_addr_t ram_size = machine->ram_size; 86 const char *bios_name = machine->firmware ?: PROM_FILENAME; 87 const char *boot_device = machine->boot_order; 88 PowerPCCPU *cpu = NULL; 89 CPUPPCState *env = NULL; 90 char *filename; 91 int i; 92 MemoryRegion *bios = g_new(MemoryRegion, 1); 93 uint32_t kernel_base, initrd_base, cmdline_base = 0; 94 int32_t kernel_size, initrd_size; 95 PCIBus *pci_bus; 96 PCIDevice *macio; 97 MACIOIDEState *macio_ide; 98 ESCCState *escc; 99 SysBusDevice *s; 100 DeviceState *dev, *pic_dev; 101 BusState *adb_bus; 102 uint64_t bios_addr; 103 int bios_size; 104 unsigned int smp_cpus = machine->smp.cpus; 105 uint16_t ppc_boot_device; 106 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 107 void *fw_cfg; 108 uint64_t tbfreq; 109 110 /* init CPUs */ 111 for (i = 0; i < smp_cpus; i++) { 112 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 113 env = &cpu->env; 114 115 /* Set time-base frequency to 16.6 Mhz */ 116 cpu_ppc_tb_init(env, TBFREQ); 117 qemu_register_reset(ppc_heathrow_reset, cpu); 118 } 119 120 /* allocate RAM */ 121 if (ram_size > 2047 * MiB) { 122 error_report("Too much memory for this machine: %" PRId64 " MB, " 123 "maximum 2047 MB", ram_size / MiB); 124 exit(1); 125 } 126 127 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 128 129 /* allocate and load firmware ROM */ 130 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE, 131 &error_fatal); 132 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); 133 134 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 135 if (filename) { 136 /* Load OpenBIOS (ELF) */ 137 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr, 138 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 139 /* Unfortunately, load_elf sign-extends reading elf32 */ 140 bios_addr = (uint32_t)bios_addr; 141 142 if (bios_size <= 0) { 143 /* or if could not load ELF try loading a binary ROM image */ 144 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 145 bios_addr = PROM_BASE; 146 } 147 g_free(filename); 148 } else { 149 bios_size = -1; 150 } 151 if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) { 152 error_report("could not load PowerPC bios '%s'", bios_name); 153 exit(1); 154 } 155 156 if (machine->kernel_filename) { 157 int bswap_needed; 158 159 #ifdef BSWAP_NEEDED 160 bswap_needed = 1; 161 #else 162 bswap_needed = 0; 163 #endif 164 kernel_base = KERNEL_LOAD_ADDR; 165 kernel_size = load_elf(machine->kernel_filename, NULL, 166 translate_kernel_address, NULL, NULL, NULL, 167 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 168 if (kernel_size < 0) 169 kernel_size = load_aout(machine->kernel_filename, kernel_base, 170 ram_size - kernel_base, bswap_needed, 171 TARGET_PAGE_SIZE); 172 if (kernel_size < 0) 173 kernel_size = load_image_targphys(machine->kernel_filename, 174 kernel_base, 175 ram_size - kernel_base); 176 if (kernel_size < 0) { 177 error_report("could not load kernel '%s'", 178 machine->kernel_filename); 179 exit(1); 180 } 181 /* load initrd */ 182 if (machine->initrd_filename) { 183 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + 184 KERNEL_GAP); 185 initrd_size = load_image_targphys(machine->initrd_filename, 186 initrd_base, 187 ram_size - initrd_base); 188 if (initrd_size < 0) { 189 error_report("could not load initial ram disk '%s'", 190 machine->initrd_filename); 191 exit(1); 192 } 193 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 194 } else { 195 initrd_base = 0; 196 initrd_size = 0; 197 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 198 } 199 ppc_boot_device = 'm'; 200 } else { 201 kernel_base = 0; 202 kernel_size = 0; 203 initrd_base = 0; 204 initrd_size = 0; 205 ppc_boot_device = '\0'; 206 for (i = 0; boot_device[i] != '\0'; i++) { 207 /* TOFIX: for now, the second IDE channel is not properly 208 * used by OHW. The Mac floppy disk are not emulated. 209 * For now, OHW cannot boot from the network. 210 */ 211 #if 0 212 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 213 ppc_boot_device = boot_device[i]; 214 break; 215 } 216 #else 217 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 218 ppc_boot_device = boot_device[i]; 219 break; 220 } 221 #endif 222 } 223 if (ppc_boot_device == '\0') { 224 error_report("No valid boot device for G3 Beige machine"); 225 exit(1); 226 } 227 } 228 229 /* XXX: we register only 1 output pin for heathrow PIC */ 230 pic_dev = qdev_new(TYPE_HEATHROW); 231 sysbus_realize_and_unref(SYS_BUS_DEVICE(pic_dev), &error_fatal); 232 233 /* Connect the heathrow PIC outputs to the 6xx bus */ 234 for (i = 0; i < smp_cpus; i++) { 235 switch (PPC_INPUT(env)) { 236 case PPC_FLAGS_INPUT_6xx: 237 qdev_connect_gpio_out(pic_dev, 0, 238 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]); 239 break; 240 default: 241 error_report("Bus model not supported on OldWorld Mac machine"); 242 exit(1); 243 } 244 } 245 246 /* Timebase Frequency */ 247 if (kvm_enabled()) { 248 tbfreq = kvmppc_get_tbfreq(); 249 } else { 250 tbfreq = TBFREQ; 251 } 252 253 /* init basic PC hardware */ 254 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 255 error_report("Only 6xx bus is supported on heathrow machine"); 256 exit(1); 257 } 258 259 /* Grackle PCI host bridge */ 260 dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); 261 qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000); 262 s = SYS_BUS_DEVICE(dev); 263 sysbus_realize_and_unref(s, &error_fatal); 264 265 sysbus_mmio_map(s, 0, GRACKLE_BASE); 266 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 267 /* PCI hole */ 268 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 269 sysbus_mmio_get_region(s, 2)); 270 /* Register 2 MB of ISA IO space */ 271 memory_region_add_subregion(get_system_memory(), 0xfe000000, 272 sysbus_mmio_get_region(s, 3)); 273 274 for (i = 0; i < 4; i++) { 275 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x15 + i)); 276 } 277 278 pci_bus = PCI_HOST_BRIDGE(dev)->bus; 279 280 pci_vga_init(pci_bus); 281 282 for (i = 0; i < nb_nics; i++) { 283 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 284 } 285 286 ide_drive_get(hd, ARRAY_SIZE(hd)); 287 288 /* MacIO */ 289 macio = pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO); 290 dev = DEVICE(macio); 291 qdev_prop_set_uint64(dev, "frequency", tbfreq); 292 object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev), 293 &error_abort); 294 295 escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc")); 296 qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0)); 297 qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1)); 298 299 pci_realize_and_unref(macio, pci_bus, &error_fatal); 300 301 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 302 "ide[0]")); 303 macio_ide_init_drives(macio_ide, hd); 304 305 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 306 "ide[1]")); 307 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 308 309 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 310 adb_bus = qdev_get_child_bus(dev, "adb.0"); 311 dev = qdev_new(TYPE_ADB_KEYBOARD); 312 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 313 dev = qdev_new(TYPE_ADB_MOUSE); 314 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 315 316 if (machine_usb(machine)) { 317 pci_create_simple(pci_bus, -1, "pci-ohci"); 318 } 319 320 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 321 graphic_depth = 15; 322 323 /* No PCI init: the BIOS will do it */ 324 325 dev = qdev_new(TYPE_FW_CFG_MEM); 326 fw_cfg = FW_CFG(dev); 327 qdev_prop_set_uint32(dev, "data_width", 1); 328 qdev_prop_set_bit(dev, "dma_enabled", false); 329 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 330 OBJECT(fw_cfg)); 331 s = SYS_BUS_DEVICE(dev); 332 sysbus_realize_and_unref(s, &error_fatal); 333 sysbus_mmio_map(s, 0, CFG_ADDR); 334 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 335 336 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 337 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 338 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 339 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 340 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 341 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 342 if (machine->kernel_cmdline) { 343 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 344 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, 345 machine->kernel_cmdline); 346 } else { 347 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 348 } 349 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 350 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 351 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 352 353 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 354 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 355 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 356 357 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 358 if (kvm_enabled()) { 359 uint8_t *hypercall; 360 361 hypercall = g_malloc(16); 362 kvmppc_get_hypercall(env, hypercall, 16); 363 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 364 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 365 } 366 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 367 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 368 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 369 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 370 371 /* MacOS NDRV VGA driver */ 372 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 373 if (filename) { 374 gchar *ndrv_file; 375 gsize ndrv_size; 376 377 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 378 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 379 } 380 g_free(filename); 381 } 382 383 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 384 } 385 386 /* 387 * Implementation of an interface to adjust firmware path 388 * for the bootindex property handling. 389 */ 390 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, 391 DeviceState *dev) 392 { 393 PCIDevice *pci; 394 IDEBus *ide_bus; 395 IDEState *ide_s; 396 MACIOIDEState *macio_ide; 397 398 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { 399 pci = PCI_DEVICE(dev); 400 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 401 } 402 403 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 404 macio_ide = MACIO_IDE(dev); 405 return g_strdup_printf("ata-3@%x", macio_ide->addr); 406 } 407 408 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) { 409 ide_bus = IDE_BUS(qdev_get_parent_bus(dev)); 410 ide_s = idebus_active_if(ide_bus); 411 412 if (ide_s->drive_kind == IDE_CD) { 413 return g_strdup("cdrom"); 414 } 415 416 return g_strdup("disk"); 417 } 418 419 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 420 return g_strdup("disk"); 421 } 422 423 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 424 return g_strdup("cdrom"); 425 } 426 427 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 428 return g_strdup("disk"); 429 } 430 431 return NULL; 432 } 433 434 static int heathrow_kvm_type(MachineState *machine, const char *arg) 435 { 436 /* Always force PR KVM */ 437 return 2; 438 } 439 440 static void heathrow_class_init(ObjectClass *oc, void *data) 441 { 442 MachineClass *mc = MACHINE_CLASS(oc); 443 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 444 445 mc->desc = "Heathrow based PowerMAC"; 446 mc->init = ppc_heathrow_init; 447 mc->block_default_type = IF_IDE; 448 mc->max_cpus = MAX_CPUS; 449 #ifndef TARGET_PPC64 450 mc->is_default = true; 451 #endif 452 /* TOFIX "cad" when Mac floppy is implemented */ 453 mc->default_boot_order = "cd"; 454 mc->kvm_type = heathrow_kvm_type; 455 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 456 mc->default_display = "std"; 457 mc->ignore_boot_device_suffixes = true; 458 mc->default_ram_id = "ppc_heathrow.ram"; 459 fwc->get_dev_path = heathrow_fw_dev_path; 460 } 461 462 static const TypeInfo ppc_heathrow_machine_info = { 463 .name = MACHINE_TYPE_NAME("g3beige"), 464 .parent = TYPE_MACHINE, 465 .class_init = heathrow_class_init, 466 .interfaces = (InterfaceInfo[]) { 467 { TYPE_FW_PATH_PROVIDER }, 468 { } 469 }, 470 }; 471 472 static void ppc_heathrow_register_types(void) 473 { 474 type_register_static(&ppc_heathrow_machine_info); 475 } 476 477 type_init(ppc_heathrow_register_types); 478