1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "hw/ppc/ppc.h" 32 #include "hw/qdev-properties.h" 33 #include "mac.h" 34 #include "hw/input/adb.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/isa/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_host.h" 40 #include "hw/boards.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/char/escc.h" 43 #include "hw/misc/macio/macio.h" 44 #include "hw/loader.h" 45 #include "hw/fw-path-provider.h" 46 #include "elf.h" 47 #include "qemu/error-report.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/reset.h" 50 #include "kvm_ppc.h" 51 #include "exec/address-spaces.h" 52 53 #define MAX_IDE_BUS 2 54 #define CFG_ADDR 0xf0000510 55 #define TBFREQ 16600000UL 56 #define CLOCKFREQ 266000000UL 57 #define BUSFREQ 66000000UL 58 59 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 60 61 #define GRACKLE_BASE 0xfec00000 62 63 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 64 Error **errp) 65 { 66 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 67 } 68 69 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 70 { 71 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 72 } 73 74 static void ppc_heathrow_reset(void *opaque) 75 { 76 PowerPCCPU *cpu = opaque; 77 78 cpu_reset(CPU(cpu)); 79 } 80 81 static void ppc_heathrow_init(MachineState *machine) 82 { 83 ram_addr_t ram_size = machine->ram_size; 84 const char *kernel_filename = machine->kernel_filename; 85 const char *kernel_cmdline = machine->kernel_cmdline; 86 const char *initrd_filename = machine->initrd_filename; 87 const char *boot_device = machine->boot_order; 88 MemoryRegion *sysmem = get_system_memory(); 89 PowerPCCPU *cpu = NULL; 90 CPUPPCState *env = NULL; 91 char *filename; 92 int linux_boot, i; 93 MemoryRegion *bios = g_new(MemoryRegion, 1); 94 uint32_t kernel_base, initrd_base, cmdline_base = 0; 95 int32_t kernel_size, initrd_size; 96 PCIBus *pci_bus; 97 PCIDevice *macio; 98 MACIOIDEState *macio_ide; 99 SysBusDevice *s; 100 DeviceState *dev, *pic_dev; 101 BusState *adb_bus; 102 int bios_size; 103 unsigned int smp_cpus = machine->smp.cpus; 104 uint16_t ppc_boot_device; 105 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 106 void *fw_cfg; 107 uint64_t tbfreq; 108 109 linux_boot = (kernel_filename != NULL); 110 111 /* init CPUs */ 112 for (i = 0; i < smp_cpus; i++) { 113 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 114 env = &cpu->env; 115 116 /* Set time-base frequency to 16.6 Mhz */ 117 cpu_ppc_tb_init(env, TBFREQ); 118 qemu_register_reset(ppc_heathrow_reset, cpu); 119 } 120 121 /* allocate RAM */ 122 if (ram_size > 2047 * MiB) { 123 error_report("Too much memory for this machine: %" PRId64 " MB, " 124 "maximum 2047 MB", ram_size / MiB); 125 exit(1); 126 } 127 128 memory_region_add_subregion(sysmem, 0, machine->ram); 129 130 /* allocate and load BIOS */ 131 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE, 132 &error_fatal); 133 134 if (bios_name == NULL) 135 bios_name = PROM_FILENAME; 136 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 137 memory_region_add_subregion(sysmem, PROM_ADDR, bios); 138 139 /* Load OpenBIOS (ELF) */ 140 if (filename) { 141 bios_size = load_elf(filename, NULL, 0, NULL, NULL, NULL, NULL, NULL, 142 1, PPC_ELF_MACHINE, 0, 0); 143 g_free(filename); 144 } else { 145 bios_size = -1; 146 } 147 if (bios_size < 0 || bios_size > BIOS_SIZE) { 148 error_report("could not load PowerPC bios '%s'", bios_name); 149 exit(1); 150 } 151 152 if (linux_boot) { 153 uint64_t lowaddr = 0; 154 int bswap_needed; 155 156 #ifdef BSWAP_NEEDED 157 bswap_needed = 1; 158 #else 159 bswap_needed = 0; 160 #endif 161 kernel_base = KERNEL_LOAD_ADDR; 162 kernel_size = load_elf(kernel_filename, NULL, 163 translate_kernel_address, NULL, 164 NULL, &lowaddr, NULL, NULL, 1, PPC_ELF_MACHINE, 165 0, 0); 166 if (kernel_size < 0) 167 kernel_size = load_aout(kernel_filename, kernel_base, 168 ram_size - kernel_base, bswap_needed, 169 TARGET_PAGE_SIZE); 170 if (kernel_size < 0) 171 kernel_size = load_image_targphys(kernel_filename, 172 kernel_base, 173 ram_size - kernel_base); 174 if (kernel_size < 0) { 175 error_report("could not load kernel '%s'", kernel_filename); 176 exit(1); 177 } 178 /* load initrd */ 179 if (initrd_filename) { 180 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 181 initrd_size = load_image_targphys(initrd_filename, initrd_base, 182 ram_size - initrd_base); 183 if (initrd_size < 0) { 184 error_report("could not load initial ram disk '%s'", 185 initrd_filename); 186 exit(1); 187 } 188 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 189 } else { 190 initrd_base = 0; 191 initrd_size = 0; 192 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 193 } 194 ppc_boot_device = 'm'; 195 } else { 196 kernel_base = 0; 197 kernel_size = 0; 198 initrd_base = 0; 199 initrd_size = 0; 200 ppc_boot_device = '\0'; 201 for (i = 0; boot_device[i] != '\0'; i++) { 202 /* TOFIX: for now, the second IDE channel is not properly 203 * used by OHW. The Mac floppy disk are not emulated. 204 * For now, OHW cannot boot from the network. 205 */ 206 #if 0 207 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 208 ppc_boot_device = boot_device[i]; 209 break; 210 } 211 #else 212 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 213 ppc_boot_device = boot_device[i]; 214 break; 215 } 216 #endif 217 } 218 if (ppc_boot_device == '\0') { 219 error_report("No valid boot device for G3 Beige machine"); 220 exit(1); 221 } 222 } 223 224 /* XXX: we register only 1 output pin for heathrow PIC */ 225 pic_dev = qdev_new(TYPE_HEATHROW); 226 sysbus_realize_and_unref(SYS_BUS_DEVICE(pic_dev), &error_fatal); 227 228 /* Connect the heathrow PIC outputs to the 6xx bus */ 229 for (i = 0; i < smp_cpus; i++) { 230 switch (PPC_INPUT(env)) { 231 case PPC_FLAGS_INPUT_6xx: 232 qdev_connect_gpio_out(pic_dev, 0, 233 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]); 234 break; 235 default: 236 error_report("Bus model not supported on OldWorld Mac machine"); 237 exit(1); 238 } 239 } 240 241 /* Timebase Frequency */ 242 if (kvm_enabled()) { 243 tbfreq = kvmppc_get_tbfreq(); 244 } else { 245 tbfreq = TBFREQ; 246 } 247 248 /* init basic PC hardware */ 249 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 250 error_report("Only 6xx bus is supported on heathrow machine"); 251 exit(1); 252 } 253 254 /* Grackle PCI host bridge */ 255 dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); 256 qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000); 257 object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev), 258 &error_abort); 259 s = SYS_BUS_DEVICE(dev); 260 sysbus_realize_and_unref(s, &error_fatal); 261 sysbus_mmio_map(s, 0, GRACKLE_BASE); 262 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 263 /* PCI hole */ 264 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 265 sysbus_mmio_get_region(s, 2)); 266 /* Register 2 MB of ISA IO space */ 267 memory_region_add_subregion(get_system_memory(), 0xfe000000, 268 sysbus_mmio_get_region(s, 3)); 269 270 pci_bus = PCI_HOST_BRIDGE(dev)->bus; 271 272 pci_vga_init(pci_bus); 273 274 for (i = 0; i < nb_nics; i++) { 275 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 276 } 277 278 ide_drive_get(hd, ARRAY_SIZE(hd)); 279 280 /* MacIO */ 281 macio = pci_new(-1, TYPE_OLDWORLD_MACIO); 282 dev = DEVICE(macio); 283 qdev_prop_set_uint64(dev, "frequency", tbfreq); 284 object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev), 285 &error_abort); 286 pci_realize_and_unref(macio, pci_bus, &error_fatal); 287 288 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 289 "ide[0]")); 290 macio_ide_init_drives(macio_ide, hd); 291 292 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 293 "ide[1]")); 294 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 295 296 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 297 adb_bus = qdev_get_child_bus(dev, "adb.0"); 298 dev = qdev_new(TYPE_ADB_KEYBOARD); 299 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 300 dev = qdev_new(TYPE_ADB_MOUSE); 301 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 302 303 if (machine_usb(machine)) { 304 pci_create_simple(pci_bus, -1, "pci-ohci"); 305 } 306 307 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 308 graphic_depth = 15; 309 310 /* No PCI init: the BIOS will do it */ 311 312 dev = qdev_new(TYPE_FW_CFG_MEM); 313 fw_cfg = FW_CFG(dev); 314 qdev_prop_set_uint32(dev, "data_width", 1); 315 qdev_prop_set_bit(dev, "dma_enabled", false); 316 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 317 OBJECT(fw_cfg)); 318 s = SYS_BUS_DEVICE(dev); 319 sysbus_realize_and_unref(s, &error_fatal); 320 sysbus_mmio_map(s, 0, CFG_ADDR); 321 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 322 323 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 324 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 325 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 326 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 327 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 328 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 329 if (kernel_cmdline) { 330 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 331 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 332 } else { 333 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 334 } 335 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 336 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 337 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 338 339 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 340 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 341 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 342 343 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 344 if (kvm_enabled()) { 345 uint8_t *hypercall; 346 347 hypercall = g_malloc(16); 348 kvmppc_get_hypercall(env, hypercall, 16); 349 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 350 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 351 } 352 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 353 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 354 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 355 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 356 357 /* MacOS NDRV VGA driver */ 358 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 359 if (filename) { 360 gchar *ndrv_file; 361 gsize ndrv_size; 362 363 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 364 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 365 } 366 g_free(filename); 367 } 368 369 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 370 } 371 372 /* 373 * Implementation of an interface to adjust firmware path 374 * for the bootindex property handling. 375 */ 376 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, 377 DeviceState *dev) 378 { 379 PCIDevice *pci; 380 IDEBus *ide_bus; 381 IDEState *ide_s; 382 MACIOIDEState *macio_ide; 383 384 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { 385 pci = PCI_DEVICE(dev); 386 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 387 } 388 389 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 390 macio_ide = MACIO_IDE(dev); 391 return g_strdup_printf("ata-3@%x", macio_ide->addr); 392 } 393 394 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) { 395 ide_bus = IDE_BUS(qdev_get_parent_bus(dev)); 396 ide_s = idebus_active_if(ide_bus); 397 398 if (ide_s->drive_kind == IDE_CD) { 399 return g_strdup("cdrom"); 400 } 401 402 return g_strdup("disk"); 403 } 404 405 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 406 return g_strdup("disk"); 407 } 408 409 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 410 return g_strdup("cdrom"); 411 } 412 413 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 414 return g_strdup("disk"); 415 } 416 417 return NULL; 418 } 419 420 static int heathrow_kvm_type(MachineState *machine, const char *arg) 421 { 422 /* Always force PR KVM */ 423 return 2; 424 } 425 426 static void heathrow_class_init(ObjectClass *oc, void *data) 427 { 428 MachineClass *mc = MACHINE_CLASS(oc); 429 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 430 431 mc->desc = "Heathrow based PowerMAC"; 432 mc->init = ppc_heathrow_init; 433 mc->block_default_type = IF_IDE; 434 mc->max_cpus = MAX_CPUS; 435 #ifndef TARGET_PPC64 436 mc->is_default = true; 437 #endif 438 /* TOFIX "cad" when Mac floppy is implemented */ 439 mc->default_boot_order = "cd"; 440 mc->kvm_type = heathrow_kvm_type; 441 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 442 mc->default_display = "std"; 443 mc->ignore_boot_device_suffixes = true; 444 mc->default_ram_id = "ppc_heathrow.ram"; 445 fwc->get_dev_path = heathrow_fw_dev_path; 446 } 447 448 static const TypeInfo ppc_heathrow_machine_info = { 449 .name = MACHINE_TYPE_NAME("g3beige"), 450 .parent = TYPE_MACHINE, 451 .class_init = heathrow_class_init, 452 .interfaces = (InterfaceInfo[]) { 453 { TYPE_FW_PATH_PROVIDER }, 454 { } 455 }, 456 }; 457 458 static void ppc_heathrow_register_types(void) 459 { 460 type_register_static(&ppc_heathrow_machine_info); 461 } 462 463 type_init(ppc_heathrow_register_types); 464