1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "hw/ppc/ppc.h" 30 #include "mac.h" 31 #include "hw/input/adb.h" 32 #include "hw/timer/m48t59.h" 33 #include "sysemu/sysemu.h" 34 #include "net/net.h" 35 #include "hw/isa/isa.h" 36 #include "hw/pci/pci.h" 37 #include "hw/boards.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/char/escc.h" 40 #include "hw/ide.h" 41 #include "hw/loader.h" 42 #include "elf.h" 43 #include "qemu/error-report.h" 44 #include "sysemu/kvm.h" 45 #include "kvm_ppc.h" 46 #include "sysemu/block-backend.h" 47 #include "exec/address-spaces.h" 48 #include "qemu/cutils.h" 49 50 #define MAX_IDE_BUS 2 51 #define CFG_ADDR 0xf0000510 52 #define TBFREQ 16600000UL 53 #define CLOCKFREQ 266000000UL 54 #define BUSFREQ 66000000UL 55 56 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 57 58 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 59 Error **errp) 60 { 61 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 62 } 63 64 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 65 { 66 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 67 } 68 69 static hwaddr round_page(hwaddr addr) 70 { 71 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 72 } 73 74 static void ppc_heathrow_reset(void *opaque) 75 { 76 PowerPCCPU *cpu = opaque; 77 78 cpu_reset(CPU(cpu)); 79 } 80 81 static void ppc_heathrow_init(MachineState *machine) 82 { 83 ram_addr_t ram_size = machine->ram_size; 84 const char *kernel_filename = machine->kernel_filename; 85 const char *kernel_cmdline = machine->kernel_cmdline; 86 const char *initrd_filename = machine->initrd_filename; 87 const char *boot_device = machine->boot_order; 88 MemoryRegion *sysmem = get_system_memory(); 89 PowerPCCPU *cpu = NULL; 90 CPUPPCState *env = NULL; 91 char *filename; 92 qemu_irq *pic, **heathrow_irqs; 93 int linux_boot, i; 94 MemoryRegion *ram = g_new(MemoryRegion, 1); 95 MemoryRegion *bios = g_new(MemoryRegion, 1); 96 MemoryRegion *isa = g_new(MemoryRegion, 1); 97 uint32_t kernel_base, initrd_base, cmdline_base = 0; 98 int32_t kernel_size, initrd_size; 99 PCIBus *pci_bus; 100 PCIDevice *macio; 101 MACIOIDEState *macio_ide; 102 DeviceState *dev; 103 BusState *adb_bus; 104 int bios_size, ndrv_size; 105 uint8_t *ndrv_file; 106 MemoryRegion *pic_mem; 107 MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1); 108 uint16_t ppc_boot_device; 109 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 110 void *fw_cfg; 111 uint64_t tbfreq; 112 113 linux_boot = (kernel_filename != NULL); 114 115 /* init CPUs */ 116 if (machine->cpu_model == NULL) 117 machine->cpu_model = "G3"; 118 for (i = 0; i < smp_cpus; i++) { 119 cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, 120 machine->cpu_model)); 121 if (cpu == NULL) { 122 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 123 exit(1); 124 } 125 env = &cpu->env; 126 127 /* Set time-base frequency to 16.6 Mhz */ 128 cpu_ppc_tb_init(env, TBFREQ); 129 qemu_register_reset(ppc_heathrow_reset, cpu); 130 } 131 132 /* allocate RAM */ 133 if (ram_size > (2047 << 20)) { 134 fprintf(stderr, 135 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", 136 ((unsigned int)ram_size / (1 << 20))); 137 exit(1); 138 } 139 140 memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram", 141 ram_size); 142 memory_region_add_subregion(sysmem, 0, ram); 143 144 /* allocate and load BIOS */ 145 memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE, 146 &error_fatal); 147 148 if (bios_name == NULL) 149 bios_name = PROM_FILENAME; 150 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 151 memory_region_set_readonly(bios, true); 152 memory_region_add_subregion(sysmem, PROM_ADDR, bios); 153 154 /* Load OpenBIOS (ELF) */ 155 if (filename) { 156 bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL, 157 1, PPC_ELF_MACHINE, 0, 0); 158 g_free(filename); 159 } else { 160 bios_size = -1; 161 } 162 if (bios_size < 0 || bios_size > BIOS_SIZE) { 163 error_report("could not load PowerPC bios '%s'", bios_name); 164 exit(1); 165 } 166 167 if (linux_boot) { 168 uint64_t lowaddr = 0; 169 int bswap_needed; 170 171 #ifdef BSWAP_NEEDED 172 bswap_needed = 1; 173 #else 174 bswap_needed = 0; 175 #endif 176 kernel_base = KERNEL_LOAD_ADDR; 177 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 178 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 179 0, 0); 180 if (kernel_size < 0) 181 kernel_size = load_aout(kernel_filename, kernel_base, 182 ram_size - kernel_base, bswap_needed, 183 TARGET_PAGE_SIZE); 184 if (kernel_size < 0) 185 kernel_size = load_image_targphys(kernel_filename, 186 kernel_base, 187 ram_size - kernel_base); 188 if (kernel_size < 0) { 189 error_report("could not load kernel '%s'", kernel_filename); 190 exit(1); 191 } 192 /* load initrd */ 193 if (initrd_filename) { 194 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 195 initrd_size = load_image_targphys(initrd_filename, initrd_base, 196 ram_size - initrd_base); 197 if (initrd_size < 0) { 198 error_report("could not load initial ram disk '%s'", 199 initrd_filename); 200 exit(1); 201 } 202 cmdline_base = round_page(initrd_base + initrd_size); 203 } else { 204 initrd_base = 0; 205 initrd_size = 0; 206 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 207 } 208 ppc_boot_device = 'm'; 209 } else { 210 kernel_base = 0; 211 kernel_size = 0; 212 initrd_base = 0; 213 initrd_size = 0; 214 ppc_boot_device = '\0'; 215 for (i = 0; boot_device[i] != '\0'; i++) { 216 /* TOFIX: for now, the second IDE channel is not properly 217 * used by OHW. The Mac floppy disk are not emulated. 218 * For now, OHW cannot boot from the network. 219 */ 220 #if 0 221 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 222 ppc_boot_device = boot_device[i]; 223 break; 224 } 225 #else 226 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 227 ppc_boot_device = boot_device[i]; 228 break; 229 } 230 #endif 231 } 232 if (ppc_boot_device == '\0') { 233 fprintf(stderr, "No valid boot device for G3 Beige machine\n"); 234 exit(1); 235 } 236 } 237 238 /* Register 2 MB of ISA IO space */ 239 memory_region_init_alias(isa, NULL, "isa_mmio", 240 get_system_io(), 0, 0x00200000); 241 memory_region_add_subregion(sysmem, 0xfe000000, isa); 242 243 /* XXX: we register only 1 output pin for heathrow PIC */ 244 heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 245 heathrow_irqs[0] = 246 g_malloc0(smp_cpus * sizeof(qemu_irq) * 1); 247 /* Connect the heathrow PIC outputs to the 6xx bus */ 248 for (i = 0; i < smp_cpus; i++) { 249 switch (PPC_INPUT(env)) { 250 case PPC_FLAGS_INPUT_6xx: 251 heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); 252 heathrow_irqs[i][0] = 253 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 254 break; 255 default: 256 error_report("Bus model not supported on OldWorld Mac machine"); 257 exit(1); 258 } 259 } 260 261 /* Timebase Frequency */ 262 if (kvm_enabled()) { 263 tbfreq = kvmppc_get_tbfreq(); 264 } else { 265 tbfreq = TBFREQ; 266 } 267 268 /* init basic PC hardware */ 269 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 270 error_report("Only 6xx bus is supported on heathrow machine"); 271 exit(1); 272 } 273 pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs); 274 pci_bus = pci_grackle_init(0xfec00000, pic, 275 get_system_memory(), 276 get_system_io()); 277 pci_vga_init(pci_bus); 278 279 escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0], 280 serial_hds[1], ESCC_CLOCK, 4); 281 memory_region_init_alias(escc_bar, NULL, "escc-bar", 282 escc_mem, 0, memory_region_size(escc_mem)); 283 284 for(i = 0; i < nb_nics; i++) 285 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 286 287 288 ide_drive_get(hd, ARRAY_SIZE(hd)); 289 290 macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO); 291 dev = DEVICE(macio); 292 qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */ 293 qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */ 294 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */ 295 qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */ 296 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */ 297 qdev_prop_set_uint64(dev, "frequency", tbfreq); 298 macio_init(macio, pic_mem, escc_bar); 299 300 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 301 "ide[0]")); 302 macio_ide_init_drives(macio_ide, hd); 303 304 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 305 "ide[1]")); 306 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 307 308 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 309 adb_bus = qdev_get_child_bus(dev, "adb.0"); 310 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 311 qdev_init_nofail(dev); 312 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 313 qdev_init_nofail(dev); 314 315 if (machine_usb(machine)) { 316 pci_create_simple(pci_bus, -1, "pci-ohci"); 317 } 318 319 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 320 graphic_depth = 15; 321 322 /* No PCI init: the BIOS will do it */ 323 324 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 325 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 326 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 327 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 328 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 329 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 330 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 331 if (kernel_cmdline) { 332 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 333 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 334 } else { 335 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 336 } 337 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 338 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 339 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 340 341 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 342 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 343 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 344 345 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 346 if (kvm_enabled()) { 347 #ifdef CONFIG_KVM 348 uint8_t *hypercall; 349 350 hypercall = g_malloc(16); 351 kvmppc_get_hypercall(env, hypercall, 16); 352 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 353 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 354 #endif 355 } 356 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 357 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 358 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 359 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 360 361 /* MacOS NDRV VGA driver */ 362 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 363 if (filename) { 364 ndrv_size = get_image_size(filename); 365 if (ndrv_size != -1) { 366 ndrv_file = g_malloc(ndrv_size); 367 ndrv_size = load_image(filename, ndrv_file); 368 369 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 370 } 371 g_free(filename); 372 } 373 374 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 375 } 376 377 static int heathrow_kvm_type(const char *arg) 378 { 379 /* Always force PR KVM */ 380 return 2; 381 } 382 383 static void heathrow_machine_init(MachineClass *mc) 384 { 385 mc->desc = "Heathrow based PowerMAC"; 386 mc->init = ppc_heathrow_init; 387 mc->block_default_type = IF_IDE; 388 mc->max_cpus = MAX_CPUS; 389 #ifndef TARGET_PPC64 390 mc->is_default = 1; 391 #endif 392 /* TOFIX "cad" when Mac floppy is implemented */ 393 mc->default_boot_order = "cd"; 394 mc->kvm_type = heathrow_kvm_type; 395 } 396 397 DEFINE_MACHINE("g3beige", heathrow_machine_init) 398