1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "hw/ppc/ppc.h" 30 #include "mac.h" 31 #include "hw/input/adb.h" 32 #include "hw/timer/m48t59.h" 33 #include "sysemu/sysemu.h" 34 #include "net/net.h" 35 #include "hw/isa/isa.h" 36 #include "hw/pci/pci.h" 37 #include "hw/boards.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/char/escc.h" 40 #include "hw/ide.h" 41 #include "hw/loader.h" 42 #include "elf.h" 43 #include "qemu/error-report.h" 44 #include "sysemu/kvm.h" 45 #include "kvm_ppc.h" 46 #include "sysemu/block-backend.h" 47 #include "exec/address-spaces.h" 48 #include "qemu/cutils.h" 49 50 #define MAX_IDE_BUS 2 51 #define CFG_ADDR 0xf0000510 52 #define TBFREQ 16600000UL 53 #define CLOCKFREQ 266000000UL 54 #define BUSFREQ 66000000UL 55 56 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 57 58 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 59 Error **errp) 60 { 61 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 62 } 63 64 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 65 { 66 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 67 } 68 69 static hwaddr round_page(hwaddr addr) 70 { 71 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 72 } 73 74 static void ppc_heathrow_reset(void *opaque) 75 { 76 PowerPCCPU *cpu = opaque; 77 78 cpu_reset(CPU(cpu)); 79 } 80 81 static void ppc_heathrow_init(MachineState *machine) 82 { 83 ram_addr_t ram_size = machine->ram_size; 84 const char *kernel_filename = machine->kernel_filename; 85 const char *kernel_cmdline = machine->kernel_cmdline; 86 const char *initrd_filename = machine->initrd_filename; 87 const char *boot_device = machine->boot_order; 88 MemoryRegion *sysmem = get_system_memory(); 89 PowerPCCPU *cpu = NULL; 90 CPUPPCState *env = NULL; 91 char *filename; 92 qemu_irq *pic, **heathrow_irqs; 93 int linux_boot, i; 94 MemoryRegion *ram = g_new(MemoryRegion, 1); 95 MemoryRegion *bios = g_new(MemoryRegion, 1); 96 MemoryRegion *isa = g_new(MemoryRegion, 1); 97 uint32_t kernel_base, initrd_base, cmdline_base = 0; 98 int32_t kernel_size, initrd_size; 99 PCIBus *pci_bus; 100 PCIDevice *macio; 101 MACIOIDEState *macio_ide; 102 DeviceState *dev; 103 BusState *adb_bus; 104 int bios_size, ndrv_size; 105 uint8_t *ndrv_file; 106 MemoryRegion *pic_mem; 107 MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1); 108 uint16_t ppc_boot_device; 109 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 110 void *fw_cfg; 111 uint64_t tbfreq; 112 113 linux_boot = (kernel_filename != NULL); 114 115 /* init CPUs */ 116 if (machine->cpu_model == NULL) 117 machine->cpu_model = "G3"; 118 for (i = 0; i < smp_cpus; i++) { 119 cpu = cpu_ppc_init(machine->cpu_model); 120 if (cpu == NULL) { 121 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 122 exit(1); 123 } 124 env = &cpu->env; 125 126 /* Set time-base frequency to 16.6 Mhz */ 127 cpu_ppc_tb_init(env, TBFREQ); 128 qemu_register_reset(ppc_heathrow_reset, cpu); 129 } 130 131 /* allocate RAM */ 132 if (ram_size > (2047 << 20)) { 133 fprintf(stderr, 134 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", 135 ((unsigned int)ram_size / (1 << 20))); 136 exit(1); 137 } 138 139 memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram", 140 ram_size); 141 memory_region_add_subregion(sysmem, 0, ram); 142 143 /* allocate and load BIOS */ 144 memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE, 145 &error_fatal); 146 147 if (bios_name == NULL) 148 bios_name = PROM_FILENAME; 149 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 150 memory_region_set_readonly(bios, true); 151 memory_region_add_subregion(sysmem, PROM_ADDR, bios); 152 153 /* Load OpenBIOS (ELF) */ 154 if (filename) { 155 bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL, 156 1, PPC_ELF_MACHINE, 0, 0); 157 g_free(filename); 158 } else { 159 bios_size = -1; 160 } 161 if (bios_size < 0 || bios_size > BIOS_SIZE) { 162 error_report("could not load PowerPC bios '%s'", bios_name); 163 exit(1); 164 } 165 166 if (linux_boot) { 167 uint64_t lowaddr = 0; 168 int bswap_needed; 169 170 #ifdef BSWAP_NEEDED 171 bswap_needed = 1; 172 #else 173 bswap_needed = 0; 174 #endif 175 kernel_base = KERNEL_LOAD_ADDR; 176 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 177 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 178 0, 0); 179 if (kernel_size < 0) 180 kernel_size = load_aout(kernel_filename, kernel_base, 181 ram_size - kernel_base, bswap_needed, 182 TARGET_PAGE_SIZE); 183 if (kernel_size < 0) 184 kernel_size = load_image_targphys(kernel_filename, 185 kernel_base, 186 ram_size - kernel_base); 187 if (kernel_size < 0) { 188 error_report("could not load kernel '%s'", kernel_filename); 189 exit(1); 190 } 191 /* load initrd */ 192 if (initrd_filename) { 193 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 194 initrd_size = load_image_targphys(initrd_filename, initrd_base, 195 ram_size - initrd_base); 196 if (initrd_size < 0) { 197 error_report("could not load initial ram disk '%s'", 198 initrd_filename); 199 exit(1); 200 } 201 cmdline_base = round_page(initrd_base + initrd_size); 202 } else { 203 initrd_base = 0; 204 initrd_size = 0; 205 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 206 } 207 ppc_boot_device = 'm'; 208 } else { 209 kernel_base = 0; 210 kernel_size = 0; 211 initrd_base = 0; 212 initrd_size = 0; 213 ppc_boot_device = '\0'; 214 for (i = 0; boot_device[i] != '\0'; i++) { 215 /* TOFIX: for now, the second IDE channel is not properly 216 * used by OHW. The Mac floppy disk are not emulated. 217 * For now, OHW cannot boot from the network. 218 */ 219 #if 0 220 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 221 ppc_boot_device = boot_device[i]; 222 break; 223 } 224 #else 225 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 226 ppc_boot_device = boot_device[i]; 227 break; 228 } 229 #endif 230 } 231 if (ppc_boot_device == '\0') { 232 fprintf(stderr, "No valid boot device for G3 Beige machine\n"); 233 exit(1); 234 } 235 } 236 237 /* Register 2 MB of ISA IO space */ 238 memory_region_init_alias(isa, NULL, "isa_mmio", 239 get_system_io(), 0, 0x00200000); 240 memory_region_add_subregion(sysmem, 0xfe000000, isa); 241 242 /* XXX: we register only 1 output pin for heathrow PIC */ 243 heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 244 heathrow_irqs[0] = 245 g_malloc0(smp_cpus * sizeof(qemu_irq) * 1); 246 /* Connect the heathrow PIC outputs to the 6xx bus */ 247 for (i = 0; i < smp_cpus; i++) { 248 switch (PPC_INPUT(env)) { 249 case PPC_FLAGS_INPUT_6xx: 250 heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); 251 heathrow_irqs[i][0] = 252 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 253 break; 254 default: 255 error_report("Bus model not supported on OldWorld Mac machine"); 256 exit(1); 257 } 258 } 259 260 /* Timebase Frequency */ 261 if (kvm_enabled()) { 262 tbfreq = kvmppc_get_tbfreq(); 263 } else { 264 tbfreq = TBFREQ; 265 } 266 267 /* init basic PC hardware */ 268 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 269 error_report("Only 6xx bus is supported on heathrow machine"); 270 exit(1); 271 } 272 pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs); 273 pci_bus = pci_grackle_init(0xfec00000, pic, 274 get_system_memory(), 275 get_system_io()); 276 pci_vga_init(pci_bus); 277 278 escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0], 279 serial_hds[1], ESCC_CLOCK, 4); 280 memory_region_init_alias(escc_bar, NULL, "escc-bar", 281 escc_mem, 0, memory_region_size(escc_mem)); 282 283 for(i = 0; i < nb_nics; i++) 284 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 285 286 287 ide_drive_get(hd, ARRAY_SIZE(hd)); 288 289 macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO); 290 dev = DEVICE(macio); 291 qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */ 292 qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */ 293 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */ 294 qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */ 295 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */ 296 qdev_prop_set_uint64(dev, "frequency", tbfreq); 297 macio_init(macio, pic_mem, escc_bar); 298 299 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 300 "ide[0]")); 301 macio_ide_init_drives(macio_ide, hd); 302 303 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 304 "ide[1]")); 305 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 306 307 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 308 adb_bus = qdev_get_child_bus(dev, "adb.0"); 309 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 310 qdev_init_nofail(dev); 311 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 312 qdev_init_nofail(dev); 313 314 if (machine_usb(machine)) { 315 pci_create_simple(pci_bus, -1, "pci-ohci"); 316 } 317 318 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 319 graphic_depth = 15; 320 321 /* No PCI init: the BIOS will do it */ 322 323 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 324 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 325 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 326 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 327 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 328 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 329 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 330 if (kernel_cmdline) { 331 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 332 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 333 } else { 334 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 335 } 336 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 337 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 338 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 339 340 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 341 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 342 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 343 344 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 345 if (kvm_enabled()) { 346 #ifdef CONFIG_KVM 347 uint8_t *hypercall; 348 349 hypercall = g_malloc(16); 350 kvmppc_get_hypercall(env, hypercall, 16); 351 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 352 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 353 #endif 354 } 355 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 356 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 357 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 358 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 359 360 /* MacOS NDRV VGA driver */ 361 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 362 if (filename) { 363 ndrv_size = get_image_size(filename); 364 if (ndrv_size != -1) { 365 ndrv_file = g_malloc(ndrv_size); 366 ndrv_size = load_image(filename, ndrv_file); 367 368 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 369 } 370 g_free(filename); 371 } 372 373 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 374 } 375 376 static int heathrow_kvm_type(const char *arg) 377 { 378 /* Always force PR KVM */ 379 return 2; 380 } 381 382 static void heathrow_machine_init(MachineClass *mc) 383 { 384 mc->desc = "Heathrow based PowerMAC"; 385 mc->init = ppc_heathrow_init; 386 mc->block_default_type = IF_IDE; 387 mc->max_cpus = MAX_CPUS; 388 #ifndef TARGET_PPC64 389 mc->is_default = 1; 390 #endif 391 /* TOFIX "cad" when Mac floppy is implemented */ 392 mc->default_boot_order = "cd"; 393 mc->kvm_type = heathrow_kvm_type; 394 } 395 396 DEFINE_MACHINE("g3beige", heathrow_machine_init) 397