1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "hw/ppc/ppc.h" 32 #include "hw/qdev-properties.h" 33 #include "mac.h" 34 #include "hw/input/adb.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/isa/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_host.h" 40 #include "hw/boards.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/char/escc.h" 43 #include "hw/misc/macio/macio.h" 44 #include "hw/loader.h" 45 #include "hw/fw-path-provider.h" 46 #include "elf.h" 47 #include "qemu/error-report.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/reset.h" 50 #include "kvm_ppc.h" 51 #include "exec/address-spaces.h" 52 53 #define MAX_IDE_BUS 2 54 #define CFG_ADDR 0xf0000510 55 #define TBFREQ 16600000UL 56 #define CLOCKFREQ 266000000UL 57 #define BUSFREQ 66000000UL 58 59 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 60 61 #define GRACKLE_BASE 0xfec00000 62 63 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 64 Error **errp) 65 { 66 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 67 } 68 69 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 70 { 71 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 72 } 73 74 static void ppc_heathrow_reset(void *opaque) 75 { 76 PowerPCCPU *cpu = opaque; 77 78 cpu_reset(CPU(cpu)); 79 } 80 81 static void ppc_heathrow_init(MachineState *machine) 82 { 83 ram_addr_t ram_size = machine->ram_size; 84 const char *kernel_filename = machine->kernel_filename; 85 const char *kernel_cmdline = machine->kernel_cmdline; 86 const char *initrd_filename = machine->initrd_filename; 87 const char *boot_device = machine->boot_order; 88 MemoryRegion *sysmem = get_system_memory(); 89 PowerPCCPU *cpu = NULL; 90 CPUPPCState *env = NULL; 91 char *filename; 92 int linux_boot, i; 93 MemoryRegion *bios = g_new(MemoryRegion, 1); 94 uint32_t kernel_base, initrd_base, cmdline_base = 0; 95 int32_t kernel_size, initrd_size; 96 PCIBus *pci_bus; 97 PCIDevice *macio; 98 MACIOIDEState *macio_ide; 99 SysBusDevice *s; 100 DeviceState *dev, *pic_dev; 101 BusState *adb_bus; 102 int bios_size; 103 unsigned int smp_cpus = machine->smp.cpus; 104 uint16_t ppc_boot_device; 105 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 106 void *fw_cfg; 107 uint64_t tbfreq; 108 109 linux_boot = (kernel_filename != NULL); 110 111 /* init CPUs */ 112 for (i = 0; i < smp_cpus; i++) { 113 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 114 env = &cpu->env; 115 116 /* Set time-base frequency to 16.6 Mhz */ 117 cpu_ppc_tb_init(env, TBFREQ); 118 qemu_register_reset(ppc_heathrow_reset, cpu); 119 } 120 121 /* allocate RAM */ 122 if (ram_size > 2047 * MiB) { 123 error_report("Too much memory for this machine: %" PRId64 " MB, " 124 "maximum 2047 MB", ram_size / MiB); 125 exit(1); 126 } 127 128 memory_region_add_subregion(sysmem, 0, machine->ram); 129 130 /* allocate and load BIOS */ 131 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE, 132 &error_fatal); 133 134 if (bios_name == NULL) 135 bios_name = PROM_FILENAME; 136 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 137 memory_region_add_subregion(sysmem, PROM_ADDR, bios); 138 139 /* Load OpenBIOS (ELF) */ 140 if (filename) { 141 bios_size = load_elf(filename, NULL, 0, NULL, NULL, NULL, NULL, NULL, 142 1, PPC_ELF_MACHINE, 0, 0); 143 g_free(filename); 144 } else { 145 bios_size = -1; 146 } 147 if (bios_size < 0 || bios_size > BIOS_SIZE) { 148 error_report("could not load PowerPC bios '%s'", bios_name); 149 exit(1); 150 } 151 152 if (linux_boot) { 153 int bswap_needed; 154 155 #ifdef BSWAP_NEEDED 156 bswap_needed = 1; 157 #else 158 bswap_needed = 0; 159 #endif 160 kernel_base = KERNEL_LOAD_ADDR; 161 kernel_size = load_elf(kernel_filename, NULL, 162 translate_kernel_address, NULL, NULL, NULL, 163 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 164 if (kernel_size < 0) 165 kernel_size = load_aout(kernel_filename, kernel_base, 166 ram_size - kernel_base, bswap_needed, 167 TARGET_PAGE_SIZE); 168 if (kernel_size < 0) 169 kernel_size = load_image_targphys(kernel_filename, 170 kernel_base, 171 ram_size - kernel_base); 172 if (kernel_size < 0) { 173 error_report("could not load kernel '%s'", kernel_filename); 174 exit(1); 175 } 176 /* load initrd */ 177 if (initrd_filename) { 178 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 179 initrd_size = load_image_targphys(initrd_filename, initrd_base, 180 ram_size - initrd_base); 181 if (initrd_size < 0) { 182 error_report("could not load initial ram disk '%s'", 183 initrd_filename); 184 exit(1); 185 } 186 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 187 } else { 188 initrd_base = 0; 189 initrd_size = 0; 190 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 191 } 192 ppc_boot_device = 'm'; 193 } else { 194 kernel_base = 0; 195 kernel_size = 0; 196 initrd_base = 0; 197 initrd_size = 0; 198 ppc_boot_device = '\0'; 199 for (i = 0; boot_device[i] != '\0'; i++) { 200 /* TOFIX: for now, the second IDE channel is not properly 201 * used by OHW. The Mac floppy disk are not emulated. 202 * For now, OHW cannot boot from the network. 203 */ 204 #if 0 205 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 206 ppc_boot_device = boot_device[i]; 207 break; 208 } 209 #else 210 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 211 ppc_boot_device = boot_device[i]; 212 break; 213 } 214 #endif 215 } 216 if (ppc_boot_device == '\0') { 217 error_report("No valid boot device for G3 Beige machine"); 218 exit(1); 219 } 220 } 221 222 /* XXX: we register only 1 output pin for heathrow PIC */ 223 pic_dev = qdev_new(TYPE_HEATHROW); 224 sysbus_realize_and_unref(SYS_BUS_DEVICE(pic_dev), &error_fatal); 225 226 /* Connect the heathrow PIC outputs to the 6xx bus */ 227 for (i = 0; i < smp_cpus; i++) { 228 switch (PPC_INPUT(env)) { 229 case PPC_FLAGS_INPUT_6xx: 230 qdev_connect_gpio_out(pic_dev, 0, 231 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]); 232 break; 233 default: 234 error_report("Bus model not supported on OldWorld Mac machine"); 235 exit(1); 236 } 237 } 238 239 /* Timebase Frequency */ 240 if (kvm_enabled()) { 241 tbfreq = kvmppc_get_tbfreq(); 242 } else { 243 tbfreq = TBFREQ; 244 } 245 246 /* init basic PC hardware */ 247 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 248 error_report("Only 6xx bus is supported on heathrow machine"); 249 exit(1); 250 } 251 252 /* Grackle PCI host bridge */ 253 dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); 254 qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000); 255 object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev), 256 &error_abort); 257 s = SYS_BUS_DEVICE(dev); 258 sysbus_realize_and_unref(s, &error_fatal); 259 sysbus_mmio_map(s, 0, GRACKLE_BASE); 260 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 261 /* PCI hole */ 262 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 263 sysbus_mmio_get_region(s, 2)); 264 /* Register 2 MB of ISA IO space */ 265 memory_region_add_subregion(get_system_memory(), 0xfe000000, 266 sysbus_mmio_get_region(s, 3)); 267 268 pci_bus = PCI_HOST_BRIDGE(dev)->bus; 269 270 pci_vga_init(pci_bus); 271 272 for (i = 0; i < nb_nics; i++) { 273 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 274 } 275 276 ide_drive_get(hd, ARRAY_SIZE(hd)); 277 278 /* MacIO */ 279 macio = pci_new(-1, TYPE_OLDWORLD_MACIO); 280 dev = DEVICE(macio); 281 qdev_prop_set_uint64(dev, "frequency", tbfreq); 282 object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev), 283 &error_abort); 284 pci_realize_and_unref(macio, pci_bus, &error_fatal); 285 286 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 287 "ide[0]")); 288 macio_ide_init_drives(macio_ide, hd); 289 290 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 291 "ide[1]")); 292 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 293 294 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 295 adb_bus = qdev_get_child_bus(dev, "adb.0"); 296 dev = qdev_new(TYPE_ADB_KEYBOARD); 297 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 298 dev = qdev_new(TYPE_ADB_MOUSE); 299 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 300 301 if (machine_usb(machine)) { 302 pci_create_simple(pci_bus, -1, "pci-ohci"); 303 } 304 305 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 306 graphic_depth = 15; 307 308 /* No PCI init: the BIOS will do it */ 309 310 dev = qdev_new(TYPE_FW_CFG_MEM); 311 fw_cfg = FW_CFG(dev); 312 qdev_prop_set_uint32(dev, "data_width", 1); 313 qdev_prop_set_bit(dev, "dma_enabled", false); 314 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 315 OBJECT(fw_cfg)); 316 s = SYS_BUS_DEVICE(dev); 317 sysbus_realize_and_unref(s, &error_fatal); 318 sysbus_mmio_map(s, 0, CFG_ADDR); 319 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 320 321 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 322 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 323 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 324 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 325 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 326 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 327 if (kernel_cmdline) { 328 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 329 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 330 } else { 331 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 332 } 333 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 334 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 335 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 336 337 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 338 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 339 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 340 341 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 342 if (kvm_enabled()) { 343 uint8_t *hypercall; 344 345 hypercall = g_malloc(16); 346 kvmppc_get_hypercall(env, hypercall, 16); 347 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 348 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 349 } 350 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 351 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 352 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 353 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 354 355 /* MacOS NDRV VGA driver */ 356 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 357 if (filename) { 358 gchar *ndrv_file; 359 gsize ndrv_size; 360 361 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 362 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 363 } 364 g_free(filename); 365 } 366 367 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 368 } 369 370 /* 371 * Implementation of an interface to adjust firmware path 372 * for the bootindex property handling. 373 */ 374 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, 375 DeviceState *dev) 376 { 377 PCIDevice *pci; 378 IDEBus *ide_bus; 379 IDEState *ide_s; 380 MACIOIDEState *macio_ide; 381 382 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { 383 pci = PCI_DEVICE(dev); 384 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 385 } 386 387 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 388 macio_ide = MACIO_IDE(dev); 389 return g_strdup_printf("ata-3@%x", macio_ide->addr); 390 } 391 392 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) { 393 ide_bus = IDE_BUS(qdev_get_parent_bus(dev)); 394 ide_s = idebus_active_if(ide_bus); 395 396 if (ide_s->drive_kind == IDE_CD) { 397 return g_strdup("cdrom"); 398 } 399 400 return g_strdup("disk"); 401 } 402 403 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 404 return g_strdup("disk"); 405 } 406 407 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 408 return g_strdup("cdrom"); 409 } 410 411 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 412 return g_strdup("disk"); 413 } 414 415 return NULL; 416 } 417 418 static int heathrow_kvm_type(MachineState *machine, const char *arg) 419 { 420 /* Always force PR KVM */ 421 return 2; 422 } 423 424 static void heathrow_class_init(ObjectClass *oc, void *data) 425 { 426 MachineClass *mc = MACHINE_CLASS(oc); 427 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 428 429 mc->desc = "Heathrow based PowerMAC"; 430 mc->init = ppc_heathrow_init; 431 mc->block_default_type = IF_IDE; 432 mc->max_cpus = MAX_CPUS; 433 #ifndef TARGET_PPC64 434 mc->is_default = true; 435 #endif 436 /* TOFIX "cad" when Mac floppy is implemented */ 437 mc->default_boot_order = "cd"; 438 mc->kvm_type = heathrow_kvm_type; 439 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 440 mc->default_display = "std"; 441 mc->ignore_boot_device_suffixes = true; 442 mc->default_ram_id = "ppc_heathrow.ram"; 443 fwc->get_dev_path = heathrow_fw_dev_path; 444 } 445 446 static const TypeInfo ppc_heathrow_machine_info = { 447 .name = MACHINE_TYPE_NAME("g3beige"), 448 .parent = TYPE_MACHINE, 449 .class_init = heathrow_class_init, 450 .interfaces = (InterfaceInfo[]) { 451 { TYPE_FW_PATH_PROVIDER }, 452 { } 453 }, 454 }; 455 456 static void ppc_heathrow_register_types(void) 457 { 458 type_register_static(&ppc_heathrow_machine_info); 459 } 460 461 type_init(ppc_heathrow_register_types); 462